| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.24 | 100.00 | 95.42 | 100.00 | 100.00 | 100.00 | 100.00 |
| T762 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4236425117 | May 09 01:02:18 PM PDT 24 | May 09 01:02:35 PM PDT 24 | 251526445 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3437820202 | May 09 01:00:33 PM PDT 24 | May 09 01:00:50 PM PDT 24 | 214246391 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.38283878 | May 09 01:01:36 PM PDT 24 | May 09 01:01:38 PM PDT 24 | 7900494 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2166794513 | May 09 12:58:44 PM PDT 24 | May 09 12:58:50 PM PDT 24 | 374593299 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1693125405 | May 09 01:02:38 PM PDT 24 | May 09 01:02:45 PM PDT 24 | 39915012 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/3.xbar_error_random.42759621 | May 09 12:59:08 PM PDT 24 | May 09 12:59:15 PM PDT 24 | 99176909 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.821281236 | May 09 12:59:21 PM PDT 24 | May 09 12:59:27 PM PDT 24 | 1663344275 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3365138492 | May 09 12:59:30 PM PDT 24 | May 09 12:59:36 PM PDT 24 | 291578883 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1529107524 | May 09 12:58:52 PM PDT 24 | May 09 12:59:14 PM PDT 24 | 1469771954 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1278436602 | May 09 01:00:21 PM PDT 24 | May 09 01:00:26 PM PDT 24 | 115481854 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2977051049 | May 09 01:00:57 PM PDT 24 | May 09 01:01:07 PM PDT 24 | 2834374992 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.349127674 | May 09 01:00:33 PM PDT 24 | May 09 01:00:48 PM PDT 24 | 2351816323 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/39.xbar_error_random.596064165 | May 09 01:02:02 PM PDT 24 | May 09 01:02:10 PM PDT 24 | 434028801 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1043839807 | May 09 01:00:26 PM PDT 24 | May 09 01:00:32 PM PDT 24 | 76906360 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/22.xbar_error_random.862734187 | May 09 01:00:42 PM PDT 24 | May 09 01:00:55 PM PDT 24 | 1511963222 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/37.xbar_same_source.4064704175 | May 09 01:01:50 PM PDT 24 | May 09 01:01:57 PM PDT 24 | 225932044 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1969377880 | May 09 12:59:41 PM PDT 24 | May 09 12:59:50 PM PDT 24 | 1204744326 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1658428987 | May 09 01:00:11 PM PDT 24 | May 09 01:00:49 PM PDT 24 | 3076872854 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.28171660 | May 09 01:01:30 PM PDT 24 | May 09 01:01:43 PM PDT 24 | 5609921076 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/41.xbar_same_source.3394176067 | May 09 01:02:15 PM PDT 24 | May 09 01:02:23 PM PDT 24 | 65397743 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3011491833 | May 09 01:00:22 PM PDT 24 | May 09 01:00:45 PM PDT 24 | 4840764924 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.142903376 | May 09 12:59:44 PM PDT 24 | May 09 12:59:53 PM PDT 24 | 223547229 ps | ||
| T202 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3135631923 | May 09 12:59:51 PM PDT 24 | May 09 01:02:40 PM PDT 24 | 169373905281 ps | ||
| T7 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.4138920310 | May 09 01:01:42 PM PDT 24 | May 09 01:03:31 PM PDT 24 | 986975548 ps | ||
| T156 | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1786891376 | May 09 01:01:29 PM PDT 24 | May 09 01:01:41 PM PDT 24 | 749725094 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.642757588 | May 09 01:00:52 PM PDT 24 | May 09 01:00:57 PM PDT 24 | 56639278 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4097509713 | May 09 01:00:01 PM PDT 24 | May 09 01:00:13 PM PDT 24 | 1498269768 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3103970424 | May 09 01:01:40 PM PDT 24 | May 09 01:03:35 PM PDT 24 | 17975964914 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1039579460 | May 09 01:01:04 PM PDT 24 | May 09 01:01:08 PM PDT 24 | 11875878 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2868698414 | May 09 12:59:58 PM PDT 24 | May 09 01:00:05 PM PDT 24 | 27047603 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1038008421 | May 09 01:01:50 PM PDT 24 | May 09 01:02:07 PM PDT 24 | 4225275843 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1868933016 | May 09 01:00:21 PM PDT 24 | May 09 01:01:16 PM PDT 24 | 17175612605 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.737325665 | May 09 01:02:15 PM PDT 24 | May 09 01:02:26 PM PDT 24 | 69448288 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1784146172 | May 09 01:01:15 PM PDT 24 | May 09 01:01:31 PM PDT 24 | 6737194694 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/13.xbar_error_random.1170718491 | May 09 01:00:01 PM PDT 24 | May 09 01:00:15 PM PDT 24 | 6781110257 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.749179656 | May 09 01:02:14 PM PDT 24 | May 09 01:02:28 PM PDT 24 | 3372050932 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1177582939 | May 09 01:00:23 PM PDT 24 | May 09 01:00:34 PM PDT 24 | 132904962 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3524522789 | May 09 01:00:45 PM PDT 24 | May 09 01:00:51 PM PDT 24 | 193815542 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3058182959 | May 09 01:00:54 PM PDT 24 | May 09 01:01:14 PM PDT 24 | 1429399991 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2468762228 | May 09 01:02:02 PM PDT 24 | May 09 01:02:15 PM PDT 24 | 1313200673 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2691875939 | May 09 12:59:50 PM PDT 24 | May 09 12:59:54 PM PDT 24 | 9726125 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.302179638 | May 09 01:00:55 PM PDT 24 | May 09 01:01:05 PM PDT 24 | 525368855 ps | ||
| T152 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2772179008 | May 09 12:59:18 PM PDT 24 | May 09 12:59:29 PM PDT 24 | 2277953058 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/2.xbar_random.3438922801 | May 09 12:58:53 PM PDT 24 | May 09 12:59:00 PM PDT 24 | 343801576 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2713902117 | May 09 01:00:36 PM PDT 24 | May 09 01:00:51 PM PDT 24 | 8275378447 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/13.xbar_random.1923657750 | May 09 01:00:00 PM PDT 24 | May 09 01:00:06 PM PDT 24 | 93109014 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3551818413 | May 09 01:01:29 PM PDT 24 | May 09 01:01:37 PM PDT 24 | 85825641 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3058982551 | May 09 01:02:17 PM PDT 24 | May 09 01:02:56 PM PDT 24 | 316659099 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1198112896 | May 09 01:00:43 PM PDT 24 | May 09 01:02:46 PM PDT 24 | 4139304232 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.325793854 | May 09 12:59:18 PM PDT 24 | May 09 12:59:35 PM PDT 24 | 1162052737 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1992685939 | May 09 01:00:02 PM PDT 24 | May 09 01:04:27 PM PDT 24 | 46117788501 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1223423665 | May 09 01:02:38 PM PDT 24 | May 09 01:02:45 PM PDT 24 | 34836963 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.858302393 | May 09 01:00:55 PM PDT 24 | May 09 01:02:48 PM PDT 24 | 2053061590 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/49.xbar_same_source.2646235719 | May 09 01:02:38 PM PDT 24 | May 09 01:02:44 PM PDT 24 | 46293785 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3918193189 | May 09 12:59:51 PM PDT 24 | May 09 12:59:58 PM PDT 24 | 1002690538 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/35.xbar_smoke.2388464688 | May 09 01:01:41 PM PDT 24 | May 09 01:01:45 PM PDT 24 | 71249293 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3504060472 | May 09 01:02:03 PM PDT 24 | May 09 01:02:11 PM PDT 24 | 3571946533 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.250002283 | May 09 01:02:26 PM PDT 24 | May 09 01:02:47 PM PDT 24 | 3563837504 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/5.xbar_error_random.1337182597 | May 09 12:59:27 PM PDT 24 | May 09 12:59:36 PM PDT 24 | 1482169838 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.45015173 | May 09 01:00:19 PM PDT 24 | May 09 01:01:38 PM PDT 24 | 4298260507 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3258437724 | May 09 12:59:50 PM PDT 24 | May 09 01:00:02 PM PDT 24 | 77060913 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.176715805 | May 09 01:02:16 PM PDT 24 | May 09 01:02:21 PM PDT 24 | 21971259 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2373540710 | May 09 01:02:26 PM PDT 24 | May 09 01:03:28 PM PDT 24 | 11352605260 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3484767134 | May 09 01:01:43 PM PDT 24 | May 09 01:02:00 PM PDT 24 | 619847118 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1140193722 | May 09 01:01:41 PM PDT 24 | May 09 01:01:55 PM PDT 24 | 925325958 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3454041216 | May 09 01:02:02 PM PDT 24 | May 09 01:02:08 PM PDT 24 | 42903876 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2533437249 | May 09 01:00:34 PM PDT 24 | May 09 01:00:43 PM PDT 24 | 450816506 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1883546257 | May 09 01:01:04 PM PDT 24 | May 09 01:02:57 PM PDT 24 | 7055081906 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2469560647 | May 09 01:01:43 PM PDT 24 | May 09 01:01:54 PM PDT 24 | 1623732369 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/49.xbar_error_random.953525746 | May 09 01:02:45 PM PDT 24 | May 09 01:02:51 PM PDT 24 | 45546434 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1722539322 | May 09 01:00:22 PM PDT 24 | May 09 01:00:44 PM PDT 24 | 862396767 ps | ||
| T10 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.726876590 | May 09 01:00:47 PM PDT 24 | May 09 01:04:08 PM PDT 24 | 8506425278 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1915352959 | May 09 12:59:28 PM PDT 24 | May 09 12:59:31 PM PDT 24 | 16131984 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3955283035 | May 09 01:02:01 PM PDT 24 | May 09 01:05:18 PM PDT 24 | 48817179440 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2101595532 | May 09 12:59:40 PM PDT 24 | May 09 12:59:48 PM PDT 24 | 1138643082 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.4272287659 | May 09 12:59:58 PM PDT 24 | May 09 01:00:07 PM PDT 24 | 1037182094 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3727845251 | May 09 12:59:51 PM PDT 24 | May 09 12:59:56 PM PDT 24 | 64027959 ps | ||
| T147 | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.65643859 | May 09 01:00:54 PM PDT 24 | May 09 01:02:57 PM PDT 24 | 34500787795 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2973559420 | May 09 01:00:54 PM PDT 24 | May 09 01:02:43 PM PDT 24 | 26315182884 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3086963858 | May 09 12:58:45 PM PDT 24 | May 09 12:58:48 PM PDT 24 | 78998567 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3324213142 | May 09 12:59:28 PM PDT 24 | May 09 12:59:42 PM PDT 24 | 7236496771 ps | ||
| T116 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1031567501 | May 09 01:00:02 PM PDT 24 | May 09 01:01:02 PM PDT 24 | 680451826 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.806155625 | May 09 01:01:42 PM PDT 24 | May 09 01:03:25 PM PDT 24 | 4611511047 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2758117617 | May 09 01:01:50 PM PDT 24 | May 09 01:01:59 PM PDT 24 | 64511764 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1318088037 | May 09 01:02:14 PM PDT 24 | May 09 01:04:33 PM PDT 24 | 74051256161 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3797948388 | May 09 12:59:05 PM PDT 24 | May 09 12:59:16 PM PDT 24 | 903397483 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2783523843 | May 09 01:01:50 PM PDT 24 | May 09 01:02:01 PM PDT 24 | 3262044610 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.724240411 | May 09 01:00:12 PM PDT 24 | May 09 01:00:20 PM PDT 24 | 522052132 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2048100005 | May 09 12:59:04 PM PDT 24 | May 09 12:59:16 PM PDT 24 | 553213013 ps | ||
| T105 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.687774216 | May 09 01:01:50 PM PDT 24 | May 09 01:02:41 PM PDT 24 | 9658716856 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.150313922 | May 09 01:01:50 PM PDT 24 | May 09 01:02:38 PM PDT 24 | 396676131 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1674497834 | May 09 01:02:33 PM PDT 24 | May 09 01:02:40 PM PDT 24 | 72722735 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.37546019 | May 09 01:01:30 PM PDT 24 | May 09 01:01:42 PM PDT 24 | 10585133699 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3093852000 | May 09 01:02:34 PM PDT 24 | May 09 01:02:45 PM PDT 24 | 94473926 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.860339704 | May 09 01:00:57 PM PDT 24 | May 09 01:02:37 PM PDT 24 | 34825818663 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3380556114 | May 09 01:02:36 PM PDT 24 | May 09 01:02:46 PM PDT 24 | 441941598 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3950133639 | May 09 01:01:15 PM PDT 24 | May 09 01:01:24 PM PDT 24 | 327880899 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3908836695 | May 09 01:00:45 PM PDT 24 | May 09 01:01:10 PM PDT 24 | 14887788231 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1822076410 | May 09 01:01:16 PM PDT 24 | May 09 01:01:32 PM PDT 24 | 2056767939 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2672858242 | May 09 01:01:14 PM PDT 24 | May 09 01:01:41 PM PDT 24 | 65591876 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/12.xbar_random.2745002103 | May 09 12:59:50 PM PDT 24 | May 09 12:59:54 PM PDT 24 | 15677200 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1703964228 | May 09 01:02:28 PM PDT 24 | May 09 01:02:30 PM PDT 24 | 9230501 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4134508399 | May 09 01:01:40 PM PDT 24 | May 09 01:01:46 PM PDT 24 | 40566985 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.4230972740 | May 09 12:58:53 PM PDT 24 | May 09 12:59:00 PM PDT 24 | 531571452 ps | ||
| T118 | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1755709447 | May 09 12:58:59 PM PDT 24 | May 09 01:01:36 PM PDT 24 | 44252917125 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3866073468 | May 09 01:02:13 PM PDT 24 | May 09 01:02:16 PM PDT 24 | 10633028 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3104576687 | May 09 01:01:32 PM PDT 24 | May 09 01:01:45 PM PDT 24 | 573876831 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.105917168 | May 09 01:01:52 PM PDT 24 | May 09 01:02:00 PM PDT 24 | 1079634634 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/42.xbar_random.3421992748 | May 09 01:02:14 PM PDT 24 | May 09 01:02:23 PM PDT 24 | 348742050 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2856143557 | May 09 01:00:01 PM PDT 24 | May 09 01:00:04 PM PDT 24 | 13403808 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/26.xbar_random.228846424 | May 09 01:01:07 PM PDT 24 | May 09 01:01:14 PM PDT 24 | 30365613 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2799725950 | May 09 01:00:11 PM PDT 24 | May 09 01:00:15 PM PDT 24 | 168837142 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/28.xbar_smoke.958163672 | May 09 01:01:20 PM PDT 24 | May 09 01:01:25 PM PDT 24 | 81264418 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/46.xbar_error_random.4040052800 | May 09 01:02:32 PM PDT 24 | May 09 01:02:38 PM PDT 24 | 49769661 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.635013015 | May 09 01:01:50 PM PDT 24 | May 09 01:01:53 PM PDT 24 | 11710469 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3649557421 | May 09 01:01:50 PM PDT 24 | May 09 01:03:57 PM PDT 24 | 5374854804 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3447892593 | May 09 01:02:32 PM PDT 24 | May 09 01:03:34 PM PDT 24 | 54635288568 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1279305118 | May 09 12:59:40 PM PDT 24 | May 09 12:59:51 PM PDT 24 | 4279421654 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3089876804 | May 09 01:02:16 PM PDT 24 | May 09 01:02:37 PM PDT 24 | 244118731 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.604329087 | May 09 01:01:49 PM PDT 24 | May 09 01:01:56 PM PDT 24 | 701960680 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1801697141 | May 09 01:00:22 PM PDT 24 | May 09 01:00:34 PM PDT 24 | 603253217 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2112953576 | May 09 01:01:16 PM PDT 24 | May 09 01:01:39 PM PDT 24 | 167146408 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2949670767 | May 09 12:58:42 PM PDT 24 | May 09 01:01:22 PM PDT 24 | 21624650386 ps | ||
| T106 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3471105715 | May 09 01:01:04 PM PDT 24 | May 09 01:06:14 PM PDT 24 | 46891982998 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2876126089 | May 09 01:01:42 PM PDT 24 | May 09 01:02:05 PM PDT 24 | 3625988531 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.910288390 | May 09 01:01:14 PM PDT 24 | May 09 01:01:55 PM PDT 24 | 2649109666 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2351015213 | May 09 01:00:29 PM PDT 24 | May 09 01:00:36 PM PDT 24 | 24236824 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1584686169 | May 09 12:59:43 PM PDT 24 | May 09 12:59:52 PM PDT 24 | 1033150831 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3499953368 | May 09 01:00:19 PM PDT 24 | May 09 01:05:55 PM PDT 24 | 63820488534 ps | ||
| T117 | /workspace/coverage/xbar_build_mode/16.xbar_random.3824843730 | May 09 01:00:21 PM PDT 24 | May 09 01:00:27 PM PDT 24 | 552169976 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4109494153 | May 09 12:59:30 PM PDT 24 | May 09 01:00:34 PM PDT 24 | 3662429103 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1570434449 | May 09 01:01:18 PM PDT 24 | May 09 01:01:31 PM PDT 24 | 434799102 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.517663963 | May 09 01:02:13 PM PDT 24 | May 09 01:02:26 PM PDT 24 | 4244788819 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1949307564 | May 09 01:01:03 PM PDT 24 | May 09 01:01:09 PM PDT 24 | 43052607 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.658862177 | May 09 01:00:52 PM PDT 24 | May 09 01:01:01 PM PDT 24 | 897696455 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1309420344 | May 09 12:59:06 PM PDT 24 | May 09 12:59:10 PM PDT 24 | 89567874 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3788716866 | May 09 01:00:21 PM PDT 24 | May 09 01:00:36 PM PDT 24 | 2486247248 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1667378767 | May 09 01:02:03 PM PDT 24 | May 09 01:02:09 PM PDT 24 | 20483107 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3089067995 | May 09 01:02:36 PM PDT 24 | May 09 01:07:27 PM PDT 24 | 45580802011 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3722757755 | May 09 01:01:02 PM PDT 24 | May 09 01:02:02 PM PDT 24 | 306037539 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.495731143 | May 09 01:02:15 PM PDT 24 | May 09 01:02:23 PM PDT 24 | 1671712802 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1226389422 | May 09 01:00:42 PM PDT 24 | May 09 01:01:34 PM PDT 24 | 22093270935 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.49005944 | May 09 01:00:26 PM PDT 24 | May 09 01:00:38 PM PDT 24 | 3309816605 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2825755629 | May 09 01:02:14 PM PDT 24 | May 09 01:02:46 PM PDT 24 | 12864999080 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1346558788 | May 09 12:58:52 PM PDT 24 | May 09 12:59:57 PM PDT 24 | 11655903671 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.766818950 | May 09 01:01:54 PM PDT 24 | May 09 01:01:59 PM PDT 24 | 63830103 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1631054192 | May 09 03:33:08 PM PDT 24 | May 09 03:33:25 PM PDT 24 | 3322304243 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1204405113 | May 09 01:00:54 PM PDT 24 | May 09 01:02:09 PM PDT 24 | 3227559363 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1416291830 | May 09 12:59:30 PM PDT 24 | May 09 01:01:55 PM PDT 24 | 123581800528 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2554219434 | May 09 01:02:33 PM PDT 24 | May 09 01:02:36 PM PDT 24 | 13702819 ps |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3304010713 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1556497952 ps |
| CPU time | 13.34 seconds |
| Started | May 09 01:00:47 PM PDT 24 |
| Finished | May 09 01:01:01 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-a6572eb2-4dbc-42ba-98fe-926e5d3e0aef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3304010713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3304010713 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3301841738 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 45784891575 ps |
| CPU time | 355.23 seconds |
| Started | May 09 01:02:12 PM PDT 24 |
| Finished | May 09 01:08:09 PM PDT 24 |
| Peak memory | 203904 kb |
| Host | smart-30bbe844-6fe2-4c96-a8c9-5af211500b93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3301841738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3301841738 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1300647980 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 45959653881 ps |
| CPU time | 334.16 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 01:05:06 PM PDT 24 |
| Peak memory | 203024 kb |
| Host | smart-c09ca255-f7d6-49d8-95f3-cffe2c2b5769 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1300647980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.1300647980 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1964863538 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 115678936824 ps |
| CPU time | 287.07 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 01:03:40 PM PDT 24 |
| Peak memory | 203604 kb |
| Host | smart-ab27750f-10a3-4b2a-bf2a-1228a4fdb81c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1964863538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1964863538 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3537922813 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 67637674082 ps |
| CPU time | 238.35 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:06:37 PM PDT 24 |
| Peak memory | 203096 kb |
| Host | smart-648aa49d-98e9-427b-9086-650dc508e3be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3537922813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.3537922813 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3376300877 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 471978893 ps |
| CPU time | 63.36 seconds |
| Started | May 09 12:59:33 PM PDT 24 |
| Finished | May 09 01:00:38 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-08892059-4372-41b9-8f84-99a913934a52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3376300877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3376300877 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1467280540 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 226166894084 ps |
| CPU time | 259.09 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:06:35 PM PDT 24 |
| Peak memory | 203676 kb |
| Host | smart-a424c6b7-993b-4b3e-be36-f0aebf6a3576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1467280540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1467280540 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2845747910 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 27681749286 ps |
| CPU time | 114.4 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:03:16 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-2626aca1-00c7-4ea9-8835-a62c9d08210e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845747910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2845747910 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4133641557 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9702315308 ps |
| CPU time | 157.47 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:03:43 PM PDT 24 |
| Peak memory | 207188 kb |
| Host | smart-6a2532f7-6167-43fc-94e0-c86f641ef557 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4133641557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.4133641557 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2659080136 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 12236202995 ps |
| CPU time | 83.76 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 01:00:19 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-8fd42bb7-fc10-467e-93b6-3e5dd77bd88e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2659080136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2659080136 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.769822104 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 727354077 ps |
| CPU time | 115.52 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-5c299abe-3f73-4bf0-9579-2d6e04d28d13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=769822104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.769822104 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2714584073 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5672441764 ps |
| CPU time | 119.5 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 01:01:44 PM PDT 24 |
| Peak memory | 205052 kb |
| Host | smart-be114885-b935-423c-a271-8634fdb669a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2714584073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2714584073 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3569445891 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 166720412 ps |
| CPU time | 35.38 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 204052 kb |
| Host | smart-1c946d39-093e-4f47-9b53-5a193452aa9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569445891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3569445891 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.4138920310 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 986975548 ps |
| CPU time | 105.3 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:03:31 PM PDT 24 |
| Peak memory | 205272 kb |
| Host | smart-bb258a30-800e-497f-8857-b73939816ab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4138920310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.4138920310 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2806977050 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 45796197523 ps |
| CPU time | 286.04 seconds |
| Started | May 09 01:02:25 PM PDT 24 |
| Finished | May 09 01:07:12 PM PDT 24 |
| Peak memory | 203040 kb |
| Host | smart-c7f08da8-1dce-4384-8392-44c0fb2ae0e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2806977050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2806977050 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.930814531 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7482028434 ps |
| CPU time | 92.35 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:01:16 PM PDT 24 |
| Peak memory | 205432 kb |
| Host | smart-76524e7a-e988-4f14-826a-3fbca8939c91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930814531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.930814531 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2056593826 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4171435397 ps |
| CPU time | 76.69 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:01:52 PM PDT 24 |
| Peak memory | 203088 kb |
| Host | smart-127a40aa-83ba-4a82-8b4b-f3f1dd244a83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2056593826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2056593826 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.89168367 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 30891885487 ps |
| CPU time | 146.75 seconds |
| Started | May 09 12:59:20 PM PDT 24 |
| Finished | May 09 01:01:48 PM PDT 24 |
| Peak memory | 203096 kb |
| Host | smart-82e613d6-f0cc-414b-ac4b-3b1b23508ae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=89168367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.89168367 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.363383701 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 6778987610 ps |
| CPU time | 117.8 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 01:01:32 PM PDT 24 |
| Peak memory | 204884 kb |
| Host | smart-058c1d1e-b126-4571-8fbf-a40024ac7ac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=363383701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.363383701 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4224104161 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 61057991 ps |
| CPU time | 8.53 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:33 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-219f8633-00b9-4ebd-be81-c1d9358b322d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224104161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4224104161 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3026576221 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 471583143 ps |
| CPU time | 40.13 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:02:25 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-f7048a8b-4264-47f3-b5c3-0176c4e1be05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026576221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3026576221 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3417069517 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1072467496 ps |
| CPU time | 111.13 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 01:01:44 PM PDT 24 |
| Peak memory | 205040 kb |
| Host | smart-c0e0a37a-b5ae-4a04-8e1f-73a4ed69b33a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417069517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3417069517 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3471105715 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 46891982998 ps |
| CPU time | 307.86 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:06:14 PM PDT 24 |
| Peak memory | 203748 kb |
| Host | smart-86f5971e-34be-4133-80f7-3b7c5792a95e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3471105715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3471105715 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2222396246 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 918216269 ps |
| CPU time | 5.65 seconds |
| Started | May 09 12:59:43 PM PDT 24 |
| Finished | May 09 12:59:51 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-aaca12bc-5b31-47bc-8e4b-3e112a86f8c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2222396246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2222396246 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2203807292 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 177153892224 ps |
| CPU time | 136.07 seconds |
| Started | May 09 12:59:59 PM PDT 24 |
| Finished | May 09 01:02:18 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-d3deaeb5-6b16-4f53-ada7-a10ebba44329 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2203807292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2203807292 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2166794513 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 374593299 ps |
| CPU time | 4.4 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 12:58:50 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-67a808db-f06a-4399-8662-4a4130cacfc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2166794513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2166794513 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2949670767 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 21624650386 ps |
| CPU time | 158.82 seconds |
| Started | May 09 12:58:42 PM PDT 24 |
| Finished | May 09 01:01:22 PM PDT 24 |
| Peak memory | 203152 kb |
| Host | smart-0c3e7bcb-6382-4455-96c4-420b8951be2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2949670767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2949670767 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.682263115 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 235553767 ps |
| CPU time | 4.34 seconds |
| Started | May 09 12:58:42 PM PDT 24 |
| Finished | May 09 12:58:48 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-6828f461-4ccd-4ded-9131-a042c2b2a0c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682263115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.682263115 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.2158812620 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1187587222 ps |
| CPU time | 12.64 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 12:58:59 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-59d6e885-616e-427c-9457-59780ef421c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2158812620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2158812620 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.1170414836 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 127190021 ps |
| CPU time | 6.14 seconds |
| Started | May 09 12:58:42 PM PDT 24 |
| Finished | May 09 12:58:49 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-c1016701-cc66-4a8d-894e-75b5471d7ebb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1170414836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1170414836 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2705284445 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 65849940138 ps |
| CPU time | 106.08 seconds |
| Started | May 09 12:58:41 PM PDT 24 |
| Finished | May 09 01:00:29 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-1f0d3d50-9442-4230-8169-ef99b7104884 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705284445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2705284445 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3885676779 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 15184577012 ps |
| CPU time | 102.39 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 01:00:28 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-cd7cbbf9-fc0b-4cbe-8336-13cfb61a9756 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3885676779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3885676779 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2373247507 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 75521713 ps |
| CPU time | 6.62 seconds |
| Started | May 09 12:58:41 PM PDT 24 |
| Finished | May 09 12:58:48 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-9ed9c0cc-0ece-4ea3-9c43-421e0e703d4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373247507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2373247507 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.4044805800 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 82640631 ps |
| CPU time | 5.36 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 12:58:51 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-0da33e1e-23cb-452a-b2dd-5f2c959a9396 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4044805800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4044805800 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3086963858 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 78998567 ps |
| CPU time | 1.76 seconds |
| Started | May 09 12:58:45 PM PDT 24 |
| Finished | May 09 12:58:48 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-cc5b49ba-63eb-4687-a5c5-815512e4c201 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3086963858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3086963858 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3891816106 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1989478217 ps |
| CPU time | 6.2 seconds |
| Started | May 09 12:58:45 PM PDT 24 |
| Finished | May 09 12:58:53 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-83de956c-2397-4ecb-a6e7-a4cebbe8f98d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891816106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3891816106 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3535571196 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1614031343 ps |
| CPU time | 10.34 seconds |
| Started | May 09 12:58:45 PM PDT 24 |
| Finished | May 09 12:58:57 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-ade0dc9b-9da8-4885-b79c-c3b8d0d44cb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3535571196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3535571196 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2393293778 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 23398061 ps |
| CPU time | 1.14 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 12:58:46 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-fc946dff-16a7-41d3-8375-78fee4425959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393293778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2393293778 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3232518290 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 332088614 ps |
| CPU time | 17.33 seconds |
| Started | May 09 12:58:41 PM PDT 24 |
| Finished | May 09 12:58:59 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-9eb40459-e330-460f-9060-01b36c614f3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3232518290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3232518290 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2050153504 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2741913065 ps |
| CPU time | 39.3 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 12:59:25 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-940555af-00c6-4c4c-8739-9b2cde32c98c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2050153504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2050153504 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1252028965 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 9768105570 ps |
| CPU time | 48.98 seconds |
| Started | May 09 12:58:42 PM PDT 24 |
| Finished | May 09 12:59:33 PM PDT 24 |
| Peak memory | 204000 kb |
| Host | smart-1b11c280-89c2-4d17-823c-e7fd1c598215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1252028965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1252028965 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.827232747 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 624793512 ps |
| CPU time | 45.05 seconds |
| Started | May 09 12:58:41 PM PDT 24 |
| Finished | May 09 12:59:27 PM PDT 24 |
| Peak memory | 203728 kb |
| Host | smart-c6c42b0b-db00-44c6-83b6-96ecd409cd57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827232747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.827232747 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.194335347 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1445414796 ps |
| CPU time | 10.94 seconds |
| Started | May 09 12:58:43 PM PDT 24 |
| Finished | May 09 12:58:55 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-06debfcc-b9b5-444f-82f1-b0c209d4ae30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194335347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.194335347 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1529107524 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1469771954 ps |
| CPU time | 19.78 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 12:59:14 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-08500982-a795-4305-9504-af8a1cb8b2f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1529107524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1529107524 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1844531883 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 572212317 ps |
| CPU time | 9.59 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 12:59:05 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-f77ba035-5e35-4c88-a35e-86207c08f90d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1844531883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1844531883 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.1337904064 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 113371209 ps |
| CPU time | 2.99 seconds |
| Started | May 09 12:58:59 PM PDT 24 |
| Finished | May 09 12:59:04 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-54f8bba8-6ea2-468e-a0dd-540ba78d4388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337904064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1337904064 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.1004172760 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 684266182 ps |
| CPU time | 11.31 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 12:59:04 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-fcee298b-0581-44eb-a34b-3def5121e2d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1004172760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1004172760 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.386236276 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 66334106819 ps |
| CPU time | 129.48 seconds |
| Started | May 09 12:58:54 PM PDT 24 |
| Finished | May 09 01:01:05 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-6881943d-f07d-4044-b098-897a9b8387a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=386236276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.386236276 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1346558788 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 11655903671 ps |
| CPU time | 63.11 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 12:59:57 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-619531ae-9a85-4c2f-a6b1-dd0f26937778 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1346558788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1346558788 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1869737120 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 89565522 ps |
| CPU time | 5.39 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 12:59:01 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-24f7aabe-a41f-4a33-bd0e-57d235e5ceb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869737120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1869737120 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2683100162 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 78357170 ps |
| CPU time | 2.67 seconds |
| Started | May 09 12:58:54 PM PDT 24 |
| Finished | May 09 12:58:59 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-1e85f86e-b67d-4e69-b0ee-73b2e2d690e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2683100162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2683100162 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.2685591578 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 10372114 ps |
| CPU time | 1.17 seconds |
| Started | May 09 12:58:45 PM PDT 24 |
| Finished | May 09 12:58:48 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-b053fdac-b117-44c1-a394-ff35b4030a05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2685591578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2685591578 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1753879392 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2424230740 ps |
| CPU time | 8.25 seconds |
| Started | May 09 12:58:44 PM PDT 24 |
| Finished | May 09 12:58:53 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-1edbf5fa-65b8-4a04-bfb7-d25d169b87e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753879392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1753879392 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3791995253 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1738675138 ps |
| CPU time | 7.96 seconds |
| Started | May 09 12:58:42 PM PDT 24 |
| Finished | May 09 12:58:51 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-1e9b05fd-2748-4ed8-8f6d-60d07e91ffe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3791995253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3791995253 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4125560867 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8710578 ps |
| CPU time | 1.17 seconds |
| Started | May 09 12:58:43 PM PDT 24 |
| Finished | May 09 12:58:46 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-3fc4b825-4488-488a-a5e2-de593221f99a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125560867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4125560867 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2876864692 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 91883300 ps |
| CPU time | 6.1 seconds |
| Started | May 09 12:59:00 PM PDT 24 |
| Finished | May 09 12:59:07 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-37fcd997-f952-417f-9077-4ce42c486961 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2876864692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2876864692 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4076795721 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1907106410 ps |
| CPU time | 24.69 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 12:59:19 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-c6aaf678-0839-49dd-878f-8aeca4f48a2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4076795721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4076795721 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1456903467 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 26694467559 ps |
| CPU time | 115.18 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 205452 kb |
| Host | smart-96d1f1d5-7b7b-4888-a105-f67f231f639a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456903467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1456903467 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.651226804 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 628196509 ps |
| CPU time | 50.2 seconds |
| Started | May 09 12:58:54 PM PDT 24 |
| Finished | May 09 12:59:46 PM PDT 24 |
| Peak memory | 205032 kb |
| Host | smart-a9ae2dcc-f24a-40e0-b014-0dca029c5e89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=651226804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.651226804 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1431164305 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3219916753 ps |
| CPU time | 12.05 seconds |
| Started | May 09 12:58:55 PM PDT 24 |
| Finished | May 09 12:59:09 PM PDT 24 |
| Peak memory | 202104 kb |
| Host | smart-3a3a1ba5-84c4-4624-97b3-f63346769b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1431164305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1431164305 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.142903376 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 223547229 ps |
| CPU time | 7.15 seconds |
| Started | May 09 12:59:44 PM PDT 24 |
| Finished | May 09 12:59:53 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-c58eeebd-9ff2-4e89-a785-49710adca347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=142903376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.142903376 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.395966756 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 57740501048 ps |
| CPU time | 145.96 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:02:09 PM PDT 24 |
| Peak memory | 203088 kb |
| Host | smart-59874feb-2f90-452b-91cb-7246484e2154 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=395966756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo w_rsp.395966756 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3658239108 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 430101537 ps |
| CPU time | 8.38 seconds |
| Started | May 09 12:59:55 PM PDT 24 |
| Finished | May 09 01:00:05 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-6c00b3eb-4d1d-43c6-bf81-f49ae3532468 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3658239108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3658239108 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.4104833415 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 676525108 ps |
| CPU time | 10.35 seconds |
| Started | May 09 12:59:39 PM PDT 24 |
| Finished | May 09 12:59:52 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-611b6052-e69e-44bc-8687-fa3bb4847108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104833415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4104833415 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.1938532702 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 809871064 ps |
| CPU time | 12.26 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:56 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-ca4b8384-0817-4dbe-a12f-00532e784b53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1938532702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1938532702 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1943403695 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 66640343779 ps |
| CPU time | 142.54 seconds |
| Started | May 09 12:59:39 PM PDT 24 |
| Finished | May 09 01:02:03 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-3832de04-d030-4c68-a31e-3141d458035c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943403695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1943403695 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2972579788 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 8502156011 ps |
| CPU time | 31.93 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 01:00:17 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-7723d0c8-1dac-4d5e-b3c4-8dd1d99c575a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2972579788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2972579788 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3193481925 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 61309966 ps |
| CPU time | 4.89 seconds |
| Started | May 09 12:59:43 PM PDT 24 |
| Finished | May 09 12:59:51 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-7d69f446-712d-4472-be6f-e8a9f34117df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193481925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3193481925 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1287160224 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 19317242 ps |
| CPU time | 2.26 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 12:59:46 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-dc801d9e-48b9-487b-88b9-e1e31a1de6af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1287160224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1287160224 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.454225399 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 138383213 ps |
| CPU time | 1.4 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:45 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-605ac61f-a744-4b21-abe4-4b2513f059d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=454225399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.454225399 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.500364022 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 12438862706 ps |
| CPU time | 10.17 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:54 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-dacd3bdc-98dd-403e-8c2b-a8bad91f0dea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=500364022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.500364022 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3500164233 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 14563483 ps |
| CPU time | 1.03 seconds |
| Started | May 09 12:59:39 PM PDT 24 |
| Finished | May 09 12:59:41 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-01e03c2f-abec-43e6-838e-c80c9e6fee42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500164233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3500164233 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1758615203 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4982481405 ps |
| CPU time | 84.75 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 01:01:16 PM PDT 24 |
| Peak memory | 203036 kb |
| Host | smart-cc521cc6-105b-471f-8842-7c10fcf3d703 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758615203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1758615203 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1785351635 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 10632476403 ps |
| CPU time | 44.71 seconds |
| Started | May 09 12:59:57 PM PDT 24 |
| Finished | May 09 01:00:43 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-bbeced0a-8a32-4e93-a775-48e7eade079b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1785351635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1785351635 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3248646604 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 399337060 ps |
| CPU time | 43.44 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 01:00:35 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-81d6601d-3894-4dd6-a15b-5a3be6f530d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3248646604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3248646604 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.975418810 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 72075883 ps |
| CPU time | 3.67 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 12:59:59 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-322450e2-113f-4f5d-a417-4aead762ee30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=975418810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.975418810 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3859679832 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2533127541 ps |
| CPU time | 10.08 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 01:00:05 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-eb4b44db-ef64-4965-8f4f-21a3d2ded7a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859679832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3859679832 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3951425849 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 25503290552 ps |
| CPU time | 75.92 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-30b4c3e4-b936-4bab-b78a-9b1367309360 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3951425849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3951425849 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.806286627 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 71308838 ps |
| CPU time | 5.19 seconds |
| Started | May 09 12:59:53 PM PDT 24 |
| Finished | May 09 01:00:00 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-673644f3-1478-4ad0-abf5-10f3d25199df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=806286627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.806286627 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3727845251 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 64027959 ps |
| CPU time | 1.56 seconds |
| Started | May 09 12:59:51 PM PDT 24 |
| Finished | May 09 12:59:56 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-cf2dd45f-68d1-412e-933a-35b4a6a3b92f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3727845251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3727845251 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.854182864 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 672564276 ps |
| CPU time | 10.3 seconds |
| Started | May 09 12:59:51 PM PDT 24 |
| Finished | May 09 01:00:04 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-8a28ec9a-ce4f-4dc3-8ddc-5ab45a1c7a3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=854182864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.854182864 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1092106259 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 6996254904 ps |
| CPU time | 16.73 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 01:00:11 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-bdb12009-1ce4-400a-a596-b68a8e85f531 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092106259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1092106259 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4061065428 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1546781923 ps |
| CPU time | 4.17 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 12:59:56 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-eb3f4daf-dba9-4cd9-963f-5e8acb06126e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4061065428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4061065428 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2825163537 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 325288719 ps |
| CPU time | 6.39 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 12:59:57 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-c89f2340-18f0-4e72-8b7d-160188dc3d92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825163537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2825163537 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3094996520 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 61752535 ps |
| CPU time | 3.63 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 12:59:56 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-4a56921e-413e-417e-a52c-180337bddf53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094996520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3094996520 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3395055691 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 90936525 ps |
| CPU time | 1.55 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 12:59:56 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-b81b4194-a94d-49bb-88c0-ff8e49aa6745 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3395055691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3395055691 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1815225987 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2405505430 ps |
| CPU time | 10.43 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-5c4a5ea2-90e9-40b0-b3a7-39c7a296212f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815225987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1815225987 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.469951356 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 961200197 ps |
| CPU time | 7.96 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 01:00:00 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-4908eac8-434a-465f-bc6c-3dadcb26fc83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=469951356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.469951356 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3807563782 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 12649234 ps |
| CPU time | 1.15 seconds |
| Started | May 09 12:59:48 PM PDT 24 |
| Finished | May 09 12:59:52 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-8918d3a1-f351-43f0-bd2e-c3e42d46069d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807563782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3807563782 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3258437724 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 77060913 ps |
| CPU time | 8.5 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 01:00:02 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-305a9fba-fd64-4fc5-92df-407652ab6c72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258437724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3258437724 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1467878369 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 313287441 ps |
| CPU time | 36.62 seconds |
| Started | May 09 12:59:51 PM PDT 24 |
| Finished | May 09 01:00:30 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-db19b474-ad46-444c-800d-166448cb0807 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467878369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1467878369 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.593513915 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1439759785 ps |
| CPU time | 101.93 seconds |
| Started | May 09 12:59:56 PM PDT 24 |
| Finished | May 09 01:01:39 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-87dd6fd5-7857-49ff-8f6b-b177c805201a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=593513915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.593513915 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1896381117 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 980225813 ps |
| CPU time | 35.37 seconds |
| Started | May 09 12:59:51 PM PDT 24 |
| Finished | May 09 01:00:29 PM PDT 24 |
| Peak memory | 203640 kb |
| Host | smart-80ac73ff-0764-48a5-974f-88dab9ee8d4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1896381117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1896381117 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.4271628339 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 812527107 ps |
| CPU time | 5.25 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 12:59:58 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-ede9e7be-7b7d-4265-a407-926863a12fe4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271628339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.4271628339 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3918193189 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1002690538 ps |
| CPU time | 4.56 seconds |
| Started | May 09 12:59:51 PM PDT 24 |
| Finished | May 09 12:59:58 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-b5e62fe4-ac60-42f3-9f81-d1768d128209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918193189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3918193189 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3135631923 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 169373905281 ps |
| CPU time | 166.01 seconds |
| Started | May 09 12:59:51 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 203288 kb |
| Host | smart-6f89ada2-8708-457b-ab9d-68275d56a2a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3135631923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.3135631923 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4097509713 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1498269768 ps |
| CPU time | 9.48 seconds |
| Started | May 09 01:00:01 PM PDT 24 |
| Finished | May 09 01:00:13 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-ccf1e61e-954d-40aa-b461-657fc2300eef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4097509713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4097509713 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1436943468 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 22934249 ps |
| CPU time | 1.57 seconds |
| Started | May 09 12:59:55 PM PDT 24 |
| Finished | May 09 12:59:58 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-a3b3f47b-d195-4f82-8aec-5d0ee4c2a62e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1436943468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1436943468 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2745002103 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 15677200 ps |
| CPU time | 1.64 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 12:59:54 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-87eaff15-119e-429a-81fb-bdb87a190efb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2745002103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2745002103 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.572893887 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 22407378222 ps |
| CPU time | 20.56 seconds |
| Started | May 09 12:59:55 PM PDT 24 |
| Finished | May 09 01:00:17 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-22d6f65c-66c7-463c-82ac-984600f9d602 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=572893887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.572893887 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.416510072 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 11266251000 ps |
| CPU time | 26.53 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 01:00:21 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-6e92f509-c307-4b4a-871b-50e31438c943 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=416510072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.416510072 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2789032624 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 60424514 ps |
| CPU time | 8.52 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 01:00:00 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-fa1d6466-c915-486d-9903-cb362c2d8fbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789032624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2789032624 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.2962190911 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5021010994 ps |
| CPU time | 10.95 seconds |
| Started | May 09 12:59:49 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-774d5225-c1d5-404a-b913-5e0d47c00deb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2962190911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2962190911 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.284845274 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 94411400 ps |
| CPU time | 1.49 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 12:59:54 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-556b2273-7067-458f-a2c5-8553b0532151 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=284845274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.284845274 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1073638005 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3876610170 ps |
| CPU time | 11.23 seconds |
| Started | May 09 12:59:57 PM PDT 24 |
| Finished | May 09 01:00:09 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-975222bd-3558-49b4-b873-93f4b471a408 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073638005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1073638005 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1393980365 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6473959204 ps |
| CPU time | 7.85 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-87d433c6-2e89-4d13-bba6-20a2062863f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1393980365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1393980365 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2691875939 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 9726125 ps |
| CPU time | 1.17 seconds |
| Started | May 09 12:59:50 PM PDT 24 |
| Finished | May 09 12:59:54 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-d44aea25-6a68-4bef-9955-78173152fc7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691875939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2691875939 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3760472955 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3430847219 ps |
| CPU time | 40.54 seconds |
| Started | May 09 01:00:02 PM PDT 24 |
| Finished | May 09 01:00:44 PM PDT 24 |
| Peak memory | 203248 kb |
| Host | smart-79ab558e-2dd3-4159-a7f0-1474adec974b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3760472955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3760472955 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1369104511 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1806304942 ps |
| CPU time | 27.14 seconds |
| Started | May 09 01:00:01 PM PDT 24 |
| Finished | May 09 01:00:30 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-13ccab02-4cc2-4b18-8817-e748c59d091d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1369104511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1369104511 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3991524742 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 246507870 ps |
| CPU time | 34.97 seconds |
| Started | May 09 01:00:01 PM PDT 24 |
| Finished | May 09 01:00:38 PM PDT 24 |
| Peak memory | 204204 kb |
| Host | smart-ac5bce3d-5e41-4822-8c62-196b692a6312 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3991524742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3991524742 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.987422158 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 870891808 ps |
| CPU time | 149.64 seconds |
| Started | May 09 01:00:02 PM PDT 24 |
| Finished | May 09 01:02:33 PM PDT 24 |
| Peak memory | 208812 kb |
| Host | smart-5663971a-9a83-4f55-9b58-411dc6885d4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987422158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.987422158 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1086225997 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 40946316 ps |
| CPU time | 3.85 seconds |
| Started | May 09 12:59:52 PM PDT 24 |
| Finished | May 09 12:59:58 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-31992f63-5403-4b43-98b9-4fc7fd14e2a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1086225997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1086225997 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2868698414 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 27047603 ps |
| CPU time | 5.08 seconds |
| Started | May 09 12:59:58 PM PDT 24 |
| Finished | May 09 01:00:05 PM PDT 24 |
| Peak memory | 201932 kb |
| Host | smart-9ce2bfe2-e9be-4ca8-a7f3-fecb6eee63bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2868698414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2868698414 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1722962799 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 41289260747 ps |
| CPU time | 180.29 seconds |
| Started | May 09 01:00:05 PM PDT 24 |
| Finished | May 09 01:03:06 PM PDT 24 |
| Peak memory | 203036 kb |
| Host | smart-c54bc62d-9673-49b1-8a59-83d56ed21daa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1722962799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1722962799 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1065764563 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 251822393 ps |
| CPU time | 2.5 seconds |
| Started | May 09 12:59:58 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-87b05054-42f0-447c-8f6d-e54c8a393f4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1065764563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1065764563 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.1170718491 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 6781110257 ps |
| CPU time | 12.14 seconds |
| Started | May 09 01:00:01 PM PDT 24 |
| Finished | May 09 01:00:15 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-04be2dcd-ab62-42ed-a62b-70aab4c60f40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1170718491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1170718491 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.1923657750 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 93109014 ps |
| CPU time | 4.36 seconds |
| Started | May 09 01:00:00 PM PDT 24 |
| Finished | May 09 01:00:06 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-49d6eaae-a790-4ce8-8280-5fcee4f3a80b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1923657750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1923657750 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.4101126376 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 30746724668 ps |
| CPU time | 64.62 seconds |
| Started | May 09 12:59:59 PM PDT 24 |
| Finished | May 09 01:01:06 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-22ec54e4-f3d4-4604-8a81-470cec15ec56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101126376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4101126376 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1235020160 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 40561759 ps |
| CPU time | 3.26 seconds |
| Started | May 09 12:59:58 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-6ac8542b-2dc4-4937-b063-374430048aa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235020160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1235020160 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.3305259271 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 57286436 ps |
| CPU time | 2.76 seconds |
| Started | May 09 01:00:00 PM PDT 24 |
| Finished | May 09 01:00:05 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-0a57a018-2ee9-45fa-9837-9d5047d89910 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305259271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3305259271 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.395535951 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 71409686 ps |
| CPU time | 1.5 seconds |
| Started | May 09 12:59:58 PM PDT 24 |
| Finished | May 09 01:00:02 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-ad22037f-d96b-4459-a8dc-d31cdd6641d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=395535951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.395535951 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2306811931 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1451110919 ps |
| CPU time | 7.54 seconds |
| Started | May 09 12:59:58 PM PDT 24 |
| Finished | May 09 01:00:08 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-b9972413-3e14-4328-a8e9-e60d20f22f7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306811931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2306811931 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3825680185 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1068889983 ps |
| CPU time | 7.78 seconds |
| Started | May 09 12:59:57 PM PDT 24 |
| Finished | May 09 01:00:07 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-ed7bc100-80fd-4b16-837d-db5d0fae2c70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3825680185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3825680185 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1681684554 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 11301883 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:00:00 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-7e316f62-7e0a-44b5-9334-ff9c708fc21e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681684554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1681684554 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2246766555 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2445141650 ps |
| CPU time | 26.8 seconds |
| Started | May 09 12:59:59 PM PDT 24 |
| Finished | May 09 01:00:28 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-b027e6f2-09c1-44e6-b4f6-b5c28d468d27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2246766555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2246766555 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1907510700 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1021271345 ps |
| CPU time | 16.88 seconds |
| Started | May 09 01:00:04 PM PDT 24 |
| Finished | May 09 01:00:22 PM PDT 24 |
| Peak memory | 201748 kb |
| Host | smart-f2f89acb-fabe-49de-9a23-f5848e47093f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1907510700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1907510700 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1031567501 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 680451826 ps |
| CPU time | 58.6 seconds |
| Started | May 09 01:00:02 PM PDT 24 |
| Finished | May 09 01:01:02 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-8799a21c-40ae-49ba-93f5-503d24af6844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1031567501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1031567501 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1411648906 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1514246627 ps |
| CPU time | 135.17 seconds |
| Started | May 09 01:00:04 PM PDT 24 |
| Finished | May 09 01:02:20 PM PDT 24 |
| Peak memory | 206616 kb |
| Host | smart-24dfa810-1d5d-48bd-b0b4-3d93fecac8d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1411648906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1411648906 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1607587223 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 166207043 ps |
| CPU time | 2.94 seconds |
| Started | May 09 01:00:02 PM PDT 24 |
| Finished | May 09 01:00:07 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-25f6ece4-3f38-4e32-8607-00647e5d779b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1607587223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1607587223 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.542931854 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 815829728 ps |
| CPU time | 3.64 seconds |
| Started | May 09 12:59:59 PM PDT 24 |
| Finished | May 09 01:00:05 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-f1b357b3-9829-469a-8686-edb55d5394fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=542931854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.542931854 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1992685939 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 46117788501 ps |
| CPU time | 262.83 seconds |
| Started | May 09 01:00:02 PM PDT 24 |
| Finished | May 09 01:04:27 PM PDT 24 |
| Peak memory | 202996 kb |
| Host | smart-b7e50321-e4d7-4197-a5d1-d715a36b7da7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1992685939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1992685939 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1868551429 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 33230407 ps |
| CPU time | 3.05 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:00:17 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-f39b9378-b98a-4c37-9b49-dc51e406037f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868551429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1868551429 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.1274612323 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2936046143 ps |
| CPU time | 9.01 seconds |
| Started | May 09 01:00:09 PM PDT 24 |
| Finished | May 09 01:00:20 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-de43882c-7bf2-491e-a7fb-778335db770f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1274612323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1274612323 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1700102537 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3510463210 ps |
| CPU time | 8.37 seconds |
| Started | May 09 01:00:02 PM PDT 24 |
| Finished | May 09 01:00:12 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-6d54a832-c8db-452e-8eb1-cc7ddd6a1b7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1700102537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1700102537 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2145423269 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 29475491460 ps |
| CPU time | 85.32 seconds |
| Started | May 09 01:00:00 PM PDT 24 |
| Finished | May 09 01:01:28 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-be741129-9143-4f7e-a705-b7c26cfe055f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145423269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2145423269 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3702461127 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 23061356752 ps |
| CPU time | 166.03 seconds |
| Started | May 09 01:00:01 PM PDT 24 |
| Finished | May 09 01:02:48 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-8dd6e17a-8876-49d9-af6a-60872da5f859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3702461127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3702461127 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3175304226 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 202491908 ps |
| CPU time | 7.2 seconds |
| Started | May 09 01:00:00 PM PDT 24 |
| Finished | May 09 01:00:10 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-369b4ed2-c1b3-4748-8f19-8b0cb4ca40e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175304226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3175304226 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.1466934487 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 33788291 ps |
| CPU time | 2.41 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:00:16 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-c50a4ce3-f88e-4e44-b188-a974809328bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1466934487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1466934487 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2810978153 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 114745735 ps |
| CPU time | 1.49 seconds |
| Started | May 09 12:59:59 PM PDT 24 |
| Finished | May 09 01:00:03 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-12cd384f-c464-400e-9100-a67cfc26f5bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2810978153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2810978153 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2335558464 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3685095995 ps |
| CPU time | 10.36 seconds |
| Started | May 09 01:00:00 PM PDT 24 |
| Finished | May 09 01:00:12 PM PDT 24 |
| Peak memory | 202336 kb |
| Host | smart-abd8073a-cf79-4c23-9a63-5ea143d6d482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335558464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2335558464 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.4272287659 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1037182094 ps |
| CPU time | 6.21 seconds |
| Started | May 09 12:59:58 PM PDT 24 |
| Finished | May 09 01:00:07 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-8f972a1a-cea3-4810-a070-e6edfeab6add |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4272287659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4272287659 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2856143557 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 13403808 ps |
| CPU time | 1.14 seconds |
| Started | May 09 01:00:01 PM PDT 24 |
| Finished | May 09 01:00:04 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-377c48cc-8323-4793-82b6-ee634fe57af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856143557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2856143557 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.1700233824 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 50006197 ps |
| CPU time | 1.71 seconds |
| Started | May 09 01:00:10 PM PDT 24 |
| Finished | May 09 01:00:14 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-2fedb76d-1fd2-4c46-bf76-b38d6139c1ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1700233824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1700233824 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.519159238 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 21930566419 ps |
| CPU time | 95.8 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:01:50 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-57bd1ae4-3713-41ca-87db-c5529e286e0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=519159238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.519159238 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1658428987 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3076872854 ps |
| CPU time | 35.78 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:49 PM PDT 24 |
| Peak memory | 203328 kb |
| Host | smart-ceebabe7-19bd-4d90-aa0c-11bb03ba773d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658428987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1658428987 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.4279486872 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 88369553 ps |
| CPU time | 2.22 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:15 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-ac12f5d7-06b5-470c-9988-bcc8cd9efddb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4279486872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4279486872 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1362644946 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 25698419 ps |
| CPU time | 5.68 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:19 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-3ee384e6-3cc0-4c3a-992e-158eac74a555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1362644946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1362644946 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1753257480 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 44331290901 ps |
| CPU time | 176.25 seconds |
| Started | May 09 01:00:10 PM PDT 24 |
| Finished | May 09 01:03:09 PM PDT 24 |
| Peak memory | 203060 kb |
| Host | smart-af7ba50f-464d-415b-b4ff-c2a939b9867f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1753257480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1753257480 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.724240411 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 522052132 ps |
| CPU time | 6.79 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:00:20 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-a8f931a2-7b3c-4ecd-85e6-0a36f9f750ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=724240411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.724240411 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.3492516774 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 218644084 ps |
| CPU time | 5.71 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:18 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-143c69de-f788-4b90-aa97-06e082f4d9f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3492516774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3492516774 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2693358707 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 40133949 ps |
| CPU time | 4.33 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:18 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-0f1228fd-827e-4520-b01d-43aa8d42588c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693358707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2693358707 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.629316161 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 66649780993 ps |
| CPU time | 97.15 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:01:50 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-e19633e5-db3a-4084-9080-49cfc9b4923e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=629316161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.629316161 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1327448611 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 21676536503 ps |
| CPU time | 43.77 seconds |
| Started | May 09 01:00:09 PM PDT 24 |
| Finished | May 09 01:00:55 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-81f1cad5-e110-4e4b-8154-b76287b1bad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1327448611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1327448611 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1584027641 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 53475716 ps |
| CPU time | 7.49 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:00:21 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-09847bae-175b-40e7-b888-8895e1e27616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584027641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1584027641 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.4061727809 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 52309020 ps |
| CPU time | 5.34 seconds |
| Started | May 09 01:00:09 PM PDT 24 |
| Finished | May 09 01:00:16 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-648a5fe2-8baf-4d3b-bbf2-d342e90bf1e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061727809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4061727809 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.825082715 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 327985194 ps |
| CPU time | 1.42 seconds |
| Started | May 09 01:00:14 PM PDT 24 |
| Finished | May 09 01:00:17 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-d27e20c2-7d94-446c-9cdb-e1904e23f73c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825082715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.825082715 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2772997160 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 10393688622 ps |
| CPU time | 7.47 seconds |
| Started | May 09 01:00:13 PM PDT 24 |
| Finished | May 09 01:00:22 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-b4a934ce-3ffe-494c-85d5-69d6f0bedf71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772997160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2772997160 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.42404465 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2011790594 ps |
| CPU time | 5.56 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:19 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-2372972a-87ef-4b45-ab39-58559532b729 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=42404465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.42404465 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3853704973 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 11025910 ps |
| CPU time | 1.28 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:14 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-eab5aad0-428e-4f7b-aa03-7bcbbd49c9bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853704973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3853704973 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4209113791 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 804988958 ps |
| CPU time | 8.63 seconds |
| Started | May 09 01:00:10 PM PDT 24 |
| Finished | May 09 01:00:21 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-76aa5105-e352-4e5d-982f-988ae2aac587 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4209113791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4209113791 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3693367828 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5318695659 ps |
| CPU time | 74.78 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:01:29 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-1700556a-700a-495f-8287-5363ea6e4b9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3693367828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3693367828 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4170722612 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1698392379 ps |
| CPU time | 193.07 seconds |
| Started | May 09 01:00:10 PM PDT 24 |
| Finished | May 09 01:03:25 PM PDT 24 |
| Peak memory | 205284 kb |
| Host | smart-f4c4d3b0-b309-4d74-9600-60efcaaba972 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4170722612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.4170722612 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2965463714 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 56743916 ps |
| CPU time | 17.14 seconds |
| Started | May 09 01:00:13 PM PDT 24 |
| Finished | May 09 01:00:31 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-ba36be48-6fca-4906-bd9d-de25bb0df83d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2965463714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.2965463714 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3690913300 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1012993541 ps |
| CPU time | 7 seconds |
| Started | May 09 01:00:13 PM PDT 24 |
| Finished | May 09 01:00:21 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-7dd40af2-45ac-4b77-be7f-595e619172a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3690913300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3690913300 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1177582939 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 132904962 ps |
| CPU time | 7.44 seconds |
| Started | May 09 01:00:23 PM PDT 24 |
| Finished | May 09 01:00:34 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-516e50bc-7858-4baf-ab48-46cf58781eb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1177582939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1177582939 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3499953368 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 63820488534 ps |
| CPU time | 333.7 seconds |
| Started | May 09 01:00:19 PM PDT 24 |
| Finished | May 09 01:05:55 PM PDT 24 |
| Peak memory | 204132 kb |
| Host | smart-ee6d5d02-44cf-4305-a5a6-9c0b276262d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3499953368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3499953368 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1579959430 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1302801655 ps |
| CPU time | 3.28 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:00:26 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-2e4d7d8a-7cf0-45be-b1f8-1779e2770b7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1579959430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1579959430 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3788716866 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2486247248 ps |
| CPU time | 12.49 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 202104 kb |
| Host | smart-11efa4fc-2a45-4350-b7db-dd6f4c8ffb2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788716866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3788716866 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.3824843730 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 552169976 ps |
| CPU time | 2.77 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:27 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-83c286a2-33ff-4a76-a9fd-5b841802af3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3824843730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3824843730 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3954740841 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 98761301170 ps |
| CPU time | 188.15 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:03:34 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-ad7d4abd-989d-481d-bbac-8a956cbf93b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954740841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3954740841 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3612193093 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 5901890338 ps |
| CPU time | 40.21 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:01:05 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-e3fe7753-d7a1-4e35-b3f5-a28cc8702589 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3612193093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3612193093 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.4092837558 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 83788238 ps |
| CPU time | 3.58 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:00:26 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-c1df757c-1a70-4971-aaf2-85ae67195d16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4092837558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4092837558 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2799725950 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 168837142 ps |
| CPU time | 1.68 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:15 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-8eed66d1-36e5-4014-b804-61492a36e438 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2799725950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2799725950 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2772006431 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2701135950 ps |
| CPU time | 8.25 seconds |
| Started | May 09 01:00:11 PM PDT 24 |
| Finished | May 09 01:00:21 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-f11849a3-83e7-4531-97fd-a19c1d9c268a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772006431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2772006431 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1548700718 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 9590872936 ps |
| CPU time | 14.19 seconds |
| Started | May 09 01:00:12 PM PDT 24 |
| Finished | May 09 01:00:28 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-5d80d3cd-0128-4c46-b8ac-b4ef9758dd08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1548700718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1548700718 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.4161942517 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 13243671 ps |
| CPU time | 1 seconds |
| Started | May 09 01:00:13 PM PDT 24 |
| Finished | May 09 01:00:16 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-02ef2cc8-20c0-4cf3-a371-4368bd6fb94d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161942517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4161942517 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.4018803376 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 8154211951 ps |
| CPU time | 100.9 seconds |
| Started | May 09 01:00:23 PM PDT 24 |
| Finished | May 09 01:02:07 PM PDT 24 |
| Peak memory | 204120 kb |
| Host | smart-b7a957b0-47a7-454b-9c15-4e5daa5074c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018803376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4018803376 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.197148203 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1252921709 ps |
| CPU time | 21.15 seconds |
| Started | May 09 01:00:19 PM PDT 24 |
| Finished | May 09 01:00:41 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-312c99f0-e696-42ba-bf36-75fff955ec7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=197148203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.197148203 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1722539322 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 862396767 ps |
| CPU time | 19.23 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:44 PM PDT 24 |
| Peak memory | 202936 kb |
| Host | smart-8b7229c5-e98b-46f3-be55-b7c9365800f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1722539322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.1722539322 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.183295317 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 822580978 ps |
| CPU time | 90.81 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 206684 kb |
| Host | smart-c776aca6-cf85-4155-87f3-cea2db802f65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=183295317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res et_error.183295317 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1043839807 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 76906360 ps |
| CPU time | 2.66 seconds |
| Started | May 09 01:00:26 PM PDT 24 |
| Finished | May 09 01:00:32 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-71bf1d1f-1ad0-48d7-bea6-f65b019cea3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1043839807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1043839807 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3375774524 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 146447622 ps |
| CPU time | 6.32 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:00:29 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-bc0170e8-f934-4c9d-bcc8-42dc06fdd6e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3375774524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3375774524 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3499860783 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 21947808612 ps |
| CPU time | 39.28 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:01:03 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-73d71e79-9cc6-41fa-bef3-050d044b8f86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3499860783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3499860783 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1623089868 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 986222401 ps |
| CPU time | 8.48 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:33 PM PDT 24 |
| Peak memory | 201932 kb |
| Host | smart-eacbcbaf-f351-4d2d-a96b-8f0bd9e8e180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1623089868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1623089868 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.224652 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 899503620 ps |
| CPU time | 11.33 seconds |
| Started | May 09 01:00:19 PM PDT 24 |
| Finished | May 09 01:00:31 PM PDT 24 |
| Peak memory | 201932 kb |
| Host | smart-9a381d75-b713-4cc9-ac75-0d4af3fdcdc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=224652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.224652 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.3382977850 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 399495868 ps |
| CPU time | 7.78 seconds |
| Started | May 09 01:00:25 PM PDT 24 |
| Finished | May 09 01:00:35 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-9b41d7e3-daf9-4de2-b54c-617675a31dff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3382977850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3382977850 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3011491833 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4840764924 ps |
| CPU time | 20.08 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:45 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-7c02d2a7-8969-4d5e-8962-ba185fcd27b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011491833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3011491833 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3889928589 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 18958912929 ps |
| CPU time | 21.43 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:46 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-46dbb607-80a5-4537-9647-313b2728e141 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3889928589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3889928589 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3046465089 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 14248664 ps |
| CPU time | 1.39 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:25 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-8c5a366e-e55d-4213-91bc-b4bf5275ad39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046465089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3046465089 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.3803111535 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 47665166 ps |
| CPU time | 4.63 seconds |
| Started | May 09 01:00:23 PM PDT 24 |
| Finished | May 09 01:00:31 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-2a45e040-e3d5-4bec-ae8d-03e31676d0fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3803111535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3803111535 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1278436602 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 115481854 ps |
| CPU time | 1.56 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:26 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-73d7b32d-8db5-4c79-957c-ece7e8ba081a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1278436602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1278436602 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1649411665 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 6460174555 ps |
| CPU time | 10.73 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-666a5f91-5e42-48a4-afde-733e9fa886b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649411665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1649411665 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3588299527 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 8489709199 ps |
| CPU time | 10.49 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:35 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-61a07214-692e-44a6-a52b-f6a83527671d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3588299527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3588299527 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1222086117 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11887905 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:26 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-faaa1a09-0ea1-42a3-a28f-aeda00d3af97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222086117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1222086117 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3554015177 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 705806023 ps |
| CPU time | 29.77 seconds |
| Started | May 09 01:00:26 PM PDT 24 |
| Finished | May 09 01:00:58 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-b2025cf3-58ee-4d9f-8b22-badb19c6bd85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554015177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3554015177 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.45015173 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 4298260507 ps |
| CPU time | 77.47 seconds |
| Started | May 09 01:00:19 PM PDT 24 |
| Finished | May 09 01:01:38 PM PDT 24 |
| Peak memory | 203000 kb |
| Host | smart-cfcaa148-92f4-4eed-aed8-fdab28d85c64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=45015173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.45015173 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.322597548 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 734278154 ps |
| CPU time | 144.43 seconds |
| Started | May 09 01:00:23 PM PDT 24 |
| Finished | May 09 01:02:50 PM PDT 24 |
| Peak memory | 207456 kb |
| Host | smart-31a56bf0-04a1-404f-bb01-6e9798ef6401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=322597548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.322597548 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3951545727 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 871093503 ps |
| CPU time | 85.3 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:01:47 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-90af017d-8c36-4480-a2f4-f982b492ccc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3951545727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3951545727 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3820403011 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1185759463 ps |
| CPU time | 8.57 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:00:30 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-64f2629f-f3e3-403d-8093-34113380b6f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3820403011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3820403011 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1302122439 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 658803245 ps |
| CPU time | 13.86 seconds |
| Started | May 09 01:00:25 PM PDT 24 |
| Finished | May 09 01:00:41 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-220ea378-f88a-47b3-86d7-b7e206a7391b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302122439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1302122439 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1283298436 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 41994165664 ps |
| CPU time | 130.43 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:02:34 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-bb8f5441-0e39-4d1c-8029-c3df234ce044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1283298436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1283298436 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3372181370 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 964299921 ps |
| CPU time | 10.82 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:00:33 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-b520f599-4a4f-491a-8a4c-d2ac27135432 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372181370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3372181370 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1801697141 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 603253217 ps |
| CPU time | 9.29 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:34 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-51c16529-fe3a-4d7e-a9f3-73b67f2ca665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1801697141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1801697141 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.2193406447 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 621235309 ps |
| CPU time | 8.42 seconds |
| Started | May 09 01:00:20 PM PDT 24 |
| Finished | May 09 01:00:30 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-c3da9a54-2d8d-4e75-aaaf-d38b7533d865 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2193406447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2193406447 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1868933016 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 17175612605 ps |
| CPU time | 51.84 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:01:16 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-b18dc702-3204-4326-bbe2-63f018d77391 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868933016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1868933016 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1988988626 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 32511588121 ps |
| CPU time | 116.13 seconds |
| Started | May 09 01:00:23 PM PDT 24 |
| Finished | May 09 01:02:22 PM PDT 24 |
| Peak memory | 202336 kb |
| Host | smart-b2c7dbf8-fe4d-48b3-9783-0e8f5d6bca61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1988988626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1988988626 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1871588819 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 19926764 ps |
| CPU time | 2.1 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:27 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-5af0cf58-2ece-49df-ba4f-e96bf6e1d7e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871588819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1871588819 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.2195749035 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 230455948 ps |
| CPU time | 2.53 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:00:28 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-d95e1e2a-ca5b-45bf-966c-97aa2552c0fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2195749035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2195749035 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.3351854541 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 21038159 ps |
| CPU time | 1.21 seconds |
| Started | May 09 01:00:24 PM PDT 24 |
| Finished | May 09 01:00:28 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-912c0cbf-d7cb-4f9e-a636-4f7460f7d056 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3351854541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3351854541 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.49005944 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3309816605 ps |
| CPU time | 9.49 seconds |
| Started | May 09 01:00:26 PM PDT 24 |
| Finished | May 09 01:00:38 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-b163ac7d-3609-44e1-8032-082f9e920337 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=49005944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.49005944 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2455366669 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 5748116575 ps |
| CPU time | 8.01 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:32 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-6ff26ea0-898c-4094-a86a-cea5cc7811d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2455366669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2455366669 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3091286352 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 8022524 ps |
| CPU time | 1.04 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:24 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-355f7d12-3bdc-41a7-85eb-1ea346df0e42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091286352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3091286352 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2621699217 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 22665243495 ps |
| CPU time | 111.23 seconds |
| Started | May 09 01:00:22 PM PDT 24 |
| Finished | May 09 01:02:17 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-3ea8abd4-e333-4896-85e2-f3cae5189453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2621699217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2621699217 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.509339012 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4073233936 ps |
| CPU time | 59.41 seconds |
| Started | May 09 01:00:34 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-f5de8b39-cac3-479c-ba27-c9f0b0ee24ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=509339012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.509339012 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1053598620 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 14327158924 ps |
| CPU time | 303.62 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:05:40 PM PDT 24 |
| Peak memory | 208896 kb |
| Host | smart-0a133532-d7d8-493c-a1f0-8c30e4929360 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1053598620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.1053598620 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.320947527 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1277104607 ps |
| CPU time | 79.7 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:01:54 PM PDT 24 |
| Peak memory | 205724 kb |
| Host | smart-e9c24202-69d9-496a-b9e2-dd23cd00ed92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=320947527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.320947527 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1519573620 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 115387880 ps |
| CPU time | 2.26 seconds |
| Started | May 09 01:00:21 PM PDT 24 |
| Finished | May 09 01:00:26 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-a26b12b5-8455-4331-8e45-3ce20338b2ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1519573620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1519573620 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2351015213 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 24236824 ps |
| CPU time | 5.09 seconds |
| Started | May 09 01:00:29 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-604df793-215c-474a-90b9-a56c39b0cb2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2351015213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2351015213 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.4005039904 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 31877784634 ps |
| CPU time | 96.64 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:02:13 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-c4cd975e-b656-42e4-ac41-3dcff95d7ba3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4005039904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.4005039904 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.725248255 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 83694419 ps |
| CPU time | 5.63 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:00:41 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-b80eef37-f964-4418-8601-f13b61d5c485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=725248255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.725248255 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.2553127742 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 864701203 ps |
| CPU time | 16.46 seconds |
| Started | May 09 01:00:32 PM PDT 24 |
| Finished | May 09 01:00:52 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-609cd660-e4a4-4055-93d9-41d1bd044adf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2553127742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2553127742 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.3320621331 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 67259015 ps |
| CPU time | 9.54 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:44 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-ffa8c0aa-3c7d-41d1-b924-815076c7af85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320621331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3320621331 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2201584289 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 71582253214 ps |
| CPU time | 119.54 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:02:35 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-f687a089-8a2a-4059-a18d-65fcb1a2ea2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201584289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2201584289 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.840430255 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 20710573769 ps |
| CPU time | 131.57 seconds |
| Started | May 09 01:00:35 PM PDT 24 |
| Finished | May 09 01:02:50 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-f698ee23-0364-4370-9801-8be17e4398d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=840430255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.840430255 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.640690841 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 97843740 ps |
| CPU time | 6.85 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:41 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-f4dd1646-87dc-40d4-aef6-64ddcecd4215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640690841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.640690841 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.1065084885 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 324961231 ps |
| CPU time | 4.59 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:00:42 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-5285ddc2-03b8-40ba-9aa6-fe38595b2f00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1065084885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1065084885 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3196141743 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 67271767 ps |
| CPU time | 1.85 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:35 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-f46266d1-1447-462c-9ece-813c95648bb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3196141743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3196141743 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.349127674 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2351816323 ps |
| CPU time | 11.51 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:00:48 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-57cbda97-e0f2-4b4a-bfa7-033656fda6ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=349127674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.349127674 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1842102101 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1872073334 ps |
| CPU time | 7.43 seconds |
| Started | May 09 01:00:29 PM PDT 24 |
| Finished | May 09 01:00:40 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-09d076c2-d305-4714-b465-d13b34f3418f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1842102101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1842102101 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1861831892 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 9165956 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:00:37 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-0bef7721-d20e-4958-89b4-645d0d81388a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861831892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1861831892 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.4019217688 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 358463177 ps |
| CPU time | 25.37 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:01:02 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-cbf514d6-8c13-4996-9284-8bf8e46d6159 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4019217688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4019217688 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3437820202 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 214246391 ps |
| CPU time | 13.39 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:00:50 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-0887d291-3f62-4138-95f8-b0db546a7870 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437820202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3437820202 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3773623089 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 558030954 ps |
| CPU time | 67.77 seconds |
| Started | May 09 01:00:32 PM PDT 24 |
| Finished | May 09 01:01:43 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-2dd9b4ad-63cd-42ca-ab3e-ce64eef0fdfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3773623089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3773623089 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1417144282 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 92380012 ps |
| CPU time | 4.88 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:38 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-96dcb932-0d67-4023-9b3f-fd8d85cd6788 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1417144282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1417144282 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1810954465 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 24980214 ps |
| CPU time | 1.36 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-e81021bf-abb0-4d3f-bbb9-66b0b69aa8ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1810954465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1810954465 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2902620632 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 37295250 ps |
| CPU time | 5.51 seconds |
| Started | May 09 12:58:55 PM PDT 24 |
| Finished | May 09 12:59:03 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-375fafe3-3218-4464-a4ac-91a2fdfab760 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2902620632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2902620632 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.781717593 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 62242593 ps |
| CPU time | 3.99 seconds |
| Started | May 09 12:58:56 PM PDT 24 |
| Finished | May 09 12:59:01 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-704d0e04-6a86-4c40-bbb1-84a8b5693329 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=781717593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.781717593 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2548472999 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 455120811 ps |
| CPU time | 9.03 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 12:59:05 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-508129d5-b656-4da0-8d55-6e73375c2939 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2548472999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2548472999 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.3438922801 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 343801576 ps |
| CPU time | 4.41 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 12:59:00 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-a09e91de-d61f-493e-bfb5-1f154d9dcdf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3438922801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3438922801 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1755709447 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 44252917125 ps |
| CPU time | 155.41 seconds |
| Started | May 09 12:58:59 PM PDT 24 |
| Finished | May 09 01:01:36 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-13e2d993-6142-4d69-a330-9e19e737f156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755709447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1755709447 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3005193883 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 12194790633 ps |
| CPU time | 34.26 seconds |
| Started | May 09 12:58:54 PM PDT 24 |
| Finished | May 09 12:59:30 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-a15962a4-6b9c-4876-a596-8be8c8f1bebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3005193883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3005193883 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2877667036 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 40048367 ps |
| CPU time | 3.77 seconds |
| Started | May 09 12:58:54 PM PDT 24 |
| Finished | May 09 12:59:00 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-b0060931-8421-4cd0-bb74-bd417c479c0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877667036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2877667036 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.2909423358 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1308873043 ps |
| CPU time | 8.39 seconds |
| Started | May 09 12:58:59 PM PDT 24 |
| Finished | May 09 12:59:09 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-0e0a6e4d-c753-44ce-91e0-01b4c5940f9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2909423358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2909423358 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2767538734 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 174332693 ps |
| CPU time | 1.87 seconds |
| Started | May 09 12:58:55 PM PDT 24 |
| Finished | May 09 12:58:59 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-8399cec4-b13d-4676-8111-d656d84563ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2767538734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2767538734 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2349206946 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11913532058 ps |
| CPU time | 6.98 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 12:59:00 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-843146b1-0f87-477a-a438-8f09851ab663 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349206946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2349206946 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.764541040 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1313823159 ps |
| CPU time | 7.54 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 12:59:02 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-5437c4b5-cb68-4f01-a07c-97a1356471b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=764541040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.764541040 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2804432021 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 14588501 ps |
| CPU time | 1.15 seconds |
| Started | May 09 12:58:59 PM PDT 24 |
| Finished | May 09 12:59:01 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-3d790767-795d-4116-9cc7-8cd4e4c585f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804432021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2804432021 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.861290575 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 10462929443 ps |
| CPU time | 65.69 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 01:00:01 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-5956d000-7442-4e2f-82a2-d8f5fe96cf0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=861290575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.861290575 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2657324765 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 7710561916 ps |
| CPU time | 67.61 seconds |
| Started | May 09 12:58:55 PM PDT 24 |
| Finished | May 09 01:00:05 PM PDT 24 |
| Peak memory | 203024 kb |
| Host | smart-8fbb5b01-0881-48f4-8a23-be2647f73e3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657324765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2657324765 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.465550937 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 478333818 ps |
| CPU time | 34.67 seconds |
| Started | May 09 12:58:52 PM PDT 24 |
| Finished | May 09 12:59:28 PM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-053de2af-44dc-43ae-96d3-5fc52c7dd4be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465550937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_ reset.465550937 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.4042178380 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 6275089581 ps |
| CPU time | 149.31 seconds |
| Started | May 09 12:58:59 PM PDT 24 |
| Finished | May 09 01:01:30 PM PDT 24 |
| Peak memory | 205884 kb |
| Host | smart-2976ddb5-645d-4b4d-8d2e-0d60172664b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4042178380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.4042178380 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.4230972740 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 531571452 ps |
| CPU time | 4.09 seconds |
| Started | May 09 12:58:53 PM PDT 24 |
| Finished | May 09 12:59:00 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-31b5753b-2d1b-43c0-a0af-f30a243525d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230972740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4230972740 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1544060285 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1113506733 ps |
| CPU time | 14.44 seconds |
| Started | May 09 01:00:32 PM PDT 24 |
| Finished | May 09 01:00:50 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-d9a4e419-028e-41b8-9a5a-7f428d642fa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1544060285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1544060285 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.510063313 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 55323702088 ps |
| CPU time | 202.48 seconds |
| Started | May 09 01:00:32 PM PDT 24 |
| Finished | May 09 01:03:58 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-ad5fe99e-db01-465f-b695-36c3ee81ead4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=510063313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.510063313 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2533437249 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 450816506 ps |
| CPU time | 5.47 seconds |
| Started | May 09 01:00:34 PM PDT 24 |
| Finished | May 09 01:00:43 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-09aa7614-531e-4434-b8bc-64e84edbda5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2533437249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2533437249 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.310326863 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 422536903 ps |
| CPU time | 3.93 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:00:39 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-58819a29-109f-46f7-8310-140f691b6c0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=310326863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.310326863 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3323498884 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 314519037 ps |
| CPU time | 3.81 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:38 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-6e0bed51-b7e8-4873-8e39-e2049dc82c61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3323498884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3323498884 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3030936933 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 20901879965 ps |
| CPU time | 22.79 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:57 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-460bbfec-b6d4-4f52-aa4a-fb5868ce38c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030936933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3030936933 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.500509299 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 20973074193 ps |
| CPU time | 121.33 seconds |
| Started | May 09 01:00:32 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-f2ed6d8f-b299-4a4a-88cf-6d62966bb7a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=500509299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.500509299 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3823558268 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 64637210 ps |
| CPU time | 9.27 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:00:44 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-1239b0c3-b4ce-4588-a8f1-aab5177b3e27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823558268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3823558268 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.28748304 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1336789593 ps |
| CPU time | 11.42 seconds |
| Started | May 09 01:00:33 PM PDT 24 |
| Finished | May 09 01:00:48 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-87bc3219-9c1a-4001-aec7-dabb3f2afe9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=28748304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.28748304 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2185663638 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 12477297 ps |
| CPU time | 1.04 seconds |
| Started | May 09 01:00:35 PM PDT 24 |
| Finished | May 09 01:00:39 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-13818205-f9ba-4720-8b56-afde9dbdb67c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2185663638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2185663638 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.359479794 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4605194138 ps |
| CPU time | 6.29 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:40 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-0bf8aa01-49dc-466d-9385-3ce99ecef17d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=359479794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.359479794 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1730575519 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 6881824731 ps |
| CPU time | 7.44 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:41 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-b284a764-d5d3-4b58-9dd2-dedb37769e31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1730575519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1730575519 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3777086907 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 20057433 ps |
| CPU time | 1.09 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-e0cd3dd2-9c4d-4941-9b83-ae721b6c6655 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777086907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3777086907 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1151681425 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3757111547 ps |
| CPU time | 46.77 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:01:21 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-fa7d5a4f-b2fc-48c1-9d0f-14c99ef04cff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1151681425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1151681425 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2943669247 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2821245964 ps |
| CPU time | 32.76 seconds |
| Started | May 09 01:00:31 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 203820 kb |
| Host | smart-15423547-aabf-48e1-ab78-6c0e38eadfa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2943669247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2943669247 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3176256710 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 197320468 ps |
| CPU time | 18.1 seconds |
| Started | May 09 01:00:35 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-0d55dffe-9b2c-40d8-b003-2490ae1ed363 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3176256710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.3176256710 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3641902163 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 435329294 ps |
| CPU time | 9.44 seconds |
| Started | May 09 01:00:29 PM PDT 24 |
| Finished | May 09 01:00:42 PM PDT 24 |
| Peak memory | 201932 kb |
| Host | smart-db764d63-e6d5-4fd2-9fce-5bbcd96299d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3641902163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3641902163 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.489760950 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1447407549 ps |
| CPU time | 18.58 seconds |
| Started | May 09 01:00:47 PM PDT 24 |
| Finished | May 09 01:01:06 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-ccc1f5ac-60fb-45f3-b273-b5406df48125 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489760950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.489760950 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1226389422 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 22093270935 ps |
| CPU time | 50.87 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:01:34 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-0d61dcac-7b28-42fc-8673-420361f30f3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1226389422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1226389422 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3524522789 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 193815542 ps |
| CPU time | 4.27 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-20d9e930-97c3-4199-a1bc-e336a4f09359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524522789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3524522789 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.2308758354 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11591625 ps |
| CPU time | 1.06 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:46 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-63ae3644-297d-4420-88f8-61b9ffbf9b36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2308758354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2308758354 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.1928268780 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 294713537 ps |
| CPU time | 5.71 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:00:53 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-6c48a5b9-4eea-4bb1-9aac-cd0f4c261ba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1928268780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1928268780 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3908836695 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 14887788231 ps |
| CPU time | 23.27 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:01:10 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-d25c3743-2146-44ac-a24d-89c5f019eb09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908836695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3908836695 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3779977812 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8284059024 ps |
| CPU time | 42.13 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:01:29 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-35700790-d9dc-47d2-a5b3-8a33c5bb9ad0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3779977812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3779977812 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3130973621 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 131605298 ps |
| CPU time | 4.63 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:50 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-e534d1f5-6deb-4efa-b4b2-72215ad9af76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130973621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3130973621 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.3100329263 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2565007652 ps |
| CPU time | 4.91 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:00:49 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-0a07cf30-72d8-4cc6-be8b-7f954ef760d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3100329263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3100329263 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.4076832361 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 57912839 ps |
| CPU time | 1.3 seconds |
| Started | May 09 01:00:30 PM PDT 24 |
| Finished | May 09 01:00:35 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-48095292-cc34-459a-897b-c9b28403552c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4076832361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4076832361 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2713902117 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 8275378447 ps |
| CPU time | 11.84 seconds |
| Started | May 09 01:00:36 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-e714059e-6ce0-4d05-90b3-beb75e630919 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713902117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2713902117 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2630497879 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1217727085 ps |
| CPU time | 8.7 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:55 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-bedfbd5d-183e-4495-b965-20d7454850e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2630497879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2630497879 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3432722964 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 8072185 ps |
| CPU time | 1.11 seconds |
| Started | May 09 01:00:36 PM PDT 24 |
| Finished | May 09 01:00:40 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-83722c09-8139-4260-b240-8b4fbf1acff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432722964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3432722964 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.491665442 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1008910183 ps |
| CPU time | 39.44 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:01:25 PM PDT 24 |
| Peak memory | 203224 kb |
| Host | smart-d39d794e-91b6-4a2f-bae6-3310a9f7b36b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=491665442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.491665442 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.785346883 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 851099281 ps |
| CPU time | 13.85 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:00:58 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-2339d16d-0a3d-4e5e-9bfd-f097c80e63df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=785346883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.785346883 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.836061985 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 133055797 ps |
| CPU time | 12.22 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:58 PM PDT 24 |
| Peak memory | 202968 kb |
| Host | smart-1890509f-8c9f-4280-bfde-07770f62a0b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=836061985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand _reset.836061985 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.726876590 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8506425278 ps |
| CPU time | 199.63 seconds |
| Started | May 09 01:00:47 PM PDT 24 |
| Finished | May 09 01:04:08 PM PDT 24 |
| Peak memory | 207280 kb |
| Host | smart-2c4dc681-8e85-4599-bc88-74fdadf032a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726876590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_res et_error.726876590 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2060552356 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 53671501 ps |
| CPU time | 1.54 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:48 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-362bf181-47b3-40f4-94f4-e58797f8764f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2060552356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2060552356 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3354218579 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1590278167 ps |
| CPU time | 19.75 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:01:06 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-90f17766-ec84-49e2-a3e5-3164653bfef1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354218579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3354218579 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.17533004 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 19441382818 ps |
| CPU time | 75.23 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:02:01 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-726843ff-3323-4213-9be7-c034ff74d472 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=17533004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow _rsp.17533004 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1774158610 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 675645427 ps |
| CPU time | 5.84 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:00:50 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-1b074ea3-de31-40ed-88c1-424ae5266245 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1774158610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1774158610 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.862734187 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1511963222 ps |
| CPU time | 12.85 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:00:55 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-7979fe86-41e2-41b6-b990-fe7353ca78ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=862734187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.862734187 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1992188881 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 55753785 ps |
| CPU time | 2.05 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:48 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-1968024a-0afc-4bea-9e83-f0e184843ecd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1992188881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1992188881 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.102738168 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 11437832818 ps |
| CPU time | 46.97 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:01:34 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-ab628ec2-567c-4ed8-b031-589df1d3aec1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=102738168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.102738168 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1345792205 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 5533570287 ps |
| CPU time | 41.72 seconds |
| Started | May 09 01:00:47 PM PDT 24 |
| Finished | May 09 01:01:30 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-76fef1f2-74e9-4988-a40a-d0919f9511fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1345792205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1345792205 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2270603506 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 173786881 ps |
| CPU time | 5.24 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-3fc65ae9-0c41-4a12-b1a7-4a5874163a51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270603506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2270603506 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2849082873 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3239343055 ps |
| CPU time | 13.2 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-25fc7231-497b-4535-a2fe-829fa09aa531 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2849082873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2849082873 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2081833766 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 42454177 ps |
| CPU time | 1.63 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:48 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-bbf0bd61-0969-4f93-8c76-c01d13323d20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2081833766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2081833766 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1849644709 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1349669469 ps |
| CPU time | 7.19 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:00:54 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-19782c0e-79c4-4761-bfed-dbf0b61768b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849644709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1849644709 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.636433612 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2434567030 ps |
| CPU time | 7.34 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:53 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-f3e213df-bfa0-47ab-a1fc-bdd46027f0a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=636433612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.636433612 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3201868372 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 9770232 ps |
| CPU time | 1.2 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:46 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-92f404bc-0a6f-4a2e-9ae5-3f4fa68595d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201868372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3201868372 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2629420567 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 791284191 ps |
| CPU time | 52.8 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:01:39 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-2b32e495-b144-4074-aa74-bfc23c9564cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2629420567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2629420567 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1469121613 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 294725797 ps |
| CPU time | 30.74 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:01:17 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-fad3f004-6321-404f-8991-8678aa165450 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1469121613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1469121613 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1198112896 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4139304232 ps |
| CPU time | 119.86 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:02:46 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-170cc52a-bef1-461b-b751-2fa3a271f982 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1198112896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1198112896 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.970202604 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 585881797 ps |
| CPU time | 41.91 seconds |
| Started | May 09 01:00:46 PM PDT 24 |
| Finished | May 09 01:01:30 PM PDT 24 |
| Peak memory | 203304 kb |
| Host | smart-f1172f6e-260e-4c49-9e0b-8d674d1c9541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=970202604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res et_error.970202604 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1380179224 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 223543307 ps |
| CPU time | 9.19 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:54 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-97959b2a-fac5-4829-80be-687a844db3cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1380179224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1380179224 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2052333678 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 40559101801 ps |
| CPU time | 315.75 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:06:02 PM PDT 24 |
| Peak memory | 203168 kb |
| Host | smart-ef1aa89b-2248-4068-82c6-54de799e7d2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2052333678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2052333678 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2602587340 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 57155054 ps |
| CPU time | 4.23 seconds |
| Started | May 09 01:00:56 PM PDT 24 |
| Finished | May 09 01:01:02 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-e2bc5158-e03b-4b8f-8077-986f0c3c9451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2602587340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2602587340 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2275021905 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 684249419 ps |
| CPU time | 4.24 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:50 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-e7cf9a07-ff32-460b-a104-aca86d1651e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2275021905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2275021905 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3605181281 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 83454565 ps |
| CPU time | 9.4 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-cae6797b-f0af-4023-9d43-1d145ff7c54c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605181281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3605181281 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3756358598 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 20907203189 ps |
| CPU time | 97.2 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:02:23 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-08282449-8a17-4a62-be15-f5e3a8733b9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756358598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3756358598 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.19498876 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 14548736693 ps |
| CPU time | 87.53 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:02:12 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-2e549fbc-81e2-49dd-ad16-251b9879b33a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=19498876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.19498876 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2296061712 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 52315925 ps |
| CPU time | 6.92 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:00:54 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-264fe505-4646-4c75-b1f0-b180f21ec8ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296061712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2296061712 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.1352682611 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 70704671 ps |
| CPU time | 5.4 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-33b5e36a-5573-44ae-9e43-cf7125e9dbdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1352682611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1352682611 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.2429593840 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 43867992 ps |
| CPU time | 1.47 seconds |
| Started | May 09 01:00:45 PM PDT 24 |
| Finished | May 09 01:00:48 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-43676a00-3735-4304-a186-3eacc9734e75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429593840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2429593840 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4111872993 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4983369837 ps |
| CPU time | 10.83 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-1aa1d900-0ac5-4547-b887-9662bc03c34f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111872993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4111872993 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4111875762 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1694963864 ps |
| CPU time | 7.25 seconds |
| Started | May 09 01:00:42 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-4c8e8256-9579-4c62-9115-72f364fa1b9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4111875762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4111875762 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2174900527 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 23121041 ps |
| CPU time | 1.07 seconds |
| Started | May 09 01:00:44 PM PDT 24 |
| Finished | May 09 01:00:47 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-83fa5941-51cb-4b9d-bad1-f5f7c2eb51ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174900527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2174900527 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2973559420 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 26315182884 ps |
| CPU time | 107.09 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 203088 kb |
| Host | smart-74363f05-844a-4478-a00c-988d28d1ca7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2973559420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2973559420 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.876257801 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3812366023 ps |
| CPU time | 56.3 seconds |
| Started | May 09 01:00:51 PM PDT 24 |
| Finished | May 09 01:01:49 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-8341f0ac-8009-4fc7-a873-113094b28fc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=876257801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.876257801 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.858302393 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2053061590 ps |
| CPU time | 110.89 seconds |
| Started | May 09 01:00:55 PM PDT 24 |
| Finished | May 09 01:02:48 PM PDT 24 |
| Peak memory | 206216 kb |
| Host | smart-6f62dfcb-ec44-43f7-988d-936c72ff4a3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858302393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand _reset.858302393 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1557503188 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1443043336 ps |
| CPU time | 109.09 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 206084 kb |
| Host | smart-fe481131-fa3d-4537-9168-8eac8d63e629 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1557503188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1557503188 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1014592791 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 50624764 ps |
| CPU time | 5 seconds |
| Started | May 09 01:00:43 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-ff1c0032-c8dc-419e-8d66-c9c86804090a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1014592791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1014592791 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3058182959 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1429399991 ps |
| CPU time | 18 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-212918d8-783a-4234-81a7-1f4cd3a7fd23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3058182959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3058182959 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.224571374 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 39477271030 ps |
| CPU time | 141.2 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:03:17 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-607b387a-9f64-42a2-b4c6-4f1343ebe5d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=224571374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.224571374 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.302179638 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 525368855 ps |
| CPU time | 8.36 seconds |
| Started | May 09 01:00:55 PM PDT 24 |
| Finished | May 09 01:01:05 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-f3490615-020f-460f-9c90-70992d41fc02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302179638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.302179638 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.347485179 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 10753477 ps |
| CPU time | 1.32 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-ea35a23f-6a10-4c7e-a43c-14e23c9678fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=347485179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.347485179 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.4292109437 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 40335647 ps |
| CPU time | 1.44 seconds |
| Started | May 09 01:00:57 PM PDT 24 |
| Finished | May 09 01:00:59 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-f65375b1-d965-40e3-9507-158d7f0fe0dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4292109437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.4292109437 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2343691537 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 94789049977 ps |
| CPU time | 199.56 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:04:15 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-c2400592-2533-4586-8252-bff6a242e2fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343691537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2343691537 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.65643859 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 34500787795 ps |
| CPU time | 122.07 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:02:57 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-8ed78ee6-dab1-4554-9ae1-5c7aaca06fd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=65643859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.65643859 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2594357509 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 355484346 ps |
| CPU time | 5.92 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:01:00 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-abb8dfde-1ee9-47b3-aaf2-588021b7ec42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594357509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2594357509 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1639633362 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1127265927 ps |
| CPU time | 9.95 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:01:06 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-687e7dd2-a416-4d7e-8ac0-a28db411db6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1639633362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1639633362 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.1183589630 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 11843964 ps |
| CPU time | 1.16 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:00:57 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-21d67690-3949-4771-bdbb-935681892d0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1183589630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1183589630 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.4169714970 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4355218835 ps |
| CPU time | 11.88 seconds |
| Started | May 09 01:00:55 PM PDT 24 |
| Finished | May 09 01:01:09 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-d66d3449-1e4a-4458-9be8-5752ee5ce38e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169714970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.4169714970 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.658862177 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 897696455 ps |
| CPU time | 7.33 seconds |
| Started | May 09 01:00:52 PM PDT 24 |
| Finished | May 09 01:01:01 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-193d56d1-8622-445f-b905-e52fc01290d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=658862177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.658862177 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1610749654 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 18381240 ps |
| CPU time | 1.08 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-44da4487-b137-495d-8423-63f589b872d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610749654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1610749654 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2290233585 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2758911613 ps |
| CPU time | 38.43 seconds |
| Started | May 09 01:00:55 PM PDT 24 |
| Finished | May 09 01:01:35 PM PDT 24 |
| Peak memory | 203096 kb |
| Host | smart-8ea7c247-b23a-4d17-9fc1-6c0af8bf7c8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2290233585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2290233585 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.879353334 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 890953566 ps |
| CPU time | 35.96 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:01:31 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-62f13f63-2e2a-4251-bcf3-dc324bbd87a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=879353334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.879353334 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3698235846 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 93144608 ps |
| CPU time | 19.05 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 204064 kb |
| Host | smart-f863039e-84e1-48f9-bc39-e4d0b70156f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3698235846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3698235846 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1204405113 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3227559363 ps |
| CPU time | 73.86 seconds |
| Started | May 09 01:00:54 PM PDT 24 |
| Finished | May 09 01:02:09 PM PDT 24 |
| Peak memory | 203768 kb |
| Host | smart-0dce1d6f-6455-427e-9650-1edf28d20064 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1204405113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.1204405113 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.642757588 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 56639278 ps |
| CPU time | 3.94 seconds |
| Started | May 09 01:00:52 PM PDT 24 |
| Finished | May 09 01:00:57 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-0ce88156-556e-4d4e-8b22-ce6dd66df4fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=642757588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.642757588 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3008623499 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 148671268 ps |
| CPU time | 9.99 seconds |
| Started | May 09 01:00:57 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-7d8a7104-34d5-41f5-93fa-d8df520fad82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008623499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3008623499 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.860339704 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 34825818663 ps |
| CPU time | 98.91 seconds |
| Started | May 09 01:00:57 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 201652 kb |
| Host | smart-edae92a1-0418-4be2-a744-0506f5cc1502 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=860339704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.860339704 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3888744141 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 181021149 ps |
| CPU time | 2.31 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:11 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-1f5032c3-f70f-4803-b129-1d7f6db2216f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888744141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3888744141 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2344827830 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 422099057 ps |
| CPU time | 4.44 seconds |
| Started | May 09 01:00:52 PM PDT 24 |
| Finished | May 09 01:00:58 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-798a3bd6-feef-4996-9a56-c07c035f4d6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2344827830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2344827830 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.3081068821 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1118563559 ps |
| CPU time | 9.24 seconds |
| Started | May 09 01:00:55 PM PDT 24 |
| Finished | May 09 01:01:06 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-f116f7b7-bfab-4a29-abb9-933b88e66226 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3081068821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3081068821 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2835172373 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 21979202465 ps |
| CPU time | 76.88 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:02:12 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-5f735ef7-0d56-424d-ad53-051c46be42be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835172373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2835172373 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.798591468 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 11132927017 ps |
| CPU time | 60.46 seconds |
| Started | May 09 01:00:56 PM PDT 24 |
| Finished | May 09 01:01:58 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-c3616a75-4ee0-4d37-813a-9a980ad184d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=798591468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.798591468 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2553590404 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 58997663 ps |
| CPU time | 4.85 seconds |
| Started | May 09 01:00:58 PM PDT 24 |
| Finished | May 09 01:01:03 PM PDT 24 |
| Peak memory | 201632 kb |
| Host | smart-b77faf2a-b913-4412-8b4c-cbb48555f52a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553590404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2553590404 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.3433348884 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 258877040 ps |
| CPU time | 2.03 seconds |
| Started | May 09 01:00:57 PM PDT 24 |
| Finished | May 09 01:01:00 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-64be4178-14c8-4a9f-82a3-e8ae8edc2719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3433348884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3433348884 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3683195402 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 202969500 ps |
| CPU time | 1.19 seconds |
| Started | May 09 01:00:53 PM PDT 24 |
| Finished | May 09 01:00:55 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-94f51370-67f7-4959-906f-0811ba9f1f73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3683195402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3683195402 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2977051049 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2834374992 ps |
| CPU time | 8.49 seconds |
| Started | May 09 01:00:57 PM PDT 24 |
| Finished | May 09 01:01:07 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-d630f509-8609-415d-9aa2-3e02de94e487 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977051049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2977051049 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1751470136 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2317653897 ps |
| CPU time | 7.65 seconds |
| Started | May 09 01:00:52 PM PDT 24 |
| Finished | May 09 01:01:02 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-383dc066-2831-4ce3-bfc3-e15955d08c36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1751470136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1751470136 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1232162605 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 8309708 ps |
| CPU time | 1.18 seconds |
| Started | May 09 01:00:52 PM PDT 24 |
| Finished | May 09 01:00:54 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-c21c09f7-2c80-4936-b2c1-6a6b97ae70e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232162605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1232162605 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3281624456 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 21424979666 ps |
| CPU time | 81.58 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:02:28 PM PDT 24 |
| Peak memory | 203920 kb |
| Host | smart-fe9da385-1377-4c34-af86-d379149a55ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281624456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3281624456 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1057902515 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 775474862 ps |
| CPU time | 49.02 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-dfd815aa-45cb-4190-b599-077f4a76ff9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1057902515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1057902515 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3074122543 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 281423134 ps |
| CPU time | 36.29 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:01:40 PM PDT 24 |
| Peak memory | 204048 kb |
| Host | smart-82c1d228-07b9-417d-b8f9-528a0eb697ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3074122543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3074122543 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.468174785 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 51062889 ps |
| CPU time | 3.91 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:12 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-a78d96dd-d7de-4ce8-b312-ed90399de913 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=468174785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.468174785 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1949307564 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 43052607 ps |
| CPU time | 4.94 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:01:09 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-293e8543-b04a-4d61-8822-879f1e36c2c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949307564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1949307564 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3454321398 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 59075675 ps |
| CPU time | 4.02 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:09 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-20efbad4-960b-4045-9938-1ed33358b1b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3454321398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3454321398 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3926805642 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 187379767 ps |
| CPU time | 4.97 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:01:10 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-5f36e08b-c073-4a21-b5d5-13261be8290d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926805642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3926805642 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.228846424 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 30365613 ps |
| CPU time | 4.46 seconds |
| Started | May 09 01:01:07 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-a1b56bd3-41a8-4f99-8966-b1492bf9d208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=228846424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.228846424 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.198564884 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 87981380721 ps |
| CPU time | 83.08 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:02:30 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-cef63f67-8836-452b-a330-02af50d084f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=198564884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.198564884 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1408322839 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 12571048535 ps |
| CPU time | 29.12 seconds |
| Started | May 09 01:01:06 PM PDT 24 |
| Finished | May 09 01:01:38 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-288bf6f8-036b-45d4-8526-f1c0c9a2d1b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1408322839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1408322839 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.666621303 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 237371960 ps |
| CPU time | 4.73 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:11 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-58a14376-291d-47fc-b722-76585d586971 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666621303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.666621303 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.4143581280 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 926560385 ps |
| CPU time | 2.62 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:01:07 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-df85f32c-3175-4e4d-a4b0-593488b8e4c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4143581280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4143581280 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.12929660 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 37467716 ps |
| CPU time | 1.41 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-58985cc3-d53a-4756-9faf-a9b3e217f1f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=12929660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.12929660 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.395145882 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1529027523 ps |
| CPU time | 7.38 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:15 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-eab062e2-a496-4009-80f4-cc743d0310c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=395145882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.395145882 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.547611414 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3512910723 ps |
| CPU time | 10.47 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:18 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-c5bd13e7-34c0-4c76-a84d-00bebbac5682 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=547611414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.547611414 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1039579460 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 11875878 ps |
| CPU time | 1.17 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-96bcc241-db7f-41cc-b96d-b1c96436a32f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039579460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1039579460 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.1144027282 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 125721456 ps |
| CPU time | 6.04 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-5bdeda88-0a91-4686-8453-c0afe28a8151 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1144027282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1144027282 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2935971596 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 801444109 ps |
| CPU time | 5.93 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:12 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-72759d70-1bd8-4f3b-8258-52e9de64d21d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2935971596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2935971596 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2722899836 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 724306898 ps |
| CPU time | 105.42 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:02:53 PM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-0ab9bfda-7434-40b4-aa0a-5b281c3824f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2722899836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2722899836 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1073430311 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 483875185 ps |
| CPU time | 61.36 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:02:06 PM PDT 24 |
| Peak memory | 205508 kb |
| Host | smart-3f666e38-a46c-43ee-bbfc-68a092f90cdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1073430311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1073430311 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3333287560 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 466809098 ps |
| CPU time | 8.69 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:15 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-0d1e2091-61d8-4413-bc76-e5997fd0246f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333287560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3333287560 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.35651571 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 217538553 ps |
| CPU time | 6.01 seconds |
| Started | May 09 01:01:07 PM PDT 24 |
| Finished | May 09 01:01:15 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-a8e3d730-57b8-4caa-ba84-2d3c8c276b29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=35651571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.35651571 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3467623454 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 5314251341 ps |
| CPU time | 39.28 seconds |
| Started | May 09 01:01:06 PM PDT 24 |
| Finished | May 09 01:01:48 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-e7b2cc99-0d03-4ea6-b1e0-8394a222ad5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3467623454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.3467623454 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1232057595 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 20938934 ps |
| CPU time | 1.92 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:11 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-8f238c05-8fcb-410b-bd3a-80484bcf6edc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1232057595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1232057595 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.1446567001 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 893507714 ps |
| CPU time | 6.75 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-4cfdefcb-b414-4268-922b-aba241940aab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446567001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1446567001 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2314876366 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2011528950 ps |
| CPU time | 6.75 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-7a9cc050-c8d7-40da-8b7d-b4f7673dfe00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2314876366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2314876366 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3674619710 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 26271257892 ps |
| CPU time | 95.04 seconds |
| Started | May 09 01:01:05 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-de5006cd-f476-4461-b81b-73fe3bb94b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674619710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3674619710 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1742389853 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 11902903490 ps |
| CPU time | 46.87 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:53 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-d4d5021e-18f9-43e4-b81d-051a04797791 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1742389853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1742389853 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3045363719 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 172033270 ps |
| CPU time | 9.13 seconds |
| Started | May 09 01:01:07 PM PDT 24 |
| Finished | May 09 01:01:19 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-fb831484-82e4-4da2-9cb7-93dbb2821a49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045363719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3045363719 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.1451697277 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5079309035 ps |
| CPU time | 10.87 seconds |
| Started | May 09 01:01:06 PM PDT 24 |
| Finished | May 09 01:01:19 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-ab86d09f-8a09-49ea-931f-e5ab499cfeca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451697277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1451697277 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.733820193 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8723189 ps |
| CPU time | 1.1 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:01:05 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-050226d2-079d-4a18-a429-e6f1417b0e55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733820193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.733820193 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.898287493 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1923523326 ps |
| CPU time | 9.1 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:16 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-4ace457e-2cac-4ef1-a1f3-87286f89169f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=898287493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.898287493 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2116508229 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 7088030472 ps |
| CPU time | 9.1 seconds |
| Started | May 09 01:01:03 PM PDT 24 |
| Finished | May 09 01:01:14 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-22926cd2-824c-4293-8e58-13da92348afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2116508229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2116508229 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3055181646 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 35190641 ps |
| CPU time | 1.29 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-e5a0934e-0a34-498a-87d1-0dd76ac8e8d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055181646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3055181646 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.605755511 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 13875312751 ps |
| CPU time | 83.5 seconds |
| Started | May 09 01:01:06 PM PDT 24 |
| Finished | May 09 01:02:32 PM PDT 24 |
| Peak memory | 203620 kb |
| Host | smart-5d5f9625-5794-4f26-92eb-26433e278109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=605755511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.605755511 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3202962340 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 8157113368 ps |
| CPU time | 60.9 seconds |
| Started | May 09 01:01:07 PM PDT 24 |
| Finished | May 09 01:02:10 PM PDT 24 |
| Peak memory | 203084 kb |
| Host | smart-30d8b15f-7594-4800-b6b6-0242b4138c28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3202962340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3202962340 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3722757755 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 306037539 ps |
| CPU time | 58.85 seconds |
| Started | May 09 01:01:02 PM PDT 24 |
| Finished | May 09 01:02:02 PM PDT 24 |
| Peak memory | 204064 kb |
| Host | smart-9b7fe87e-802c-4562-9c3f-3f7a7f77bc77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3722757755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3722757755 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1883546257 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 7055081906 ps |
| CPU time | 110.91 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:02:57 PM PDT 24 |
| Peak memory | 206148 kb |
| Host | smart-90cdfbcc-4e90-4eab-ae91-3f6a2544fd7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1883546257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.1883546257 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1128834460 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 290819483 ps |
| CPU time | 1.93 seconds |
| Started | May 09 01:01:04 PM PDT 24 |
| Finished | May 09 01:01:08 PM PDT 24 |
| Peak memory | 201900 kb |
| Host | smart-a64aac27-e48b-4322-a17f-e00f8120f8b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1128834460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1128834460 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.560865905 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 973648980 ps |
| CPU time | 18.83 seconds |
| Started | May 09 01:01:17 PM PDT 24 |
| Finished | May 09 01:01:41 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-1682d321-61d5-407e-89b9-9577ecc02dd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=560865905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.560865905 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.429025680 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5767413144 ps |
| CPU time | 44.55 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:02:01 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-94eaeed4-3b72-48e9-958b-54e4fb600cd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=429025680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.429025680 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.205732239 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1640340141 ps |
| CPU time | 10.94 seconds |
| Started | May 09 01:01:20 PM PDT 24 |
| Finished | May 09 01:01:34 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-2c07403d-e60c-42ee-bd59-76a9794ba8d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=205732239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.205732239 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2318835229 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 29757719 ps |
| CPU time | 3.85 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:22 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-42405254-bbf3-40ff-bb9a-be36985640bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2318835229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2318835229 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.2881545750 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 655038274 ps |
| CPU time | 11.92 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:33 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-b32740ee-a799-4462-b3f8-ffbbe5e65b1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2881545750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2881545750 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1233067504 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 130722067989 ps |
| CPU time | 121.92 seconds |
| Started | May 09 01:01:17 PM PDT 24 |
| Finished | May 09 01:03:24 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-a6adaf6d-4690-4188-ab1b-571349094530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233067504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1233067504 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.862355384 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4150322440 ps |
| CPU time | 27.83 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:01:49 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-76c59a3b-aaa9-48c5-acc2-75ec2fd333d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=862355384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.862355384 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.276828938 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9715164 ps |
| CPU time | 1.12 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:22 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-981faf4e-2305-4a22-b766-114828420e2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276828938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.276828938 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.775262997 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 52818177 ps |
| CPU time | 3.52 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:23 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-1822049a-00f2-4c5c-a831-96035aa18497 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775262997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.775262997 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.958163672 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 81264418 ps |
| CPU time | 1.69 seconds |
| Started | May 09 01:01:20 PM PDT 24 |
| Finished | May 09 01:01:25 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-36879136-44f1-409e-ba0e-f9f936cde1dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958163672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.958163672 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4102002084 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3984619836 ps |
| CPU time | 11.37 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:31 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-e42fcb69-7f25-4ac7-905d-cee60cfe51e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102002084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4102002084 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1784146172 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 6737194694 ps |
| CPU time | 10.85 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:31 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-0375708f-c979-4775-9000-572ca6a851b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1784146172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1784146172 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3568026058 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 11696130 ps |
| CPU time | 1.21 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:21 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-2914a4d8-796c-4ae4-85a3-4d33473dd88b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568026058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3568026058 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.910288390 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2649109666 ps |
| CPU time | 35.38 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-f00531aa-1673-4a2f-bf70-f75caa474609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=910288390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.910288390 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1414908684 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2263553728 ps |
| CPU time | 33.71 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:51 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-cc5e11fa-bb4e-471a-b2ff-6b3bdc16c254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1414908684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1414908684 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2672858242 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 65591876 ps |
| CPU time | 23.35 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:41 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-1c6e10c4-df51-4f16-a21e-6565d2dc397f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2672858242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2672858242 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.179612325 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 760780925 ps |
| CPU time | 18.5 seconds |
| Started | May 09 01:01:17 PM PDT 24 |
| Finished | May 09 01:01:41 PM PDT 24 |
| Peak memory | 203028 kb |
| Host | smart-3db9a237-836e-4ac0-968c-fce416e16a22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=179612325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res et_error.179612325 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.878896699 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 31653849 ps |
| CPU time | 2.99 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:20 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-5a11d002-4bbf-4027-a480-7413c2bdfca0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=878896699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.878896699 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1245209700 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 59300082 ps |
| CPU time | 9.29 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:26 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-1f0a74a1-b4f8-4733-a7fa-9f7539f4e2bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1245209700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1245209700 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2114174836 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2298834932 ps |
| CPU time | 19.12 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:01:40 PM PDT 24 |
| Peak memory | 202332 kb |
| Host | smart-13aa9e4d-f08f-45bb-9d4b-32d2519941a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2114174836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2114174836 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.637249447 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 375839494 ps |
| CPU time | 7.49 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:26 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-5fc191de-8adc-4b28-b29b-a621b60976c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=637249447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.637249447 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.3329646625 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2674422935 ps |
| CPU time | 11.03 seconds |
| Started | May 09 01:01:13 PM PDT 24 |
| Finished | May 09 01:01:26 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-bbdf2c5f-d380-401b-9c5e-0023379140bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3329646625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3329646625 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.527733116 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 96166912 ps |
| CPU time | 2.09 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:21 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-a85dd3d0-cdfb-4fb7-941f-6ddd6d4e1256 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=527733116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.527733116 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2154801421 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 52138876100 ps |
| CPU time | 102.38 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:03:04 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-3148075e-0e01-480a-b9dc-709552360e45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154801421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2154801421 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1406485708 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 5625722205 ps |
| CPU time | 38.75 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-a2831dce-1ae7-4b41-b86c-7c76aa893259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1406485708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1406485708 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.32247001 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 70708987 ps |
| CPU time | 4.79 seconds |
| Started | May 09 01:01:19 PM PDT 24 |
| Finished | May 09 01:01:28 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-8735d245-d3d6-4d59-81a6-27c87eec9727 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.32247001 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3950133639 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 327880899 ps |
| CPU time | 3.29 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:24 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-97dfbbb8-95ea-4b08-8711-89d6d27629cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3950133639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3950133639 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2757618951 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 53743120 ps |
| CPU time | 1.6 seconds |
| Started | May 09 01:01:13 PM PDT 24 |
| Finished | May 09 01:01:19 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-2a59755b-6cf4-448f-9aaf-060fb922970c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2757618951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2757618951 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.109977836 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3677031972 ps |
| CPU time | 12.59 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:33 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-2ccb7b23-898d-49b2-aa13-df0b3e2734c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=109977836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.109977836 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3272514189 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 809843931 ps |
| CPU time | 5.02 seconds |
| Started | May 09 01:01:19 PM PDT 24 |
| Finished | May 09 01:01:28 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-bce09ed3-2478-4fd8-b54f-10dd943ef2e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3272514189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3272514189 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.4206419923 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8227055 ps |
| CPU time | 1.11 seconds |
| Started | May 09 01:01:18 PM PDT 24 |
| Finished | May 09 01:01:24 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-c60fb38b-9cdf-42d6-a914-69830070dd73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206419923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.4206419923 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1614679421 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 777057721 ps |
| CPU time | 15.89 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-48c80564-0d27-4caa-9441-a9142d396cde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1614679421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1614679421 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.507667281 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 449551153 ps |
| CPU time | 38.72 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:02:00 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-e0b5bc7d-b8bd-458a-9c3d-995c31492880 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=507667281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.507667281 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2112953576 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 167146408 ps |
| CPU time | 17.43 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:01:39 PM PDT 24 |
| Peak memory | 203992 kb |
| Host | smart-7beaa5f1-62eb-4824-8d0f-04f939b311e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2112953576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2112953576 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.165188082 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 403766317 ps |
| CPU time | 27.85 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:47 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-15b0ccd0-057c-4c18-9141-dfd411e12cd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=165188082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.165188082 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2550917613 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 52149125 ps |
| CPU time | 3.95 seconds |
| Started | May 09 01:01:17 PM PDT 24 |
| Finished | May 09 01:01:26 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-1b5ef431-72a8-47c8-bbfd-8715ae9d0d33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2550917613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2550917613 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2048100005 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 553213013 ps |
| CPU time | 11.26 seconds |
| Started | May 09 12:59:04 PM PDT 24 |
| Finished | May 09 12:59:16 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-19ba6961-5b52-4223-9b30-fdd897e95a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048100005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2048100005 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1625295110 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 41469518991 ps |
| CPU time | 241.68 seconds |
| Started | May 09 12:59:08 PM PDT 24 |
| Finished | May 09 01:03:11 PM PDT 24 |
| Peak memory | 203104 kb |
| Host | smart-a8c3fb37-8632-4a6d-bb36-f321b361d3a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1625295110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1625295110 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1586573866 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 707746619 ps |
| CPU time | 11.6 seconds |
| Started | May 09 12:59:06 PM PDT 24 |
| Finished | May 09 12:59:19 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-2b2e3b10-c550-4db5-8a26-1c6b2cce5056 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1586573866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1586573866 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.42759621 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 99176909 ps |
| CPU time | 5.03 seconds |
| Started | May 09 12:59:08 PM PDT 24 |
| Finished | May 09 12:59:15 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-9b04b3f5-0cbf-4075-9365-5f788d11a1cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=42759621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.42759621 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.2408377503 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 10997350 ps |
| CPU time | 1.3 seconds |
| Started | May 09 12:59:06 PM PDT 24 |
| Finished | May 09 12:59:09 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-603f9c18-607c-4b7d-b003-5472cc946c0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2408377503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2408377503 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2832386754 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 79518849827 ps |
| CPU time | 114.76 seconds |
| Started | May 09 12:59:08 PM PDT 24 |
| Finished | May 09 01:01:04 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-5a5594d1-492f-4995-b345-2562ba0e113b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832386754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2832386754 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3539678615 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 23342811208 ps |
| CPU time | 103.39 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 01:00:51 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-def962ea-a8e1-4d72-b28a-7572779255f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3539678615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3539678615 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1977933145 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 130395381 ps |
| CPU time | 7.17 seconds |
| Started | May 09 12:59:03 PM PDT 24 |
| Finished | May 09 12:59:11 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-e9feb4e0-babb-484c-9765-b85482fb8e32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977933145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1977933145 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3797948388 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 903397483 ps |
| CPU time | 7.99 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:16 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-789d321d-3f5a-44a9-8ad5-4f152d0244f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3797948388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3797948388 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2269561948 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 27496183 ps |
| CPU time | 1.03 seconds |
| Started | May 09 12:58:54 PM PDT 24 |
| Finished | May 09 12:58:57 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-837ba39c-c921-40f5-a358-b1a094ea70a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2269561948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2269561948 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4276228473 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1404528786 ps |
| CPU time | 6.22 seconds |
| Started | May 09 12:59:07 PM PDT 24 |
| Finished | May 09 12:59:15 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-354b3bf0-b48c-4c48-81ac-0b3fbd28464b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276228473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4276228473 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.308378648 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1242418780 ps |
| CPU time | 5.31 seconds |
| Started | May 09 12:59:03 PM PDT 24 |
| Finished | May 09 12:59:10 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-1cead59e-7031-4257-ab90-dc0a2d5ecb9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=308378648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.308378648 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.4016555054 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 10985734 ps |
| CPU time | 1.17 seconds |
| Started | May 09 12:59:03 PM PDT 24 |
| Finished | May 09 12:59:06 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-c5638f2c-7ea5-4d3f-abd7-f766643b8bfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016555054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.4016555054 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3837168813 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 105950347 ps |
| CPU time | 14.6 seconds |
| Started | May 09 12:59:03 PM PDT 24 |
| Finished | May 09 12:59:19 PM PDT 24 |
| Peak memory | 202700 kb |
| Host | smart-87ae3855-4126-4b59-9071-1f3cc8fab3bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3837168813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3837168813 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3134039549 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7646645813 ps |
| CPU time | 63.51 seconds |
| Started | May 09 12:59:04 PM PDT 24 |
| Finished | May 09 01:00:09 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-84291bb0-cfbd-4811-92b6-7df1dea15033 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3134039549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3134039549 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3378943956 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 37930659 ps |
| CPU time | 20.61 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:26 PM PDT 24 |
| Peak memory | 203048 kb |
| Host | smart-0399f93c-0f4c-4a7b-9084-6ddaeac74d3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3378943956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3378943956 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2138429117 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 162926979 ps |
| CPU time | 10.1 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:18 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-d2616951-f4f4-4997-890f-6ab8eccf7f84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2138429117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.2138429117 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3463900410 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 10433477 ps |
| CPU time | 1.03 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:08 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-4dd7b377-a0d7-49d7-80b2-d91ed967fc34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463900410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3463900410 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1541567311 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 40553453 ps |
| CPU time | 8.65 seconds |
| Started | May 09 01:01:20 PM PDT 24 |
| Finished | May 09 01:01:32 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-1a9fab3a-da64-4c51-a093-83a02cf3b19a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1541567311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1541567311 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.295248566 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 33335812774 ps |
| CPU time | 110.7 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:03:12 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-d941d364-f21a-4552-8014-61c8809708e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=295248566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.295248566 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1570434449 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 434799102 ps |
| CPU time | 8.72 seconds |
| Started | May 09 01:01:18 PM PDT 24 |
| Finished | May 09 01:01:31 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-e0ad8a79-8dfe-43c2-8dc9-fefbfe8e940c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570434449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1570434449 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.2546002541 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1361195168 ps |
| CPU time | 9.35 seconds |
| Started | May 09 01:01:14 PM PDT 24 |
| Finished | May 09 01:01:27 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-e798631f-305d-497a-a14a-3e16cf4443c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2546002541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2546002541 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2843051114 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 66066104 ps |
| CPU time | 5.74 seconds |
| Started | May 09 01:01:18 PM PDT 24 |
| Finished | May 09 01:01:28 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-4c1a184c-42f9-4ab1-97ee-f017b945eb49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2843051114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2843051114 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.4282565033 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 8974352640 ps |
| CPU time | 25.76 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-67cdd4ad-66d3-458c-8143-8090bd2a23ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4282565033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4282565033 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2038331986 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 53135207 ps |
| CPU time | 2.15 seconds |
| Started | May 09 01:01:20 PM PDT 24 |
| Finished | May 09 01:01:26 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-b58aa786-7fad-4647-bb29-06b79c7aeacc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038331986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2038331986 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.2638546426 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1129344553 ps |
| CPU time | 9.08 seconds |
| Started | May 09 01:01:18 PM PDT 24 |
| Finished | May 09 01:01:32 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-bd7ae837-a2c5-48ff-9af3-7bd3b5c07c84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2638546426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2638546426 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.496350648 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 25414824 ps |
| CPU time | 1.17 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:01:22 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-d6e0a06d-179b-49c9-865c-f577b768cadb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=496350648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.496350648 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1822076410 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2056767939 ps |
| CPU time | 10.44 seconds |
| Started | May 09 01:01:16 PM PDT 24 |
| Finished | May 09 01:01:32 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-3ac9292a-9270-4fa2-8767-2abda11d0bd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822076410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1822076410 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1815889811 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5732460724 ps |
| CPU time | 7.35 seconds |
| Started | May 09 01:01:15 PM PDT 24 |
| Finished | May 09 01:01:28 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-be87103f-c9c8-47b9-8d35-54b0838fb7f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1815889811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1815889811 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1093720171 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8001448 ps |
| CPU time | 1.06 seconds |
| Started | May 09 01:01:13 PM PDT 24 |
| Finished | May 09 01:01:18 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-b62e4831-3a23-4acb-86ca-fc4b637c8fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093720171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1093720171 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3459676486 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 7218264804 ps |
| CPU time | 59.37 seconds |
| Started | May 09 01:01:18 PM PDT 24 |
| Finished | May 09 01:02:22 PM PDT 24 |
| Peak memory | 203052 kb |
| Host | smart-0422fdf0-bf26-4ca4-8693-e3c06837b442 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3459676486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3459676486 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.985558664 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2072248735 ps |
| CPU time | 22.76 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:57 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-65eb47d2-ad8c-4e7b-8656-0e2b00af01ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=985558664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.985558664 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.362831437 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 374665211 ps |
| CPU time | 75.73 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:02:50 PM PDT 24 |
| Peak memory | 204260 kb |
| Host | smart-30512a05-bf29-4603-a35f-97bdbf67ca6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362831437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand _reset.362831437 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.508588782 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 120730090 ps |
| CPU time | 20.77 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:52 PM PDT 24 |
| Peak memory | 203040 kb |
| Host | smart-7640823f-1a55-4ee0-8166-764a1ddbafdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=508588782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res et_error.508588782 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2060758082 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10462892 ps |
| CPU time | 1.1 seconds |
| Started | May 09 01:01:18 PM PDT 24 |
| Finished | May 09 01:01:24 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-c115ec06-911e-4506-8b69-d8cfe6dde4d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2060758082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2060758082 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1230202115 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 995280913 ps |
| CPU time | 4.1 seconds |
| Started | May 09 01:01:28 PM PDT 24 |
| Finished | May 09 01:01:35 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-b15190c8-dc55-408b-89d3-640741aae653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1230202115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1230202115 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2862339683 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 24072863233 ps |
| CPU time | 156.93 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:04:08 PM PDT 24 |
| Peak memory | 202696 kb |
| Host | smart-7f0be527-16d8-4bc0-8769-c3b01ad744a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2862339683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2862339683 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2713618394 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 548256145 ps |
| CPU time | 5.39 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-a248c420-b653-4da7-adf0-df13712c3aca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2713618394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2713618394 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3104576687 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 573876831 ps |
| CPU time | 9.98 seconds |
| Started | May 09 01:01:32 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-c14b48c8-33ef-4ded-90ec-7116dbd437d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3104576687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3104576687 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.279803770 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1625010575 ps |
| CPU time | 11.23 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-979c646c-51e8-4748-afc0-3b0da10cb802 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=279803770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.279803770 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3049133401 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 17325225834 ps |
| CPU time | 69.93 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-dbb260c6-e53e-45a6-b013-28f68ed3c383 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049133401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3049133401 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.524151108 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 17149792773 ps |
| CPU time | 125.2 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:03:38 PM PDT 24 |
| Peak memory | 202116 kb |
| Host | smart-ed517168-439d-4906-8b19-c7132478b93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=524151108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.524151108 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3307515715 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 20818460 ps |
| CPU time | 2.36 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:34 PM PDT 24 |
| Peak memory | 201924 kb |
| Host | smart-f874bdfd-690a-4e40-a039-65a214cb3e7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307515715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3307515715 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1040352962 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 79892663 ps |
| CPU time | 2.72 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-ab7be1a1-4d31-4e4f-9389-6065e42b7582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1040352962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1040352962 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.116174179 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 29446838 ps |
| CPU time | 1.26 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:33 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-94ea79a5-1696-4216-b281-91b4cb4c2fd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=116174179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.116174179 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.28171660 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5609921076 ps |
| CPU time | 10.33 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:01:43 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-b57d4a34-7f23-4960-a56f-66978e8f0d17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.28171660 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.37546019 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 10585133699 ps |
| CPU time | 8.59 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:01:42 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-5417f237-b6cd-4bc9-8951-810aa6bfd5ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=37546019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.37546019 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.38283878 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 7900494 ps |
| CPU time | 1.05 seconds |
| Started | May 09 01:01:36 PM PDT 24 |
| Finished | May 09 01:01:38 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-fa315a55-545b-4671-9d29-cb859914ebdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38283878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.38283878 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2419567169 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 56494193 ps |
| CPU time | 6.95 seconds |
| Started | May 09 01:01:34 PM PDT 24 |
| Finished | May 09 01:01:42 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-ae0007ca-7405-47f2-879f-81210a7a5ed3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419567169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2419567169 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2245719366 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4442770294 ps |
| CPU time | 29.54 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:02:04 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-0f000118-1648-4eb7-b407-698e107d9978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2245719366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2245719366 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3344048775 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 192507705 ps |
| CPU time | 13.42 seconds |
| Started | May 09 01:01:28 PM PDT 24 |
| Finished | May 09 01:01:44 PM PDT 24 |
| Peak memory | 203052 kb |
| Host | smart-fa5aface-dca1-4ca7-8470-2b0fd98ebe88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3344048775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3344048775 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.998654496 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1274121202 ps |
| CPU time | 75.24 seconds |
| Started | May 09 01:01:34 PM PDT 24 |
| Finished | May 09 01:02:51 PM PDT 24 |
| Peak memory | 204020 kb |
| Host | smart-4abed9e7-c9b6-4de1-aea9-76ae09d9bf3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=998654496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res et_error.998654496 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1786891376 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 749725094 ps |
| CPU time | 9.13 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:41 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-88be8e2c-fd82-4d19-b454-61e03b1ab508 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1786891376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1786891376 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.112891003 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 37740156 ps |
| CPU time | 4.06 seconds |
| Started | May 09 01:01:32 PM PDT 24 |
| Finished | May 09 01:01:39 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-d0dbcb0c-c6be-4b04-a56f-500260379daa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=112891003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.112891003 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.438712994 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 83890489094 ps |
| CPU time | 189.97 seconds |
| Started | May 09 01:01:27 PM PDT 24 |
| Finished | May 09 01:04:39 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-a9100216-ee67-4903-aeea-a780820b5b54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=438712994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.438712994 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1480144940 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2118736498 ps |
| CPU time | 6.77 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:01:40 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-8f07ffef-4a26-41e1-992d-c4faa2b5022b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1480144940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1480144940 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3551818413 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 85825641 ps |
| CPU time | 5.1 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-120437ad-b7a0-4868-8bbd-1e7a01f81bca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3551818413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3551818413 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2777168055 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2775654757 ps |
| CPU time | 11.81 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-fcf5578a-bdac-4ff8-b60d-8d748def45be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2777168055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2777168055 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3520319836 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 23050385339 ps |
| CPU time | 49.22 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:02:24 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-e5800b59-2b82-45e7-9150-823b27e61c33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520319836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3520319836 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1480814481 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 59346869206 ps |
| CPU time | 85.75 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:02:59 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-e2101122-5838-4dfc-9300-7b8c94978b85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1480814481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1480814481 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3967196642 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 299641141 ps |
| CPU time | 4.46 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:36 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-30b6ca97-2a1c-4da6-94a4-9c564e0afbd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967196642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3967196642 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1647411305 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 186240382 ps |
| CPU time | 3.27 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:34 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-1ef01dc3-fccd-4b46-97de-0cea0f2e417d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1647411305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1647411305 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.1532237620 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9598637 ps |
| CPU time | 1.21 seconds |
| Started | May 09 01:01:32 PM PDT 24 |
| Finished | May 09 01:01:36 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-35e7a57a-835d-40e0-bf07-d3f7f791536a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532237620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1532237620 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2562966384 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1519728049 ps |
| CPU time | 6.3 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:01:40 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-ee9f4df9-c2c3-494d-8493-c034092c92c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562966384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2562966384 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1858719243 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1081263156 ps |
| CPU time | 6.54 seconds |
| Started | May 09 01:01:28 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-3def3e0b-bcf7-4497-9695-025005c70c91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1858719243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1858719243 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.132692520 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 14711224 ps |
| CPU time | 1.01 seconds |
| Started | May 09 01:01:32 PM PDT 24 |
| Finished | May 09 01:01:36 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-d8aa6c38-41ba-4e0e-8fce-ae3ea1c3d55b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132692520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.132692520 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.999297869 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4880935686 ps |
| CPU time | 60.08 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:02:34 PM PDT 24 |
| Peak memory | 203064 kb |
| Host | smart-4d1892e8-d5a1-4719-a180-ffac85dbd03b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=999297869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.999297869 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1482624343 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 644579468 ps |
| CPU time | 47.53 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:02:21 PM PDT 24 |
| Peak memory | 203008 kb |
| Host | smart-4c43dad6-4cf4-4722-bf02-21cff917056a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1482624343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1482624343 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.934680110 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 459171704 ps |
| CPU time | 62.9 seconds |
| Started | May 09 01:01:30 PM PDT 24 |
| Finished | May 09 01:02:36 PM PDT 24 |
| Peak memory | 205472 kb |
| Host | smart-fc844c4e-e025-47e4-9d65-300497ed2613 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=934680110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res et_error.934680110 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2740345942 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 213760723 ps |
| CPU time | 5.06 seconds |
| Started | May 09 01:01:33 PM PDT 24 |
| Finished | May 09 01:01:40 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-34911dee-5af2-4369-8bed-ad0e61f61be3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2740345942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2740345942 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1682056463 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 149805307 ps |
| CPU time | 4.64 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:49 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-f5643a58-c509-415c-a91b-73946d6b356c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1682056463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1682056463 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2733134470 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 32885278587 ps |
| CPU time | 203.47 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:05:08 PM PDT 24 |
| Peak memory | 203220 kb |
| Host | smart-a8f88cc2-af85-4247-9e4f-00f49776c232 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2733134470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2733134470 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1552433454 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1231188891 ps |
| CPU time | 8.03 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:01:54 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-0f81ac2f-350c-4135-8e8a-301d5d80251c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1552433454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1552433454 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.3759559378 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 12849567 ps |
| CPU time | 1.39 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:43 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-b1ca66d8-0dab-452a-979d-3d99b81a9229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3759559378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3759559378 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2153230178 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 592817517 ps |
| CPU time | 10.93 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-b93a95e4-1858-421b-aa9a-281b368c7c9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2153230178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2153230178 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2143736440 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 41372156443 ps |
| CPU time | 161.14 seconds |
| Started | May 09 01:01:39 PM PDT 24 |
| Finished | May 09 01:04:21 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-680ddd05-aa37-45e3-bc3a-4c702459c533 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143736440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2143736440 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2876126089 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 3625988531 ps |
| CPU time | 19.59 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:02:05 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-8ba00dfd-7f92-40a5-a4e5-2dee525320cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2876126089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2876126089 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.615222229 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 28204743 ps |
| CPU time | 2.61 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:01:49 PM PDT 24 |
| Peak memory | 201924 kb |
| Host | smart-023e7aae-5261-4127-89e0-8a08bc2bfe26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615222229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.615222229 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.3787268157 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 36876683 ps |
| CPU time | 2.11 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:47 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-5de66b55-6647-440f-8d27-6151db1a0a16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3787268157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3787268157 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1867551073 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 10956873 ps |
| CPU time | 1.09 seconds |
| Started | May 09 01:01:29 PM PDT 24 |
| Finished | May 09 01:01:32 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-76d56afa-64e3-4374-b04d-def3738425c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1867551073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1867551073 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.463698275 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2460928215 ps |
| CPU time | 9.42 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:43 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-5fa38809-0310-421c-a29f-18bea53d41e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=463698275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.463698275 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.791991866 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 856724116 ps |
| CPU time | 6.6 seconds |
| Started | May 09 01:01:31 PM PDT 24 |
| Finished | May 09 01:01:41 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-9e53c8eb-4c4f-4976-a70c-b4b435fbde3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=791991866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.791991866 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4193811684 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 10094283 ps |
| CPU time | 1.23 seconds |
| Started | May 09 01:01:28 PM PDT 24 |
| Finished | May 09 01:01:32 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-c2473aa8-6def-471d-b892-aec8ba24998e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193811684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4193811684 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3879777947 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 225489901 ps |
| CPU time | 18.49 seconds |
| Started | May 09 01:01:39 PM PDT 24 |
| Finished | May 09 01:01:59 PM PDT 24 |
| Peak memory | 202664 kb |
| Host | smart-e80e3121-3f4a-4230-b69b-4ed1866f0a91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3879777947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3879777947 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3370622982 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 21487712599 ps |
| CPU time | 100.27 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:03:23 PM PDT 24 |
| Peak memory | 203216 kb |
| Host | smart-a95b12b6-4bb1-4334-8c5c-dd39cd195e97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3370622982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3370622982 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.806155625 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4611511047 ps |
| CPU time | 99.09 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:03:25 PM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-102c574c-5519-4d75-96cb-de82d614b4e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=806155625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res et_error.806155625 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4134508399 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 40566985 ps |
| CPU time | 4 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-2b2673ea-1707-445a-8993-72702c72d589 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134508399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4134508399 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.801296046 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 68547524 ps |
| CPU time | 11.09 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-72615097-6796-4b08-a4a1-cb6f29bf5c4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=801296046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.801296046 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3103970424 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 17975964914 ps |
| CPU time | 113.62 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:03:35 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-77ecb19f-9b4c-42a2-a431-27ee1f9c0b64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3103970424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3103970424 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3446348642 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 434646887 ps |
| CPU time | 4.66 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:50 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-733aaefd-6801-4a78-b2ed-56b90d4d4607 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446348642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3446348642 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2389991986 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 13448597 ps |
| CPU time | 1.49 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-0fdb6487-ba8e-4537-a3dc-b31d6ab2effc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2389991986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2389991986 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.779046845 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 168966993 ps |
| CPU time | 2.93 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-b89ffc60-02cd-4135-9f75-011e744c2d6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=779046845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.779046845 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2027148963 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 21734963870 ps |
| CPU time | 74.96 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:03:01 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-5a91969c-f7eb-4616-95c0-327d7034211f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027148963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2027148963 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1585958127 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7938980044 ps |
| CPU time | 27.19 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:02:11 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-7452aae9-0589-4d71-883d-f796b03b222a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1585958127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1585958127 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2012454834 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 65363953 ps |
| CPU time | 8.08 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:50 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-23edd48f-554e-4322-95be-5beba1a1c176 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012454834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2012454834 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.990374631 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1845092103 ps |
| CPU time | 8.2 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:51 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-62a6bba0-d968-4047-8dde-8f6f5562cbc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=990374631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.990374631 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1090158131 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 76494097 ps |
| CPU time | 1.33 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-223f8f14-690d-4808-9ac2-df376f079fc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1090158131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1090158131 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.963364710 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2411878970 ps |
| CPU time | 11.41 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-dc11b0e2-c350-497b-a5c6-34c90fc17a73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=963364710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.963364710 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1912706737 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 6256835091 ps |
| CPU time | 7.47 seconds |
| Started | May 09 01:01:38 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 201924 kb |
| Host | smart-a05d19c3-3a6f-4994-a12a-5b27828ba76b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1912706737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1912706737 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2173264184 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 18912560 ps |
| CPU time | 1.15 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:43 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-02435f5c-08a9-4433-814a-8edd2115785c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173264184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2173264184 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.115384856 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13537620622 ps |
| CPU time | 45.96 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:02:30 PM PDT 24 |
| Peak memory | 203536 kb |
| Host | smart-493aa942-ba17-4d59-b774-536714283e34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=115384856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.115384856 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.907345601 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1474775579 ps |
| CPU time | 9.5 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:51 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-6b9a33b4-8a01-42fc-a8ca-5eae5ed35867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=907345601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.907345601 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1627554184 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 659036944 ps |
| CPU time | 110.49 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:03:37 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-4800673b-8586-43a8-a44d-33701b89b44f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1627554184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1627554184 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.762606423 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 38911567 ps |
| CPU time | 3.4 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:01:50 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-e5a30cd0-e0b8-4ab7-89f1-f1ba2716cda4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762606423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.762606423 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.192445233 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 517759837 ps |
| CPU time | 12.37 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-21a9eff2-cfa0-42df-a36a-d5b054b7d7a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=192445233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.192445233 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3187740919 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 118240822271 ps |
| CPU time | 301.08 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:06:47 PM PDT 24 |
| Peak memory | 202996 kb |
| Host | smart-873b33c2-c6f0-4b66-8646-598a133d8808 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3187740919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.3187740919 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1223776960 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 21618617 ps |
| CPU time | 2.6 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-af6d6fed-bab8-49a0-afb0-9f19a153fb77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223776960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1223776960 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.3779502367 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 221931286 ps |
| CPU time | 3.99 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:48 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-20a83f3f-d3a2-4a21-9241-0c3dd3647b1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3779502367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3779502367 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.471005040 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 314148165 ps |
| CPU time | 4.6 seconds |
| Started | May 09 01:01:39 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-ed8ebd52-3d45-4c1e-b23c-442b165d30b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=471005040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.471005040 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3241010579 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 33011630603 ps |
| CPU time | 155.8 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:04:21 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-0f715bdd-5edf-4810-967f-3ab751c132c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241010579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3241010579 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2469560647 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1623732369 ps |
| CPU time | 7.28 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:01:54 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-884f8740-9d65-4edf-83c8-b0ba6e155c1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2469560647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2469560647 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1949296738 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 44005007 ps |
| CPU time | 5 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:48 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-27db0c8e-ba68-4958-80ff-3133966abf23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949296738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1949296738 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1140193722 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 925325958 ps |
| CPU time | 10.83 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-d18c1f26-b99d-43e5-aae7-60bf8835dab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1140193722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1140193722 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.2388464688 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 71249293 ps |
| CPU time | 1.7 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-b80cf4c6-e1df-44e5-ae30-437f16577a65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388464688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2388464688 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1165237865 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4090296528 ps |
| CPU time | 9.86 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:02:02 PM PDT 24 |
| Peak memory | 202340 kb |
| Host | smart-8489434c-ba61-490e-a359-57d0fe2fea79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165237865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1165237865 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.4032372383 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 475415987 ps |
| CPU time | 4.1 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:50 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-b797f166-8f79-40ec-8277-61168d3b9bdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4032372383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.4032372383 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1154793765 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10917471 ps |
| CPU time | 1.39 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:47 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-4983cdf1-7e68-4adf-a705-261265b7553f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154793765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1154793765 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1494469610 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 12820942838 ps |
| CPU time | 67.24 seconds |
| Started | May 09 01:01:40 PM PDT 24 |
| Finished | May 09 01:02:50 PM PDT 24 |
| Peak memory | 203036 kb |
| Host | smart-37cc8644-8f40-4c12-85a8-31513c83e9e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1494469610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1494469610 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3484767134 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 619847118 ps |
| CPU time | 14.05 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:02:00 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-212f0ca4-547c-40b5-8f9b-aacde37fbebf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484767134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3484767134 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2548175681 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 54937621 ps |
| CPU time | 8.13 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:51 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-eced5897-05b7-46d5-a8b8-b60167e8ce5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2548175681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.2548175681 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2334602025 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 840984618 ps |
| CPU time | 119.12 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:03:44 PM PDT 24 |
| Peak memory | 207672 kb |
| Host | smart-187232fe-b3f4-4bc4-8353-8f17231aa4c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334602025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2334602025 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.931192862 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 93918882 ps |
| CPU time | 2.28 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:46 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-0b879fe7-3d67-4abb-b181-eb941e55128f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931192862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.931192862 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3362340882 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 38356572 ps |
| CPU time | 10.02 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:54 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-e6c7ded9-1145-4422-97c4-1a30ae5a73bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3362340882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3362340882 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.519654678 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 70598140536 ps |
| CPU time | 292.86 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:06:38 PM PDT 24 |
| Peak memory | 203680 kb |
| Host | smart-1e938aaf-240d-4496-ad46-38626c76026c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=519654678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.519654678 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1914435873 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 145653341 ps |
| CPU time | 3.52 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:49 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-aed7d50d-0e8d-42f8-99f0-26bf99a299bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1914435873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1914435873 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.825764154 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 598196975 ps |
| CPU time | 9.83 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 201900 kb |
| Host | smart-c8dbc54f-f324-4ad2-9213-3a7540a42c9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825764154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.825764154 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.2679829142 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 473505849 ps |
| CPU time | 6.22 seconds |
| Started | May 09 01:01:45 PM PDT 24 |
| Finished | May 09 01:01:54 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-3eec9a4f-d73c-4294-bafc-fa0e4a67339d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2679829142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2679829142 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1434925175 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 9443052790 ps |
| CPU time | 36.53 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:02:21 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-fcbc54bc-73fe-4aff-8c36-8578f78f1d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434925175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1434925175 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3555409694 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 23096483525 ps |
| CPU time | 36.53 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:02:23 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-d15d7a94-c37d-4b0e-b178-5ac9d0d22f1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3555409694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3555409694 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1585425455 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 95765928 ps |
| CPU time | 4.13 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:01:51 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-2a7d0d3d-9774-42f8-bb38-d69059a71e39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585425455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1585425455 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.3203142388 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 43261664 ps |
| CPU time | 3.92 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-587b1a90-3fd5-401c-bbc8-ce19ca9a6b76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3203142388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3203142388 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1062207147 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 22389427 ps |
| CPU time | 1.13 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:44 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-28ba5a81-30c2-49c4-8183-e5593365fda3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1062207147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1062207147 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2290220326 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1963875545 ps |
| CPU time | 10.42 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:01:57 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-41cd510e-240c-4cf4-b439-1f88fbedaa01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290220326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2290220326 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3050178754 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2121279859 ps |
| CPU time | 7.34 seconds |
| Started | May 09 01:01:42 PM PDT 24 |
| Finished | May 09 01:01:53 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-0513f97c-f7bc-4f4f-a857-0410dedc91c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3050178754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3050178754 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.4179910553 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 28393782 ps |
| CPU time | 1.2 seconds |
| Started | May 09 01:01:41 PM PDT 24 |
| Finished | May 09 01:01:45 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-23d1cb76-d4fb-44b8-a076-955255b5fedc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179910553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.4179910553 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3740660458 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1652543292 ps |
| CPU time | 19.43 seconds |
| Started | May 09 01:01:43 PM PDT 24 |
| Finished | May 09 01:02:06 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-d07c6e78-b359-43f4-9226-edbba39eae91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740660458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3740660458 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.883133531 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 208202976 ps |
| CPU time | 23.76 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:16 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-328bb0ce-0655-40b7-b2bb-87408801453f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883133531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.883133531 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3080807773 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 179643901 ps |
| CPU time | 33.27 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:02:25 PM PDT 24 |
| Peak memory | 204556 kb |
| Host | smart-f03f7c38-1c66-48ad-a133-e94a91e14a41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080807773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3080807773 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2282404084 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1502083973 ps |
| CPU time | 96.34 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:03:28 PM PDT 24 |
| Peak memory | 204088 kb |
| Host | smart-9dcfb314-ca6c-4dc6-96e3-5c53b246f803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282404084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2282404084 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2758117617 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 64511764 ps |
| CPU time | 7.1 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:59 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-501451ca-2b0e-4deb-9ef9-aff9b202f6b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758117617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2758117617 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3841263301 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2625875041 ps |
| CPU time | 16.71 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:02:07 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-d182170a-8140-412c-a3cd-9d9785fc9558 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3841263301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3841263301 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3192396494 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 25358908627 ps |
| CPU time | 53.39 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-9787f385-2460-4eb4-a025-437d876a20a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3192396494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3192396494 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2677902470 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 193006129 ps |
| CPU time | 3.94 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:01:58 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-ed199103-fa74-4fb4-b8da-7c5d38ac276d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2677902470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2677902470 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1120022452 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 78205595 ps |
| CPU time | 2 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-856148ba-5e56-4d58-be22-b9b49094535d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1120022452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1120022452 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.4260108979 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 193617676 ps |
| CPU time | 3.14 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:57 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-f0e3f73c-047f-4151-86a7-de3d1c77dd7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4260108979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.4260108979 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3842792526 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 38030715937 ps |
| CPU time | 37.83 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:32 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-4e91b35d-ec76-4276-bf8f-24ddd4149d21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842792526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3842792526 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2549888629 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 10861281215 ps |
| CPU time | 46.48 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:02:41 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-b7aabfc0-fa29-43b0-bd9c-59e7434ce5ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2549888629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2549888629 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.766818950 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 63830103 ps |
| CPU time | 3.06 seconds |
| Started | May 09 01:01:54 PM PDT 24 |
| Finished | May 09 01:01:59 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-43fccb0e-2da0-482b-96e1-140e6300683b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766818950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.766818950 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.4064704175 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 225932044 ps |
| CPU time | 3.62 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:57 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-b06070a2-04c6-401a-b2e2-28cddcc5a3a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064704175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4064704175 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.1356863187 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 9311900 ps |
| CPU time | 1.23 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:01:52 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-c2ec7790-ef44-493c-9d4c-25430da848ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1356863187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1356863187 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1522421402 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2061838028 ps |
| CPU time | 10.2 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:03 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-49dbf750-b8ea-4698-90e1-3f296d054fb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522421402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1522421402 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.704015036 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1329040089 ps |
| CPU time | 6.43 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:02:01 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-d10e00a5-931b-4cd7-90e4-693428498839 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=704015036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.704015036 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3086490595 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 10342335 ps |
| CPU time | 1.18 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:54 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-55578f57-2875-46d2-ae4f-cd349604c876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086490595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3086490595 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.150313922 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 396676131 ps |
| CPU time | 45.07 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:38 PM PDT 24 |
| Peak memory | 203024 kb |
| Host | smart-be64ba33-4217-49d7-a592-23a01327d6e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=150313922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.150313922 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.992841100 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1256209505 ps |
| CPU time | 14.02 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-1db34d98-35a7-480f-ad31-21ceb99f508e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992841100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.992841100 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.4221637164 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 181579558 ps |
| CPU time | 18.16 seconds |
| Started | May 09 01:01:48 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 202984 kb |
| Host | smart-14c5140f-0614-4c30-a7fc-0b83267f0b5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221637164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.4221637164 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3115383008 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 836803712 ps |
| CPU time | 46.42 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 203760 kb |
| Host | smart-69aef9b5-189d-4f9d-a8ad-46d5bed1e37b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3115383008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3115383008 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.635013015 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 11710469 ps |
| CPU time | 1.01 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:53 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-6bdb84a6-6fb3-4704-936f-877d7ce9c388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=635013015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.635013015 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3525833824 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 563695177 ps |
| CPU time | 11.42 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:05 PM PDT 24 |
| Peak memory | 201728 kb |
| Host | smart-22fc5cd6-5178-47f3-b364-8c90f1af7841 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3525833824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3525833824 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2119953567 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 5227456373 ps |
| CPU time | 36.27 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:29 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-a5dc31df-af7d-4fbf-b00a-9f6eeaf8c473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2119953567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2119953567 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.105917168 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1079634634 ps |
| CPU time | 5.98 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:02:00 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-0413d6f2-cd52-4906-9f1e-923cc151877e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=105917168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.105917168 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.4285212597 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 70664973 ps |
| CPU time | 1.84 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-48e5d97f-6b58-44df-996b-615f2eccba8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4285212597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4285212597 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2325848261 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 65663483 ps |
| CPU time | 5.98 seconds |
| Started | May 09 01:01:55 PM PDT 24 |
| Finished | May 09 01:02:03 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-71da56d6-e161-4391-8a71-926b4c9bac27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325848261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2325848261 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1854306363 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 9823902121 ps |
| CPU time | 42.74 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-0ccf1698-72b7-4da9-aee2-ea5929637a0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854306363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1854306363 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.385039940 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 30270122753 ps |
| CPU time | 102.06 seconds |
| Started | May 09 01:01:53 PM PDT 24 |
| Finished | May 09 01:03:37 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-3fe0fc80-ea89-430c-aff3-a3590c48e522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=385039940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.385039940 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3834431865 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 164738330 ps |
| CPU time | 7.5 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:01 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-e7dcea39-f3fe-41d7-bebd-56eadfd1c3ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834431865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3834431865 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1890248975 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 858393260 ps |
| CPU time | 9.68 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:02:04 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-e0d4be98-e778-4f2b-a974-b305d24d1a0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1890248975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1890248975 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.4013073498 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 64929428 ps |
| CPU time | 1.42 seconds |
| Started | May 09 01:01:48 PM PDT 24 |
| Finished | May 09 01:01:51 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-0f89f6ac-8684-44ee-a231-b5ecef73579c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013073498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4013073498 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2783523843 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3262044610 ps |
| CPU time | 7.28 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:01 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-a73e9f4b-b42a-49e5-ad77-a7800f34620b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783523843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2783523843 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3651371743 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1571204474 ps |
| CPU time | 8.25 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:02 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-f30cc807-df6e-4dcc-b84a-746bcb26863e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3651371743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3651371743 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.4059453890 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 9111567 ps |
| CPU time | 0.99 seconds |
| Started | May 09 01:01:54 PM PDT 24 |
| Finished | May 09 01:01:57 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-f1f82f74-bf86-477b-815b-1be600cd6480 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059453890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.4059453890 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.4234122023 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4009347239 ps |
| CPU time | 65.3 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:59 PM PDT 24 |
| Peak memory | 204136 kb |
| Host | smart-48e5974f-7043-4d04-8c63-e1b070b4069b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234122023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.4234122023 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.4172162023 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2495949587 ps |
| CPU time | 33.48 seconds |
| Started | May 09 01:01:51 PM PDT 24 |
| Finished | May 09 01:02:28 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-85aa7a06-e8b6-4673-9703-05568b2e96d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172162023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4172162023 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.687774216 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 9658716856 ps |
| CPU time | 48.55 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:41 PM PDT 24 |
| Peak memory | 204904 kb |
| Host | smart-33f54ced-b150-45eb-8f9e-d2aefc3c2f9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=687774216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand _reset.687774216 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3649557421 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5374854804 ps |
| CPU time | 125.2 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:03:57 PM PDT 24 |
| Peak memory | 208956 kb |
| Host | smart-e0de7264-574e-4b54-bde4-6a0f68b045a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3649557421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3649557421 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3943499244 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 283308728 ps |
| CPU time | 5.87 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:01:59 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-b639d60c-ec1d-42a2-abf0-13716198ae72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3943499244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3943499244 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1667378767 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 20483107 ps |
| CPU time | 3.64 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:09 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-2c9fbeb5-8f20-42ef-9c91-6479401b23c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1667378767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1667378767 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3637393059 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 227317760100 ps |
| CPU time | 281.18 seconds |
| Started | May 09 01:02:04 PM PDT 24 |
| Finished | May 09 01:06:47 PM PDT 24 |
| Peak memory | 203004 kb |
| Host | smart-2d819a02-f53e-4fac-806b-4939c42f5427 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3637393059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3637393059 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.4235883854 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 616836970 ps |
| CPU time | 7.54 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:14 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-9defaa38-ef7d-44a4-833d-ce1123cd8eee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4235883854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.4235883854 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.596064165 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 434028801 ps |
| CPU time | 5.74 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:10 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-0ec1d3fe-4aae-480e-a231-4bba43acb25f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=596064165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.596064165 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1619364371 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 115102756 ps |
| CPU time | 2.28 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:01:57 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-b13fe82c-0500-46cb-a767-8de81067f492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1619364371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1619364371 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.800050453 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 15885093861 ps |
| CPU time | 51.15 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:57 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-80a21624-7dc6-4443-9c68-fb272ade4bb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=800050453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.800050453 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.690448742 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1916541264 ps |
| CPU time | 5.4 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:09 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-ed946327-c65c-4212-a34a-b5220117509a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=690448742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.690448742 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1594370102 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 54905522 ps |
| CPU time | 4.16 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:01:59 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-84a5adb0-f457-4944-ab0c-a4baf5b3102e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594370102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1594370102 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.2788022402 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 58768782 ps |
| CPU time | 6.12 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:10 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-0b369bc8-c03c-447f-9ed2-1abbe248a3dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2788022402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2788022402 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.3077706453 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 75282364 ps |
| CPU time | 1.69 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:01:52 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-01cc782b-a15a-4913-aea3-a2f9891ccf7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3077706453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3077706453 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1038008421 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4225275843 ps |
| CPU time | 13.54 seconds |
| Started | May 09 01:01:50 PM PDT 24 |
| Finished | May 09 01:02:07 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-43ac8eb7-5e9e-4bff-a70b-c5fcc68258ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038008421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1038008421 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.604329087 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 701960680 ps |
| CPU time | 4.94 seconds |
| Started | May 09 01:01:49 PM PDT 24 |
| Finished | May 09 01:01:56 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-946d179e-25cb-4073-a132-7a76d0125a16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=604329087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.604329087 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2635477899 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 8699305 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:01:52 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-dc64a5d7-c3c0-4334-a1fa-1039688e0ab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635477899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2635477899 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.4094625144 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 794428270 ps |
| CPU time | 52.58 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:58 PM PDT 24 |
| Peak memory | 205372 kb |
| Host | smart-8dbcf8ba-1317-459b-9524-21f61a8101f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4094625144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4094625144 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2389115088 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1204353769 ps |
| CPU time | 22.35 seconds |
| Started | May 09 01:02:01 PM PDT 24 |
| Finished | May 09 01:02:24 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-a7d35867-9bd9-4c98-a8aa-108239cd9a58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2389115088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2389115088 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.36101056 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 10379262438 ps |
| CPU time | 178.58 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:05:03 PM PDT 24 |
| Peak memory | 208132 kb |
| Host | smart-2f78e012-1f18-421b-a1c8-da8a1bf88c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36101056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_ reset.36101056 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.194454403 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 425104788 ps |
| CPU time | 48.22 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:53 PM PDT 24 |
| Peak memory | 203456 kb |
| Host | smart-91a01311-492c-46b6-ab87-0d9ac46250e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194454403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res et_error.194454403 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3520975897 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2078235170 ps |
| CPU time | 9.25 seconds |
| Started | May 09 01:02:00 PM PDT 24 |
| Finished | May 09 01:02:11 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-2711096d-f204-42d4-8889-9b340d4f2243 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3520975897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3520975897 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2154543562 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2386285102 ps |
| CPU time | 20.33 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 12:59:41 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-1d759f7c-09ad-47a9-86c9-e117df7e9b88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2154543562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2154543562 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.821281236 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1663344275 ps |
| CPU time | 5.28 seconds |
| Started | May 09 12:59:21 PM PDT 24 |
| Finished | May 09 12:59:27 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-fa74a747-5968-40eb-920e-2406a8a0d2db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=821281236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.821281236 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.325793854 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1162052737 ps |
| CPU time | 14.57 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:35 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-ce8ba80b-5d34-43d0-b67b-398b8610e44a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325793854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.325793854 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.230707804 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 799660268 ps |
| CPU time | 5.57 seconds |
| Started | May 09 12:59:08 PM PDT 24 |
| Finished | May 09 12:59:15 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-5e9110c8-8cfb-49d4-af35-6f67a3b05689 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230707804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.230707804 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1161670793 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 12611368018 ps |
| CPU time | 51.54 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:59 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-e60b69e7-f0dd-4e63-af98-3cf8fa8c44f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161670793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1161670793 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1350754587 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1509999504 ps |
| CPU time | 7.38 seconds |
| Started | May 09 12:59:08 PM PDT 24 |
| Finished | May 09 12:59:17 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-f72b7e3a-f581-4cd8-a47b-5d947a6f5735 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1350754587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1350754587 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1309420344 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 89567874 ps |
| CPU time | 1.79 seconds |
| Started | May 09 12:59:06 PM PDT 24 |
| Finished | May 09 12:59:10 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-a761e684-4636-4755-af58-7c005293c09b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309420344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1309420344 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.3429020460 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 83072362 ps |
| CPU time | 2.62 seconds |
| Started | May 09 12:59:17 PM PDT 24 |
| Finished | May 09 12:59:20 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-c4f3620a-6ba6-4df0-b222-45d03dd7f8f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3429020460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3429020460 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3183911553 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 53982613 ps |
| CPU time | 1.47 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:08 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-90a99d77-15ee-480b-8a54-d0b958224a1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3183911553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3183911553 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4175367927 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3454721525 ps |
| CPU time | 10.56 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:18 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-3599c5b2-d1d1-4725-9deb-719f69398cb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175367927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4175367927 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1861595972 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3970266254 ps |
| CPU time | 10.99 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:17 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-12d689a4-1e66-40e8-a5c7-549a9211b63b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1861595972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1861595972 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.144619665 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 11116262 ps |
| CPU time | 1.1 seconds |
| Started | May 09 12:59:05 PM PDT 24 |
| Finished | May 09 12:59:07 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-04b5462d-7a8d-401b-9367-24529145a592 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144619665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.144619665 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2355326318 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 639905282 ps |
| CPU time | 33.84 seconds |
| Started | May 09 12:59:21 PM PDT 24 |
| Finished | May 09 12:59:56 PM PDT 24 |
| Peak memory | 203024 kb |
| Host | smart-3bdf52ac-d9f0-4018-8f62-e228e228c9dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2355326318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2355326318 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1452822292 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5074267357 ps |
| CPU time | 75.38 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-e66189ad-a07c-4353-830f-5af5eb5b30fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1452822292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1452822292 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2305704142 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 40893882 ps |
| CPU time | 3.1 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:23 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-71d35bd1-2074-408a-9300-cafda90c91b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2305704142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2305704142 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.182495466 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 319830303 ps |
| CPU time | 29.6 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:48 PM PDT 24 |
| Peak memory | 204056 kb |
| Host | smart-174bbd74-2f7f-449f-b958-e01b969a9173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=182495466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.182495466 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3697383562 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 146654847 ps |
| CPU time | 3.53 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:23 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-4ceb251a-51bb-4224-aca0-47318603e03e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3697383562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3697383562 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.791289560 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 12250230 ps |
| CPU time | 1.44 seconds |
| Started | May 09 01:02:04 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-8fd0d729-6ce6-4455-810e-9ab52439f6db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=791289560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.791289560 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3955283035 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 48817179440 ps |
| CPU time | 194.88 seconds |
| Started | May 09 01:02:01 PM PDT 24 |
| Finished | May 09 01:05:18 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-36345170-49d5-4f24-b900-44d23631a21b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3955283035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3955283035 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3454041216 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 42903876 ps |
| CPU time | 2.84 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 201924 kb |
| Host | smart-7bdf9ba3-af06-4881-a24d-ea07603edcd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3454041216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3454041216 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.4022497389 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1772377126 ps |
| CPU time | 13.47 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:17 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-4b6c403b-86f5-46b1-b032-a0e01b970366 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4022497389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.4022497389 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.1646431055 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3596422223 ps |
| CPU time | 11.76 seconds |
| Started | May 09 01:02:01 PM PDT 24 |
| Finished | May 09 01:02:15 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-875f4a6b-ea8d-4dbc-a0e1-e905a51c3e2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646431055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1646431055 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3732089074 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 108767267541 ps |
| CPU time | 122.28 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:04:07 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-d6aa69e6-76b0-42d3-8abb-5db10ef8e434 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732089074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3732089074 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3230821860 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 40316424510 ps |
| CPU time | 112.29 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:03:57 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-68f64eb6-368a-48c4-8417-ff5b56b880cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3230821860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3230821860 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2361877136 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 34441274 ps |
| CPU time | 4.06 seconds |
| Started | May 09 01:02:00 PM PDT 24 |
| Finished | May 09 01:02:06 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-e3fcc571-f330-438f-9403-7ce38f83f7d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361877136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2361877136 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2468762228 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1313200673 ps |
| CPU time | 10.33 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:15 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-a9d95e37-9ad3-4dbb-8f36-7730abffa23d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2468762228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2468762228 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.1248082000 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 62148527 ps |
| CPU time | 1.32 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:06 PM PDT 24 |
| Peak memory | 201924 kb |
| Host | smart-efe64837-af08-4785-a25c-20f6a755a2ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1248082000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1248082000 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.791128677 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3187087903 ps |
| CPU time | 9.35 seconds |
| Started | May 09 01:02:01 PM PDT 24 |
| Finished | May 09 01:02:12 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-1a511a77-c32c-4356-8c14-e1252b2e6dfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=791128677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.791128677 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1750807546 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2409305650 ps |
| CPU time | 9.2 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:13 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-b3e13f21-7ff7-4b2e-af5b-2ee3826918f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1750807546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1750807546 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3378779286 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10507873 ps |
| CPU time | 1.06 seconds |
| Started | May 09 01:02:01 PM PDT 24 |
| Finished | May 09 01:02:04 PM PDT 24 |
| Peak memory | 201932 kb |
| Host | smart-3c169df0-a085-4849-8ccf-f74fbf53f667 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378779286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3378779286 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3966322131 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8982364303 ps |
| CPU time | 59.88 seconds |
| Started | May 09 01:02:04 PM PDT 24 |
| Finished | May 09 01:03:06 PM PDT 24 |
| Peak memory | 203624 kb |
| Host | smart-4fb90af8-9a05-4be4-9cdd-9976b3522f20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3966322131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3966322131 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2100874711 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 10801296841 ps |
| CPU time | 29.25 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:35 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-8818a7d2-a9a2-45c3-aa9f-d09e10e04c81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100874711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2100874711 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.169760710 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3967459335 ps |
| CPU time | 176.91 seconds |
| Started | May 09 01:02:01 PM PDT 24 |
| Finished | May 09 01:05:00 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-6ac96eea-af35-4c9c-b2d5-dc33c7db7f6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=169760710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.169760710 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3872121721 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3549083571 ps |
| CPU time | 53.94 seconds |
| Started | May 09 01:02:05 PM PDT 24 |
| Finished | May 09 01:03:01 PM PDT 24 |
| Peak memory | 204140 kb |
| Host | smart-35797bad-8af3-4f2f-a372-90b523b88104 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3872121721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3872121721 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1024882768 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 53214173 ps |
| CPU time | 1.46 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:07 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-3b809e58-8369-4982-a7d9-d66ef04c0431 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1024882768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1024882768 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1129319472 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 365172726 ps |
| CPU time | 6.77 seconds |
| Started | May 09 01:02:16 PM PDT 24 |
| Finished | May 09 01:02:25 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-7e002359-52cd-4817-8657-0f4fa16b6a45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1129319472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1129319472 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2857750685 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 151575207 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:02:12 PM PDT 24 |
| Finished | May 09 01:02:15 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-d601a8cc-4bef-4685-a11f-899155252593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2857750685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2857750685 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.3261438723 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 428109030 ps |
| CPU time | 3.78 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:20 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-2c84b5f1-4f33-4f0b-8570-afeadfedcd4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261438723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3261438723 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.931754722 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 605281163 ps |
| CPU time | 12.33 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:16 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-be0e9e30-448f-4fc1-a7a2-ae309ee3e1f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931754722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.931754722 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.16866871 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 50600075068 ps |
| CPU time | 73.34 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:03:30 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-b32707f0-e30d-4d8d-b006-2dba3826057b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=16866871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.16866871 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3441907341 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 20241472737 ps |
| CPU time | 141.13 seconds |
| Started | May 09 01:02:12 PM PDT 24 |
| Finished | May 09 01:04:35 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-dd79d6f4-02ae-4b4f-8bf4-e657cbb6e7ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3441907341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3441907341 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2275055209 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 36527007 ps |
| CPU time | 4.22 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:10 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-8cac24d9-4e3c-4fa6-8b19-bb491c906b03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275055209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2275055209 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.3394176067 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 65397743 ps |
| CPU time | 4.84 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:23 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-7581a702-2153-4909-b3bb-77002475fe5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394176067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3394176067 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2936473936 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 55381689 ps |
| CPU time | 1.45 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:06 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-72f7e714-ac13-414d-b945-d4abba43b6bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2936473936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2936473936 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.167349666 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 7516202787 ps |
| CPU time | 8.61 seconds |
| Started | May 09 01:02:02 PM PDT 24 |
| Finished | May 09 01:02:14 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-ffda774f-a775-4ea6-9bfb-c7ae9bb964c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=167349666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.167349666 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3504060472 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3571946533 ps |
| CPU time | 4.99 seconds |
| Started | May 09 01:02:03 PM PDT 24 |
| Finished | May 09 01:02:11 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-571a02a3-6bb4-4118-8ac4-bafe4703b87d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3504060472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3504060472 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2153498796 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 13826865 ps |
| CPU time | 1.04 seconds |
| Started | May 09 01:02:04 PM PDT 24 |
| Finished | May 09 01:02:08 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-b2d50839-c1bc-4f90-8f10-0d28aff63c6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153498796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2153498796 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3991749851 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 183859121 ps |
| CPU time | 21.12 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:38 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-bae0a5a8-5c12-48ca-b267-144e879d59a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3991749851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3991749851 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.238197484 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 5940988088 ps |
| CPU time | 28.79 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:46 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-898299ad-f3fc-4fcf-bf67-fe8e496a4662 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=238197484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.238197484 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4236425117 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 251526445 ps |
| CPU time | 15.31 seconds |
| Started | May 09 01:02:18 PM PDT 24 |
| Finished | May 09 01:02:35 PM PDT 24 |
| Peak memory | 204056 kb |
| Host | smart-21d815e0-e31b-40fe-8379-c5b12efd6b84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4236425117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.4236425117 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1132335835 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11654674365 ps |
| CPU time | 201.53 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:05:40 PM PDT 24 |
| Peak memory | 205396 kb |
| Host | smart-12108899-8971-4154-843b-63fb2f06339e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1132335835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.1132335835 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1949231448 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 389605832 ps |
| CPU time | 4.63 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:21 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-b49db112-293f-4290-ac67-122f4b2a8729 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949231448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1949231448 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.578812449 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1979325888 ps |
| CPU time | 7.74 seconds |
| Started | May 09 01:02:16 PM PDT 24 |
| Finished | May 09 01:02:26 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-f9ac4663-f590-4983-9a8f-61d4627a5db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=578812449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.578812449 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.326960724 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 134575083 ps |
| CPU time | 2.31 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:19 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-354c9fd7-420d-4152-9dde-a0633460925f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=326960724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.326960724 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.932805080 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 194496691 ps |
| CPU time | 3.69 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:22 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-3fb209ce-f01c-4566-89ef-15f918197180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=932805080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.932805080 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.3421992748 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 348742050 ps |
| CPU time | 6.88 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:23 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-bb2240cb-eb06-4dc2-8c16-946aaf8f1229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3421992748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3421992748 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1307695687 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4086637037 ps |
| CPU time | 19.68 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:38 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-b4fef0e9-2edc-49af-9470-d56044e2fd9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307695687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1307695687 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2825755629 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 12864999080 ps |
| CPU time | 29.23 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:46 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-41081c6b-ed95-4aad-811b-b34607f1fe0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2825755629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2825755629 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.581423979 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 17291587 ps |
| CPU time | 1.64 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:20 PM PDT 24 |
| Peak memory | 201900 kb |
| Host | smart-a70dd0f1-ed79-4c46-a7dc-ca4ea2f1cb2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581423979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.581423979 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3343089669 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 164816368 ps |
| CPU time | 2.44 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:21 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-3f708583-01d4-4621-8dcc-c8b1ccf6ad48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3343089669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3343089669 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.1505452382 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 8966483 ps |
| CPU time | 1.24 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:19 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-364480e9-100e-4520-99df-6b2f4387cacf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505452382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1505452382 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.325367460 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3938829673 ps |
| CPU time | 7.9 seconds |
| Started | May 09 01:02:16 PM PDT 24 |
| Finished | May 09 01:02:27 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-78f33165-9160-485d-9a6e-e2ffc1a590fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=325367460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.325367460 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.517663963 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4244788819 ps |
| CPU time | 10.99 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:26 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-4828fa35-b452-4c3c-b488-625ddd80cc06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=517663963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.517663963 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1606838221 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 10179170 ps |
| CPU time | 1.37 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:18 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-70b39e1b-7f70-40d9-befc-6daa0f00a2b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606838221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1606838221 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1121364938 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 13610969933 ps |
| CPU time | 84.18 seconds |
| Started | May 09 01:02:18 PM PDT 24 |
| Finished | May 09 01:03:44 PM PDT 24 |
| Peak memory | 204740 kb |
| Host | smart-d086b6a3-0034-4169-ac62-a2ffd48479fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1121364938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1121364938 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.642380171 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5187037565 ps |
| CPU time | 34.68 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:53 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-4c29086d-cb37-402a-b556-99e128b38b1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=642380171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.642380171 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3276125448 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 608555801 ps |
| CPU time | 80.74 seconds |
| Started | May 09 01:02:18 PM PDT 24 |
| Finished | May 09 01:03:40 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-7c3958ea-a177-41bf-abd2-9f52b3912f7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3276125448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3276125448 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3266347815 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 222887176 ps |
| CPU time | 18.39 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:36 PM PDT 24 |
| Peak memory | 202992 kb |
| Host | smart-996d265e-0fff-4d3b-bff0-4b54a1244cdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3266347815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3266347815 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2761808638 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 26898781 ps |
| CPU time | 3.24 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:19 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-14dadad8-df4f-430b-851a-44af7294c12e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2761808638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2761808638 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3803641280 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3497913670 ps |
| CPU time | 22.84 seconds |
| Started | May 09 01:02:12 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-6647ebb4-438b-4dad-a775-89cce8227a91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3803641280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3803641280 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1318088037 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 74051256161 ps |
| CPU time | 136.25 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:04:33 PM PDT 24 |
| Peak memory | 203076 kb |
| Host | smart-c7e8a58e-7a21-47a5-8d57-3ee2c3afc2af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1318088037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1318088037 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1028178937 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 447560767 ps |
| CPU time | 6.81 seconds |
| Started | May 09 01:02:16 PM PDT 24 |
| Finished | May 09 01:02:25 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-4af787f0-8100-4bbd-a183-4d16ed0e4a27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028178937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1028178937 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.2522314624 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 6242545057 ps |
| CPU time | 13.38 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:28 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-d2e2d533-aa57-4847-8cf4-2722eaf2c4d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2522314624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2522314624 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.1237965082 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 36821889 ps |
| CPU time | 4.88 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:23 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-16f0149b-2754-4a57-b99f-a8200f97288e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1237965082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1237965082 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.932405262 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 133364351708 ps |
| CPU time | 78.82 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:03:35 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-0db629a7-4c6f-4862-abad-02de03f7bb66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=932405262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.932405262 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3169821611 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 74552875211 ps |
| CPU time | 141.99 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:04:40 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-7ae043d3-ef7c-4ba9-8136-2eb2063f2c31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3169821611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3169821611 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.737325665 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 69448288 ps |
| CPU time | 8.25 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:26 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-471e085e-6254-4263-b10c-39079b8e5e65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737325665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.737325665 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1313790986 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 61692443 ps |
| CPU time | 4.19 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:22 PM PDT 24 |
| Peak memory | 201664 kb |
| Host | smart-49f962df-0631-47f7-aea7-4ad791ed4c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1313790986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1313790986 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3195189941 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 43916914 ps |
| CPU time | 1.44 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:16 PM PDT 24 |
| Peak memory | 201940 kb |
| Host | smart-a2bff000-a8e8-40bb-94b4-d8b8422e0d5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3195189941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3195189941 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.749179656 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3372050932 ps |
| CPU time | 10.5 seconds |
| Started | May 09 01:02:14 PM PDT 24 |
| Finished | May 09 01:02:28 PM PDT 24 |
| Peak memory | 201756 kb |
| Host | smart-e1eb0ccb-38cc-4db5-85aa-d4192f2cdd74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=749179656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.749179656 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2374349450 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2752135101 ps |
| CPU time | 8.16 seconds |
| Started | May 09 01:02:17 PM PDT 24 |
| Finished | May 09 01:02:27 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-9789022a-a723-4b03-8c55-7e6ebeff5f5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2374349450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2374349450 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.544114519 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 24171860 ps |
| CPU time | 1.02 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:16 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-77c4c619-264f-48cd-84fe-54430dfee9e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544114519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.544114519 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3704198468 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 53065639 ps |
| CPU time | 1.35 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:15 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-e9256c07-f7b4-4910-84b5-2638aaa31994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3704198468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3704198468 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.92659225 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 10021570398 ps |
| CPU time | 37.07 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:52 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-23e23825-a1ac-4498-b2ae-98e79e2f97a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92659225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.92659225 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3058982551 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 316659099 ps |
| CPU time | 36.71 seconds |
| Started | May 09 01:02:17 PM PDT 24 |
| Finished | May 09 01:02:56 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-aba315b7-da45-46fd-b466-dbfb4d3b79d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3058982551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3058982551 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3089876804 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 244118731 ps |
| CPU time | 19.03 seconds |
| Started | May 09 01:02:16 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 203180 kb |
| Host | smart-14c52f5e-3c12-42b7-8d95-63dfa1116bce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3089876804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3089876804 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.176715805 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 21971259 ps |
| CPU time | 2.07 seconds |
| Started | May 09 01:02:16 PM PDT 24 |
| Finished | May 09 01:02:21 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-c6bb3b70-d608-452a-909f-b8c16ab4d13b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176715805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.176715805 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3417759766 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1239362647 ps |
| CPU time | 14.78 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-f7355377-a864-4cbc-b8b2-d0e7ff9a1637 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417759766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3417759766 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3447892593 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 54635288568 ps |
| CPU time | 59.61 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:03:34 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-8d5ea82f-25e8-49cd-89aa-714354220f05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3447892593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3447892593 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2581461200 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 562585340 ps |
| CPU time | 7.04 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-22540552-5981-4074-ae71-624f3ea26abb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581461200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2581461200 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.3229540525 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1040690642 ps |
| CPU time | 7.99 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-7b6710c3-15dc-4af1-a897-2ca9b524d4da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3229540525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3229540525 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.1232114149 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 5214586639 ps |
| CPU time | 13.81 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:02:48 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-235d9705-c41d-4704-bcfc-d994cb4619b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1232114149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1232114149 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.995152586 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 19678465715 ps |
| CPU time | 35.39 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:03:11 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-f6c77596-2ae8-487e-b4f9-9cfb8a00fbd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=995152586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.995152586 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3036505293 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 33724261784 ps |
| CPU time | 155.23 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:05:04 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-5cd019fc-ee5f-4696-889e-8d5aca6745a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3036505293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3036505293 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1769750731 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 160250728 ps |
| CPU time | 4.91 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:34 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-49496e26-4453-446d-a57f-f8932565bc8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769750731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1769750731 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1674497834 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 72722735 ps |
| CPU time | 4.83 seconds |
| Started | May 09 01:02:33 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-9661ffd0-c39c-4db9-bf1a-5a88045254e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1674497834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1674497834 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1245605134 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 37756018 ps |
| CPU time | 1.34 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:20 PM PDT 24 |
| Peak memory | 201968 kb |
| Host | smart-db625713-8956-4848-a722-c896ad66145f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1245605134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1245605134 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3811018349 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3505539762 ps |
| CPU time | 6.94 seconds |
| Started | May 09 01:02:17 PM PDT 24 |
| Finished | May 09 01:02:26 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-4e6887a4-8cc0-4073-a9a8-8dcdef682d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811018349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3811018349 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.495731143 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1671712802 ps |
| CPU time | 5.21 seconds |
| Started | May 09 01:02:15 PM PDT 24 |
| Finished | May 09 01:02:23 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-6ce2d09b-0f6c-4dbd-b8f1-fe30cc140ab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=495731143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.495731143 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3866073468 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 10633028 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:02:13 PM PDT 24 |
| Finished | May 09 01:02:16 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-16c14efe-bd7e-4c70-a8f5-3f2c4157793b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866073468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3866073468 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1552916447 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3747087924 ps |
| CPU time | 32.04 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:03:10 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-7c39e171-cd7e-4842-8490-12662e882996 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1552916447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1552916447 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2137077636 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 13211928846 ps |
| CPU time | 37.14 seconds |
| Started | May 09 01:02:33 PM PDT 24 |
| Finished | May 09 01:03:13 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-a21d6d7d-a470-4aaa-98f6-007419702c91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2137077636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2137077636 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3370422067 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7718027 ps |
| CPU time | 4.32 seconds |
| Started | May 09 01:02:33 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-5838c0b4-8beb-4853-aff3-ee9e9a234eb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3370422067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3370422067 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1577364209 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 522672689 ps |
| CPU time | 47.25 seconds |
| Started | May 09 01:02:33 PM PDT 24 |
| Finished | May 09 01:03:23 PM PDT 24 |
| Peak memory | 203104 kb |
| Host | smart-befda524-cb51-4a6e-bbe1-d1ca24c2b28f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577364209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.1577364209 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2204043025 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 146837208 ps |
| CPU time | 5.13 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:35 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-c4c453b6-c28e-4b94-8142-ffcc0d0eed70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2204043025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2204043025 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2875991535 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 22559323 ps |
| CPU time | 1.95 seconds |
| Started | May 09 01:02:33 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-97a5cb30-64b8-462a-892e-2065e4ca6609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2875991535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2875991535 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.269659998 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 62202803 ps |
| CPU time | 4.79 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:33 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-a72d416f-51e0-4a7d-9a82-5f9b89d7231e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=269659998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.269659998 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2204876710 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 350660007 ps |
| CPU time | 2.37 seconds |
| Started | May 09 01:02:30 PM PDT 24 |
| Finished | May 09 01:02:34 PM PDT 24 |
| Peak memory | 201924 kb |
| Host | smart-ded2c943-bccd-4514-b740-1cec255e4365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2204876710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2204876710 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.1029763600 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 89328372 ps |
| CPU time | 7.67 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-8637238e-07d7-4497-ab00-a2da7b719540 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029763600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1029763600 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1460363974 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 15582384211 ps |
| CPU time | 31.37 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:03:00 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-1bc9ad22-e5f5-4c2a-9cb4-a08c1627952c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460363974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1460363974 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1738430667 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 18978853931 ps |
| CPU time | 113.33 seconds |
| Started | May 09 01:02:25 PM PDT 24 |
| Finished | May 09 01:04:20 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-68fb73b2-6c11-4155-8868-8df473197570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1738430667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1738430667 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2360916060 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 71588315 ps |
| CPU time | 6.2 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:42 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-92af2ede-b0ce-4150-acaa-8a031822a80f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360916060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2360916060 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.3477656596 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 63716116 ps |
| CPU time | 4.17 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-50aa3bbb-62a1-4aa4-844e-38be14ac6459 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477656596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3477656596 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.660943647 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 14690990 ps |
| CPU time | 1.3 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:02:37 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-ec16f443-9a60-4c7b-b273-278be98f784f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=660943647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.660943647 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2576848993 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1616656196 ps |
| CPU time | 7.28 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:36 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-c329075a-7795-42b0-9921-a86dd38f12c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576848993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2576848993 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2328926577 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1034159921 ps |
| CPU time | 6.06 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:34 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-f77cc234-fe2d-4e1e-aeea-787875d75578 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2328926577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2328926577 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3191135264 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 12147054 ps |
| CPU time | 1.18 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:31 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-8cce7a34-a995-49ab-a92b-c175713b87ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191135264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3191135264 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.783768977 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1114895642 ps |
| CPU time | 18.9 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:48 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-38783b46-02ba-4f47-874a-ad98eb6276a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=783768977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.783768977 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3305019978 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 13520618805 ps |
| CPU time | 78.08 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:03:48 PM PDT 24 |
| Peak memory | 203100 kb |
| Host | smart-506bc397-af7b-402f-a9d2-575b1b28de3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305019978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3305019978 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.589631886 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2068749116 ps |
| CPU time | 117.15 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:04:25 PM PDT 24 |
| Peak memory | 206036 kb |
| Host | smart-5a380e43-466c-47ea-b56b-55e09a8bd6e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=589631886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.589631886 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3093852000 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 94473926 ps |
| CPU time | 9.58 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 202952 kb |
| Host | smart-3017598f-d737-48d0-aa68-737dbca6fa3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093852000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3093852000 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2158637816 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 10325893 ps |
| CPU time | 1.29 seconds |
| Started | May 09 01:02:31 PM PDT 24 |
| Finished | May 09 01:02:33 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-a8791bc6-d885-4a36-be65-6d54ca077939 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2158637816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2158637816 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2622066831 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 260796768 ps |
| CPU time | 3.96 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:02:39 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-b4e63f4e-5b5b-497d-9dda-4120ec9215c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2622066831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2622066831 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3024191336 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 302057236 ps |
| CPU time | 2.71 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:32 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-fefc8e5b-d871-4188-a99e-1453e356f602 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3024191336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3024191336 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.4040052800 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 49769661 ps |
| CPU time | 2.31 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:02:38 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-e87d2c95-d585-46c6-8a3c-392ecdbaa0bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040052800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4040052800 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.46970883 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 81186847 ps |
| CPU time | 3.28 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:39 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-8ddfe3d5-d708-41b7-910c-d86bd1ad01c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46970883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.46970883 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3485132964 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 23311119591 ps |
| CPU time | 115.23 seconds |
| Started | May 09 01:02:31 PM PDT 24 |
| Finished | May 09 01:04:27 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-57170c38-f20c-42e5-be29-71a6b0eb8784 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485132964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3485132964 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.250002283 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3563837504 ps |
| CPU time | 19.41 seconds |
| Started | May 09 01:02:26 PM PDT 24 |
| Finished | May 09 01:02:47 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-acfb2fca-c569-49eb-8672-32507b723fbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=250002283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.250002283 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1253156922 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 84801517 ps |
| CPU time | 7.52 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-fe0c5d8d-90c9-4b9f-acad-12e92172c206 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253156922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1253156922 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.2082241085 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 65199923 ps |
| CPU time | 6.12 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-66d897e7-ca2d-48e3-967f-3726862b77ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2082241085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2082241085 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.993166280 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 49218781 ps |
| CPU time | 1.53 seconds |
| Started | May 09 01:02:30 PM PDT 24 |
| Finished | May 09 01:02:33 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-34a74857-6c52-4f46-aa58-c602644341d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=993166280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.993166280 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1360046159 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4730695929 ps |
| CPU time | 10.24 seconds |
| Started | May 09 01:02:30 PM PDT 24 |
| Finished | May 09 01:02:41 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-30f54348-df8c-4230-a445-3c1e54133c33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360046159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1360046159 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2994235114 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2702682940 ps |
| CPU time | 11.2 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 202344 kb |
| Host | smart-0f9ee075-4816-47ee-96c2-e8bd061b50df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2994235114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2994235114 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1703964228 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 9230501 ps |
| CPU time | 1.19 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:30 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-de96a07e-a5ea-4f3b-892b-1b47c8891a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703964228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1703964228 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1301610859 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 86692149 ps |
| CPU time | 7.86 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:36 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-67e41e01-e548-4dfe-8f80-10cd332e4f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301610859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1301610859 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2373540710 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 11352605260 ps |
| CPU time | 60.44 seconds |
| Started | May 09 01:02:26 PM PDT 24 |
| Finished | May 09 01:03:28 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-c0e91415-ba03-4cca-b8ff-487c066a88a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2373540710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2373540710 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1855637083 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 53464424 ps |
| CPU time | 7.2 seconds |
| Started | May 09 01:02:27 PM PDT 24 |
| Finished | May 09 01:02:35 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-59a8f581-9028-4490-84c8-b586ddb358f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1855637083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1855637083 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3482106631 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3612590671 ps |
| CPU time | 115.16 seconds |
| Started | May 09 01:02:30 PM PDT 24 |
| Finished | May 09 01:04:26 PM PDT 24 |
| Peak memory | 205396 kb |
| Host | smart-a067179b-3e53-47d7-9434-dbbf845ba4d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3482106631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.3482106631 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2536382262 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 170468975 ps |
| CPU time | 4.01 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:02:39 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-6bb28fb2-b1ce-4ee6-8fa5-2938018187b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2536382262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2536382262 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2307533490 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12062105 ps |
| CPU time | 1.26 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:02:40 PM PDT 24 |
| Peak memory | 201936 kb |
| Host | smart-685463af-43c6-4cbb-9bf6-27d503d59cde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307533490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2307533490 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3089067995 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 45580802011 ps |
| CPU time | 286.94 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:07:27 PM PDT 24 |
| Peak memory | 203704 kb |
| Host | smart-39dbbe27-94b5-4975-9ffd-7aefef1aa673 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3089067995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3089067995 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2159087969 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1171947753 ps |
| CPU time | 10.04 seconds |
| Started | May 09 01:02:42 PM PDT 24 |
| Finished | May 09 01:02:54 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-735254b1-5217-43a8-bcae-d6394b33de2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2159087969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2159087969 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.3721102294 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 491093351 ps |
| CPU time | 4.72 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-71a7d5bb-42f1-42b5-ac50-40edd6335b89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3721102294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3721102294 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2340248016 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1121341594 ps |
| CPU time | 4.68 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:41 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-c76605d8-f6e7-48e0-b211-ae78332bda72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2340248016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2340248016 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2136376746 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 119701157580 ps |
| CPU time | 160.09 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:05:18 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-bda0c413-5461-4cb7-8a46-b00a568f48b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136376746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2136376746 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.881894735 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10944411431 ps |
| CPU time | 50.49 seconds |
| Started | May 09 01:02:41 PM PDT 24 |
| Finished | May 09 01:03:33 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-c277069b-009a-4455-b92c-edc656e4e80a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=881894735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.881894735 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2099823150 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 151146336 ps |
| CPU time | 5.27 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-9a3b3d18-5fd2-4f1b-a3dc-229fa75da5b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099823150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2099823150 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.564680180 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 974715352 ps |
| CPU time | 11.36 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:53 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-9dbf36be-cf3d-4fcf-a8eb-9b78a0f4e031 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=564680180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.564680180 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.2180181971 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 61238510 ps |
| CPU time | 1.31 seconds |
| Started | May 09 01:02:28 PM PDT 24 |
| Finished | May 09 01:02:30 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-50a4b3a1-e921-468a-9be0-c22a8811877c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2180181971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2180181971 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.4147147606 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4522579405 ps |
| CPU time | 7.05 seconds |
| Started | May 09 01:02:31 PM PDT 24 |
| Finished | May 09 01:02:39 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-ac44efe7-a3b7-40e1-8f80-a68128566493 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147147606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.4147147606 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2888713302 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 9704665672 ps |
| CPU time | 9.96 seconds |
| Started | May 09 01:02:32 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-ca433717-1dad-40ba-a00e-1181263ffd9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2888713302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2888713302 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2554219434 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 13702819 ps |
| CPU time | 1.16 seconds |
| Started | May 09 01:02:33 PM PDT 24 |
| Finished | May 09 01:02:36 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-bb84dd2b-4e1d-4753-b2ec-95bf7845a2a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554219434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2554219434 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3313552494 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 196066413 ps |
| CPU time | 18.01 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:55 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-501cb5c9-f624-46af-bd02-40f1c1360c02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3313552494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3313552494 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.836605327 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2718357510 ps |
| CPU time | 30.77 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:03:10 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-8e120b8e-3ebb-4c36-beab-386eb1eaf4c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=836605327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.836605327 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1148322900 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 813899513 ps |
| CPU time | 74.24 seconds |
| Started | May 09 01:02:45 PM PDT 24 |
| Finished | May 09 01:04:00 PM PDT 24 |
| Peak memory | 207292 kb |
| Host | smart-af3247ba-cf1d-42c5-99f9-86fb656dca8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1148322900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1148322900 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1252814180 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 885688971 ps |
| CPU time | 113.52 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:04:35 PM PDT 24 |
| Peak memory | 207620 kb |
| Host | smart-c7944808-8928-4995-845f-4453dd97ef0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1252814180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1252814180 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.5053439 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 401007985 ps |
| CPU time | 7.58 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-0f5742a2-3f1c-4635-b452-16f7ad3e2f4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=5053439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.5053439 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2735607266 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 644682692 ps |
| CPU time | 8.04 seconds |
| Started | May 09 01:02:40 PM PDT 24 |
| Finished | May 09 01:02:51 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-b4b89d83-2b27-456a-9676-9bfd761ced9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2735607266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2735607266 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3149557615 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31441045782 ps |
| CPU time | 52.41 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:03:33 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-ac588ffe-5397-47e7-80ab-df67204ce5e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3149557615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.3149557615 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3380556114 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 441941598 ps |
| CPU time | 6.38 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:02:46 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-69bc9ab1-cc92-4f64-821a-7cd781ccaca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3380556114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3380556114 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.2307606112 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 550212526 ps |
| CPU time | 9.86 seconds |
| Started | May 09 01:02:46 PM PDT 24 |
| Finished | May 09 01:02:58 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-043df974-0f24-47fc-9eb8-673a79f0f3d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307606112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2307606112 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.2764352115 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 727189434 ps |
| CPU time | 9.38 seconds |
| Started | May 09 01:02:44 PM PDT 24 |
| Finished | May 09 01:02:55 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-66170a4f-0133-4ec6-bec3-de9d7f5c4e5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2764352115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2764352115 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1685068803 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 43176123935 ps |
| CPU time | 63.45 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:03:43 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-1fb26212-26e4-4641-86ae-3df4d7906750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685068803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1685068803 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.267750347 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13390264026 ps |
| CPU time | 85.24 seconds |
| Started | May 09 01:02:34 PM PDT 24 |
| Finished | May 09 01:04:02 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-1b21f00b-c046-4d63-bdd7-b348f780820f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=267750347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.267750347 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1693125405 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 39915012 ps |
| CPU time | 3.27 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-a0ab1706-e501-40e2-9369-e7d7f792f5fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693125405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1693125405 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1223423665 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 34836963 ps |
| CPU time | 3.55 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-e254dd1d-390e-41ac-8476-05002ebed6cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223423665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1223423665 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.3132275371 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 16418721 ps |
| CPU time | 1.15 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:02:39 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-59c5cfd3-0a37-436f-884d-0c635d7209c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3132275371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3132275371 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1492898633 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 9536106272 ps |
| CPU time | 8.63 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:02:49 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-a512f8a5-79c4-4d71-8a2a-2b36c5c83e58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492898633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1492898633 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3929037967 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2641491091 ps |
| CPU time | 11.93 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:02:52 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-151794fe-b89c-4360-81fb-3a5c71aae163 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3929037967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3929037967 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2694711176 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 12665411 ps |
| CPU time | 1.16 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:02:39 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-12fc5b5a-a382-4033-9e90-fd9d0039a2db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694711176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2694711176 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2962546217 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 479998083 ps |
| CPU time | 13.22 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:54 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-77503764-fb8d-443f-a828-90d1d4ef2ddf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2962546217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2962546217 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1631054192 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3322304243 ps |
| CPU time | 16.36 seconds |
| Started | May 09 03:33:08 PM PDT 24 |
| Finished | May 09 03:33:25 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-5b76e488-7240-4f7a-86b9-26032354437a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1631054192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1631054192 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2887421001 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1889584417 ps |
| CPU time | 88.87 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:04:09 PM PDT 24 |
| Peak memory | 206208 kb |
| Host | smart-396e1aef-0c0c-413d-a6e6-68bd3d355f78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2887421001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2887421001 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1476568231 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3700367663 ps |
| CPU time | 59.5 seconds |
| Started | May 09 03:56:28 PM PDT 24 |
| Finished | May 09 03:57:28 PM PDT 24 |
| Peak memory | 204168 kb |
| Host | smart-5b3f81f3-8aa3-4d36-941e-9c83dfcde5ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1476568231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1476568231 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.530516956 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 334486669 ps |
| CPU time | 4.85 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-77f6be38-6d1b-41f3-aa46-c5ce3934b593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=530516956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.530516956 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2605692473 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 146806866 ps |
| CPU time | 3.55 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-14677d85-4346-4fbc-9b5f-3cf3efa14952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2605692473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2605692473 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3749279338 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 149342333151 ps |
| CPU time | 271.1 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:07:12 PM PDT 24 |
| Peak memory | 203552 kb |
| Host | smart-ee5c4e39-5b3c-4e5f-9932-d8435e902733 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3749279338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3749279338 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.645708573 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 50649421 ps |
| CPU time | 2.56 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-c84fce0f-3e8e-41dd-aeee-04e892a929fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=645708573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.645708573 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.953525746 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 45546434 ps |
| CPU time | 4.76 seconds |
| Started | May 09 01:02:45 PM PDT 24 |
| Finished | May 09 01:02:51 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-e94f976a-98cd-49ac-a7fe-1edec3d68f20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=953525746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.953525746 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.218580616 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1084492727 ps |
| CPU time | 7.55 seconds |
| Started | May 09 01:02:35 PM PDT 24 |
| Finished | May 09 01:02:45 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-d060696d-4fae-4797-8ec4-e004113b2e55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=218580616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.218580616 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.316309111 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 8381989190 ps |
| CPU time | 11.8 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:02:52 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-489d5fd6-7d82-4141-82a0-ecf02453547a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=316309111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.316309111 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3548583510 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 20371179931 ps |
| CPU time | 114.93 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:04:37 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-ead5ae36-86bd-4416-b1c8-8366ddcc033c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3548583510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3548583510 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2177155692 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 50396869 ps |
| CPU time | 3.06 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 201932 kb |
| Host | smart-337b8835-5e89-4597-a1d4-bb287b876059 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177155692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2177155692 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.2646235719 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 46293785 ps |
| CPU time | 2.78 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:44 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-28b97125-9e15-40c0-b74d-9a85ea837cac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646235719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2646235719 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1002767653 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 50019890 ps |
| CPU time | 1.62 seconds |
| Started | May 09 02:48:38 PM PDT 24 |
| Finished | May 09 02:48:45 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-8a8e3060-0728-4e21-bd22-cd15cd673ce0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1002767653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1002767653 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.712759338 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2413763787 ps |
| CPU time | 11.63 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:53 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-d6f209ff-c9fb-4d69-8b52-ea301659708c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=712759338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.712759338 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.4002275804 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4166293127 ps |
| CPU time | 6.2 seconds |
| Started | May 09 01:02:40 PM PDT 24 |
| Finished | May 09 01:02:49 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-e64600b4-4778-4f4b-874b-b90a64958941 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4002275804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.4002275804 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.534228080 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 7995659 ps |
| CPU time | 1 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:43 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-be57c230-e033-493d-a77f-dfcf65b05d3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534228080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.534228080 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1616717779 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 136315671 ps |
| CPU time | 8.91 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:02:50 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-a648cb32-18d6-4221-9b06-fc076de0c319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1616717779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1616717779 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.879655494 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 67168696 ps |
| CPU time | 7.02 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:02:47 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-b1331765-dbe0-4d15-9150-50853d88172b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=879655494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.879655494 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1403790388 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5770217512 ps |
| CPU time | 63.16 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:03:42 PM PDT 24 |
| Peak memory | 206304 kb |
| Host | smart-1d2790ef-eb2b-4f68-8742-c459954016bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1403790388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1403790388 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2564335656 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1109655989 ps |
| CPU time | 58.97 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:03:41 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-2db3ca32-265e-45e0-b0fc-e7629ef17134 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2564335656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.2564335656 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2023139618 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 65099596 ps |
| CPU time | 4.99 seconds |
| Started | May 09 01:02:39 PM PDT 24 |
| Finished | May 09 01:02:47 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-43eb42ec-d3fa-4f24-b9eb-f5b6de78d286 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2023139618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2023139618 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2772179008 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2277953058 ps |
| CPU time | 9.04 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:29 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-b6f709b5-fea5-412e-820d-e3d8a43c2fa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2772179008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2772179008 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1325052540 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 453841617589 ps |
| CPU time | 408.18 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 01:06:09 PM PDT 24 |
| Peak memory | 204092 kb |
| Host | smart-95bf7963-8f66-49fa-98c8-4704b422ff8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1325052540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.1325052540 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3365138492 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 291578883 ps |
| CPU time | 2.53 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 12:59:36 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-bebbc28a-fbd2-43f0-8cec-b5310d60441c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3365138492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3365138492 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.1337182597 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1482169838 ps |
| CPU time | 7.46 seconds |
| Started | May 09 12:59:27 PM PDT 24 |
| Finished | May 09 12:59:36 PM PDT 24 |
| Peak memory | 202016 kb |
| Host | smart-872bdcc8-ad1d-4bf6-8064-ffa46ac30a13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337182597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1337182597 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2483582962 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 675406574 ps |
| CPU time | 10.04 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 12:59:30 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-82a73ea2-3e18-43a4-957e-02caec6c774d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2483582962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2483582962 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2947047137 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 74703781686 ps |
| CPU time | 93.73 seconds |
| Started | May 09 12:59:21 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-11123d99-6450-49fb-9c16-76f27845877b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947047137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2947047137 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4268455869 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4922869391 ps |
| CPU time | 22.11 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 12:59:43 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-bf0be2f2-ff92-49f8-95bc-3cec17b16893 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4268455869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4268455869 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.18749849 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 29582488 ps |
| CPU time | 3.3 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 12:59:24 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-37ec4c09-99f8-4c28-a3e6-13baa611ac85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18749849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.18749849 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2442556711 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 30495418 ps |
| CPU time | 3.4 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:35 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-0c561598-9e76-4b94-84fb-21508c2416c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2442556711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2442556711 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.75668398 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 36049873 ps |
| CPU time | 1.45 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:21 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-c6f782eb-aff7-4b46-8e96-42d6ffdf3a64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=75668398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.75668398 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3495195350 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1612203614 ps |
| CPU time | 5.96 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 12:59:26 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-abccc2eb-1e5d-4f87-89c3-cc4e58d24e53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495195350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3495195350 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.357254633 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4085875777 ps |
| CPU time | 7.48 seconds |
| Started | May 09 12:59:18 PM PDT 24 |
| Finished | May 09 12:59:26 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-ec902e7a-99f8-497a-99ea-0f8f72c41f50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=357254633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.357254633 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1541146096 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 10593815 ps |
| CPU time | 1.32 seconds |
| Started | May 09 12:59:19 PM PDT 24 |
| Finished | May 09 12:59:22 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-47c7c9e4-ba34-4aa4-82e8-41a55f462eea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541146096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1541146096 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.874583982 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 203862426 ps |
| CPU time | 17.75 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 12:59:48 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-20d01dae-e06f-4cca-bca1-a61d13bdaba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874583982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.874583982 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4109494153 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3662429103 ps |
| CPU time | 60.56 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 01:00:34 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-7939ffb7-2527-4788-8d8a-a5a87076ce74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4109494153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4109494153 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3478690857 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 7020778 ps |
| CPU time | 6.45 seconds |
| Started | May 09 12:59:27 PM PDT 24 |
| Finished | May 09 12:59:35 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-f3b281b7-dfdb-4936-9a04-183245eb4eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3478690857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3478690857 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.547212506 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2194403796 ps |
| CPU time | 110.24 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 01:01:21 PM PDT 24 |
| Peak memory | 206840 kb |
| Host | smart-ed3ef0af-e772-47e3-bb14-697217740fcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=547212506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.547212506 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3728949638 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 508637078 ps |
| CPU time | 4.35 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 12:59:34 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-362a5acf-2af9-4171-8334-f2c3d9851613 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3728949638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3728949638 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2126839300 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 603883316 ps |
| CPU time | 6.61 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 12:59:41 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-4c8d295d-4c18-4917-92b4-b69737737912 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2126839300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2126839300 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1861076996 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 22263511827 ps |
| CPU time | 147.69 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 01:01:59 PM PDT 24 |
| Peak memory | 203216 kb |
| Host | smart-c85d53bd-029a-4e9d-9ce0-7f98fe852767 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1861076996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1861076996 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.667270358 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 587096295 ps |
| CPU time | 10.17 seconds |
| Started | May 09 12:59:32 PM PDT 24 |
| Finished | May 09 12:59:45 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-36f08315-94f4-46fc-b6fd-5825e036c0b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=667270358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.667270358 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.3527568879 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 570181151 ps |
| CPU time | 4.44 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 12:59:38 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-7df4f74d-826b-48a4-98c7-bf3b56fb12e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527568879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3527568879 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.3498642831 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 99877509 ps |
| CPU time | 2.23 seconds |
| Started | May 09 12:59:27 PM PDT 24 |
| Finished | May 09 12:59:32 PM PDT 24 |
| Peak memory | 202020 kb |
| Host | smart-2a633679-92af-4069-8482-f9183dc72093 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498642831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3498642831 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2154409070 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 35151519405 ps |
| CPU time | 126.76 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 01:01:37 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-3b4436af-2a83-4ed6-aa72-b1cb0c8b9abc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154409070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2154409070 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3348148634 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 22217353419 ps |
| CPU time | 116.67 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 01:01:27 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-11478043-f2a4-40d5-80bd-a63e150f97c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3348148634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3348148634 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1192762106 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 92776384 ps |
| CPU time | 8.58 seconds |
| Started | May 09 12:59:27 PM PDT 24 |
| Finished | May 09 12:59:37 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-ae3af4b6-f411-4285-abd3-5d28a17b8d99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192762106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1192762106 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3159631873 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3296401629 ps |
| CPU time | 8.04 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 12:59:42 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-44b7b8be-ec3c-49b9-95e6-15b0e5637c56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3159631873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3159631873 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.2398639968 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 79223495 ps |
| CPU time | 1.61 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 12:59:36 PM PDT 24 |
| Peak memory | 201756 kb |
| Host | smart-6d111702-5ee2-49b0-8586-c4ce4486f1d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2398639968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2398639968 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3324213142 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 7236496771 ps |
| CPU time | 10.34 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 12:59:42 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-8acd8bb4-9099-4383-beff-1996b1b26a77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324213142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3324213142 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.4018040474 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1404977852 ps |
| CPU time | 7.41 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 12:59:37 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-8fddb147-8762-46e1-be54-a2c5dd598964 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4018040474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.4018040474 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3105077397 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 12021708 ps |
| CPU time | 1.13 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 12:59:33 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-91d7a2bd-f668-4760-be63-1f919dbfff00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105077397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3105077397 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3751661744 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 779020286 ps |
| CPU time | 51.85 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 01:00:23 PM PDT 24 |
| Peak memory | 205292 kb |
| Host | smart-4d244a16-e3c3-48c8-92c6-28eb0185b49c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3751661744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3751661744 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1197918621 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8319632181 ps |
| CPU time | 68.63 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 01:00:42 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-f0eb2395-3920-40ad-a208-89faa53b0cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1197918621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1197918621 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.4182484927 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1584186698 ps |
| CPU time | 61.86 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 01:00:36 PM PDT 24 |
| Peak memory | 205440 kb |
| Host | smart-c67fc52e-6130-4c42-852d-c66cdbabd6fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4182484927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.4182484927 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.852573934 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 11964268 ps |
| CPU time | 1.34 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:34 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-e7d3f719-6c55-42f4-8abf-ad0835080eee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=852573934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.852573934 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.939535260 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1553692041 ps |
| CPU time | 9.46 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 12:59:44 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-21631fbe-a2f6-4416-b142-ee726f4bed0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=939535260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.939535260 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.4057813953 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1004093301 ps |
| CPU time | 4.23 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 12:59:38 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-b1696c57-168a-4cc3-a3ec-7ad3987cc72e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4057813953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.4057813953 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.3032345885 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 135423894 ps |
| CPU time | 1.61 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:34 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-f93188bd-8697-42b8-b295-61881a4e3f0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3032345885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3032345885 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.3096730851 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 48522220 ps |
| CPU time | 5.18 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 12:59:39 PM PDT 24 |
| Peak memory | 202012 kb |
| Host | smart-68a95721-9c45-4579-a5e2-6c4bde724baa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3096730851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3096730851 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1859888830 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 130017437126 ps |
| CPU time | 175.88 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 01:02:28 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-1bde9976-43ef-4f03-b01d-aec64e1a3df8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859888830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1859888830 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1416291830 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 123581800528 ps |
| CPU time | 141.71 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 01:01:55 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-02cb4b74-a713-494e-bbbb-3de6d70cb2c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1416291830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1416291830 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1003211800 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 36210181 ps |
| CPU time | 3.15 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 12:59:37 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-6bed05a5-2c67-4d03-babf-978012b90fab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003211800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1003211800 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2948206796 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 633296720 ps |
| CPU time | 3.38 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:37 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-056a9c5e-abe7-49ab-b36b-2716a333f00a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2948206796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2948206796 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1915352959 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 16131984 ps |
| CPU time | 1.19 seconds |
| Started | May 09 12:59:28 PM PDT 24 |
| Finished | May 09 12:59:31 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-f7daca8d-ed18-4fba-ae30-217815fedd87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915352959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1915352959 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2453330230 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 10259927297 ps |
| CPU time | 9.9 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:43 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-ebe6777d-37a2-4d9d-bb08-b97d05a75749 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453330230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2453330230 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1810258200 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2631080897 ps |
| CPU time | 8.69 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 12:59:43 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-669cf045-1474-46df-bf3b-477b5ca56e47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1810258200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1810258200 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.612007821 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 8242544 ps |
| CPU time | 1.14 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:34 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-846bd789-ea92-497a-addf-ea95eadc26c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612007821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.612007821 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2764113953 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 981152026 ps |
| CPU time | 52.76 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 01:00:26 PM PDT 24 |
| Peak memory | 203176 kb |
| Host | smart-4fa35858-5efb-4bfd-869c-766fde384677 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2764113953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2764113953 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3175021267 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 491370235 ps |
| CPU time | 19.85 seconds |
| Started | May 09 12:59:33 PM PDT 24 |
| Finished | May 09 12:59:55 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-0abb7260-9b69-40fd-880a-3c1a88fa9e58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175021267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3175021267 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1097303645 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 422673605 ps |
| CPU time | 50.54 seconds |
| Started | May 09 12:59:30 PM PDT 24 |
| Finished | May 09 01:00:24 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-e67ebbc8-73ef-420b-81db-8ea3054fca61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097303645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1097303645 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1677548920 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 399279165 ps |
| CPU time | 3.21 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:36 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-73f94cc3-38a4-4648-b0e9-89c5691d759c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1677548920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1677548920 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3329901567 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 12578381 ps |
| CPU time | 1.74 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 12:59:46 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-635063c6-eea2-4511-8d6b-6fea2ae271d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3329901567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3329901567 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1768786644 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 37615795172 ps |
| CPU time | 286.18 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:04:29 PM PDT 24 |
| Peak memory | 203548 kb |
| Host | smart-280e3ca1-5fb2-48aa-b057-cadeb85cdbb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1768786644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.1768786644 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1969377880 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1204744326 ps |
| CPU time | 6.07 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:50 PM PDT 24 |
| Peak memory | 201948 kb |
| Host | smart-9f45184f-7e5d-415d-b754-d7f7230ff522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1969377880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1969377880 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.4120702543 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 9104269 ps |
| CPU time | 1.08 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 12:59:45 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-1e212761-282f-45d7-b224-43ecd4609889 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4120702543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.4120702543 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.409238062 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 53083063 ps |
| CPU time | 7.12 seconds |
| Started | May 09 12:59:29 PM PDT 24 |
| Finished | May 09 12:59:40 PM PDT 24 |
| Peak memory | 201944 kb |
| Host | smart-a37288d9-6f81-4e5a-8e37-c0e38f709055 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409238062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.409238062 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1279305118 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4279421654 ps |
| CPU time | 9.19 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 12:59:51 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-373548cd-8880-4799-b53b-511e60191319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279305118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1279305118 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3463662130 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 7556234371 ps |
| CPU time | 34.6 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:00:17 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-94eb2e3c-525f-4c74-ae58-d44cd3668edd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3463662130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3463662130 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1274083905 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 111747946 ps |
| CPU time | 4.73 seconds |
| Started | May 09 12:59:38 PM PDT 24 |
| Finished | May 09 12:59:44 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-48e9b72e-947f-488c-b1d5-18c05edfddd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274083905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1274083905 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2101595532 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1138643082 ps |
| CPU time | 5.79 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 12:59:48 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-8016361d-1152-4a6d-ae01-73d4d0d7144e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101595532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2101595532 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.3144814632 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 77564285 ps |
| CPU time | 1.35 seconds |
| Started | May 09 12:59:33 PM PDT 24 |
| Finished | May 09 12:59:36 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-5c57eecd-90a5-4736-85d3-ecc97b6cea75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3144814632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3144814632 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1569567084 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5110447939 ps |
| CPU time | 9.47 seconds |
| Started | May 09 12:59:27 PM PDT 24 |
| Finished | May 09 12:59:38 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-54a7a579-84cf-4793-ac5f-f1c8b6fece84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569567084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1569567084 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1552939044 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1701600344 ps |
| CPU time | 8.46 seconds |
| Started | May 09 12:59:31 PM PDT 24 |
| Finished | May 09 12:59:43 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-d824fe60-d25d-4383-92b5-f41b773f0bc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1552939044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1552939044 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1389275416 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 22156720 ps |
| CPU time | 1.39 seconds |
| Started | May 09 12:59:33 PM PDT 24 |
| Finished | May 09 12:59:36 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-e031d1de-219f-43f9-866f-c55845829f72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389275416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1389275416 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3908004530 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 747985552 ps |
| CPU time | 32.19 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 01:00:16 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-be80289f-a945-4c6e-9c6b-c4d5db2ba305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3908004530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3908004530 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1623019415 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4435383119 ps |
| CPU time | 39.38 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 01:00:24 PM PDT 24 |
| Peak memory | 203556 kb |
| Host | smart-30a9c6f9-391a-4b5d-8193-676b6b781315 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1623019415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1623019415 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1584686169 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1033150831 ps |
| CPU time | 6.9 seconds |
| Started | May 09 12:59:43 PM PDT 24 |
| Finished | May 09 12:59:52 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-b3b06699-dcef-4206-a272-4329e0978efb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1584686169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1584686169 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2502586827 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 23693389 ps |
| CPU time | 3 seconds |
| Started | May 09 12:59:44 PM PDT 24 |
| Finished | May 09 12:59:50 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-3bd7e72a-a168-4793-a6ae-544037eb547e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2502586827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2502586827 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.359508086 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 15676774375 ps |
| CPU time | 85.37 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:01:09 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-d7be69ac-b998-4f77-ad36-5c91db679f5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=359508086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow _rsp.359508086 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2084396296 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 338166829 ps |
| CPU time | 4.87 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 12:59:50 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-06598859-e90c-4917-8223-6db997ae092e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2084396296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2084396296 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.2956776583 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2784816266 ps |
| CPU time | 8.18 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 12:59:51 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-f53df0f3-210d-43bc-8227-87aa387c2844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2956776583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2956776583 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.544114899 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 700959894 ps |
| CPU time | 12.43 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:57 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-3491b5af-acbf-4ed4-83ff-b7f73abb5bac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544114899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.544114899 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2881498584 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 29925032118 ps |
| CPU time | 149.37 seconds |
| Started | May 09 12:59:43 PM PDT 24 |
| Finished | May 09 01:02:15 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-ca1aa9d0-7a9e-437f-9941-397fee38238b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881498584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2881498584 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.721868766 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 16903698897 ps |
| CPU time | 61.78 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:00:44 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-f687f44d-b675-4743-a47b-12f2fd7febcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=721868766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.721868766 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3385095453 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 211287972 ps |
| CPU time | 7.91 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:52 PM PDT 24 |
| Peak memory | 201992 kb |
| Host | smart-4ff379e7-a62e-497e-b373-a33e34d73e8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385095453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3385095453 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1289465965 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 309256347 ps |
| CPU time | 4.19 seconds |
| Started | May 09 12:59:42 PM PDT 24 |
| Finished | May 09 12:59:49 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-97fcf889-9c6d-4635-b2f8-3662a63cc0ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289465965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1289465965 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.2670766285 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 17568489 ps |
| CPU time | 1.14 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:45 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-73285590-7b6a-479d-b0ff-281986d57a8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2670766285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2670766285 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3808193177 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2792265899 ps |
| CPU time | 9.71 seconds |
| Started | May 09 12:59:39 PM PDT 24 |
| Finished | May 09 12:59:50 PM PDT 24 |
| Peak memory | 202008 kb |
| Host | smart-7525f12f-ad67-41c1-9a80-e366df9e20e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808193177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3808193177 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.59696266 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5670641005 ps |
| CPU time | 9.55 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:54 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-92401638-9c63-4802-9c78-bded10e12985 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=59696266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.59696266 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2197180350 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 9806331 ps |
| CPU time | 1.14 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 12:59:44 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-0c9fc0a3-1d54-4462-9e8f-c8cd4338f048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197180350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2197180350 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3025163502 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 5303359228 ps |
| CPU time | 55.87 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:00:39 PM PDT 24 |
| Peak memory | 204028 kb |
| Host | smart-821152ae-ddc8-4418-ba8f-5fa146880698 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025163502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3025163502 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1208778967 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 96163308 ps |
| CPU time | 9.52 seconds |
| Started | May 09 12:59:41 PM PDT 24 |
| Finished | May 09 12:59:54 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-e322a1c9-cdf6-4740-b4f0-dc8d1e62ebd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1208778967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1208778967 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2028349390 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 630037214 ps |
| CPU time | 70.31 seconds |
| Started | May 09 12:59:43 PM PDT 24 |
| Finished | May 09 01:00:56 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-d5c2b191-047c-4add-adb4-b2b217ffc379 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028349390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.2028349390 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1112688123 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 837325715 ps |
| CPU time | 77.23 seconds |
| Started | May 09 12:59:40 PM PDT 24 |
| Finished | May 09 01:01:01 PM PDT 24 |
| Peak memory | 204172 kb |
| Host | smart-43c0aa67-d336-4498-ab14-f5835e10cfed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1112688123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1112688123 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1080516191 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 122517767 ps |
| CPU time | 5.98 seconds |
| Started | May 09 12:59:44 PM PDT 24 |
| Finished | May 09 12:59:52 PM PDT 24 |
| Peak memory | 201996 kb |
| Host | smart-3cf0a6e4-1ee3-431d-93dc-8f008353ef36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1080516191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1080516191 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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