Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 484 1 T28 2 T44 1 T9 3
all_values[1] 498 1 T5 1 T13 1 T28 1
all_values[2] 502 1 T13 2 T28 1 T9 2
all_values[3] 426 1 T3 1 T13 3 T9 3
all_values[4] 536 1 T3 1 T5 1 T13 1
all_values[5] 477 1 T5 1 T13 6 T28 1
all_values[6] 489 1 T3 1 T5 1 T13 2
all_values[7] 491 1 T3 2 T5 2 T20 1
all_values[8] 493 1 T3 1 T13 4 T28 3
all_values[9] 477 1 T13 4 T44 1 T9 2
all_values[10] 508 1 T3 2 T20 1 T13 4
all_values[11] 468 1 T5 1 T44 1 T9 1
all_values[12] 524 1 T5 1 T13 1 T44 1
all_values[13] 501 1 T13 3 T28 1 T44 1
all_values[14] 498 1 T3 1 T5 1 T13 3
all_values[15] 512 1 T3 3 T5 1 T13 3
all_values[16] 482 1 T5 1 T13 4 T28 1
all_values[17] 465 1 T3 1 T13 1 T44 1
all_values[18] 466 1 T5 1 T13 7 T28 1
all_values[19] 486 1 T13 3 T44 1 T9 1
all_values[20] 480 1 T13 2 T28 1 T38 2
all_values[21] 516 1 T3 1 T5 2 T13 7
all_values[22] 493 1 T13 2 T44 1 T9 1
all_values[23] 477 1 T5 1 T13 4 T44 1
all_values[24] 474 1 T5 1 T13 2 T9 2
all_values[25] 529 1 T5 1 T13 4 T28 1
all_values[26] 553 1 T13 2 T9 3 T38 1

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