| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.36 | 100.00 | 96.18 | 100.00 | 100.00 | 100.00 | 100.00 |
| T756 | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.177031269 | May 12 12:29:18 PM PDT 24 | May 12 12:29:21 PM PDT 24 | 146090334 ps | ||
| T757 | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1090837343 | May 12 12:28:22 PM PDT 24 | May 12 12:28:26 PM PDT 24 | 70534545 ps | ||
| T758 | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3703959323 | May 12 12:30:09 PM PDT 24 | May 12 12:31:10 PM PDT 24 | 32101474283 ps | ||
| T759 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1499212559 | May 12 12:28:16 PM PDT 24 | May 12 12:28:59 PM PDT 24 | 3550292959 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1967435094 | May 12 12:29:19 PM PDT 24 | May 12 12:30:59 PM PDT 24 | 6408266101 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.636101266 | May 12 12:30:03 PM PDT 24 | May 12 12:30:10 PM PDT 24 | 60131080 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/1.xbar_random.832690183 | May 12 12:26:51 PM PDT 24 | May 12 12:26:54 PM PDT 24 | 14135910 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1156310328 | May 12 12:29:50 PM PDT 24 | May 12 12:30:04 PM PDT 24 | 673781685 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1238271004 | May 12 12:28:53 PM PDT 24 | May 12 12:28:56 PM PDT 24 | 32450335 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.907739782 | May 12 12:28:58 PM PDT 24 | May 12 12:29:00 PM PDT 24 | 8655380 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3060876463 | May 12 12:29:56 PM PDT 24 | May 12 12:30:09 PM PDT 24 | 10566629780 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1687832372 | May 12 12:29:18 PM PDT 24 | May 12 12:29:51 PM PDT 24 | 6359162149 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.194459971 | May 12 12:28:44 PM PDT 24 | May 12 12:28:47 PM PDT 24 | 64197744 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2353174863 | May 12 12:30:11 PM PDT 24 | May 12 12:30:24 PM PDT 24 | 2598283483 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.128000669 | May 12 12:28:13 PM PDT 24 | May 12 12:29:50 PM PDT 24 | 791004293 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2969483577 | May 12 12:29:07 PM PDT 24 | May 12 12:29:32 PM PDT 24 | 374148350 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1211423681 | May 12 12:30:03 PM PDT 24 | May 12 12:30:24 PM PDT 24 | 5065310726 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/26.xbar_random.2597423942 | May 12 12:29:26 PM PDT 24 | May 12 12:29:29 PM PDT 24 | 53642172 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2663278481 | May 12 12:29:49 PM PDT 24 | May 12 12:30:39 PM PDT 24 | 342852545 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2233257897 | May 12 12:27:49 PM PDT 24 | May 12 12:28:01 PM PDT 24 | 3806875890 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1614366484 | May 12 12:28:54 PM PDT 24 | May 12 12:29:25 PM PDT 24 | 13552546106 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.879189328 | May 12 12:28:45 PM PDT 24 | May 12 12:28:56 PM PDT 24 | 3588518826 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1022915996 | May 12 12:28:50 PM PDT 24 | May 12 12:29:02 PM PDT 24 | 4042633555 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1578124215 | May 12 12:27:49 PM PDT 24 | May 12 12:27:53 PM PDT 24 | 63447006 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.177569551 | May 12 12:30:10 PM PDT 24 | May 12 12:31:28 PM PDT 24 | 644468614 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.116231432 | May 12 12:28:56 PM PDT 24 | May 12 12:29:35 PM PDT 24 | 341390065 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/33.xbar_smoke.3730273176 | May 12 12:29:28 PM PDT 24 | May 12 12:29:30 PM PDT 24 | 71093796 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1808091199 | May 12 12:30:13 PM PDT 24 | May 12 12:30:19 PM PDT 24 | 815659979 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.4122874791 | May 12 12:29:29 PM PDT 24 | May 12 12:30:00 PM PDT 24 | 3889437726 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/29.xbar_random.3982352736 | May 12 12:29:12 PM PDT 24 | May 12 12:29:16 PM PDT 24 | 178721437 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2881046301 | May 12 12:29:02 PM PDT 24 | May 12 12:29:14 PM PDT 24 | 4368253207 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.932566711 | May 12 12:30:11 PM PDT 24 | May 12 12:30:22 PM PDT 24 | 2379552344 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3835974326 | May 12 12:29:48 PM PDT 24 | May 12 12:34:42 PM PDT 24 | 55983533814 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1583020916 | May 12 12:29:50 PM PDT 24 | May 12 12:29:54 PM PDT 24 | 18384794 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/23.xbar_random.3525653607 | May 12 12:28:56 PM PDT 24 | May 12 12:29:02 PM PDT 24 | 895120629 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/6.xbar_random.4153956908 | May 12 12:27:59 PM PDT 24 | May 12 12:28:04 PM PDT 24 | 23890660 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/1.xbar_smoke.2345961202 | May 12 12:25:59 PM PDT 24 | May 12 12:26:01 PM PDT 24 | 8744293 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.272826211 | May 12 12:28:39 PM PDT 24 | May 12 12:28:57 PM PDT 24 | 6321579120 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2062913692 | May 12 12:30:06 PM PDT 24 | May 12 12:30:13 PM PDT 24 | 299611921 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1176386151 | May 12 12:28:52 PM PDT 24 | May 12 12:29:27 PM PDT 24 | 288832066 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.446414393 | May 12 12:28:46 PM PDT 24 | May 12 12:30:06 PM PDT 24 | 82555649834 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1937383225 | May 12 12:28:10 PM PDT 24 | May 12 12:28:17 PM PDT 24 | 240000693 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.489051076 | May 12 12:29:33 PM PDT 24 | May 12 12:29:43 PM PDT 24 | 1078605801 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3386051733 | May 12 12:29:59 PM PDT 24 | May 12 12:30:05 PM PDT 24 | 259853019 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3394580951 | May 12 12:29:33 PM PDT 24 | May 12 12:29:38 PM PDT 24 | 75352109 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.591808272 | May 12 12:29:34 PM PDT 24 | May 12 12:29:45 PM PDT 24 | 144737230 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/41.xbar_smoke.946698238 | May 12 12:29:54 PM PDT 24 | May 12 12:29:56 PM PDT 24 | 117806871 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/17.xbar_same_source.867031011 | May 12 12:28:39 PM PDT 24 | May 12 12:28:41 PM PDT 24 | 24897515 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4232790547 | May 12 12:30:06 PM PDT 24 | May 12 12:30:58 PM PDT 24 | 47970241211 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2349901339 | May 12 12:26:45 PM PDT 24 | May 12 12:28:07 PM PDT 24 | 27229289400 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/1.xbar_error_random.488734114 | May 12 12:25:57 PM PDT 24 | May 12 12:26:06 PM PDT 24 | 1416521136 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/11.xbar_same_source.4166953781 | May 12 12:28:25 PM PDT 24 | May 12 12:28:33 PM PDT 24 | 2964854166 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1575072518 | May 12 12:26:59 PM PDT 24 | May 12 12:27:58 PM PDT 24 | 5744224751 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3226897148 | May 12 12:29:04 PM PDT 24 | May 12 12:29:06 PM PDT 24 | 9191268 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3835131218 | May 12 12:28:08 PM PDT 24 | May 12 12:28:46 PM PDT 24 | 5061161471 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1770006980 | May 12 12:30:08 PM PDT 24 | May 12 12:31:29 PM PDT 24 | 7423359919 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.4213412746 | May 12 12:28:48 PM PDT 24 | May 12 12:29:00 PM PDT 24 | 4656153690 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.968115408 | May 12 12:28:00 PM PDT 24 | May 12 12:28:04 PM PDT 24 | 13341403 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2291614362 | May 12 12:30:00 PM PDT 24 | May 12 12:30:31 PM PDT 24 | 279582447 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.89452850 | May 12 12:24:38 PM PDT 24 | May 12 12:24:42 PM PDT 24 | 29832768 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3333851235 | May 12 12:28:32 PM PDT 24 | May 12 12:28:45 PM PDT 24 | 274854354 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.881807540 | May 12 12:28:55 PM PDT 24 | May 12 12:29:34 PM PDT 24 | 8328221210 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.454264313 | May 12 12:28:15 PM PDT 24 | May 12 12:28:20 PM PDT 24 | 55514467 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.239759438 | May 12 12:28:18 PM PDT 24 | May 12 12:28:39 PM PDT 24 | 1807685508 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2167668167 | May 12 12:29:20 PM PDT 24 | May 12 12:29:34 PM PDT 24 | 1841104260 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3473082808 | May 12 12:27:57 PM PDT 24 | May 12 12:28:00 PM PDT 24 | 26172018 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1669467988 | May 12 12:27:57 PM PDT 24 | May 12 12:30:19 PM PDT 24 | 93398543757 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2302464394 | May 12 12:30:21 PM PDT 24 | May 12 12:30:30 PM PDT 24 | 14076386087 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1616948907 | May 12 12:27:59 PM PDT 24 | May 12 12:28:18 PM PDT 24 | 2046479068 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3440766281 | May 12 12:28:21 PM PDT 24 | May 12 12:29:40 PM PDT 24 | 32070819296 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3459620528 | May 12 12:29:37 PM PDT 24 | May 12 12:29:45 PM PDT 24 | 78770490 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.484274676 | May 12 12:29:10 PM PDT 24 | May 12 12:30:39 PM PDT 24 | 37368338905 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3314356016 | May 12 12:28:40 PM PDT 24 | May 12 12:28:44 PM PDT 24 | 118179912 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.759002437 | May 12 12:26:52 PM PDT 24 | May 12 12:27:01 PM PDT 24 | 1381799439 ps | ||
| T153 | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1869842527 | May 12 12:29:20 PM PDT 24 | May 12 12:29:33 PM PDT 24 | 694286605 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/28.xbar_smoke.2297024273 | May 12 12:29:11 PM PDT 24 | May 12 12:29:12 PM PDT 24 | 115814181 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.84831269 | May 12 12:28:02 PM PDT 24 | May 12 12:28:11 PM PDT 24 | 1280984396 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3316506287 | May 12 12:30:08 PM PDT 24 | May 12 12:30:14 PM PDT 24 | 218420074 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2284920552 | May 12 12:27:56 PM PDT 24 | May 12 12:28:04 PM PDT 24 | 153109927 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1403448756 | May 12 12:30:08 PM PDT 24 | May 12 12:30:10 PM PDT 24 | 15072502 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2267010153 | May 12 12:28:30 PM PDT 24 | May 12 12:28:38 PM PDT 24 | 1553612175 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3733882960 | May 12 12:29:01 PM PDT 24 | May 12 12:29:10 PM PDT 24 | 6527813984 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1412563321 | May 12 12:29:20 PM PDT 24 | May 12 12:29:27 PM PDT 24 | 1772790644 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.814787215 | May 12 12:29:56 PM PDT 24 | May 12 12:30:06 PM PDT 24 | 1739977185 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1839903188 | May 12 12:30:02 PM PDT 24 | May 12 12:30:10 PM PDT 24 | 63133131 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.912974930 | May 12 12:28:09 PM PDT 24 | May 12 12:28:25 PM PDT 24 | 4067065973 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3481664769 | May 12 12:28:31 PM PDT 24 | May 12 12:28:40 PM PDT 24 | 1605872926 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/34.xbar_same_source.555681242 | May 12 12:29:32 PM PDT 24 | May 12 12:29:39 PM PDT 24 | 270009033 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3372383928 | May 12 12:27:58 PM PDT 24 | May 12 12:28:02 PM PDT 24 | 10162339 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2345154196 | May 12 12:28:46 PM PDT 24 | May 12 12:31:48 PM PDT 24 | 28817203548 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3363299489 | May 12 12:29:12 PM PDT 24 | May 12 12:29:16 PM PDT 24 | 28233914 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.348769141 | May 12 12:30:02 PM PDT 24 | May 12 12:30:06 PM PDT 24 | 27682757 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/29.xbar_error_random.4164168840 | May 12 12:29:33 PM PDT 24 | May 12 12:29:40 PM PDT 24 | 588202627 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.181343895 | May 12 12:28:23 PM PDT 24 | May 12 12:28:28 PM PDT 24 | 255002839 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4229135671 | May 12 12:29:32 PM PDT 24 | May 12 12:29:37 PM PDT 24 | 410950442 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1582886462 | May 12 12:29:03 PM PDT 24 | May 12 12:29:11 PM PDT 24 | 1540391600 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.329142077 | May 12 12:30:08 PM PDT 24 | May 12 12:30:17 PM PDT 24 | 2559689685 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3075368157 | May 12 12:29:20 PM PDT 24 | May 12 12:30:24 PM PDT 24 | 37154658861 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3051720841 | May 12 12:29:08 PM PDT 24 | May 12 12:29:24 PM PDT 24 | 222394129 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/28.xbar_same_source.2033866648 | May 12 12:29:07 PM PDT 24 | May 12 12:29:09 PM PDT 24 | 127549639 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.584134501 | May 12 12:28:10 PM PDT 24 | May 12 12:28:13 PM PDT 24 | 67284124 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2119034307 | May 12 12:26:45 PM PDT 24 | May 12 12:27:55 PM PDT 24 | 30623445802 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4234258335 | May 12 12:30:00 PM PDT 24 | May 12 12:30:53 PM PDT 24 | 6165397220 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3003912394 | May 12 12:30:08 PM PDT 24 | May 12 12:30:14 PM PDT 24 | 281309969 ps | ||
| T17 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1772003870 | May 12 12:29:37 PM PDT 24 | May 12 12:32:15 PM PDT 24 | 21785535155 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2518259860 | May 12 12:29:40 PM PDT 24 | May 12 12:29:50 PM PDT 24 | 2421843889 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3201962600 | May 12 12:28:52 PM PDT 24 | May 12 12:30:10 PM PDT 24 | 22852740549 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1449147762 | May 12 12:28:24 PM PDT 24 | May 12 12:28:32 PM PDT 24 | 507391512 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2545429740 | May 12 12:29:37 PM PDT 24 | May 12 12:29:44 PM PDT 24 | 612423713 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3084075617 | May 12 12:30:04 PM PDT 24 | May 12 12:30:23 PM PDT 24 | 80952119 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1418535427 | May 12 12:27:57 PM PDT 24 | May 12 12:28:25 PM PDT 24 | 470794753 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.2149910256 | May 12 12:29:49 PM PDT 24 | May 12 12:30:13 PM PDT 24 | 150468845 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.928463499 | May 12 12:28:05 PM PDT 24 | May 12 12:29:20 PM PDT 24 | 718591947 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/30.xbar_random.337180935 | May 12 12:29:50 PM PDT 24 | May 12 12:29:58 PM PDT 24 | 690269747 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/8.xbar_smoke.950504532 | May 12 12:28:06 PM PDT 24 | May 12 12:28:09 PM PDT 24 | 111828967 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2012528764 | May 12 12:30:12 PM PDT 24 | May 12 12:30:23 PM PDT 24 | 581750647 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.478069792 | May 12 12:30:00 PM PDT 24 | May 12 12:33:09 PM PDT 24 | 118100456645 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2817318818 | May 12 12:29:13 PM PDT 24 | May 12 12:29:16 PM PDT 24 | 282423014 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3031161838 | May 12 12:29:18 PM PDT 24 | May 12 12:29:31 PM PDT 24 | 4637735736 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/49.xbar_random.1326933728 | May 12 12:30:15 PM PDT 24 | May 12 12:30:30 PM PDT 24 | 4960651702 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/39.xbar_error_random.1250640858 | May 12 12:29:51 PM PDT 24 | May 12 12:30:04 PM PDT 24 | 1337097497 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.146124310 | May 12 12:30:09 PM PDT 24 | May 12 12:30:14 PM PDT 24 | 23419826 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3226881061 | May 12 12:29:26 PM PDT 24 | May 12 12:29:28 PM PDT 24 | 22992469 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.887951656 | May 12 12:28:03 PM PDT 24 | May 12 12:28:07 PM PDT 24 | 22884580 ps | ||
| T105 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3367354042 | May 12 12:28:30 PM PDT 24 | May 12 12:31:07 PM PDT 24 | 4992456915 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3882575099 | May 12 12:29:32 PM PDT 24 | May 12 12:31:19 PM PDT 24 | 34959976280 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3026397176 | May 12 12:29:30 PM PDT 24 | May 12 12:30:41 PM PDT 24 | 829744766 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.961788135 | May 12 12:27:53 PM PDT 24 | May 12 12:28:03 PM PDT 24 | 100977610 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.403955401 | May 12 12:29:53 PM PDT 24 | May 12 12:29:56 PM PDT 24 | 28790992 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/44.xbar_random.1588944060 | May 12 12:29:57 PM PDT 24 | May 12 12:30:04 PM PDT 24 | 53450795 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2630480326 | May 12 12:30:00 PM PDT 24 | May 12 12:34:45 PM PDT 24 | 146738298021 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/11.xbar_random.1657339273 | May 12 12:28:12 PM PDT 24 | May 12 12:28:19 PM PDT 24 | 394781481 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/25.xbar_smoke.97381059 | May 12 12:29:11 PM PDT 24 | May 12 12:29:13 PM PDT 24 | 62352516 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3849177938 | May 12 12:28:02 PM PDT 24 | May 12 12:28:18 PM PDT 24 | 10130392306 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/12.xbar_error_random.658135217 | May 12 12:28:29 PM PDT 24 | May 12 12:28:35 PM PDT 24 | 678554541 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2839600831 | May 12 12:28:44 PM PDT 24 | May 12 12:28:46 PM PDT 24 | 14574280 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1696651351 | May 12 12:27:55 PM PDT 24 | May 12 12:29:11 PM PDT 24 | 501323412 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/20.xbar_same_source.3776921999 | May 12 12:28:44 PM PDT 24 | May 12 12:28:56 PM PDT 24 | 1687615290 ps | ||
| T106 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3561954287 | May 12 12:29:33 PM PDT 24 | May 12 12:29:51 PM PDT 24 | 3032724375 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.4000788740 | May 12 12:30:09 PM PDT 24 | May 12 12:30:13 PM PDT 24 | 192857145 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2935001400 | May 12 12:30:01 PM PDT 24 | May 12 12:30:25 PM PDT 24 | 489907820 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.853014049 | May 12 12:27:58 PM PDT 24 | May 12 12:28:05 PM PDT 24 | 48668878 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1594176418 | May 12 12:29:25 PM PDT 24 | May 12 12:29:28 PM PDT 24 | 117052050 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3025453645 | May 12 12:30:01 PM PDT 24 | May 12 12:30:12 PM PDT 24 | 3110306412 ps | ||
| T133 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2967564086 | May 12 12:29:06 PM PDT 24 | May 12 12:32:10 PM PDT 24 | 32871097110 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1352988698 | May 12 12:29:31 PM PDT 24 | May 12 12:29:54 PM PDT 24 | 4828199205 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2620246207 | May 12 12:28:09 PM PDT 24 | May 12 12:28:21 PM PDT 24 | 1344550844 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1897620722 | May 12 12:28:13 PM PDT 24 | May 12 12:28:16 PM PDT 24 | 19302438 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/21.xbar_smoke.498183601 | May 12 12:28:48 PM PDT 24 | May 12 12:28:50 PM PDT 24 | 17939417 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.2347798764 | May 12 12:30:04 PM PDT 24 | May 12 12:30:24 PM PDT 24 | 2428911173 ps |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2069202791 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 915692316 ps |
| CPU time | 14.51 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:33 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-8123cc2d-b76b-48b5-b861-b2aec5f72064 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2069202791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2069202791 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.185486260 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 44515737203 ps |
| CPU time | 284.57 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:33:33 PM PDT 24 |
| Peak memory | 203660 kb |
| Host | smart-143065d2-e81b-4be1-8f6a-229bf3100636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=185486260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.185486260 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1378585379 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 48943001355 ps |
| CPU time | 288.06 seconds |
| Started | May 12 12:28:09 PM PDT 24 |
| Finished | May 12 12:32:59 PM PDT 24 |
| Peak memory | 203400 kb |
| Host | smart-42ec4dd1-92e6-45bf-85ca-3a62b19d7823 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1378585379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.1378585379 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1406586126 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 56185526639 ps |
| CPU time | 273.63 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:34:42 PM PDT 24 |
| Peak memory | 202908 kb |
| Host | smart-27f62809-95e0-43d9-b01b-2c5ceb5abc1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1406586126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1406586126 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1184546248 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 72049572711 ps |
| CPU time | 351.19 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:34:05 PM PDT 24 |
| Peak memory | 202956 kb |
| Host | smart-341882c7-6250-4677-b944-dc11c104fdb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1184546248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1184546248 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.918294099 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 457369745 ps |
| CPU time | 92.3 seconds |
| Started | May 12 12:28:01 PM PDT 24 |
| Finished | May 12 12:29:36 PM PDT 24 |
| Peak memory | 204420 kb |
| Host | smart-02cdf7b5-4ff4-44f2-bb17-a3a053974986 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=918294099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_ reset.918294099 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3401529564 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 30011870348 ps |
| CPU time | 155.34 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:32:09 PM PDT 24 |
| Peak memory | 202928 kb |
| Host | smart-7e14e145-a5ca-4109-88d1-eeb902087a5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3401529564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3401529564 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3152829668 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3307633209 ps |
| CPU time | 12.15 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:52 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-c7e19672-844d-4d16-9487-7fd9d3231d09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152829668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3152829668 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1737616893 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7304033685 ps |
| CPU time | 100.94 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:31:12 PM PDT 24 |
| Peak memory | 206228 kb |
| Host | smart-281ac238-728a-47a5-b2de-e8529d5ce4e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1737616893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.1737616893 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2553592479 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 48225168081 ps |
| CPU time | 227.62 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:33:41 PM PDT 24 |
| Peak memory | 202832 kb |
| Host | smart-24178bef-7278-4b46-b6b3-06e27ef5c6fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2553592479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.2553592479 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1095221486 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8513203079 ps |
| CPU time | 150.29 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:32:28 PM PDT 24 |
| Peak memory | 204792 kb |
| Host | smart-14fabf91-8a54-47cc-8c9a-4e12c0d29dd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1095221486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1095221486 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1546950514 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 18121139851 ps |
| CPU time | 219.98 seconds |
| Started | May 12 12:29:43 PM PDT 24 |
| Finished | May 12 12:33:24 PM PDT 24 |
| Peak memory | 206464 kb |
| Host | smart-8ac35557-812c-4cb5-9374-5106535a54c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1546950514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1546950514 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1145579063 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 804601129 ps |
| CPU time | 74.73 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:30:44 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-7770ede0-8eed-494e-adc5-f40573399072 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1145579063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1145579063 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.467866275 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 721979621 ps |
| CPU time | 14.57 seconds |
| Started | May 12 12:28:23 PM PDT 24 |
| Finished | May 12 12:28:38 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-71af5a22-84e4-4ce5-9079-eb4f49134d95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=467866275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.467866275 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.818287612 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15503070246 ps |
| CPU time | 132.19 seconds |
| Started | May 12 12:28:30 PM PDT 24 |
| Finished | May 12 12:30:43 PM PDT 24 |
| Peak memory | 206512 kb |
| Host | smart-b1712a41-5547-4523-af2f-390abe6b8420 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=818287612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.818287612 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3377305370 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 466123712 ps |
| CPU time | 85.65 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:29:23 PM PDT 24 |
| Peak memory | 204200 kb |
| Host | smart-06d304ee-9101-4e91-bf72-bfa6d150b90b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3377305370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3377305370 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2469286960 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1847764783 ps |
| CPU time | 80.47 seconds |
| Started | May 12 12:30:16 PM PDT 24 |
| Finished | May 12 12:31:37 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-c6584e3f-5338-4a13-ae69-5d36d467e497 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2469286960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2469286960 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1231845709 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 59509761725 ps |
| CPU time | 211.03 seconds |
| Started | May 12 12:28:35 PM PDT 24 |
| Finished | May 12 12:32:07 PM PDT 24 |
| Peak memory | 202932 kb |
| Host | smart-e0e6f117-70bc-4d9a-91f5-86cea051d129 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1231845709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.1231845709 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.4267449290 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 7166216484 ps |
| CPU time | 133.59 seconds |
| Started | May 12 12:27:53 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-26787e0e-4366-49df-8447-9b2fdb162942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4267449290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.4267449290 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3367354042 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4992456915 ps |
| CPU time | 156.61 seconds |
| Started | May 12 12:28:30 PM PDT 24 |
| Finished | May 12 12:31:07 PM PDT 24 |
| Peak memory | 207776 kb |
| Host | smart-fbe34b1f-257f-44e7-9289-0c534b37ea34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3367354042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3367354042 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1646670774 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8900585844 ps |
| CPU time | 159.93 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:32:48 PM PDT 24 |
| Peak memory | 204832 kb |
| Host | smart-8efd94a7-37ac-489f-aec9-137aafb92fc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646670774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1646670774 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3553414148 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 103340142 ps |
| CPU time | 21.72 seconds |
| Started | May 12 12:28:32 PM PDT 24 |
| Finished | May 12 12:28:54 PM PDT 24 |
| Peak memory | 202836 kb |
| Host | smart-bd2c2c24-28f2-4d6a-a1e9-988cd218ee02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3553414148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.3553414148 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3167321611 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 724470512 ps |
| CPU time | 7.09 seconds |
| Started | May 12 12:26:50 PM PDT 24 |
| Finished | May 12 12:26:58 PM PDT 24 |
| Peak memory | 201484 kb |
| Host | smart-6b0d51ac-ba6e-4310-b356-4bf64390481e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3167321611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3167321611 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3129193220 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1380980006 ps |
| CPU time | 9.13 seconds |
| Started | May 12 12:24:50 PM PDT 24 |
| Finished | May 12 12:25:00 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-f37f47f6-e20f-4c14-9130-18ad5d79602b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3129193220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3129193220 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2296551239 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 27167061865 ps |
| CPU time | 173.16 seconds |
| Started | May 12 12:22:43 PM PDT 24 |
| Finished | May 12 12:25:37 PM PDT 24 |
| Peak memory | 203260 kb |
| Host | smart-70e21120-f125-4046-ab58-3f3816585be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2296551239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2296551239 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.639443006 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 36391053 ps |
| CPU time | 1.38 seconds |
| Started | May 12 12:24:53 PM PDT 24 |
| Finished | May 12 12:24:54 PM PDT 24 |
| Peak memory | 201900 kb |
| Host | smart-55f5ec51-e820-4de7-b0ce-4a355c3901f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=639443006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.639443006 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.1884389158 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 73499580 ps |
| CPU time | 6.02 seconds |
| Started | May 12 12:22:21 PM PDT 24 |
| Finished | May 12 12:22:27 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-052e378a-8e9c-4a21-a3ef-081a34ce4ccf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884389158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1884389158 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.2972919807 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 100408409 ps |
| CPU time | 1.57 seconds |
| Started | May 12 12:26:52 PM PDT 24 |
| Finished | May 12 12:26:54 PM PDT 24 |
| Peak memory | 201492 kb |
| Host | smart-6fec111b-5a01-4d10-8ced-1413624a9173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2972919807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2972919807 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2349901339 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 27229289400 ps |
| CPU time | 80.8 seconds |
| Started | May 12 12:26:45 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 200572 kb |
| Host | smart-6caf58ec-0b5c-4741-85e0-05811aa4b81f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349901339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2349901339 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2119034307 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 30623445802 ps |
| CPU time | 69.15 seconds |
| Started | May 12 12:26:45 PM PDT 24 |
| Finished | May 12 12:27:55 PM PDT 24 |
| Peak memory | 200596 kb |
| Host | smart-ced28fb9-cd97-4258-a7d6-95f3873c76ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2119034307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2119034307 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.25773469 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 250554002 ps |
| CPU time | 5.55 seconds |
| Started | May 12 12:26:57 PM PDT 24 |
| Finished | May 12 12:27:04 PM PDT 24 |
| Peak memory | 201436 kb |
| Host | smart-e84d75ff-70e5-4162-a904-4db769f92df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25773469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.25773469 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2858959673 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 29007007 ps |
| CPU time | 1.46 seconds |
| Started | May 12 12:25:58 PM PDT 24 |
| Finished | May 12 12:26:01 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-641c141e-292c-4a1e-85a2-b5ccca6cecf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2858959673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2858959673 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.1353065551 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 26582373 ps |
| CPU time | 1.08 seconds |
| Started | May 12 12:26:57 PM PDT 24 |
| Finished | May 12 12:26:59 PM PDT 24 |
| Peak memory | 200972 kb |
| Host | smart-bd744aaa-2c26-4890-bb03-459b294b9b0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1353065551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1353065551 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.980874420 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1403624777 ps |
| CPU time | 6.7 seconds |
| Started | May 12 12:26:47 PM PDT 24 |
| Finished | May 12 12:26:55 PM PDT 24 |
| Peak memory | 201432 kb |
| Host | smart-64fa0966-951f-4d65-9e58-bab511dda579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=980874420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.980874420 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.759002437 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1381799439 ps |
| CPU time | 8.42 seconds |
| Started | May 12 12:26:52 PM PDT 24 |
| Finished | May 12 12:27:01 PM PDT 24 |
| Peak memory | 201516 kb |
| Host | smart-d16ce084-0819-4aa8-b9e7-8bef89c37247 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=759002437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.759002437 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.4035927250 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 13596194 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:24:32 PM PDT 24 |
| Finished | May 12 12:24:34 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-3364a94d-883a-4c84-b5fb-25a0ba59b53e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035927250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.4035927250 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.486228514 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1224120492 ps |
| CPU time | 27.09 seconds |
| Started | May 12 12:25:59 PM PDT 24 |
| Finished | May 12 12:26:28 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-958561f8-a7a6-47f5-b508-849760885164 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486228514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.486228514 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1575072518 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 5744224751 ps |
| CPU time | 57.74 seconds |
| Started | May 12 12:26:59 PM PDT 24 |
| Finished | May 12 12:27:58 PM PDT 24 |
| Peak memory | 202624 kb |
| Host | smart-eb5458b2-8395-4853-aa3b-1aa2ed987f87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1575072518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1575072518 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.4070344781 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6357776307 ps |
| CPU time | 97.26 seconds |
| Started | May 12 12:26:00 PM PDT 24 |
| Finished | May 12 12:27:38 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-90b22606-f210-44ac-bb78-dbe7f7bf5bcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070344781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.4070344781 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3512730918 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 947524398 ps |
| CPU time | 115.49 seconds |
| Started | May 12 12:26:31 PM PDT 24 |
| Finished | May 12 12:28:27 PM PDT 24 |
| Peak memory | 207564 kb |
| Host | smart-6256fe2d-d87f-48a5-afda-ef658df32e75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3512730918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3512730918 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.413159518 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 485716660 ps |
| CPU time | 7.84 seconds |
| Started | May 12 12:26:58 PM PDT 24 |
| Finished | May 12 12:27:07 PM PDT 24 |
| Peak memory | 201472 kb |
| Host | smart-00070e2c-a61c-444b-b69d-70db95d30a18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413159518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.413159518 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3306059640 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4404116611 ps |
| CPU time | 29.38 seconds |
| Started | May 12 12:26:51 PM PDT 24 |
| Finished | May 12 12:27:22 PM PDT 24 |
| Peak memory | 201628 kb |
| Host | smart-c3b2550c-5e85-4b02-852e-76040fbbb84f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3306059640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3306059640 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2808530049 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 70880022 ps |
| CPU time | 1.35 seconds |
| Started | May 12 12:27:50 PM PDT 24 |
| Finished | May 12 12:27:52 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-7557f183-ef24-431f-9f4c-35e91d5a0435 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2808530049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2808530049 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.488734114 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1416521136 ps |
| CPU time | 6.34 seconds |
| Started | May 12 12:25:57 PM PDT 24 |
| Finished | May 12 12:26:06 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-c0cb57c7-0432-4031-9819-8333f04939b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=488734114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.488734114 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.832690183 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 14135910 ps |
| CPU time | 1.63 seconds |
| Started | May 12 12:26:51 PM PDT 24 |
| Finished | May 12 12:26:54 PM PDT 24 |
| Peak memory | 200788 kb |
| Host | smart-8a9a9eb5-7fc6-46e8-b6fc-fa98f4415d49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=832690183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.832690183 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.353404924 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 23225041253 ps |
| CPU time | 71.59 seconds |
| Started | May 12 12:23:01 PM PDT 24 |
| Finished | May 12 12:24:13 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-d3d5b0e5-e4b2-4cd4-9535-8d4b72ef011e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=353404924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.353404924 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3321358685 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 8234712735 ps |
| CPU time | 21.12 seconds |
| Started | May 12 12:25:57 PM PDT 24 |
| Finished | May 12 12:26:19 PM PDT 24 |
| Peak memory | 201604 kb |
| Host | smart-c647b6f2-d48e-4652-b2f0-c0b2fa834489 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3321358685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3321358685 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.89452850 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 29832768 ps |
| CPU time | 3.75 seconds |
| Started | May 12 12:24:38 PM PDT 24 |
| Finished | May 12 12:24:42 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-02ee276d-cf17-4912-a0a4-f3dc8c3a3cf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89452850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.89452850 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.1605829166 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 429035506 ps |
| CPU time | 2.36 seconds |
| Started | May 12 12:23:51 PM PDT 24 |
| Finished | May 12 12:23:54 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-a6496415-36b4-488e-8eeb-7a3f04b37e51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1605829166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1605829166 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.2345961202 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 8744293 ps |
| CPU time | 1.06 seconds |
| Started | May 12 12:25:59 PM PDT 24 |
| Finished | May 12 12:26:01 PM PDT 24 |
| Peak memory | 201484 kb |
| Host | smart-c4c2b058-a735-4f91-ad96-92265add73b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345961202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2345961202 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1629714886 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1233568268 ps |
| CPU time | 6.24 seconds |
| Started | May 12 12:25:56 PM PDT 24 |
| Finished | May 12 12:26:03 PM PDT 24 |
| Peak memory | 201468 kb |
| Host | smart-07a7156b-1744-4dd0-936c-cd48454823d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629714886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1629714886 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.941099699 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1781332605 ps |
| CPU time | 9.7 seconds |
| Started | May 12 12:24:09 PM PDT 24 |
| Finished | May 12 12:24:19 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-06a46eb9-e6e2-4e9b-986a-28d3e0e52202 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=941099699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.941099699 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2346255726 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 8508853 ps |
| CPU time | 0.97 seconds |
| Started | May 12 12:27:08 PM PDT 24 |
| Finished | May 12 12:27:09 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-8be7db04-e65d-4134-aa5c-2e65b538ab4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346255726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2346255726 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2318359915 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2231703072 ps |
| CPU time | 20.9 seconds |
| Started | May 12 12:27:51 PM PDT 24 |
| Finished | May 12 12:28:13 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-d8fe243d-e85f-4f58-8366-8a260cd0d2b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2318359915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2318359915 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1418535427 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 470794753 ps |
| CPU time | 27.6 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:25 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-ac0e3215-bde9-46af-adcb-05d8cf32ba97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1418535427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1418535427 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2338771618 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 990651670 ps |
| CPU time | 168.31 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:30:50 PM PDT 24 |
| Peak memory | 206252 kb |
| Host | smart-d9f700af-c098-4d82-b311-b9b736ed221e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2338771618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2338771618 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2427412935 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 884711727 ps |
| CPU time | 8.05 seconds |
| Started | May 12 12:27:47 PM PDT 24 |
| Finished | May 12 12:27:56 PM PDT 24 |
| Peak memory | 201760 kb |
| Host | smart-9481afbe-13cf-4484-a5f4-a11872846be9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2427412935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2427412935 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2691761942 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 61479723 ps |
| CPU time | 7.62 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:28:19 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-75fa29c2-daf0-4fb7-832e-82ccfa2f1e91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2691761942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2691761942 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1689997486 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5948995964 ps |
| CPU time | 16.29 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:28:25 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-30b0995e-e490-46ae-9700-e3ac0cccd2c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1689997486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1689997486 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2588649399 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 30791110 ps |
| CPU time | 2.53 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-c4c4aa91-b90b-42cc-8f70-0d62bc222556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588649399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2588649399 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2575211242 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 83172392 ps |
| CPU time | 3.81 seconds |
| Started | May 12 12:28:19 PM PDT 24 |
| Finished | May 12 12:28:24 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-f62b6f75-ffc4-4253-814a-8c39d91968e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2575211242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2575211242 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.665542720 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 919955099 ps |
| CPU time | 5.7 seconds |
| Started | May 12 12:28:07 PM PDT 24 |
| Finished | May 12 12:28:14 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-bf2a19e1-6a08-4a40-9269-60033737571d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=665542720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.665542720 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2074824910 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 9347679178 ps |
| CPU time | 28.62 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-efeec3c1-9d7c-4b65-8594-8a929810d1d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074824910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2074824910 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3835131218 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 5061161471 ps |
| CPU time | 35.45 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:28:46 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-472a531c-0d75-4272-a11f-538d9bbda4c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3835131218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3835131218 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2211119602 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 76939850 ps |
| CPU time | 5.4 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:20 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-94001a29-2e24-4fa8-97be-a0c40c0bbe0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211119602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2211119602 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1107357956 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 158674049 ps |
| CPU time | 3.99 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-2d72e009-24b0-4ba6-85ed-15d00c47dca4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1107357956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1107357956 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.436299826 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8635168 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:15 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-9ff4aa8e-04b4-4a59-85a3-3b94d193242b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=436299826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.436299826 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2645326991 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2140304474 ps |
| CPU time | 10.22 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:24 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-a777b24b-4b1f-4d86-9b3d-037ba1e4c7f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645326991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2645326991 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2978757602 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3889059227 ps |
| CPU time | 11 seconds |
| Started | May 12 12:28:14 PM PDT 24 |
| Finished | May 12 12:28:26 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-7cb621a5-d9f1-426f-8cdd-40649a0fa96a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2978757602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2978757602 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1051331255 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 14998966 ps |
| CPU time | 1.04 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201704 kb |
| Host | smart-df92c009-ff9d-4cd9-b2a3-15df203f5ccb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051331255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1051331255 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.252381360 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 6155632018 ps |
| CPU time | 18.82 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:28:42 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-b5661d12-509c-4315-a361-effb17caf600 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=252381360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.252381360 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3463958421 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 3746280109 ps |
| CPU time | 29.77 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:47 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-83580f6c-7109-4fbd-9ddb-eb4b7ca7479e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463958421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3463958421 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1184512241 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 176088979 ps |
| CPU time | 22.29 seconds |
| Started | May 12 12:28:17 PM PDT 24 |
| Finished | May 12 12:28:40 PM PDT 24 |
| Peak memory | 203940 kb |
| Host | smart-5b400d0a-e16e-4a3b-9b1d-b6f82897e230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184512241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1184512241 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1415334959 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 491761565 ps |
| CPU time | 52.89 seconds |
| Started | May 12 12:28:21 PM PDT 24 |
| Finished | May 12 12:29:15 PM PDT 24 |
| Peak memory | 203444 kb |
| Host | smart-0250cc2b-3e97-4878-ab75-9d8657137721 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1415334959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1415334959 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.584134501 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 67284124 ps |
| CPU time | 1.28 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:28:13 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-959c5646-806f-40d0-a635-ac6740fb474d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=584134501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.584134501 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3280550404 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 683973727 ps |
| CPU time | 11.66 seconds |
| Started | May 12 12:28:31 PM PDT 24 |
| Finished | May 12 12:28:44 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-9675b74b-8999-4246-9e0b-124bb2d048a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3280550404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3280550404 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1496771200 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 175540780 ps |
| CPU time | 4.95 seconds |
| Started | May 12 12:28:21 PM PDT 24 |
| Finished | May 12 12:28:27 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-7a87ce23-1c54-4e06-b3af-0f226c8aaee7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1496771200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1496771200 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.171193650 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 55326336 ps |
| CPU time | 6.14 seconds |
| Started | May 12 12:28:15 PM PDT 24 |
| Finished | May 12 12:28:22 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-2ac5bb2f-170e-4ae6-a7f0-e699bcb6bd1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171193650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.171193650 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1657339273 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 394781481 ps |
| CPU time | 5 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:19 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-43f3ba44-c808-401f-8a13-a658bd7858d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1657339273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1657339273 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1932946221 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 11721646372 ps |
| CPU time | 53.71 seconds |
| Started | May 12 12:28:33 PM PDT 24 |
| Finished | May 12 12:29:28 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-b880d0e2-e0c1-4050-b2ec-f783db46b995 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932946221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1932946221 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4258029009 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1226522842 ps |
| CPU time | 6.73 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:21 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-d16ae9f2-b01c-4885-a3ce-d53bc8c2a66d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4258029009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4258029009 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1449147762 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 507391512 ps |
| CPU time | 7.15 seconds |
| Started | May 12 12:28:24 PM PDT 24 |
| Finished | May 12 12:28:32 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-496947f0-ed2a-44b3-9b66-df126cee3edb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449147762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1449147762 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.4166953781 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2964854166 ps |
| CPU time | 8.43 seconds |
| Started | May 12 12:28:25 PM PDT 24 |
| Finished | May 12 12:28:33 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-95059c7d-b9fa-491f-b3ba-e00452cc6288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4166953781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4166953781 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.897214672 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 73959655 ps |
| CPU time | 1.45 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-14790494-28b2-4036-9e1f-7b1e578924e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=897214672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.897214672 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3861598522 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5574885742 ps |
| CPU time | 9.12 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:26 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-76bd8edd-4d8a-409f-a5a8-69b2a66a5b32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861598522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3861598522 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.4218826601 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 814392986 ps |
| CPU time | 5.65 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:23 PM PDT 24 |
| Peak memory | 201744 kb |
| Host | smart-d979766b-0d93-4ae6-bcb4-95b544e8803b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4218826601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.4218826601 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.50504897 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 8128754 ps |
| CPU time | 1.03 seconds |
| Started | May 12 12:28:28 PM PDT 24 |
| Finished | May 12 12:28:30 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-c8126258-5ab6-483a-8f2c-2d35dc75b73e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50504897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.50504897 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1499212559 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3550292959 ps |
| CPU time | 41.82 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 202908 kb |
| Host | smart-0fc59579-f15a-4a15-9193-5fd6b43be9d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1499212559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1499212559 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2093388031 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 14836165776 ps |
| CPU time | 47.88 seconds |
| Started | May 12 12:28:23 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 202968 kb |
| Host | smart-d6799ff4-7ba0-4a91-9ded-c39fb8f626fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093388031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2093388031 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1553017572 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2106423032 ps |
| CPU time | 214.74 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:31:51 PM PDT 24 |
| Peak memory | 204112 kb |
| Host | smart-5dd21f3c-d606-4a14-89ea-554fe03bf092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1553017572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1553017572 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3102382885 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 21097266338 ps |
| CPU time | 231.31 seconds |
| Started | May 12 12:28:17 PM PDT 24 |
| Finished | May 12 12:32:09 PM PDT 24 |
| Peak memory | 207980 kb |
| Host | smart-19a842fc-2828-4696-89d4-85cff30b96e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3102382885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3102382885 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2947578257 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 77267528 ps |
| CPU time | 4.77 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:22 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-8e01467a-1be6-4011-8b3c-ceb230d4c944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2947578257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2947578257 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.896539796 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 67471879 ps |
| CPU time | 2.26 seconds |
| Started | May 12 12:28:34 PM PDT 24 |
| Finished | May 12 12:28:37 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-bbe2c511-7429-4275-a454-2efc18a32b35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=896539796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.896539796 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3556312695 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 8748950870 ps |
| CPU time | 64.14 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-e46c9fd8-4b52-4c3b-97bc-20c5be6a1d2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3556312695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.3556312695 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2428130595 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 800305870 ps |
| CPU time | 6.04 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:28:52 PM PDT 24 |
| Peak memory | 201704 kb |
| Host | smart-452537b8-2b32-40eb-b1e0-68fae5fbb251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2428130595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2428130595 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.658135217 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 678554541 ps |
| CPU time | 5.96 seconds |
| Started | May 12 12:28:29 PM PDT 24 |
| Finished | May 12 12:28:35 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-97262ce3-0941-47ef-a708-c8c8070049db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=658135217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.658135217 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3261112413 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1007821736 ps |
| CPU time | 15.41 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:29:01 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-3b785ea2-a2b3-4b19-9354-1aef297c0f52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261112413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3261112413 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3745775529 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 185201029310 ps |
| CPU time | 154.38 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:31:14 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-acf3741d-c659-4460-839a-d27572c0c4b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745775529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3745775529 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.446414393 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 82555649834 ps |
| CPU time | 78.32 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-f5837366-2b7f-49d2-8ebd-7842588b96e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=446414393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.446414393 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.454264313 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 55514467 ps |
| CPU time | 4.92 seconds |
| Started | May 12 12:28:15 PM PDT 24 |
| Finished | May 12 12:28:20 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-bd927902-edd7-4cb9-b1bb-af2aaa5de69d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454264313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.454264313 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.1192973266 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 119439065 ps |
| CPU time | 4.44 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:28:27 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-cfb221f5-2854-44ae-b24c-81c5dce9c1fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1192973266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1192973266 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1897620722 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 19302438 ps |
| CPU time | 1.09 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-eea61cb1-9f3c-4f62-abd3-b79bf991c3c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897620722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1897620722 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.22401133 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1636168358 ps |
| CPU time | 7.29 seconds |
| Started | May 12 12:28:35 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-e56d4d49-9520-477f-abed-c9f4dba3fb72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=22401133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.22401133 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.131323966 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1804210890 ps |
| CPU time | 13.47 seconds |
| Started | May 12 12:28:17 PM PDT 24 |
| Finished | May 12 12:28:31 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-f7c705f4-6c81-40bb-8665-7f17692b6d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=131323966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.131323966 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2737701913 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 9561686 ps |
| CPU time | 1.08 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-7dc19911-e4b3-4786-a437-cb2bc110855b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737701913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2737701913 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3411287467 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 809549956 ps |
| CPU time | 26.8 seconds |
| Started | May 12 12:28:23 PM PDT 24 |
| Finished | May 12 12:28:51 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-091a7eed-24ce-4f84-9e2a-b4cb3e53879a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3411287467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3411287467 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.561048008 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 420731910 ps |
| CPU time | 36.16 seconds |
| Started | May 12 12:28:24 PM PDT 24 |
| Finished | May 12 12:29:01 PM PDT 24 |
| Peak memory | 203880 kb |
| Host | smart-28fd324d-a70b-4347-b3d9-56831ab640b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561048008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.561048008 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1356885578 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 17179963219 ps |
| CPU time | 202.23 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:32:03 PM PDT 24 |
| Peak memory | 207060 kb |
| Host | smart-bcbb1403-285c-4289-9716-1eb5dc96885a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1356885578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1356885578 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2693653449 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 621276407 ps |
| CPU time | 7.37 seconds |
| Started | May 12 12:28:24 PM PDT 24 |
| Finished | May 12 12:28:32 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-09ec3f76-834e-4232-b063-11f6bab7a806 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693653449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2693653449 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3440766281 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 32070819296 ps |
| CPU time | 78.42 seconds |
| Started | May 12 12:28:21 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 202876 kb |
| Host | smart-5f15686f-c5b6-455d-9c6d-535e9acd5b91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3440766281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3440766281 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3623440747 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 106720767 ps |
| CPU time | 1.08 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-edf86676-4bc1-41ea-ba2a-6617113cd78d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3623440747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3623440747 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.2211037649 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 74085349 ps |
| CPU time | 7.31 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:28:30 PM PDT 24 |
| Peak memory | 201748 kb |
| Host | smart-b291a806-4fc6-49fe-8fe9-c779a088fd85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211037649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2211037649 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.4263268329 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 54412548 ps |
| CPU time | 7.35 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:53 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-11395dcf-0818-4778-bb8b-2d11165ab07e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4263268329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.4263268329 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3188820312 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 25647862421 ps |
| CPU time | 93.38 seconds |
| Started | May 12 12:28:23 PM PDT 24 |
| Finished | May 12 12:29:57 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-4d0e255b-16fb-4442-955b-2de01403b910 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188820312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3188820312 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.739113177 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 12151059634 ps |
| CPU time | 94.9 seconds |
| Started | May 12 12:28:20 PM PDT 24 |
| Finished | May 12 12:29:56 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-a8c5786d-2cf0-4bed-be9f-55f22388c8a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=739113177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.739113177 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.4015857219 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 15738209 ps |
| CPU time | 1.67 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:28:24 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-4145a692-ef6e-4b34-adea-e8fe1a93b03d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015857219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.4015857219 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.2508500970 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2184260179 ps |
| CPU time | 8.67 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:28:51 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-03e0aba7-9211-4131-8fcd-30cdb3fd355e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2508500970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2508500970 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.2183086915 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 13174385 ps |
| CPU time | 1.02 seconds |
| Started | May 12 12:28:21 PM PDT 24 |
| Finished | May 12 12:28:22 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-84093040-0e2a-4691-9fa6-cd452a343bab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2183086915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2183086915 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3458060580 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2479744862 ps |
| CPU time | 11.48 seconds |
| Started | May 12 12:28:23 PM PDT 24 |
| Finished | May 12 12:28:36 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-1b6d1736-2a5d-4def-b5b5-0aab749d706c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458060580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3458060580 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2267010153 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1553612175 ps |
| CPU time | 8.5 seconds |
| Started | May 12 12:28:30 PM PDT 24 |
| Finished | May 12 12:28:38 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-54139ba9-bc4a-4a75-8b19-6e271e4ce646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2267010153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2267010153 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2815115335 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 8963290 ps |
| CPU time | 1.07 seconds |
| Started | May 12 12:28:33 PM PDT 24 |
| Finished | May 12 12:28:34 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-921f5ada-f2c3-426b-ba17-fe8cfdf090a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815115335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2815115335 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3251922510 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2265858327 ps |
| CPU time | 37.24 seconds |
| Started | May 12 12:28:28 PM PDT 24 |
| Finished | May 12 12:29:05 PM PDT 24 |
| Peak memory | 202860 kb |
| Host | smart-bb2fdc47-fb0e-495e-a1c2-93f06976e811 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251922510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3251922510 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2595199221 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 611647897 ps |
| CPU time | 21.36 seconds |
| Started | May 12 12:28:25 PM PDT 24 |
| Finished | May 12 12:28:47 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-7b7c9e46-4643-4be5-b5af-9732c191b1fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2595199221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2595199221 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3717136229 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 144672786 ps |
| CPU time | 29.8 seconds |
| Started | May 12 12:28:25 PM PDT 24 |
| Finished | May 12 12:28:55 PM PDT 24 |
| Peak memory | 203228 kb |
| Host | smart-3b4cf4b2-5634-4cac-8b9f-83a3267ba5e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3717136229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.3717136229 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1090837343 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 70534545 ps |
| CPU time | 2.75 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:28:26 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-8adce549-73c0-4111-816d-c6ee7c4fde53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1090837343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1090837343 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3767257620 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 533071565 ps |
| CPU time | 6.48 seconds |
| Started | May 12 12:28:31 PM PDT 24 |
| Finished | May 12 12:28:38 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-b4e6fcbc-4300-4337-8685-de4d1e6730f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3767257620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3767257620 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2833735021 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 71220145675 ps |
| CPU time | 267.32 seconds |
| Started | May 12 12:28:29 PM PDT 24 |
| Finished | May 12 12:32:56 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-62405db6-6b9f-4ac5-9cb8-161194940cf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2833735021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.2833735021 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2839600831 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 14574280 ps |
| CPU time | 1.34 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:46 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-7fabb7cd-15d1-4bf6-9498-14599a0bd777 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2839600831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2839600831 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2970100372 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 73664967 ps |
| CPU time | 1.34 seconds |
| Started | May 12 12:28:30 PM PDT 24 |
| Finished | May 12 12:28:31 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-5b92c3e8-3ce8-41b7-b33e-600765ab8467 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970100372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2970100372 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.3717585830 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1628081750 ps |
| CPU time | 10.32 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:51 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-e0613619-dea1-4084-a456-c3bdecaf9e66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3717585830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3717585830 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3731733568 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 31236657796 ps |
| CPU time | 131.76 seconds |
| Started | May 12 12:28:36 PM PDT 24 |
| Finished | May 12 12:30:48 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-ce076e71-58a4-45a8-802d-d13a516f77e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731733568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3731733568 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2330086623 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 6401040426 ps |
| CPU time | 40.15 seconds |
| Started | May 12 12:28:35 PM PDT 24 |
| Finished | May 12 12:29:15 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-e3e7c191-c879-4243-9273-a44451cbce4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2330086623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2330086623 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2042954615 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 98083225 ps |
| CPU time | 6.15 seconds |
| Started | May 12 12:28:26 PM PDT 24 |
| Finished | May 12 12:28:33 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-23c1130e-818c-4247-811e-a06fcf8ecbb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042954615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2042954615 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.2033746902 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 191850731 ps |
| CPU time | 1.56 seconds |
| Started | May 12 12:28:35 PM PDT 24 |
| Finished | May 12 12:28:37 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-959f74c3-5d77-4d2a-9de9-5d94c29a8989 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2033746902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2033746902 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.711371423 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 9762077 ps |
| CPU time | 1.28 seconds |
| Started | May 12 12:28:27 PM PDT 24 |
| Finished | May 12 12:28:29 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-d8560b0a-36bb-4ae3-9f39-4d63ed500b5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711371423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.711371423 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1829221 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 6242649559 ps |
| CPU time | 11.02 seconds |
| Started | May 12 12:28:27 PM PDT 24 |
| Finished | May 12 12:28:39 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-58e0a0d5-a60a-4f1b-b50b-2f100ce97335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1829221 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3481664769 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1605872926 ps |
| CPU time | 8.46 seconds |
| Started | May 12 12:28:31 PM PDT 24 |
| Finished | May 12 12:28:40 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-60f09f45-c678-4f3b-aea7-f96722a7e916 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3481664769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3481664769 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3360853127 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 11507987 ps |
| CPU time | 1.12 seconds |
| Started | May 12 12:28:28 PM PDT 24 |
| Finished | May 12 12:28:29 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-f046391d-211a-48e2-81bb-eeb4b5bbbcd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360853127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3360853127 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.330221470 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2357019131 ps |
| CPU time | 7.47 seconds |
| Started | May 12 12:28:33 PM PDT 24 |
| Finished | May 12 12:28:41 PM PDT 24 |
| Peak memory | 201928 kb |
| Host | smart-620e3b23-5f86-459e-afc8-717b784a8ae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=330221470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.330221470 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3960522038 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1098173969 ps |
| CPU time | 18.87 seconds |
| Started | May 12 12:28:36 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-fcbec503-2a07-4fe9-9de0-9844ebb8d27c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960522038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3960522038 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.236638709 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 6064149188 ps |
| CPU time | 178.31 seconds |
| Started | May 12 12:28:34 PM PDT 24 |
| Finished | May 12 12:31:32 PM PDT 24 |
| Peak memory | 206832 kb |
| Host | smart-516e553a-22a0-4259-bc65-e4e4dc0b1ade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=236638709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.236638709 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1634442877 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 103437665 ps |
| CPU time | 1.49 seconds |
| Started | May 12 12:28:38 PM PDT 24 |
| Finished | May 12 12:28:40 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-d6228a98-3029-4c3e-b65c-d580b8c9e98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1634442877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1634442877 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3388620031 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 122708155 ps |
| CPU time | 7.19 seconds |
| Started | May 12 12:28:34 PM PDT 24 |
| Finished | May 12 12:28:42 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-8e9cdef1-1283-4a6f-b81d-8120ec0d432a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3388620031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3388620031 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.272826211 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 6321579120 ps |
| CPU time | 17.26 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-aadfed62-9333-485a-a9de-6a4cdfb41847 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=272826211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo w_rsp.272826211 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3178779309 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 198595510 ps |
| CPU time | 6.42 seconds |
| Started | May 12 12:28:34 PM PDT 24 |
| Finished | May 12 12:28:41 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-d9b5596f-aa1c-43f5-bf05-ff5941db0c3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3178779309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3178779309 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.879189328 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3588518826 ps |
| CPU time | 10.2 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-06a52b6b-3f91-49e0-8c55-a53786a800d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=879189328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.879189328 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.3884142697 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 700948517 ps |
| CPU time | 11.39 seconds |
| Started | May 12 12:28:33 PM PDT 24 |
| Finished | May 12 12:28:45 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-4bf749f5-d0b5-4ced-b558-c89fe008cf0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3884142697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3884142697 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1929600129 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 32135874807 ps |
| CPU time | 100.35 seconds |
| Started | May 12 12:28:40 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-3d797866-c877-4ad8-b39a-85acb1d177c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929600129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1929600129 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3223490606 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 29910139193 ps |
| CPU time | 35.09 seconds |
| Started | May 12 12:28:32 PM PDT 24 |
| Finished | May 12 12:29:08 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-67936c4e-ca02-4952-8f16-5bd36d2172c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3223490606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3223490606 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1686541140 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 111001242 ps |
| CPU time | 8.08 seconds |
| Started | May 12 12:28:37 PM PDT 24 |
| Finished | May 12 12:28:46 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-97a6daef-58e6-4be3-9929-2336c600457c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686541140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1686541140 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3903355243 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1586930007 ps |
| CPU time | 8.89 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:28:52 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-de165d40-2081-428b-ada9-fb42ed0d1da4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3903355243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3903355243 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.1326455207 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 323788203 ps |
| CPU time | 1.36 seconds |
| Started | May 12 12:28:33 PM PDT 24 |
| Finished | May 12 12:28:35 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-737de9a4-bf0c-4de7-97e4-a803ac8af6a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1326455207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1326455207 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2400863146 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1617051592 ps |
| CPU time | 7.9 seconds |
| Started | May 12 12:28:34 PM PDT 24 |
| Finished | May 12 12:28:42 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-4ae6e770-4b34-4a8e-b3fa-8919863aea25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400863146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2400863146 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.4013524100 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 893495717 ps |
| CPU time | 5.97 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:51 PM PDT 24 |
| Peak memory | 201716 kb |
| Host | smart-3ef98999-89aa-4ef1-9d00-ffeac522472e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4013524100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4013524100 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3626323865 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 9790479 ps |
| CPU time | 1.2 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:41 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-d14c2afd-295a-4cfa-a257-af85698aa0a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626323865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3626323865 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4221803538 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 835019795 ps |
| CPU time | 6.27 seconds |
| Started | May 12 12:28:32 PM PDT 24 |
| Finished | May 12 12:28:39 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-5676068f-5784-4a00-b9f6-ab5b9e83264a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221803538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4221803538 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3333851235 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 274854354 ps |
| CPU time | 12.2 seconds |
| Started | May 12 12:28:32 PM PDT 24 |
| Finished | May 12 12:28:45 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-fb80643d-aff5-4191-b81f-12846310400f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333851235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3333851235 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3807837633 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3563630175 ps |
| CPU time | 89.67 seconds |
| Started | May 12 12:28:38 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 205428 kb |
| Host | smart-0ce7e0f0-42ea-4fd5-a249-d84b2866a04d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3807837633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3807837633 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4259138785 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 518554422 ps |
| CPU time | 42.12 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:29:29 PM PDT 24 |
| Peak memory | 202872 kb |
| Host | smart-198c9142-47bd-4323-a944-08f6ef8ff98a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4259138785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.4259138785 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3314356016 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 118179912 ps |
| CPU time | 2.97 seconds |
| Started | May 12 12:28:40 PM PDT 24 |
| Finished | May 12 12:28:44 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-0c129077-f61d-42ca-bf1a-869d72b63029 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314356016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3314356016 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3472405319 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 28915672 ps |
| CPU time | 4.43 seconds |
| Started | May 12 12:28:38 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-92bcbad6-6709-42c5-9aed-b87e911d6602 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3472405319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3472405319 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2074229803 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 441706439 ps |
| CPU time | 7.33 seconds |
| Started | May 12 12:28:41 PM PDT 24 |
| Finished | May 12 12:28:49 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-d0622680-3d82-4d6a-91e4-d77de7e0ae92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2074229803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2074229803 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.1156412136 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 952105070 ps |
| CPU time | 4.84 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:28:48 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-4420162a-5448-40bb-95b2-e782959b1464 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1156412136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1156412136 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.4064166493 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 15458176 ps |
| CPU time | 1.17 seconds |
| Started | May 12 12:28:40 PM PDT 24 |
| Finished | May 12 12:28:42 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-3bfe035c-026a-4915-8362-d517f47d01e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064166493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4064166493 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1744399276 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 15029778697 ps |
| CPU time | 54.94 seconds |
| Started | May 12 12:28:36 PM PDT 24 |
| Finished | May 12 12:29:31 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-47b61061-4ecb-4d88-8310-216fae005af5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744399276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1744399276 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2099815616 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 41809621098 ps |
| CPU time | 173.07 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:31:35 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-b528588c-26eb-4cc4-895c-4ad0994210ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2099815616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2099815616 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4088616557 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 98265095 ps |
| CPU time | 3.7 seconds |
| Started | May 12 12:28:37 PM PDT 24 |
| Finished | May 12 12:28:41 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-36c09ea9-77c0-4adb-a05d-14ecd237a9f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088616557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4088616557 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.417449624 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1946140495 ps |
| CPU time | 9.59 seconds |
| Started | May 12 12:28:43 PM PDT 24 |
| Finished | May 12 12:28:53 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-9e1ee99e-8b8d-47ab-aad2-e935fa9a3d96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=417449624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.417449624 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1708900242 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 72861356 ps |
| CPU time | 1.58 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:42 PM PDT 24 |
| Peak memory | 201756 kb |
| Host | smart-c2eafda8-7e6f-450c-b8b3-446c7ac544aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708900242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1708900242 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3911271505 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2691539437 ps |
| CPU time | 10.31 seconds |
| Started | May 12 12:28:32 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-74044f10-8deb-4354-8631-00d7e2944bf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911271505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3911271505 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1014964104 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5387490941 ps |
| CPU time | 12.12 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:28:55 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-3786bae6-3766-45df-910e-7966b7c2dbe0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1014964104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1014964104 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.412738137 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 14322745 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:28:48 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-f04c3618-6c12-4e06-a6c9-7f9a169955de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412738137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.412738137 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2518633122 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 5184746172 ps |
| CPU time | 54.98 seconds |
| Started | May 12 12:28:41 PM PDT 24 |
| Finished | May 12 12:29:36 PM PDT 24 |
| Peak memory | 202844 kb |
| Host | smart-3e27ce56-15ff-4d45-9abf-552a611259af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2518633122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2518633122 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1955509699 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 5289855839 ps |
| CPU time | 61.25 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:29:41 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-e4aecc71-84a5-4301-8bae-d59b501697ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1955509699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1955509699 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3882810406 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 13081358812 ps |
| CPU time | 126.63 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:30:51 PM PDT 24 |
| Peak memory | 204864 kb |
| Host | smart-82f5c378-efa3-4f70-9116-9999b65077ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3882810406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3882810406 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3185202305 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1771850958 ps |
| CPU time | 33.98 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:29:17 PM PDT 24 |
| Peak memory | 203304 kb |
| Host | smart-e7b13639-db9f-42f5-876c-0485759c579d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3185202305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3185202305 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1204197141 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 212955955 ps |
| CPU time | 3.48 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-e9ae08fb-6ba0-4b4a-bb14-41c04ea95b7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1204197141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1204197141 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.412810634 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1360994061 ps |
| CPU time | 21.47 seconds |
| Started | May 12 12:28:40 PM PDT 24 |
| Finished | May 12 12:29:03 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-ae14e994-f51d-4906-9b02-3f5eb2b19bb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=412810634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.412810634 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1450215438 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 12827362732 ps |
| CPU time | 67.09 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:29:52 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-f4387155-8db5-4dd3-8f33-289b82a7e2b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1450215438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1450215438 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1340652915 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 813372593 ps |
| CPU time | 6.56 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:51 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-fb16115d-61d6-4579-9942-df2e408c8375 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1340652915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1340652915 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.3739405791 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 71822668 ps |
| CPU time | 2.26 seconds |
| Started | May 12 12:28:37 PM PDT 24 |
| Finished | May 12 12:28:39 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-b412d4ce-f868-4bed-bd1e-814210ec9d1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739405791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3739405791 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.4141946956 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 68427377 ps |
| CPU time | 8.89 seconds |
| Started | May 12 12:28:42 PM PDT 24 |
| Finished | May 12 12:28:52 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-84a852ae-4111-44f9-8507-7eb341e81b2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4141946956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4141946956 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3455934620 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 47147855537 ps |
| CPU time | 199.41 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:32:07 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-4804c13e-cc59-4750-858c-e793bfd89eb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455934620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3455934620 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4272121260 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 19554746056 ps |
| CPU time | 41.09 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:29:21 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-1e1e4633-bcf1-4480-8813-085a203ecaec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4272121260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4272121260 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.156528878 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 19388257 ps |
| CPU time | 2.53 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:48 PM PDT 24 |
| Peak memory | 201704 kb |
| Host | smart-dbcc1a95-1c7b-44b4-b0ff-1c10f79f5c87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156528878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.156528878 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.867031011 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 24897515 ps |
| CPU time | 1.39 seconds |
| Started | May 12 12:28:39 PM PDT 24 |
| Finished | May 12 12:28:41 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-f5f83bf4-67e1-4a7d-be80-5eaa720609d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=867031011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.867031011 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1907760022 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 69468035 ps |
| CPU time | 1.9 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:28:48 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-30185eb4-deca-44f5-95ca-37871edc1b08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1907760022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1907760022 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3465507372 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2625465107 ps |
| CPU time | 8.63 seconds |
| Started | May 12 12:28:43 PM PDT 24 |
| Finished | May 12 12:28:53 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-2e5758de-fb52-439d-8386-ba5fb70203e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3465507372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3465507372 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3117700500 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 11191784 ps |
| CPU time | 1.16 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:28:47 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-edbf4f13-2574-45bf-813c-d9ec186c5761 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117700500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3117700500 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2662151779 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9015753474 ps |
| CPU time | 34.62 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:29:21 PM PDT 24 |
| Peak memory | 202932 kb |
| Host | smart-b0437870-5a41-42f1-808f-da325745a299 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662151779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2662151779 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1905166630 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 46645412854 ps |
| CPU time | 100.77 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:30:35 PM PDT 24 |
| Peak memory | 203080 kb |
| Host | smart-3ac345a4-53e8-4746-b754-f79f1a2f421d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1905166630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1905166630 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.851294839 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1551844767 ps |
| CPU time | 86.04 seconds |
| Started | May 12 12:28:41 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-7ccd3dde-3bc0-4da0-9db5-bbe34123ea40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851294839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.851294839 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.235264115 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4456202516 ps |
| CPU time | 120.16 seconds |
| Started | May 12 12:28:49 PM PDT 24 |
| Finished | May 12 12:30:49 PM PDT 24 |
| Peak memory | 205268 kb |
| Host | smart-c203cc7a-dfe5-4dbc-adc8-cac431e76a93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=235264115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.235264115 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.194459971 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 64197744 ps |
| CPU time | 1.92 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:47 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-5c63b502-b95c-4ba9-9ed2-7e8bd80853db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194459971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.194459971 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1238271004 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 32450335 ps |
| CPU time | 1.64 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-42b5f893-6faf-4615-8c49-a198d502dfca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238271004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1238271004 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4221615672 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 103644390596 ps |
| CPU time | 258.65 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:33:07 PM PDT 24 |
| Peak memory | 202916 kb |
| Host | smart-2476f4c0-73aa-497b-9495-77d58be1aa30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4221615672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.4221615672 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2095128740 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 661084614 ps |
| CPU time | 8.36 seconds |
| Started | May 12 12:28:50 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-5caf630b-024b-4a0e-baa1-ead302c02bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2095128740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2095128740 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3615739584 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 72927073 ps |
| CPU time | 5.83 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:03 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-81a9e045-331f-4801-b207-9fb5fe8b2e60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3615739584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3615739584 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.1964064930 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 132289566 ps |
| CPU time | 2.16 seconds |
| Started | May 12 12:28:51 PM PDT 24 |
| Finished | May 12 12:28:54 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-0a6ea0ab-eba3-41e1-92b7-529c27495f0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1964064930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1964064930 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2743359867 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 35857836205 ps |
| CPU time | 52.13 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:45 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-e6b310cd-a9b0-4ef0-a73e-dcc8044d46c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743359867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2743359867 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3201962600 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 22852740549 ps |
| CPU time | 76.59 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-9d8e993f-3f98-4a96-8fd6-0a465fd4527d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3201962600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3201962600 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.132331430 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 16257785 ps |
| CPU time | 1.74 seconds |
| Started | May 12 12:28:50 PM PDT 24 |
| Finished | May 12 12:28:53 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-ce359cc9-f3f3-4e88-a58a-ad632b03e837 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132331430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.132331430 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.992014829 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 70043564 ps |
| CPU time | 3.39 seconds |
| Started | May 12 12:28:54 PM PDT 24 |
| Finished | May 12 12:28:58 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-93fb598c-f6b8-4eb6-9b2a-6f870fab233a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992014829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.992014829 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.1307281726 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 68695847 ps |
| CPU time | 1.65 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:28:50 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-24f6b14a-fd54-43d4-8807-b75ed8eb999b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307281726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1307281726 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1022915996 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4042633555 ps |
| CPU time | 10.81 seconds |
| Started | May 12 12:28:50 PM PDT 24 |
| Finished | May 12 12:29:02 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-9f234382-3362-46c5-ab93-4ccea3f6d99b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022915996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1022915996 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.808492164 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1186575689 ps |
| CPU time | 8.06 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-9b919497-bffd-4458-a51c-cdc925fbc10d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=808492164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.808492164 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3092826885 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 9240000 ps |
| CPU time | 1.1 seconds |
| Started | May 12 12:28:54 PM PDT 24 |
| Finished | May 12 12:28:55 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-33e1b023-4308-4858-823a-d1a34049a619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092826885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3092826885 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.676954674 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1532603105 ps |
| CPU time | 25.35 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 202604 kb |
| Host | smart-12da8b52-17d9-49dd-99b9-19873f21bfd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=676954674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.676954674 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3179122122 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2080955741 ps |
| CPU time | 29.43 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:29:15 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-76ab31f6-2705-4c11-abb1-0477a24fec3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3179122122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3179122122 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1795781695 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 568263063 ps |
| CPU time | 86.73 seconds |
| Started | May 12 12:28:54 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 207788 kb |
| Host | smart-e247a2bf-f25b-4db9-a605-ce992b734bc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1795781695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.1795781695 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.755982349 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 6754445114 ps |
| CPU time | 82.32 seconds |
| Started | May 12 12:28:49 PM PDT 24 |
| Finished | May 12 12:30:12 PM PDT 24 |
| Peak memory | 205444 kb |
| Host | smart-749d9094-cd3e-49fc-a147-a9e338c779b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=755982349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.755982349 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4283966821 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 546599497 ps |
| CPU time | 10.3 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-98fb2026-87e7-422f-a950-34210946d8b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283966821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4283966821 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1224879790 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2652194752 ps |
| CPU time | 24.27 seconds |
| Started | May 12 12:28:49 PM PDT 24 |
| Finished | May 12 12:29:14 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-53780531-7e54-4cd4-ad1d-9f7d97f6e8c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1224879790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1224879790 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1718574882 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 600637543 ps |
| CPU time | 9.34 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-697e4486-2db4-4f19-ae0e-2615baf03829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1718574882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1718574882 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.2037576247 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 519561735 ps |
| CPU time | 9.13 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-c6039ddf-cda5-462b-bfae-0d390b09527f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2037576247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2037576247 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.316988308 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 969980328 ps |
| CPU time | 7.3 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-de392a91-d914-497c-a180-dff9a059db21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=316988308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.316988308 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1614366484 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 13552546106 ps |
| CPU time | 31.14 seconds |
| Started | May 12 12:28:54 PM PDT 24 |
| Finished | May 12 12:29:25 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-b46e8e35-2c43-4f04-aa96-077c69b0bf4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614366484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1614366484 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2345154196 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 28817203548 ps |
| CPU time | 181.43 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:31:48 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-050ce858-3c54-4a89-af8c-26add8df8fd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2345154196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2345154196 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.4171350714 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 35318583 ps |
| CPU time | 2.06 seconds |
| Started | May 12 12:28:48 PM PDT 24 |
| Finished | May 12 12:28:51 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-ab4e84f3-766e-4e73-a68f-253fa5ac8b97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171350714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.4171350714 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.125297781 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1679458031 ps |
| CPU time | 3.25 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-cbf8f032-986e-4c75-b5e0-a4b4e7247b88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=125297781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.125297781 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.830576096 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 105383266 ps |
| CPU time | 1.26 seconds |
| Started | May 12 12:28:48 PM PDT 24 |
| Finished | May 12 12:28:50 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-d915ed8f-cd28-4bda-9ff2-0c67df40f4b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830576096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.830576096 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.123889450 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 6448357396 ps |
| CPU time | 7.05 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:29:01 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-7c0ba26c-6e2a-4234-8250-e476ed130b18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=123889450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.123889450 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.516695413 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1920080851 ps |
| CPU time | 10.37 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:04 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-9fb2f154-07bb-483c-a6f2-32c6954cdda3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=516695413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.516695413 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.145033840 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 11172341 ps |
| CPU time | 1.1 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:28:55 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-407d6dad-0250-429d-8e7e-15208562289f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145033840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.145033840 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1377174934 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 7556462741 ps |
| CPU time | 61.44 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:29:48 PM PDT 24 |
| Peak memory | 202940 kb |
| Host | smart-6afa09e5-683e-48c8-8e4f-687900ed6915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1377174934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1377174934 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1112399033 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 138110512 ps |
| CPU time | 11.31 seconds |
| Started | May 12 12:28:50 PM PDT 24 |
| Finished | May 12 12:29:02 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-3df81384-a7df-47e0-a72b-f5d0581adb03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1112399033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1112399033 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1646049588 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3871849819 ps |
| CPU time | 86.23 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:30:23 PM PDT 24 |
| Peak memory | 203976 kb |
| Host | smart-0581bc71-4c06-4588-af58-6a20ca2f65e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646049588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.1646049588 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1135627603 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 127110770 ps |
| CPU time | 26.67 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:20 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-927c7590-63b3-45c0-8cc1-75f6c1335a39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1135627603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1135627603 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3940094030 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 41461082 ps |
| CPU time | 4.56 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:28:53 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-52b00413-03ab-4880-9d93-1673c9116306 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940094030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3940094030 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1616948907 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2046479068 ps |
| CPU time | 17.27 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-311c014c-1bfb-4caa-9121-8fa517a940d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1616948907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1616948907 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3105114063 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 50523156194 ps |
| CPU time | 191.05 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:31:22 PM PDT 24 |
| Peak memory | 202888 kb |
| Host | smart-b1630b35-fcd0-407e-8a3d-bcb0fe170df2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3105114063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3105114063 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.776313881 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 77103427 ps |
| CPU time | 1.36 seconds |
| Started | May 12 12:27:53 PM PDT 24 |
| Finished | May 12 12:27:55 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-678ccfa7-3184-47fb-892f-de74fb392831 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=776313881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.776313881 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2196985741 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 17769069 ps |
| CPU time | 2.06 seconds |
| Started | May 12 12:27:51 PM PDT 24 |
| Finished | May 12 12:27:54 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-4ea49507-136c-4fb0-947d-b7bb4febade8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2196985741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2196985741 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1854644196 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1925454093 ps |
| CPU time | 11.81 seconds |
| Started | May 12 12:27:52 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-d675cfd7-9cff-4df0-8f78-74edd1d8e428 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854644196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1854644196 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4278537347 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 8178298335 ps |
| CPU time | 29.59 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:31 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-b9a2b5cd-baff-4da1-ae60-38a793efa2a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278537347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4278537347 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.347788894 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 20992182416 ps |
| CPU time | 91.47 seconds |
| Started | May 12 12:27:53 PM PDT 24 |
| Finished | May 12 12:29:25 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-1e33ebc7-8202-4b6c-a1f9-a7f63099c921 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=347788894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.347788894 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.236513591 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 57580783 ps |
| CPU time | 6.22 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-acf95904-3a90-47af-956e-c378de9357b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236513591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.236513591 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.4018287475 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1678090863 ps |
| CPU time | 12.52 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:14 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-9a0cdd0d-2cd5-436e-8b4b-9270976e81bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018287475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4018287475 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3599074738 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 88501866 ps |
| CPU time | 1.41 seconds |
| Started | May 12 12:27:52 PM PDT 24 |
| Finished | May 12 12:27:55 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-1bf989c6-b95f-48ce-94c1-eb8c1ec9bd22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3599074738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3599074738 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3352804515 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2198013877 ps |
| CPU time | 9.92 seconds |
| Started | May 12 12:27:54 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-e959d13d-e9d5-406d-aa5d-09f4d2c97808 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352804515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3352804515 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2224219576 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 841210858 ps |
| CPU time | 6.6 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:06 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-4ecb4c23-e4f2-4519-a733-400eeb61ad27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2224219576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2224219576 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1062738144 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 14115627 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:00 PM PDT 24 |
| Peak memory | 201748 kb |
| Host | smart-d233aac2-fd26-476a-b096-1ac5d758b36b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062738144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1062738144 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3341379211 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 309235043 ps |
| CPU time | 13.39 seconds |
| Started | May 12 12:27:53 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-17133c01-39a9-414c-8b3b-f6edc79d46d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3341379211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3341379211 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1409871035 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1705296798 ps |
| CPU time | 22.45 seconds |
| Started | May 12 12:27:56 PM PDT 24 |
| Finished | May 12 12:28:19 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-e16c411e-339e-482b-8b5c-7af6fc43163b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1409871035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1409871035 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2751083131 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 167751937 ps |
| CPU time | 24.74 seconds |
| Started | May 12 12:27:54 PM PDT 24 |
| Finished | May 12 12:28:19 PM PDT 24 |
| Peak memory | 202812 kb |
| Host | smart-19a625e5-e30d-48e3-8281-99457ba155de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751083131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.2751083131 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.230078996 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4404546750 ps |
| CPU time | 88.15 seconds |
| Started | May 12 12:27:45 PM PDT 24 |
| Finished | May 12 12:29:14 PM PDT 24 |
| Peak memory | 205012 kb |
| Host | smart-66ad93f7-d77f-4ac6-8317-aab021a094e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230078996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.230078996 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.504478343 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4016381999 ps |
| CPU time | 11.13 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:12 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-ec40b37d-713a-468d-af0d-e835b27e05df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=504478343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.504478343 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2589949530 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 88209314 ps |
| CPU time | 1.89 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:28:50 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-553aedef-c724-4e11-8ded-a6faae5dd91a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589949530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2589949530 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1826000124 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 81510231808 ps |
| CPU time | 112.03 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:30:40 PM PDT 24 |
| Peak memory | 202936 kb |
| Host | smart-5550e5db-ea1f-4ca8-be5f-d6b99b60abd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1826000124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.1826000124 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.945524127 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 541581267 ps |
| CPU time | 2.04 seconds |
| Started | May 12 12:28:51 PM PDT 24 |
| Finished | May 12 12:28:54 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-1e2773c1-4a72-43fd-aca1-dfb6bcb835d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=945524127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.945524127 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.4135216182 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 843051776 ps |
| CPU time | 9.63 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:55 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-10cd3a69-c392-45db-b92f-9c3edc356c6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4135216182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4135216182 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.4026059872 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 586771616 ps |
| CPU time | 10.92 seconds |
| Started | May 12 12:28:51 PM PDT 24 |
| Finished | May 12 12:29:02 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-c3f13481-f8f2-477e-824a-4fa0b79a4b6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4026059872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.4026059872 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3931846306 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 46129352422 ps |
| CPU time | 147.61 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:31:15 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-774c3db4-a5b2-493b-9419-bec0071bed48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931846306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3931846306 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1467445387 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 58049239950 ps |
| CPU time | 66.49 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-3a6a1a25-2859-44b2-8a79-0dc2dd151f96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1467445387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1467445387 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.893267932 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 63331785 ps |
| CPU time | 4.58 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201644 kb |
| Host | smart-e41c6bd8-88fe-4dfb-9dd4-3d0e1c7f9660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893267932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.893267932 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.3776921999 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1687615290 ps |
| CPU time | 11.71 seconds |
| Started | May 12 12:28:44 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-438cc5f7-14e0-4593-bc62-da97cc5d86d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3776921999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3776921999 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2674210287 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 21402430 ps |
| CPU time | 0.95 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:28:48 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-2fa76c09-3c82-43ec-b7e7-c0db83228a5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2674210287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2674210287 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3101887180 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3243892240 ps |
| CPU time | 10.69 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-e1c9de80-c938-4030-97df-3bb55fa81642 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101887180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3101887180 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2118196864 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5947223570 ps |
| CPU time | 6.98 seconds |
| Started | May 12 12:28:46 PM PDT 24 |
| Finished | May 12 12:28:54 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-f346c447-3c5e-4d99-bef0-f5ca32173c23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2118196864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2118196864 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1487229458 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 19101474 ps |
| CPU time | 1.04 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:28:47 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-13e4a9ee-3bad-4e11-a1e6-c6b67244034d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487229458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1487229458 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1176386151 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 288832066 ps |
| CPU time | 34.89 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201680 kb |
| Host | smart-6a747010-5e50-48d1-8d14-f858541b1b1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176386151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1176386151 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3861217254 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 151696727 ps |
| CPU time | 11.02 seconds |
| Started | May 12 12:28:47 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 201708 kb |
| Host | smart-493158be-a5d0-498a-ae9b-3a00456ff28f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3861217254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3861217254 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1848727846 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 848146503 ps |
| CPU time | 84.88 seconds |
| Started | May 12 12:28:45 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 204084 kb |
| Host | smart-c3a4399d-9151-44b5-9d5c-87a0c5cc0c7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1848727846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1848727846 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.806600821 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 480030132 ps |
| CPU time | 55.32 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 204064 kb |
| Host | smart-f4316a94-8376-445d-bd40-faa8f3d35e45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=806600821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res et_error.806600821 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.4213412746 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 4656153690 ps |
| CPU time | 11.2 seconds |
| Started | May 12 12:28:48 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-a5963762-8dc2-4eb7-a964-d0db5bbcbc63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213412746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4213412746 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.4165785409 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 496072953 ps |
| CPU time | 9.02 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:29:02 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-cd4a3e7c-cb1c-403e-9178-8f7ae52dd2c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4165785409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.4165785409 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3088583669 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 87876193614 ps |
| CPU time | 85.75 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:30:20 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-acf28ab8-e55c-4825-abd7-94ba9796c33a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3088583669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3088583669 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.469723145 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 66878956 ps |
| CPU time | 2.86 seconds |
| Started | May 12 12:29:08 PM PDT 24 |
| Finished | May 12 12:29:12 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-a0663231-54cc-423c-8d31-0890dc308bfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=469723145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.469723145 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1870697554 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 26594436 ps |
| CPU time | 1.77 seconds |
| Started | May 12 12:28:51 PM PDT 24 |
| Finished | May 12 12:28:54 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-cd4b2455-0f9d-4ecf-ac38-3641f5ae55d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1870697554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1870697554 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.1876281058 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1025190610 ps |
| CPU time | 7.32 seconds |
| Started | May 12 12:28:50 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-6bde0881-8e8b-4e0c-ac69-f63cafc2e0fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1876281058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1876281058 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3902603463 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 33061861075 ps |
| CPU time | 107.67 seconds |
| Started | May 12 12:29:00 PM PDT 24 |
| Finished | May 12 12:30:49 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-e395ef23-9c96-43b2-a043-772b45d06cab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902603463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3902603463 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.217393360 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 103997616533 ps |
| CPU time | 112.82 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:30:47 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-059d83f7-2560-4bf5-b961-05032a5b33c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=217393360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.217393360 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.200905729 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 62662597 ps |
| CPU time | 6.48 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:09 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-ce5b0096-74dd-4c85-9836-0b6a394f84bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200905729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.200905729 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2693165912 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 89482526 ps |
| CPU time | 1.64 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:28:55 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-efabcb81-8ca2-49c1-b240-6f77df3b4d7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693165912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2693165912 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.498183601 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 17939417 ps |
| CPU time | 1.08 seconds |
| Started | May 12 12:28:48 PM PDT 24 |
| Finished | May 12 12:28:50 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-5558c3b2-3310-4e69-899b-b82075886fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=498183601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.498183601 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.473426895 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2374338480 ps |
| CPU time | 7.71 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:29:01 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-60a1cc1f-0542-4faa-bc32-983e5c562fd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473426895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.473426895 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.4025358098 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1258187005 ps |
| CPU time | 8.81 seconds |
| Started | May 12 12:28:51 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-7f6c4a58-7970-43e5-ab5f-e11dde955de4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4025358098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.4025358098 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2716531244 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 9903606 ps |
| CPU time | 1.21 seconds |
| Started | May 12 12:28:58 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-da6a7340-3957-475e-806c-ab4f27c5c9de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716531244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2716531244 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3754248447 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 133010001 ps |
| CPU time | 10.66 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:13 PM PDT 24 |
| Peak memory | 201524 kb |
| Host | smart-26da716f-5891-4bd0-adb3-a09b66808be0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3754248447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3754248447 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1243798577 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 644341441 ps |
| CPU time | 38.14 seconds |
| Started | May 12 12:29:00 PM PDT 24 |
| Finished | May 12 12:29:39 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-e4098557-a626-409e-9694-4b16a8b51e57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1243798577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1243798577 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4181600357 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 764589203 ps |
| CPU time | 97.71 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:30:42 PM PDT 24 |
| Peak memory | 205816 kb |
| Host | smart-c44dc491-5dfa-48b9-8a2d-2475eec9e7bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4181600357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.4181600357 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1811445733 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 832125865 ps |
| CPU time | 86.85 seconds |
| Started | May 12 12:28:54 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 206088 kb |
| Host | smart-57de9002-4667-474b-95d5-956e02615fb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1811445733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1811445733 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.470468867 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 722644391 ps |
| CPU time | 12.32 seconds |
| Started | May 12 12:28:58 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-4398d87b-3e2e-475e-8f81-2c878f2ca0be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=470468867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.470468867 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1159368329 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 46718058 ps |
| CPU time | 5.43 seconds |
| Started | May 12 12:28:53 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-e9d2a786-ec8d-47d1-ad6b-d5c640808b85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1159368329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1159368329 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.401800592 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 34497077540 ps |
| CPU time | 110.2 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:30:48 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-3800e3a3-2b07-48b7-b260-33c00e27826a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=401800592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo w_rsp.401800592 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.89289752 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2332132664 ps |
| CPU time | 10.28 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:13 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-ae13d3bc-a3ea-4ec7-b75c-3f68171efdd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=89289752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.89289752 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.1526354817 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 59040694 ps |
| CPU time | 6.94 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:10 PM PDT 24 |
| Peak memory | 201732 kb |
| Host | smart-eca311a5-7214-49e4-8c05-e8f9d4cace81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1526354817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1526354817 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.409014623 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 70384124 ps |
| CPU time | 6.99 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:10 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-57350ee5-7bec-4450-ae21-4ba5639fcc8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409014623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.409014623 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2442834072 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 66182422312 ps |
| CPU time | 146.17 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:31:19 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-451f65f8-58aa-42fe-9c97-7e270a809eed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442834072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2442834072 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3432222324 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 30671460118 ps |
| CPU time | 60.56 seconds |
| Started | May 12 12:28:59 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-50e5f841-f1f9-4a57-834e-996e318754d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3432222324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3432222324 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3821999093 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 101729803 ps |
| CPU time | 5.69 seconds |
| Started | May 12 12:28:52 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 201748 kb |
| Host | smart-89a3cbff-5c4b-48a8-8871-c37d0fb3952e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821999093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3821999093 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.3446213554 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1491553453 ps |
| CPU time | 6.34 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:04 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-c0e93999-1967-4db5-af21-6900d47b6091 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446213554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3446213554 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.385664724 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 47181259 ps |
| CPU time | 1.5 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:04 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-81c80007-e14f-45e7-a365-4204566bd19b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=385664724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.385664724 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1319632757 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3880504852 ps |
| CPU time | 10.56 seconds |
| Started | May 12 12:29:05 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-e262e46e-77ee-45a7-88ce-144fffca11cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319632757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1319632757 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3987230898 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3389807650 ps |
| CPU time | 9.08 seconds |
| Started | May 12 12:28:48 PM PDT 24 |
| Finished | May 12 12:28:58 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-cd74720e-7107-4cd9-8376-fb50d9f1205f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3987230898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3987230898 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3436690004 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 10961967 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:28:55 PM PDT 24 |
| Finished | May 12 12:28:57 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-08da9641-bb4f-4ae3-b3c4-b87c8847409c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436690004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3436690004 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1424841687 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 5538078 ps |
| CPU time | 0.72 seconds |
| Started | May 12 12:28:59 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 193544 kb |
| Host | smart-55278fdf-81ef-4067-8b6b-5b69f5bc852c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1424841687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1424841687 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3051720841 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 222394129 ps |
| CPU time | 15.46 seconds |
| Started | May 12 12:29:08 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-ec6567b9-a043-48f5-8de6-9556973b40ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3051720841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3051720841 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1009980198 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 139902975 ps |
| CPU time | 14.02 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 202792 kb |
| Host | smart-c0c682d9-f92d-4fdc-8173-2a3e1df161f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1009980198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1009980198 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.4192553375 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 148949048 ps |
| CPU time | 24.74 seconds |
| Started | May 12 12:29:24 PM PDT 24 |
| Finished | May 12 12:29:49 PM PDT 24 |
| Peak memory | 202848 kb |
| Host | smart-9e532836-10a8-41b1-afec-89f0a1d4f76d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4192553375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.4192553375 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2881046301 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4368253207 ps |
| CPU time | 11.18 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:14 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-b001db30-5fe5-4b4b-9521-cbf735560fc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2881046301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2881046301 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2907600000 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 109422499 ps |
| CPU time | 2.77 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:05 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-a3c82c6c-2e0b-46db-b314-30f7248ed8f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2907600000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2907600000 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3391378501 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 104852008981 ps |
| CPU time | 173.08 seconds |
| Started | May 12 12:28:58 PM PDT 24 |
| Finished | May 12 12:31:51 PM PDT 24 |
| Peak memory | 202908 kb |
| Host | smart-e4daaf8c-1630-4883-bf88-dd618e35cb7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3391378501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3391378501 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1443259897 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 52192613 ps |
| CPU time | 2.6 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-a0d4cac5-1e0e-492b-ad55-b90ea56a6a96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443259897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1443259897 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3525653607 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 895120629 ps |
| CPU time | 4.89 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:02 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-a3949e99-e3f3-4cc6-8c34-b895cd8fd3ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3525653607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3525653607 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3888517563 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 47646581817 ps |
| CPU time | 117.99 seconds |
| Started | May 12 12:28:58 PM PDT 24 |
| Finished | May 12 12:30:57 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-f2193356-a8fb-4092-a097-3994ff78c7d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888517563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3888517563 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.221060792 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 21318383042 ps |
| CPU time | 102.12 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:30:45 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-5ca21890-dacc-4a9a-a545-12c6f66bf04b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=221060792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.221060792 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1105787315 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 121875876 ps |
| CPU time | 7.66 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:29:06 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-8d396952-89b3-4024-bd87-9cf030876410 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105787315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1105787315 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.4035736393 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5076866892 ps |
| CPU time | 11.44 seconds |
| Started | May 12 12:28:59 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-49e76807-36ba-42fd-a1aa-9f0317b634e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4035736393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4035736393 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.2283390923 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8909214 ps |
| CPU time | 1.09 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:28:58 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-03d39282-bbae-419c-aacb-1514e11d1dba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2283390923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2283390923 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3976559353 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5646065802 ps |
| CPU time | 12.09 seconds |
| Started | May 12 12:29:00 PM PDT 24 |
| Finished | May 12 12:29:12 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-072f637b-5f5b-4050-ada2-19f79a621a81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976559353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3976559353 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2546014591 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5343673747 ps |
| CPU time | 10.34 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:29:08 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-7a956d75-c90e-4e51-b578-e15de63e9b59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2546014591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2546014591 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1409123420 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8601065 ps |
| CPU time | 1.04 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:03 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-964b89d8-78e6-4036-89f5-86a55ee55990 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409123420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1409123420 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.116231432 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 341390065 ps |
| CPU time | 38.11 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:35 PM PDT 24 |
| Peak memory | 203892 kb |
| Host | smart-2e7dcd0f-0db0-4cc9-adb8-3bb98e199e8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=116231432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.116231432 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1426563759 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 350646441 ps |
| CPU time | 9.9 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:13 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-2e0d63d7-5100-4f11-8975-4c1d58385ace |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1426563759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1426563759 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3255732442 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 620949048 ps |
| CPU time | 60.93 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 205844 kb |
| Host | smart-fedc35e0-10bd-4151-9a9e-a15d6f51044e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3255732442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3255732442 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.87874124 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1169894962 ps |
| CPU time | 39.17 seconds |
| Started | May 12 12:28:55 PM PDT 24 |
| Finished | May 12 12:29:36 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-887bf689-24b6-4238-b31a-c5d22931d95c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87874124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rese t_error.87874124 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2042787802 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 310248929 ps |
| CPU time | 5.64 seconds |
| Started | May 12 12:29:10 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-01fb5d0d-ac70-474a-b34c-c47a48be9f9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2042787802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2042787802 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.155647769 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1047044871 ps |
| CPU time | 18.8 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:21 PM PDT 24 |
| Peak memory | 201524 kb |
| Host | smart-385d5d7e-dcc8-458e-80a4-1a2b222431bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=155647769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.155647769 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.154728089 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 150412872965 ps |
| CPU time | 265.43 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:33:23 PM PDT 24 |
| Peak memory | 203364 kb |
| Host | smart-37421459-6a13-418d-b426-59ebe2374544 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=154728089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.154728089 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2858307958 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 76690193 ps |
| CPU time | 3.15 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:01 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-009d0a85-6dbd-4e2d-8bbf-b5cdcf5a3991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2858307958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2858307958 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.1052309529 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1315571016 ps |
| CPU time | 2.73 seconds |
| Started | May 12 12:28:55 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-5aa44c8e-d8e2-4ed6-8245-b0b5562c96b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1052309529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1052309529 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.823512669 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 38465692 ps |
| CPU time | 3.02 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:05 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-01ce7890-e721-44c4-b683-698ec29c0e20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=823512669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.823512669 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2357123924 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 19222367183 ps |
| CPU time | 63.52 seconds |
| Started | May 12 12:29:09 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-a8211d4b-2927-44f5-bc0a-9391052179a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357123924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2357123924 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.604296135 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 17482468420 ps |
| CPU time | 116.3 seconds |
| Started | May 12 12:28:55 PM PDT 24 |
| Finished | May 12 12:30:52 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-3aedf96c-630b-4d83-a7d4-1a42a8c30ad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=604296135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.604296135 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2603120711 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 19685833 ps |
| CPU time | 2.41 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-aa6c930f-f0ba-4383-a8e3-053bd144f2fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603120711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2603120711 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1660035647 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 649914406 ps |
| CPU time | 5.91 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:03 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-e66b65e5-ab10-4dc1-a3fc-4a72e1b78fc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1660035647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1660035647 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.121317114 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 9174986 ps |
| CPU time | 1.26 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:28:58 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-14f461e9-c1f4-4150-b986-d547db4d2e84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121317114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.121317114 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3029891341 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4391772625 ps |
| CPU time | 9.92 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:12 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-307b813f-8742-457a-a569-cb1aba393d8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029891341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3029891341 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3733882960 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 6527813984 ps |
| CPU time | 8.39 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:10 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-33bf13a1-94be-4c4c-a1bc-ce5db6a09985 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3733882960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3733882960 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.206925656 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 11700087 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-198fe27a-b924-4abb-9ab3-389bdcc42561 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206925656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.206925656 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.3675279867 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 23494871663 ps |
| CPU time | 69.57 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 202928 kb |
| Host | smart-94308cda-c640-42e8-957a-ce5a97cf9b09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3675279867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3675279867 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.197838688 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4154787710 ps |
| CPU time | 50.25 seconds |
| Started | May 12 12:28:56 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-be46ce60-f072-4aa0-be81-6627b4a92ef4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=197838688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.197838688 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3271113374 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5932351622 ps |
| CPU time | 120.67 seconds |
| Started | May 12 12:28:59 PM PDT 24 |
| Finished | May 12 12:31:01 PM PDT 24 |
| Peak memory | 206124 kb |
| Host | smart-d572446b-88a3-452c-a567-78cf28abc19b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3271113374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3271113374 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3881618921 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 489098943 ps |
| CPU time | 52.21 seconds |
| Started | May 12 12:29:05 PM PDT 24 |
| Finished | May 12 12:29:58 PM PDT 24 |
| Peak memory | 204436 kb |
| Host | smart-beaa9159-5542-46b5-af61-f0aeec1fe692 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3881618921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3881618921 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1738343547 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 104512194 ps |
| CPU time | 7.4 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:26 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-d7f63a40-8562-499e-bc84-3f6f0a6e3cc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1738343547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1738343547 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1423213323 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 370529862 ps |
| CPU time | 7.58 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-cfc7752d-85e2-4d6d-a0ca-ecb092eacfd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1423213323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1423213323 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.5328519 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 16998358557 ps |
| CPU time | 130.53 seconds |
| Started | May 12 12:29:15 PM PDT 24 |
| Finished | May 12 12:31:27 PM PDT 24 |
| Peak memory | 203380 kb |
| Host | smart-f75de337-2cb4-4f16-a57e-a5cb6bbe693d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=5328519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.5328519 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1357877928 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 940884113 ps |
| CPU time | 5.35 seconds |
| Started | May 12 12:29:21 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-1a6dbf43-9b44-4ec8-b14f-c5f0af537a5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1357877928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1357877928 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2438119007 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 23082979 ps |
| CPU time | 2.07 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:29:34 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-0479a823-2b90-4c1b-8228-615814d7fca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2438119007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2438119007 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2618093878 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2209429054 ps |
| CPU time | 7.79 seconds |
| Started | May 12 12:28:59 PM PDT 24 |
| Finished | May 12 12:29:07 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-5d291bff-d6d2-4b2e-9252-bcad05adc6ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2618093878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2618093878 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1122517117 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 30911013647 ps |
| CPU time | 80.07 seconds |
| Started | May 12 12:28:57 PM PDT 24 |
| Finished | May 12 12:30:18 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-1c559091-95dd-4449-b75a-555909e98cd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122517117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1122517117 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.881807540 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8328221210 ps |
| CPU time | 38.68 seconds |
| Started | May 12 12:28:55 PM PDT 24 |
| Finished | May 12 12:29:34 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-97ccabdf-a20f-440b-a551-abd96f14a80f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=881807540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.881807540 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3777282226 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 65773524 ps |
| CPU time | 5.42 seconds |
| Started | May 12 12:29:14 PM PDT 24 |
| Finished | May 12 12:29:21 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-7552d98d-0715-4157-a849-0665b84f27f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777282226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3777282226 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.3986614175 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2524475399 ps |
| CPU time | 11.85 seconds |
| Started | May 12 12:28:55 PM PDT 24 |
| Finished | May 12 12:29:07 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-f1bcbfc2-9463-44fb-acfd-71a20c5c4ae0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986614175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3986614175 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.97381059 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 62352516 ps |
| CPU time | 1.55 seconds |
| Started | May 12 12:29:11 PM PDT 24 |
| Finished | May 12 12:29:13 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-26ea3286-e7e4-4ccc-bf8e-df581eba65c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=97381059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.97381059 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.63688836 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4554582861 ps |
| CPU time | 11.62 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:14 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-cfeb4cb0-bd90-4d52-a338-6497cfcd0de2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=63688836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.63688836 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1193523980 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 805237816 ps |
| CPU time | 7.26 seconds |
| Started | May 12 12:29:16 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-12cd0673-d715-4746-9b79-c41b120208cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1193523980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1193523980 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.907739782 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 8655380 ps |
| CPU time | 1 seconds |
| Started | May 12 12:28:58 PM PDT 24 |
| Finished | May 12 12:29:00 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-d0f84833-791c-4a07-9d17-d8edf72286cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907739782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.907739782 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1393760559 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1176376519 ps |
| CPU time | 12.36 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-fbbd3650-7e15-4672-b855-2a9df9661118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1393760559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1393760559 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.657726586 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 417252182 ps |
| CPU time | 37.67 seconds |
| Started | May 12 12:29:15 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-3ee1ee3e-f298-49bd-92eb-90a6d58bd226 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=657726586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.657726586 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3973130695 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 134800053 ps |
| CPU time | 35.66 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:39 PM PDT 24 |
| Peak memory | 203984 kb |
| Host | smart-7de356bb-86d4-4dc0-91a4-3855454da976 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3973130695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.3973130695 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3025790252 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1571997986 ps |
| CPU time | 114.5 seconds |
| Started | May 12 12:29:16 PM PDT 24 |
| Finished | May 12 12:31:11 PM PDT 24 |
| Peak memory | 205096 kb |
| Host | smart-2e3f9250-a3e8-487d-a107-b613dd091225 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025790252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3025790252 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.179351652 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 998178925 ps |
| CPU time | 10.67 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:43 PM PDT 24 |
| Peak memory | 201708 kb |
| Host | smart-0fc8a9be-e78d-4353-90b5-9a19390c21fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=179351652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.179351652 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1676798820 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 83235128 ps |
| CPU time | 7.76 seconds |
| Started | May 12 12:29:00 PM PDT 24 |
| Finished | May 12 12:29:08 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-3ffe09ae-2643-4553-a333-3c47303affb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1676798820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1676798820 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.729291579 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 15112672418 ps |
| CPU time | 70.7 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:30:15 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-02b3a7cd-98a9-42b0-a2a2-4a32f6c1ec31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=729291579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.729291579 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1669550854 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 79939331 ps |
| CPU time | 4.5 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:23 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-d2649c41-2e88-47c4-94d9-97443bf464cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1669550854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1669550854 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2866518264 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 121154462 ps |
| CPU time | 5.01 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:09 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-19f9e57b-fb43-4469-8171-079adf0e3e2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866518264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2866518264 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2597423942 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 53642172 ps |
| CPU time | 1.73 seconds |
| Started | May 12 12:29:26 PM PDT 24 |
| Finished | May 12 12:29:29 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-7f89b566-884d-4344-975c-96d4eb9e7750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2597423942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2597423942 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4193878965 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6630376346 ps |
| CPU time | 6.4 seconds |
| Started | May 12 12:29:01 PM PDT 24 |
| Finished | May 12 12:29:08 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-1374ed3e-802e-4a25-ba00-388acd203334 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193878965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4193878965 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3478417593 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 9300739171 ps |
| CPU time | 24.26 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:29 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-fafdf78f-2f9b-4151-915c-6f91b209c17d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3478417593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3478417593 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2302866186 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 68532534 ps |
| CPU time | 5.86 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:10 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-a87e324f-60e2-4ff2-94e1-97b6bcfaae0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302866186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2302866186 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3474340824 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 16711851 ps |
| CPU time | 1.94 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:06 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-c7c5782f-51eb-41d8-8dc6-5b3b375979f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3474340824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3474340824 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1560556722 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 9993018 ps |
| CPU time | 1.21 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:06 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-0b258435-86e3-4cea-99dc-6bcd5dc4fccf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1560556722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1560556722 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1582886462 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1540391600 ps |
| CPU time | 7.09 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-10e22ebf-546e-4b83-8f6d-5f794156c685 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582886462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1582886462 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1506963201 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 17258500462 ps |
| CPU time | 13.49 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-78e6a53a-2399-47f1-a581-f2b24ef26139 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1506963201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1506963201 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3226897148 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 9191268 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:06 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-68cb0c62-6767-4c24-bc95-41f561557348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226897148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3226897148 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.640875985 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 17454406458 ps |
| CPU time | 53.81 seconds |
| Started | May 12 12:29:11 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-cb351884-1058-4b0f-8750-2914f230eff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=640875985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.640875985 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1266624106 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 6470671147 ps |
| CPU time | 82.34 seconds |
| Started | May 12 12:29:03 PM PDT 24 |
| Finished | May 12 12:30:27 PM PDT 24 |
| Peak memory | 202996 kb |
| Host | smart-13ab0a70-4da0-4df1-b852-ba23891b3851 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1266624106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1266624106 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.389810314 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 602302800 ps |
| CPU time | 43.43 seconds |
| Started | May 12 12:29:06 PM PDT 24 |
| Finished | May 12 12:29:50 PM PDT 24 |
| Peak memory | 203760 kb |
| Host | smart-32707b90-2629-4017-a4c3-6c32fd0ea17c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=389810314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.389810314 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.896367637 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 553461743 ps |
| CPU time | 3.97 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:09 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-8d6d23ce-5060-48c2-80f9-1cfab8d16300 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=896367637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.896367637 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1094692579 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 473455019 ps |
| CPU time | 3.57 seconds |
| Started | May 12 12:29:00 PM PDT 24 |
| Finished | May 12 12:29:04 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-05b741ae-60f5-4e45-8bbb-9b770cfae98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1094692579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1094692579 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1099287024 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 90212799663 ps |
| CPU time | 288.04 seconds |
| Started | May 12 12:29:05 PM PDT 24 |
| Finished | May 12 12:33:53 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-76ecb9a8-9860-4691-a939-37e182ce5564 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1099287024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.1099287024 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.516396880 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 554804693 ps |
| CPU time | 9.09 seconds |
| Started | May 12 12:29:10 PM PDT 24 |
| Finished | May 12 12:29:19 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-8d4d91b7-85a8-45a7-89c9-88afdeac02c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=516396880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.516396880 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3930164532 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 38618643 ps |
| CPU time | 4.25 seconds |
| Started | May 12 12:29:06 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-34072829-44fb-4ffa-80f2-e6aa04817923 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930164532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3930164532 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.832785412 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 60064670 ps |
| CPU time | 6.23 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-ba7061e9-6f05-450e-93fe-df53f315b7d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=832785412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.832785412 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1690282858 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 34870991762 ps |
| CPU time | 139.15 seconds |
| Started | May 12 12:29:17 PM PDT 24 |
| Finished | May 12 12:31:37 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-cf0bfefd-43c7-4d10-80a6-8a8bcdb48b63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690282858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1690282858 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4138078318 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 27936778003 ps |
| CPU time | 103.93 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:30:57 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-c0a18e0f-3fdf-4e82-b415-bf44bb0269a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4138078318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4138078318 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.596728021 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 14223082 ps |
| CPU time | 1.57 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:05 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-3183cce4-2729-4190-b37f-5f71f95e785b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596728021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.596728021 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.2095709373 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1336348094 ps |
| CPU time | 13.76 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:19 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-ab062d44-be77-4f8a-83d8-c85f8f6ba2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2095709373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2095709373 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1594176418 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 117052050 ps |
| CPU time | 1.77 seconds |
| Started | May 12 12:29:25 PM PDT 24 |
| Finished | May 12 12:29:28 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-1acae586-d7b7-4f72-b9bd-88f004c27b3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1594176418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1594176418 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4278879189 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3688589632 ps |
| CPU time | 10.23 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:15 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-008ae297-ab78-4343-b6aa-ccf6fc10bd0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278879189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4278879189 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3257087275 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2800944716 ps |
| CPU time | 7.57 seconds |
| Started | May 12 12:29:02 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-73ed101c-5223-4b10-9ef8-3a3baa11dba1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3257087275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3257087275 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.846880731 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 9935964 ps |
| CPU time | 1.32 seconds |
| Started | May 12 12:29:22 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-de6d5a65-edde-41c6-be9a-2dc2d5bf3af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846880731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.846880731 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1967435094 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 6408266101 ps |
| CPU time | 98.96 seconds |
| Started | May 12 12:29:19 PM PDT 24 |
| Finished | May 12 12:30:59 PM PDT 24 |
| Peak memory | 203784 kb |
| Host | smart-756cef38-58cb-4f4e-b779-f5fda4fce359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1967435094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1967435094 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2969483577 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 374148350 ps |
| CPU time | 23.89 seconds |
| Started | May 12 12:29:07 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-ff5bbb34-df05-4cc2-bf7a-03fdff676b1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2969483577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2969483577 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1734064081 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 323129127 ps |
| CPU time | 47.67 seconds |
| Started | May 12 12:29:04 PM PDT 24 |
| Finished | May 12 12:29:53 PM PDT 24 |
| Peak memory | 203984 kb |
| Host | smart-147e431b-2d46-4c25-a035-aa9d0b273d70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1734064081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.1734064081 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1743584267 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 5798273396 ps |
| CPU time | 78.43 seconds |
| Started | May 12 12:29:15 PM PDT 24 |
| Finished | May 12 12:30:34 PM PDT 24 |
| Peak memory | 205284 kb |
| Host | smart-2c47bcb7-74a2-49f7-9632-ce6cce97d886 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1743584267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.1743584267 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.528221368 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1456786404 ps |
| CPU time | 6.6 seconds |
| Started | May 12 12:29:00 PM PDT 24 |
| Finished | May 12 12:29:07 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-f0db8a54-e552-4ca4-b546-4acca02a6b68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=528221368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.528221368 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.91507555 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3188386555 ps |
| CPU time | 10.54 seconds |
| Started | May 12 12:29:07 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-2913bf8b-551c-4782-871b-1bc89db8926a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=91507555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.91507555 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2967564086 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 32871097110 ps |
| CPU time | 183.46 seconds |
| Started | May 12 12:29:06 PM PDT 24 |
| Finished | May 12 12:32:10 PM PDT 24 |
| Peak memory | 202980 kb |
| Host | smart-e1d06558-7a01-4bde-8077-d13fb408e7c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2967564086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.2967564086 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.177031269 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 146090334 ps |
| CPU time | 2.92 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:21 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-bf508e51-5099-489b-bf5c-c20dae2ba618 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177031269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.177031269 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3252056346 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 681505961 ps |
| CPU time | 10.3 seconds |
| Started | May 12 12:29:09 PM PDT 24 |
| Finished | May 12 12:29:20 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-b33d4732-8813-4c0d-bd41-9210878b4538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3252056346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3252056346 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.89430707 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 69962003 ps |
| CPU time | 3.39 seconds |
| Started | May 12 12:29:09 PM PDT 24 |
| Finished | May 12 12:29:13 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-3e5a17bb-4d09-4cab-b357-7b589f6b25bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=89430707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.89430707 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.597554366 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4395262748 ps |
| CPU time | 10.6 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-bd27bdb4-9255-49d7-b706-63604ce6d86a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=597554366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.597554366 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.484274676 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 37368338905 ps |
| CPU time | 88.5 seconds |
| Started | May 12 12:29:10 PM PDT 24 |
| Finished | May 12 12:30:39 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-f1ffdfb7-f090-411d-a402-dc3c5d7709dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=484274676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.484274676 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2027820172 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 9801591 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:29:11 PM PDT 24 |
| Finished | May 12 12:29:13 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-6d5a5975-9469-4abc-856e-e2d29a187e34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027820172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2027820172 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.2033866648 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 127549639 ps |
| CPU time | 1.72 seconds |
| Started | May 12 12:29:07 PM PDT 24 |
| Finished | May 12 12:29:09 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-ab7b6e6e-f6fc-46e3-a1f8-3ef18f8a9275 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2033866648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2033866648 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.2297024273 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 115814181 ps |
| CPU time | 1.31 seconds |
| Started | May 12 12:29:11 PM PDT 24 |
| Finished | May 12 12:29:12 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-9ae84074-31ff-46ef-bef8-447d4bc24be0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2297024273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2297024273 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.581651386 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4608856375 ps |
| CPU time | 9.16 seconds |
| Started | May 12 12:29:17 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-568db3de-9dd2-4405-95e7-77c6848362d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=581651386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.581651386 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3455493223 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1864354331 ps |
| CPU time | 9.83 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-b2c5aebb-9697-400e-ad3d-efad54d74dd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3455493223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3455493223 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4002941455 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 10571469 ps |
| CPU time | 1.13 seconds |
| Started | May 12 12:29:10 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-94d79caa-09f0-47da-bb94-ffc64582a0e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002941455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4002941455 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.807351943 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1253119382 ps |
| CPU time | 52.38 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:30:27 PM PDT 24 |
| Peak memory | 204124 kb |
| Host | smart-b0889f9c-9682-4d96-ab17-f8b13f28e911 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=807351943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.807351943 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2189482973 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 26807809468 ps |
| CPU time | 88.24 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:30:41 PM PDT 24 |
| Peak memory | 203924 kb |
| Host | smart-984f69cf-b461-43fa-a8d2-8e8938281a4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2189482973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2189482973 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.602145910 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 149304240 ps |
| CPU time | 26.17 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 203852 kb |
| Host | smart-740f4058-d5e5-40c3-a7c9-19c290bee582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=602145910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.602145910 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3521238829 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 98276801 ps |
| CPU time | 4.39 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:17 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-28889790-ff6f-4f26-aaec-4d7ca91e262d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3521238829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3521238829 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1612695204 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1047893471 ps |
| CPU time | 10.28 seconds |
| Started | May 12 12:29:07 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-09c45bb6-fc20-44b8-ac23-8a56242d625b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1612695204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1612695204 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2247730011 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1328557334 ps |
| CPU time | 15.8 seconds |
| Started | May 12 12:29:14 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-12076ff6-fd4d-4be7-b0a4-1ea9138e1748 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2247730011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2247730011 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3198150862 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 19826457673 ps |
| CPU time | 16.94 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-7677f417-be09-4326-804a-bfc2bd445bb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3198150862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3198150862 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2817318818 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 282423014 ps |
| CPU time | 2.49 seconds |
| Started | May 12 12:29:13 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-2473d118-25b3-4e3d-bf35-cdd07ba26f47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817318818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2817318818 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.4164168840 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 588202627 ps |
| CPU time | 6.49 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-170b1933-fd80-4861-89f5-7940288a0635 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4164168840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4164168840 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.3982352736 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 178721437 ps |
| CPU time | 3.02 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-0a6e16d6-999a-4ae5-9059-15712a24358d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3982352736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3982352736 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3249848955 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2703037121 ps |
| CPU time | 6.41 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:20 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-3761b152-6138-474d-88c0-2c28452da936 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249848955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3249848955 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.982347558 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 28727291201 ps |
| CPU time | 92.6 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:31:09 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-11453682-744c-4f5f-b268-f7e2eb0e6815 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=982347558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.982347558 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.660626484 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 115681791 ps |
| CPU time | 6.98 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:29 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-bf87fc3f-1cc5-4c11-bec4-d6c692985e81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660626484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.660626484 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3363299489 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 28233914 ps |
| CPU time | 2.84 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-4b8f7da2-fac8-478b-8c2e-4a29823d941a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3363299489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3363299489 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.968271461 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 275540760 ps |
| CPU time | 1.41 seconds |
| Started | May 12 12:29:15 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-af812148-76f9-4845-9a9d-b103a9508c81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=968271461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.968271461 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2582077189 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 6829128426 ps |
| CPU time | 9.24 seconds |
| Started | May 12 12:29:14 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-1c71bec2-4686-4bea-bced-6c9e99a9a999 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582077189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2582077189 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2497786237 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2319580503 ps |
| CPU time | 12.53 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:25 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-7ca39492-8222-402a-9587-d67dc0908878 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2497786237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2497786237 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3142790078 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 9909607 ps |
| CPU time | 1.27 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:14 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-d610388a-90c4-4a55-b98b-8516d6241c77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142790078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3142790078 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.4049969360 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 5859856493 ps |
| CPU time | 91.41 seconds |
| Started | May 12 12:29:14 PM PDT 24 |
| Finished | May 12 12:30:46 PM PDT 24 |
| Peak memory | 205404 kb |
| Host | smart-3848ebf6-387b-4ea6-a111-bdffe73a8fc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049969360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4049969360 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2490205338 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6944096230 ps |
| CPU time | 22.82 seconds |
| Started | May 12 12:29:19 PM PDT 24 |
| Finished | May 12 12:29:43 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-cd9920a9-d8fb-42cc-a541-d3b04a568780 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2490205338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2490205338 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.4158597815 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1712683610 ps |
| CPU time | 22.84 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:35 PM PDT 24 |
| Peak memory | 202800 kb |
| Host | smart-edee8dfa-2479-469c-bf79-b68d122cf1d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4158597815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.4158597815 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3642829550 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 78133677 ps |
| CPU time | 4.84 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-b7a337b5-0955-4d49-a7df-393b1f333ea9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3642829550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3642829550 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2298623822 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 48544215 ps |
| CPU time | 5.88 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:20 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-c98f4d1e-05a6-4399-a6b9-c28b42098b13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2298623822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2298623822 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.23558064 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 286132402046 ps |
| CPU time | 383.15 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:34:21 PM PDT 24 |
| Peak memory | 203712 kb |
| Host | smart-a739ed20-4a99-4978-9b79-d0c5969f2c20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=23558064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.23558064 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.857559308 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 864402302 ps |
| CPU time | 10.97 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-d937316f-e1bf-43fd-b465-94ed4d9dc1f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=857559308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.857559308 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1059299481 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 903311340 ps |
| CPU time | 13.09 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:19 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-edb2da9a-5575-4f30-8101-e498e76544bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1059299481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1059299481 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.1878013368 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 288801470 ps |
| CPU time | 9.24 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:28:11 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-3fb86074-cd40-4201-9593-3dede91f1c80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878013368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1878013368 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.154311214 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 41502783380 ps |
| CPU time | 121.93 seconds |
| Started | May 12 12:27:53 PM PDT 24 |
| Finished | May 12 12:29:56 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-7206206c-ad22-409a-87cd-a331737ccded |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=154311214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.154311214 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4037917932 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 10050367106 ps |
| CPU time | 73.91 seconds |
| Started | May 12 12:27:54 PM PDT 24 |
| Finished | May 12 12:29:09 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-d85f44ce-142b-4cb0-a437-0872ee3af722 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4037917932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4037917932 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1578124215 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 63447006 ps |
| CPU time | 3.59 seconds |
| Started | May 12 12:27:49 PM PDT 24 |
| Finished | May 12 12:27:53 PM PDT 24 |
| Peak memory | 201760 kb |
| Host | smart-c305d1b8-fa29-4325-8cc2-1cc914fd63fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578124215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1578124215 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3429650840 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 820086285 ps |
| CPU time | 8.16 seconds |
| Started | May 12 12:27:50 PM PDT 24 |
| Finished | May 12 12:28:00 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-833b40dc-ba57-48c6-a408-4fd18ceb9403 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3429650840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3429650840 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1823544539 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 219421551 ps |
| CPU time | 1.51 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:06 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-787dd9d8-3f52-486d-8937-dfc642a245a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1823544539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1823544539 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2233257897 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3806875890 ps |
| CPU time | 11.2 seconds |
| Started | May 12 12:27:49 PM PDT 24 |
| Finished | May 12 12:28:01 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-4334c5b8-d7f7-4a4f-8d2f-3b5fcca198c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233257897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2233257897 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.948497175 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1108072698 ps |
| CPU time | 6.21 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-fa048148-5239-40b9-9473-0a16602940b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=948497175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.948497175 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1415113103 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 8192987 ps |
| CPU time | 1.11 seconds |
| Started | May 12 12:27:56 PM PDT 24 |
| Finished | May 12 12:27:57 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-c383ca43-17c8-434f-a4df-52ae7ae23a5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415113103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1415113103 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.961788135 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 100977610 ps |
| CPU time | 9.06 seconds |
| Started | May 12 12:27:53 PM PDT 24 |
| Finished | May 12 12:28:03 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-fa97aeff-5eff-4446-8dbe-d24d6f05e2f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=961788135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.961788135 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3625884538 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 762352545 ps |
| CPU time | 7.32 seconds |
| Started | May 12 12:27:52 PM PDT 24 |
| Finished | May 12 12:28:00 PM PDT 24 |
| Peak memory | 201760 kb |
| Host | smart-8a14c1fa-22d1-47a7-8eac-74569838cd57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625884538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3625884538 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1696651351 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 501323412 ps |
| CPU time | 74.77 seconds |
| Started | May 12 12:27:55 PM PDT 24 |
| Finished | May 12 12:29:11 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-6ff15dbb-3eeb-4e22-b19f-f867650eea6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1696651351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.1696651351 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3052091792 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 383004821 ps |
| CPU time | 42.72 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:44 PM PDT 24 |
| Peak memory | 203772 kb |
| Host | smart-c342f472-b68a-463c-b315-b20e94b3d988 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3052091792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.3052091792 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3190693458 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 585028931 ps |
| CPU time | 4.48 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-c4abd853-8c39-4811-8ce8-a6dc4efccc98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3190693458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3190693458 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1903812030 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 50315009 ps |
| CPU time | 6.85 seconds |
| Started | May 12 12:29:19 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-1ac86ba2-b44c-48a9-bbcf-9f0edaa28630 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1903812030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1903812030 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2267997078 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2384411257 ps |
| CPU time | 18.05 seconds |
| Started | May 12 12:29:16 PM PDT 24 |
| Finished | May 12 12:29:35 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-f74d64fa-ed21-4bc3-b769-00ee3b369acd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2267997078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2267997078 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.421174573 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 428673600 ps |
| CPU time | 7.75 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:29 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-6412c421-2acd-4a3d-8eba-e0e552a4c29e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=421174573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.421174573 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.684169619 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1079739313 ps |
| CPU time | 9.58 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:31 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-550f7de5-9034-4a30-9889-c12075a670bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=684169619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.684169619 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.337180935 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 690269747 ps |
| CPU time | 6.51 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:29:58 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-b49b75f3-5d2c-49f0-9a8c-056f32bda4bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=337180935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.337180935 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1687832372 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 6359162149 ps |
| CPU time | 32.12 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:51 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-acc04049-3d4f-43b0-bca0-d81d8720ec09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687832372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1687832372 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2299011708 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 15517486028 ps |
| CPU time | 102.65 seconds |
| Started | May 12 12:29:16 PM PDT 24 |
| Finished | May 12 12:30:59 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-e161c959-2d93-4c5f-950f-77622e29c9b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2299011708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2299011708 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.859409304 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 390760274 ps |
| CPU time | 5.93 seconds |
| Started | May 12 12:29:16 PM PDT 24 |
| Finished | May 12 12:29:23 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-64c858b6-814f-47e9-b11e-61910586c1eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859409304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.859409304 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3031161838 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4637735736 ps |
| CPU time | 12.53 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:31 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-6e163430-828f-4e1f-9c07-094ef8bd7be4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3031161838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3031161838 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.2981348519 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 73691269 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:29:28 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-cf00597e-0409-479d-b902-ccf2ed580f90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2981348519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2981348519 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.952848548 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4326647134 ps |
| CPU time | 11.38 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:44 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-d5d4573b-01d2-4290-a264-172cec0cb973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=952848548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.952848548 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1174554792 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 968167396 ps |
| CPU time | 7.93 seconds |
| Started | May 12 12:29:12 PM PDT 24 |
| Finished | May 12 12:29:21 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-2bdcb780-feea-4b2c-a9b5-ff66abbb4994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1174554792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1174554792 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3754959419 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 9763646 ps |
| CPU time | 1.2 seconds |
| Started | May 12 12:29:17 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-9dc4021a-15aa-4003-a98b-64c40ae6c171 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754959419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3754959419 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2056820247 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 6089980329 ps |
| CPU time | 84.39 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:31:00 PM PDT 24 |
| Peak memory | 204012 kb |
| Host | smart-813783a0-35d1-4363-842a-a79557cebc5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2056820247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2056820247 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.356760962 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 6949795 ps |
| CPU time | 0.72 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:35 PM PDT 24 |
| Peak memory | 193560 kb |
| Host | smart-19e06447-0372-443a-94e2-9fa44bdd8570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=356760962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.356760962 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3152515182 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1180385303 ps |
| CPU time | 147.2 seconds |
| Started | May 12 12:29:19 PM PDT 24 |
| Finished | May 12 12:31:47 PM PDT 24 |
| Peak memory | 204488 kb |
| Host | smart-5f96def8-4a08-4a45-a14b-c694577de94a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3152515182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.3152515182 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2589577955 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 696953814 ps |
| CPU time | 82.66 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:30:44 PM PDT 24 |
| Peak memory | 203940 kb |
| Host | smart-b945b3d3-80f5-4e5e-b21e-105316419bf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589577955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2589577955 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.511551680 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 456633445 ps |
| CPU time | 1.85 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-326874ab-ea24-4bc2-a7ca-29421950277e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=511551680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.511551680 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.62533448 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 61195904 ps |
| CPU time | 1.56 seconds |
| Started | May 12 12:29:13 PM PDT 24 |
| Finished | May 12 12:29:16 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-05935b84-9af9-4454-9f4e-65d9b956f937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=62533448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.62533448 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3835974326 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 55983533814 ps |
| CPU time | 293.78 seconds |
| Started | May 12 12:29:48 PM PDT 24 |
| Finished | May 12 12:34:42 PM PDT 24 |
| Peak memory | 203440 kb |
| Host | smart-8cde87d2-79e5-4798-9e2b-cad5b9fb5bd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3835974326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.3835974326 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.52942195 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 32382273 ps |
| CPU time | 1.91 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-e3dda194-dd41-4495-9003-73cb6bf38209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52942195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.52942195 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3157055825 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 98696879 ps |
| CPU time | 7.46 seconds |
| Started | May 12 12:29:45 PM PDT 24 |
| Finished | May 12 12:29:53 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-9217240b-fd3e-421b-9350-24839f0eddad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157055825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3157055825 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.3881615800 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 533371526 ps |
| CPU time | 6.83 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:29:26 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-a623df0a-8562-4a7f-97e4-f1b1c89aa02c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3881615800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3881615800 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3075368157 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 37154658861 ps |
| CPU time | 62.7 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:30:24 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-f71fec47-df87-4152-b057-2947d6151925 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075368157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3075368157 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1848815181 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1370088410 ps |
| CPU time | 5.96 seconds |
| Started | May 12 12:29:21 PM PDT 24 |
| Finished | May 12 12:29:28 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-7c356201-8856-400d-adac-cd4fe0743a3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1848815181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1848815181 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.4208980767 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 9761340 ps |
| CPU time | 1.1 seconds |
| Started | May 12 12:29:27 PM PDT 24 |
| Finished | May 12 12:29:29 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-ec22e541-c6ac-43db-abdb-b57aa0de1714 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208980767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.4208980767 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1036315933 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1474386332 ps |
| CPU time | 6.27 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:29:56 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-84d87d14-a582-4e42-ac16-bcf015f2a3b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1036315933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1036315933 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.3555143383 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 94947813 ps |
| CPU time | 1.51 seconds |
| Started | May 12 12:29:22 PM PDT 24 |
| Finished | May 12 12:29:24 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-aa89612b-3bef-4124-acd6-35395ac4844c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3555143383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3555143383 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4042556414 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 3309284723 ps |
| CPU time | 12.41 seconds |
| Started | May 12 12:29:19 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-0e8d2e8e-e36f-4221-9c8d-001c0a40a72e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042556414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4042556414 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3228440816 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1692614418 ps |
| CPU time | 5.15 seconds |
| Started | May 12 12:29:16 PM PDT 24 |
| Finished | May 12 12:29:22 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-42c67f64-949e-44ab-a81d-165ee0d6c9f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3228440816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3228440816 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1411520583 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 16494036 ps |
| CPU time | 1.11 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:23 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-47e8b66a-1bfa-43fa-a1dc-3e779e2f0c9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411520583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1411520583 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2591006499 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 326557660 ps |
| CPU time | 23.49 seconds |
| Started | May 12 12:29:48 PM PDT 24 |
| Finished | May 12 12:30:12 PM PDT 24 |
| Peak memory | 202676 kb |
| Host | smart-eb2f6a07-a758-4cb0-9369-c51639b799c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2591006499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2591006499 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3340748302 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 6189540177 ps |
| CPU time | 56.06 seconds |
| Started | May 12 12:29:47 PM PDT 24 |
| Finished | May 12 12:30:44 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-d8b31da3-eca4-4248-9a66-fcb91c3521cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3340748302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3340748302 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3026397176 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 829744766 ps |
| CPU time | 70.01 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:30:41 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-99530aac-6a82-4133-a03e-2d2de2985f13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026397176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3026397176 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4108245203 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 8246415521 ps |
| CPU time | 142.47 seconds |
| Started | May 12 12:29:18 PM PDT 24 |
| Finished | May 12 12:31:41 PM PDT 24 |
| Peak memory | 205680 kb |
| Host | smart-fdb2b231-5171-403b-99bb-ceda148a25e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4108245203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.4108245203 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1869842527 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 694286605 ps |
| CPU time | 11.43 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:33 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-af27bb8c-b573-4759-9d05-b0167686b102 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1869842527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1869842527 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3561954287 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3032724375 ps |
| CPU time | 17.22 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:51 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-1284fc1b-a566-4ccf-85ec-9dd2cd18fd1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3561954287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3561954287 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1352988698 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 4828199205 ps |
| CPU time | 22.37 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-de2ca375-882a-4886-98d1-e99be935c01c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1352988698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1352988698 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2429910718 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 30066200 ps |
| CPU time | 3.19 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:33 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-ae1151a4-9e03-4713-9498-1c948de7422c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429910718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2429910718 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.1839707838 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 422932141 ps |
| CPU time | 4.43 seconds |
| Started | May 12 12:29:25 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-a75dcb84-e68a-4ac7-aa08-a85d6aa1c738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1839707838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1839707838 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.3375649219 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 385312967 ps |
| CPU time | 2.31 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:35 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-bbc630d2-c6d7-4d15-9424-8fa1a3265c0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3375649219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3375649219 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1300857606 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 15849306396 ps |
| CPU time | 48.31 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:30:09 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-0a930980-e123-4203-8740-34d0150b3c13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300857606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1300857606 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.66694534 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3353858094 ps |
| CPU time | 10.95 seconds |
| Started | May 12 12:29:27 PM PDT 24 |
| Finished | May 12 12:29:39 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-bcc6329d-b11d-4a68-b5ec-245596e20577 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=66694534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.66694534 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.460316320 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 39751699 ps |
| CPU time | 5.16 seconds |
| Started | May 12 12:29:21 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-03ea53ab-c767-4e98-8ad6-6b2170185cdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460316320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.460316320 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1021203709 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 798115633 ps |
| CPU time | 3.36 seconds |
| Started | May 12 12:29:26 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-7ef69937-af77-41ff-b137-1ede44b5e498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1021203709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1021203709 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.1380767900 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 60869670 ps |
| CPU time | 1.58 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:22 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-2a6bf8d1-0bb7-4c28-a84e-b8cf796c25a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1380767900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1380767900 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1412563321 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1772790644 ps |
| CPU time | 6.35 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:27 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-54d5b3a4-7b5a-4efe-8110-ff183afd243d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412563321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1412563321 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2167668167 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1841104260 ps |
| CPU time | 12.63 seconds |
| Started | May 12 12:29:20 PM PDT 24 |
| Finished | May 12 12:29:34 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-bfc41aa9-10c6-4c51-8c82-d39c53c640d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2167668167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2167668167 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3226881061 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 22992469 ps |
| CPU time | 1.09 seconds |
| Started | May 12 12:29:26 PM PDT 24 |
| Finished | May 12 12:29:28 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-5e1d1884-8327-4a6e-8d7d-c4c00c586120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226881061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3226881061 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3280829409 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 456213537 ps |
| CPU time | 13.63 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:29:44 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-8201a63a-4708-465c-ad91-73f9d2b9efc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3280829409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3280829409 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3987377171 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1971003906 ps |
| CPU time | 13.13 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 201708 kb |
| Host | smart-e2197891-7074-4c35-91ba-0b91cc065729 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3987377171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3987377171 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.669534839 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 9057513582 ps |
| CPU time | 82.84 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:30:52 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-6a1300e4-d9f9-44a8-bb4a-eb1f97dcc85a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=669534839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand _reset.669534839 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1597260719 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 538452852 ps |
| CPU time | 74.11 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:30:43 PM PDT 24 |
| Peak memory | 204280 kb |
| Host | smart-29d79803-de1e-43a6-a359-2d3069f6cfde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1597260719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1597260719 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3582379956 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 98547896 ps |
| CPU time | 4.41 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:29:36 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-fda0c215-982d-4338-b896-0d9cc30daaee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582379956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3582379956 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.2079281046 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 899461165 ps |
| CPU time | 12.4 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:42 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-26677cd5-d8c2-4b5e-a4ba-b7531dedeb95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079281046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2079281046 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2076364708 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 40455723 ps |
| CPU time | 3.5 seconds |
| Started | May 12 12:29:26 PM PDT 24 |
| Finished | May 12 12:29:31 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-8cc5c0c8-f5aa-4833-9903-f5db2a77ca61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2076364708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2076364708 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.3740177561 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1365859071 ps |
| CPU time | 16.06 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-2975feff-e10f-4289-a403-38d4ebe76951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740177561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3740177561 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2680531282 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 424286506 ps |
| CPU time | 8.25 seconds |
| Started | May 12 12:29:26 PM PDT 24 |
| Finished | May 12 12:29:35 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-3af20402-9c3a-44b5-ac57-621a5ca743e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2680531282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2680531282 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3508104020 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 22986321132 ps |
| CPU time | 42.65 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:30:18 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-c1933025-f514-4e1c-9702-a09dcb1dc5dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508104020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3508104020 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1712584275 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1161091221 ps |
| CPU time | 4.44 seconds |
| Started | May 12 12:29:25 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-9d837246-6baa-43f0-8443-dd93251029fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1712584275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1712584275 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.381655507 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 32135659 ps |
| CPU time | 3.07 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-fae907c8-fb2e-4de8-bbcf-c8773f679611 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381655507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.381655507 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.1907035420 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 45043791 ps |
| CPU time | 4.42 seconds |
| Started | May 12 12:29:36 PM PDT 24 |
| Finished | May 12 12:29:41 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-89044988-f639-4013-a5a4-4f023a9298ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1907035420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1907035420 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.3730273176 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 71093796 ps |
| CPU time | 1.39 seconds |
| Started | May 12 12:29:28 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-99682488-ab1e-484a-a9df-bf59edbb01a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3730273176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3730273176 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4199414105 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3772027561 ps |
| CPU time | 10.26 seconds |
| Started | May 12 12:29:26 PM PDT 24 |
| Finished | May 12 12:29:37 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-bdb35dad-b1d2-4382-b70d-37389703fe1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199414105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4199414105 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.489051076 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1078605801 ps |
| CPU time | 8.14 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:43 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-a85aa4d0-29cf-4368-9c09-60579c656ca6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=489051076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.489051076 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4019899086 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 13424403 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-3f8da28d-0f4b-4c20-8e38-025204a64d10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019899086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4019899086 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.4122874791 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3889437726 ps |
| CPU time | 31.3 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-dd1fdbb1-99b3-4555-a856-702c80e1086e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4122874791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4122874791 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3673272730 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 243632964 ps |
| CPU time | 1.33 seconds |
| Started | May 12 12:29:29 PM PDT 24 |
| Finished | May 12 12:29:31 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-ec305bb3-b2cb-4237-8834-8760af295038 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3673272730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3673272730 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2644645284 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 662902782 ps |
| CPU time | 63.9 seconds |
| Started | May 12 12:29:27 PM PDT 24 |
| Finished | May 12 12:30:31 PM PDT 24 |
| Peak memory | 204112 kb |
| Host | smart-02bb3e70-ef7c-4929-87ac-4db64fda885b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2644645284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.2644645284 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.410791705 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 137009555 ps |
| CPU time | 28.56 seconds |
| Started | May 12 12:29:25 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 203152 kb |
| Host | smart-b9c48181-5eef-4ad7-9cf3-22e9058d7d34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=410791705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res et_error.410791705 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.990719885 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 130945441 ps |
| CPU time | 5.47 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:29:41 PM PDT 24 |
| Peak memory | 201712 kb |
| Host | smart-7c5949fe-91a3-401c-8eb7-485ea7e2ccc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=990719885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.990719885 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1453602210 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 253105588 ps |
| CPU time | 11.57 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-f9473220-4e57-4b1f-a86b-5fddbd0aa984 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1453602210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1453602210 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3882575099 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 34959976280 ps |
| CPU time | 106.48 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:31:19 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-2f1cd189-8947-4208-9d43-280eae91d85c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3882575099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3882575099 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4229135671 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 410950442 ps |
| CPU time | 4.8 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:37 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-2008d3a1-3dc1-4b50-9254-eea2f4f6968a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4229135671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4229135671 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1443613487 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 50317005 ps |
| CPU time | 5.42 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:38 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-8048970b-854a-4c2c-8136-6e2f6055101b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443613487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1443613487 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.2191775249 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1349315405 ps |
| CPU time | 13.19 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:29:48 PM PDT 24 |
| Peak memory | 201740 kb |
| Host | smart-81fcd71e-dc0d-4c32-af5f-040d269880d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2191775249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2191775249 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1115532726 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 24123571146 ps |
| CPU time | 111.56 seconds |
| Started | May 12 12:29:25 PM PDT 24 |
| Finished | May 12 12:31:17 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-333a0506-ee0a-4107-9d1d-04a5ebfd14dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115532726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1115532726 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2034951513 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 11221534251 ps |
| CPU time | 69.23 seconds |
| Started | May 12 12:29:27 PM PDT 24 |
| Finished | May 12 12:30:37 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-a2360de7-d93e-405b-bbbb-b9a7ebeca6e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2034951513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2034951513 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3394580951 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 75352109 ps |
| CPU time | 4.3 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:38 PM PDT 24 |
| Peak memory | 201716 kb |
| Host | smart-ddceccc6-5449-4d81-b0c3-8560ac95e944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394580951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3394580951 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.555681242 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 270009033 ps |
| CPU time | 5.59 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:39 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-c4cf1e5e-40a7-4859-88d8-bc90d340fc68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=555681242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.555681242 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.2165916804 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 43636334 ps |
| CPU time | 1.39 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-8941f0e7-8daa-4d0a-b90f-b1f06d3f3566 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2165916804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2165916804 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.4017391863 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2111514499 ps |
| CPU time | 9.46 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:29:41 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-d79d68bf-6df1-44ad-8d18-63970f3da230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017391863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4017391863 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.491819622 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1547230801 ps |
| CPU time | 4.84 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:29:36 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-7011b8f4-e7ca-48c5-b6f9-cf58874a12fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=491819622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.491819622 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1598570874 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8309304 ps |
| CPU time | 1 seconds |
| Started | May 12 12:29:30 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-5523a248-49e5-429f-bf1c-e91d915546b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598570874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1598570874 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.591808272 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 144737230 ps |
| CPU time | 10.55 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:29:45 PM PDT 24 |
| Peak memory | 202776 kb |
| Host | smart-20f6f645-79af-49f2-b804-fc857b5dd14d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=591808272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.591808272 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.909772803 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2907535574 ps |
| CPU time | 35.05 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:30:11 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-ba727aca-7bd8-4f62-90f3-3164231770f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=909772803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.909772803 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.636180770 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 856755064 ps |
| CPU time | 126.89 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:31:42 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-65b0dbf1-6271-453b-99bc-d4bd0c3016ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=636180770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand _reset.636180770 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3027123011 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 12073873412 ps |
| CPU time | 60.11 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:30:33 PM PDT 24 |
| Peak memory | 204688 kb |
| Host | smart-59ece645-c879-450a-be60-e388831a7222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3027123011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.3027123011 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.894668278 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 187169391 ps |
| CPU time | 1.83 seconds |
| Started | May 12 12:29:31 PM PDT 24 |
| Finished | May 12 12:29:34 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-4bccadfd-37c0-4644-b274-63d17c984d74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=894668278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.894668278 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3679568173 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 91599138 ps |
| CPU time | 8.75 seconds |
| Started | May 12 12:29:32 PM PDT 24 |
| Finished | May 12 12:29:42 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-3ad6d74d-71c0-49c1-b3c4-a052e5afdda0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679568173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3679568173 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2525082466 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 103336439586 ps |
| CPU time | 175.72 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:32:56 PM PDT 24 |
| Peak memory | 202932 kb |
| Host | smart-6b295e47-8127-4752-8eb0-2ec17a1e7e3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2525082466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2525082466 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1586605614 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 308599235 ps |
| CPU time | 2.29 seconds |
| Started | May 12 12:29:39 PM PDT 24 |
| Finished | May 12 12:29:42 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-2a38b85b-e6dd-4152-b856-e33717e533f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1586605614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1586605614 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.777136258 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 864406449 ps |
| CPU time | 6.3 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:29:44 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-3812e4e3-def2-44fe-bf1b-d2a6189b8a54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=777136258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.777136258 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.3841593509 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 170892054 ps |
| CPU time | 7.32 seconds |
| Started | May 12 12:29:34 PM PDT 24 |
| Finished | May 12 12:29:43 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-c2ad0a06-e92c-4115-99bc-91a65901bb2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3841593509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3841593509 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3782523503 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 14160853397 ps |
| CPU time | 30.98 seconds |
| Started | May 12 12:29:44 PM PDT 24 |
| Finished | May 12 12:30:16 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-b706ee65-0792-49fc-850c-4a521021f66e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782523503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3782523503 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2193602853 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 867873697 ps |
| CPU time | 6.29 seconds |
| Started | May 12 12:29:44 PM PDT 24 |
| Finished | May 12 12:29:50 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-4dbd730a-48bb-4e62-8065-2072185659c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2193602853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2193602853 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2894041243 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 43464792 ps |
| CPU time | 2.58 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:29:38 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-04ce42a4-cd12-42ed-bf36-58fc77b26366 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894041243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2894041243 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.4021457281 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 182795622 ps |
| CPU time | 3.83 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:29:43 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-0611a45d-032b-468c-a216-d5c8f5675e5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4021457281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4021457281 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.491576765 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 95585759 ps |
| CPU time | 1.21 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-3fab0698-4a00-4489-9e7b-47041bc72e54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=491576765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.491576765 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2375488949 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1846982445 ps |
| CPU time | 9.46 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:29:45 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-a1e16957-8518-4cd6-9189-36a0a54de983 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375488949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2375488949 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3179193341 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2127227388 ps |
| CPU time | 6.66 seconds |
| Started | May 12 12:29:45 PM PDT 24 |
| Finished | May 12 12:29:52 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-d392c537-03e8-4ae8-86e8-d024e9c95bc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3179193341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3179193341 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1772086229 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 9726547 ps |
| CPU time | 1.13 seconds |
| Started | May 12 12:29:47 PM PDT 24 |
| Finished | May 12 12:29:49 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-c446737e-7492-4518-a0b7-637a91ecad69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772086229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1772086229 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2426586914 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1463354996 ps |
| CPU time | 25.66 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-1ff3e9bd-971f-434d-af5d-23a2f1005817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426586914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2426586914 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2304942829 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1704205813 ps |
| CPU time | 25.87 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:30:07 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-0c205111-5db3-4777-a7f7-21a8abb52f2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304942829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2304942829 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1342881540 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 255973075 ps |
| CPU time | 69.78 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:30:44 PM PDT 24 |
| Peak memory | 204164 kb |
| Host | smart-b354997f-7fea-4626-a7e6-e6cae27bb6f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1342881540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1342881540 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1000969918 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 323331748 ps |
| CPU time | 38.48 seconds |
| Started | May 12 12:29:45 PM PDT 24 |
| Finished | May 12 12:30:25 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-682cad7d-b2f4-4f55-bc66-6eaefbec52f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1000969918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1000969918 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1573827877 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 100167066 ps |
| CPU time | 5.56 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:29:46 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-c6857d25-3cfe-47ca-99c9-b2e50b86ced7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1573827877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1573827877 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3162264127 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 46873537 ps |
| CPU time | 7.38 seconds |
| Started | May 12 12:29:46 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-723221e9-7e98-44d4-9b43-9fdf23d33cf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3162264127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3162264127 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.413626231 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 15547053409 ps |
| CPU time | 58.62 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:30:33 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-838f1e33-0dd5-458a-9dc1-cef99fe6636b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=413626231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.413626231 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4252159948 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14903995 ps |
| CPU time | 0.99 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:29:37 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-69b7d794-f9de-44fc-95b2-42d48a10ffd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4252159948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4252159948 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.2365368662 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 35810281 ps |
| CPU time | 2.42 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:37 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-f6210c12-5762-4659-9318-587ccc1f176c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2365368662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2365368662 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3926923582 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 982113987 ps |
| CPU time | 13.01 seconds |
| Started | May 12 12:29:39 PM PDT 24 |
| Finished | May 12 12:29:53 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-1c73fb8d-32a5-4ba2-95f5-c26aafd9b201 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926923582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3926923582 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2149929420 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 8260731627 ps |
| CPU time | 16.65 seconds |
| Started | May 12 12:29:43 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-d5bf7e8f-667e-495e-bfb2-89b1de311a89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149929420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2149929420 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.4108611593 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 13470496775 ps |
| CPU time | 59.14 seconds |
| Started | May 12 12:30:01 PM PDT 24 |
| Finished | May 12 12:31:01 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-cd5ec49c-d67e-4ca5-adb0-2e4d2cf6ad80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4108611593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4108611593 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2273587876 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 18817384 ps |
| CPU time | 1.64 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-5cbfd263-df30-4827-8891-1cd0dcae3f69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273587876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2273587876 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.3606869908 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 505765236 ps |
| CPU time | 6.69 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:29:45 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-682a4219-2ad2-42bd-b54e-bdff8523692a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3606869908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3606869908 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1631778868 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 121744092 ps |
| CPU time | 1.78 seconds |
| Started | May 12 12:29:36 PM PDT 24 |
| Finished | May 12 12:29:39 PM PDT 24 |
| Peak memory | 201656 kb |
| Host | smart-3e98ba0b-5088-4884-a253-4bd6447bfe4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1631778868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1631778868 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3172946964 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3221577460 ps |
| CPU time | 8.87 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-7f5c8ae3-8742-4c5c-8074-f1528b39f636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172946964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3172946964 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2566714314 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2118925659 ps |
| CPU time | 13 seconds |
| Started | May 12 12:29:33 PM PDT 24 |
| Finished | May 12 12:29:46 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-d1e2bf9e-834d-448c-9e4d-7a2f80140781 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2566714314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2566714314 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3016701644 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 13437386 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:29:36 PM PDT 24 |
| Finished | May 12 12:29:38 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-cb48e146-9e20-4284-8bd1-e0e249429225 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016701644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3016701644 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2492969181 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 475090026 ps |
| CPU time | 27.16 seconds |
| Started | May 12 12:29:35 PM PDT 24 |
| Finished | May 12 12:30:03 PM PDT 24 |
| Peak memory | 202836 kb |
| Host | smart-92a2ac9a-9ec3-40db-91c6-a7e82a84d874 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492969181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2492969181 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1024167010 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 7741811394 ps |
| CPU time | 53.77 seconds |
| Started | May 12 12:29:36 PM PDT 24 |
| Finished | May 12 12:30:31 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-c7081018-ad26-40f1-8d34-09a10b0bbd5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1024167010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1024167010 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3787372971 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 10309987641 ps |
| CPU time | 137.74 seconds |
| Started | May 12 12:29:53 PM PDT 24 |
| Finished | May 12 12:32:12 PM PDT 24 |
| Peak memory | 205448 kb |
| Host | smart-f0713fac-9e2a-46f7-a031-cc6ec52bad3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3787372971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3787372971 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1772003870 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 21785535155 ps |
| CPU time | 156.24 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:32:15 PM PDT 24 |
| Peak memory | 207904 kb |
| Host | smart-f5f5fa67-9596-46ee-b2d8-1ac4074289d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1772003870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1772003870 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1681635101 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 61570543 ps |
| CPU time | 2.63 seconds |
| Started | May 12 12:29:39 PM PDT 24 |
| Finished | May 12 12:29:42 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-08326b4f-0a00-495f-8c1d-c447f3f29e0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1681635101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1681635101 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.842987281 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 233697391 ps |
| CPU time | 6.03 seconds |
| Started | May 12 12:29:39 PM PDT 24 |
| Finished | May 12 12:29:46 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-ef226c07-260b-41d8-b0ee-acf9d67e9607 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=842987281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.842987281 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3195641590 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 25857547548 ps |
| CPU time | 166.02 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:32:27 PM PDT 24 |
| Peak memory | 203000 kb |
| Host | smart-4ddba67a-ab62-4f74-853e-1a2ca2289ec3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3195641590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3195641590 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2834408263 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 702331513 ps |
| CPU time | 3.44 seconds |
| Started | May 12 12:29:42 PM PDT 24 |
| Finished | May 12 12:29:46 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-bed48308-bcd3-4ca0-bd10-52dabea6efb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834408263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2834408263 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.3631881745 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 41713425 ps |
| CPU time | 4.28 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:29:43 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-2c2c93e1-f36c-4591-94fd-59c44c3dba5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3631881745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3631881745 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.1096890377 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 526030789 ps |
| CPU time | 7.66 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:29:47 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-eb9ff9bc-3bd7-4e38-ad3f-04208b0c398d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1096890377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1096890377 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3724112648 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 13325563744 ps |
| CPU time | 40.19 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-96c75947-d466-406c-9cd7-9ea58e7fd0f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724112648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3724112648 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2831217105 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 21621281668 ps |
| CPU time | 105.33 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:31:26 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-c2a327aa-01d9-4bd2-9ef5-466be10c14a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2831217105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2831217105 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3459620528 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 78770490 ps |
| CPU time | 6.94 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:29:45 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-ae1b9420-a127-4622-8e42-5be219547403 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459620528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3459620528 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.3479785778 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 150284838 ps |
| CPU time | 5.5 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:29:45 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-9281455d-e295-4c72-a235-ca8b9d36b827 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3479785778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3479785778 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.1963658961 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 11596858 ps |
| CPU time | 1.09 seconds |
| Started | May 12 12:29:36 PM PDT 24 |
| Finished | May 12 12:29:38 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-f8b0f716-8fcd-4a1b-b89a-362527c44fa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1963658961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1963658961 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1902742661 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3409999941 ps |
| CPU time | 10.77 seconds |
| Started | May 12 12:29:39 PM PDT 24 |
| Finished | May 12 12:29:51 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-d124ad69-2fe5-462f-b16f-0ad65db3a038 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902742661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1902742661 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2545429740 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 612423713 ps |
| CPU time | 5.46 seconds |
| Started | May 12 12:29:37 PM PDT 24 |
| Finished | May 12 12:29:44 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-5b96e9d0-ee32-45a4-9576-a2d7b87e40a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2545429740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2545429740 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.86553784 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 8341540 ps |
| CPU time | 1.02 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:29:40 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-6037c429-2b78-451c-88ed-53862b058a97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86553784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.86553784 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.2648923418 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 43886429 ps |
| CPU time | 3.5 seconds |
| Started | May 12 12:29:47 PM PDT 24 |
| Finished | May 12 12:29:52 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-f424b9d6-bf0e-4d5f-a208-196a489d5704 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2648923418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2648923418 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.4167923999 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4226727060 ps |
| CPU time | 32.4 seconds |
| Started | May 12 12:29:39 PM PDT 24 |
| Finished | May 12 12:30:12 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-fb5804f6-958e-4ff3-a6c6-86c7ca24fbcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4167923999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.4167923999 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3403870376 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 616020585 ps |
| CPU time | 112.68 seconds |
| Started | May 12 12:29:53 PM PDT 24 |
| Finished | May 12 12:31:47 PM PDT 24 |
| Peak memory | 203944 kb |
| Host | smart-1e39a407-6c62-4cfe-93fa-e9f188094545 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403870376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3403870376 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4228465744 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 188439481 ps |
| CPU time | 27.72 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:30:07 PM PDT 24 |
| Peak memory | 202868 kb |
| Host | smart-ddabcb3a-262e-4545-b1c7-c6ed9e5484eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4228465744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.4228465744 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.23294757 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 793717736 ps |
| CPU time | 10.28 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:29:51 PM PDT 24 |
| Peak memory | 201748 kb |
| Host | smart-33281ce6-93a4-4691-85d4-1db9e4b913ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=23294757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.23294757 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1916270127 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 56487140 ps |
| CPU time | 4.11 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-c7dccdf0-83c9-4d5b-bd30-5aedfa698d05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1916270127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1916270127 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.56128138 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 63238561344 ps |
| CPU time | 350.99 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:35:43 PM PDT 24 |
| Peak memory | 202892 kb |
| Host | smart-da4315d0-4cc8-4bf1-ab19-105744742662 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=56128138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow _rsp.56128138 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2636869458 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 20375321 ps |
| CPU time | 1.87 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:29:53 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-0e258bda-f0f3-435a-83f6-d527470b38a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2636869458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2636869458 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1266241458 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 84572680 ps |
| CPU time | 5.8 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:29:56 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-38830d37-e13a-41e9-8767-92df579a2fa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1266241458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1266241458 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.533865417 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1434650161 ps |
| CPU time | 15.74 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-94862ad4-e047-4a58-acd0-f78df4f08880 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=533865417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.533865417 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.4274572289 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 49299894866 ps |
| CPU time | 124.43 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:31:45 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-e83b77f1-54bd-41d5-b9b1-3276979a8752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274572289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4274572289 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.261783840 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 14354494063 ps |
| CPU time | 114.19 seconds |
| Started | May 12 12:29:42 PM PDT 24 |
| Finished | May 12 12:31:36 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-4a02bda2-1445-4c0a-a60e-9edbd82d461b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=261783840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.261783840 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3066782182 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 43805657 ps |
| CPU time | 6.27 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:29:48 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-d2a611e9-7f85-448c-8a34-2a48ed450d71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066782182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3066782182 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.172209641 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 186466473 ps |
| CPU time | 2.48 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:29:55 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-550154ea-0ff1-46a5-bff5-fd842120bb5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=172209641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.172209641 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1614461627 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 65364797 ps |
| CPU time | 1.71 seconds |
| Started | May 12 12:29:38 PM PDT 24 |
| Finished | May 12 12:29:41 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-2b1e3101-7e30-4720-956f-3abe0c847899 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1614461627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1614461627 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2518259860 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2421843889 ps |
| CPU time | 9.19 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:29:50 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-c43d07f6-58d4-42c7-a84a-fa9dbc892163 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518259860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2518259860 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2449551874 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 769190609 ps |
| CPU time | 5.02 seconds |
| Started | May 12 12:29:40 PM PDT 24 |
| Finished | May 12 12:29:46 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-77a3df2c-3974-42b2-9167-43e6764feb65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2449551874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2449551874 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2810911583 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11894128 ps |
| CPU time | 1.07 seconds |
| Started | May 12 12:29:55 PM PDT 24 |
| Finished | May 12 12:29:57 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-ebe03d6b-45a4-4a32-9d3f-119e7b3b3f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810911583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2810911583 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2663278481 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 342852545 ps |
| CPU time | 49.3 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:30:39 PM PDT 24 |
| Peak memory | 203880 kb |
| Host | smart-7617a8fc-e64c-44f8-a3e1-a2f48f18cf4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2663278481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2663278481 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3598545198 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 185158652 ps |
| CPU time | 17.88 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:30:17 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-91672e3e-fbc4-4670-b673-15427ef5e482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3598545198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3598545198 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1037595847 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 184643949 ps |
| CPU time | 24.06 seconds |
| Started | May 12 12:29:45 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 203116 kb |
| Host | smart-c50eaeac-5e10-43d0-97eb-05e82cd0b2e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037595847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1037595847 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3608166441 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 459455023 ps |
| CPU time | 88.66 seconds |
| Started | May 12 12:29:53 PM PDT 24 |
| Finished | May 12 12:31:23 PM PDT 24 |
| Peak memory | 207004 kb |
| Host | smart-ffa083be-f4a3-48b9-b087-9468b24a610c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3608166441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3608166441 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3386051733 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 259853019 ps |
| CPU time | 4.17 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:30:05 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-57b0b74e-e6d3-4482-a517-1f9e73218a47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386051733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3386051733 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2868927823 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2141392372 ps |
| CPU time | 22.29 seconds |
| Started | May 12 12:29:43 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-1d9138ae-3ea5-4bb8-9b16-e6fe76db0fd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2868927823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2868927823 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.403955401 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 28790992 ps |
| CPU time | 1.3 seconds |
| Started | May 12 12:29:53 PM PDT 24 |
| Finished | May 12 12:29:56 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-c9a28cee-a59e-48fa-bd7c-f031214dd460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=403955401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.403955401 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.1250640858 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1337097497 ps |
| CPU time | 10.78 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201732 kb |
| Host | smart-da617822-f881-4bd6-9f90-8502cf0d1ce2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1250640858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1250640858 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.4005215863 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 570294712 ps |
| CPU time | 6.24 seconds |
| Started | May 12 12:29:45 PM PDT 24 |
| Finished | May 12 12:29:52 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-98b6cd4b-49a1-4995-b80b-245c19658a24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4005215863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.4005215863 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2046053908 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 20599928928 ps |
| CPU time | 41.55 seconds |
| Started | May 12 12:29:42 PM PDT 24 |
| Finished | May 12 12:30:24 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-f6bb122b-9e8a-42be-bd47-df37c30fd388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046053908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2046053908 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.796365231 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 37942664058 ps |
| CPU time | 177.83 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:32:50 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-095939fe-3ca3-4f1b-a8ad-a1e6c3ffa7e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=796365231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.796365231 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.4044762582 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 116304216 ps |
| CPU time | 5.29 seconds |
| Started | May 12 12:29:53 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 201732 kb |
| Host | smart-ab6c6fbf-f2a6-4326-a832-1bfa35f5165e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044762582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.4044762582 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1583020916 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 18384794 ps |
| CPU time | 1.57 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-fcce1088-4e2d-4b4a-8b1d-cae71be2ddd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583020916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1583020916 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.1323309771 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 60841435 ps |
| CPU time | 1.49 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-23bbfee8-c2b6-4397-916e-ba7beb4ac918 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1323309771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1323309771 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.814787215 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1739977185 ps |
| CPU time | 9.28 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-471ae59a-9788-40d8-8d8a-57f27b8d0740 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=814787215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.814787215 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3610080262 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1230352817 ps |
| CPU time | 9.37 seconds |
| Started | May 12 12:29:44 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-3d6fa70f-b3b5-411d-9bb6-0ee9c5a65ad7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3610080262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3610080262 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.201396720 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 7808022 ps |
| CPU time | 1.1 seconds |
| Started | May 12 12:29:46 PM PDT 24 |
| Finished | May 12 12:29:48 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-15122794-5ef0-4d25-9c61-d8397829d58f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201396720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.201396720 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3984602213 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 207946957 ps |
| CPU time | 22.24 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:30:15 PM PDT 24 |
| Peak memory | 203044 kb |
| Host | smart-a670c72b-4427-412c-b303-09ac1e6eac17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3984602213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3984602213 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.197586430 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1962796323 ps |
| CPU time | 28.17 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:30:29 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-122ecfcb-a4fc-4ed4-9070-4bfb346ccc80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=197586430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.197586430 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3765657465 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 397264229 ps |
| CPU time | 35.1 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:33 PM PDT 24 |
| Peak memory | 203344 kb |
| Host | smart-0967a9ba-f8a4-4d66-bfa6-8a545fdfd8e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3765657465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3765657465 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2326584833 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 109120593 ps |
| CPU time | 4.48 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:30:01 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-51877dfa-1e85-48a9-948e-58077f3044c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2326584833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2326584833 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.4275477055 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 156019217 ps |
| CPU time | 13.98 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:15 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-36329d69-e211-4aa8-824e-9bb6552d3f1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4275477055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4275477055 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1669467988 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 93398543757 ps |
| CPU time | 140.12 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:30:19 PM PDT 24 |
| Peak memory | 202828 kb |
| Host | smart-148edba4-b208-421d-b37b-32eaf74282d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1669467988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.1669467988 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1146282034 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1402723896 ps |
| CPU time | 9.26 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:14 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-40e4d683-d18f-4640-a833-35f7d7910132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1146282034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1146282034 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3473082808 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 26172018 ps |
| CPU time | 1.62 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:00 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-3dfe20b3-6cce-40e1-83c1-408c34dfb3af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3473082808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3473082808 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1846015270 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1078536825 ps |
| CPU time | 2.52 seconds |
| Started | May 12 12:27:56 PM PDT 24 |
| Finished | May 12 12:27:59 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-ac9e86b9-888d-42aa-8728-01a50822b739 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1846015270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1846015270 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.525043737 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 58944745978 ps |
| CPU time | 66.26 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:29:08 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-0c808e26-da32-4669-9564-11a4bf4af571 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=525043737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.525043737 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1329272857 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9662154430 ps |
| CPU time | 23.58 seconds |
| Started | May 12 12:27:56 PM PDT 24 |
| Finished | May 12 12:28:21 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-c4f52e5c-4702-4c66-a069-4f79f5aec1ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1329272857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1329272857 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1508245272 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 184324597 ps |
| CPU time | 4.42 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:04 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-0c9cade5-1067-4c08-9648-327308883b74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508245272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1508245272 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1124204635 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 111783445 ps |
| CPU time | 6.01 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:10 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-600d8baf-e7bb-4a21-8deb-6df450e4e37d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1124204635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1124204635 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.4193238593 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 11963777 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:01 PM PDT 24 |
| Peak memory | 201732 kb |
| Host | smart-8a0714e0-ada0-4f8b-9d0d-f1e2b6583efb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4193238593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4193238593 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3397668622 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 6216170559 ps |
| CPU time | 10.31 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:09 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-accb3da5-a28a-46f4-99b3-ef2eaa57733b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397668622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3397668622 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3390814239 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3381495052 ps |
| CPU time | 13.56 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:17 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-4ac02490-148c-4cc8-8264-9e095bac5d11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3390814239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3390814239 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1462531888 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 16449023 ps |
| CPU time | 1.06 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:06 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-22bdaa2f-7844-4f2c-aa79-79298461b0bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462531888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1462531888 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.181343895 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 255002839 ps |
| CPU time | 4.53 seconds |
| Started | May 12 12:28:23 PM PDT 24 |
| Finished | May 12 12:28:28 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-61bc336f-3dc2-46af-95bd-cc1a7277dbfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=181343895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.181343895 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1042732813 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 842775968 ps |
| CPU time | 15.83 seconds |
| Started | May 12 12:27:55 PM PDT 24 |
| Finished | May 12 12:28:11 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-2ed9f34e-ec43-4009-bde2-9b4a53c17981 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1042732813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1042732813 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4143714701 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 25783958 ps |
| CPU time | 10.26 seconds |
| Started | May 12 12:27:52 PM PDT 24 |
| Finished | May 12 12:28:04 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-e67f94ca-86d6-418f-82e8-ebaf053ea09b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4143714701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.4143714701 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.590528275 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 211603613 ps |
| CPU time | 14.26 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:19 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-8b0d0614-77e3-4b0d-914b-64bfab3ea72e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=590528275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.590528275 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2284920552 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 153109927 ps |
| CPU time | 7 seconds |
| Started | May 12 12:27:56 PM PDT 24 |
| Finished | May 12 12:28:04 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-80698492-08a1-4ae1-89f5-eac7f61c53a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2284920552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2284920552 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.2347798764 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2428911173 ps |
| CPU time | 19.02 seconds |
| Started | May 12 12:30:04 PM PDT 24 |
| Finished | May 12 12:30:24 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-88ba9fa3-7a95-46bc-a6cb-5078317ad9f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347798764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.2347798764 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1189807509 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 23674236291 ps |
| CPU time | 135.43 seconds |
| Started | May 12 12:29:55 PM PDT 24 |
| Finished | May 12 12:32:11 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-bd8932f7-fdf6-420c-badc-e854acb77f7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1189807509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1189807509 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4022546502 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 53521904 ps |
| CPU time | 5.02 seconds |
| Started | May 12 12:29:52 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-97ecb1b9-1555-4dbe-bd9f-65feef619c8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4022546502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4022546502 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.415481712 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 874707354 ps |
| CPU time | 11.5 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:30:03 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-e354a6e9-c3bb-49f3-9019-40216a74ed52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=415481712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.415481712 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.857997347 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 102746781 ps |
| CPU time | 3.84 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-3024fc21-dd58-4e78-b73e-2279c1eb054d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=857997347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.857997347 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3205326520 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 29030339271 ps |
| CPU time | 119.09 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:31:59 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-c6d4e69d-b015-49ea-a52b-b0a380d45e3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205326520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3205326520 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.263633182 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 14452396934 ps |
| CPU time | 91.83 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:31:24 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-7da2ec50-14d7-44d5-85ae-238914a5a81a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=263633182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.263633182 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1700566844 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 125788132 ps |
| CPU time | 6.16 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:29:58 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-3e31b434-a9ce-423a-b67e-f393cd62a932 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700566844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1700566844 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2846530913 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 26582794 ps |
| CPU time | 2.63 seconds |
| Started | May 12 12:29:54 PM PDT 24 |
| Finished | May 12 12:29:58 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-c3a37746-7e3f-477d-a552-4718f916699f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2846530913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2846530913 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.636556486 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 114991585 ps |
| CPU time | 1.56 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-faf3f1a1-60e4-45f4-88aa-0b19a867f2b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=636556486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.636556486 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3025453645 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3110306412 ps |
| CPU time | 10.04 seconds |
| Started | May 12 12:30:01 PM PDT 24 |
| Finished | May 12 12:30:12 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-c2e84f7c-506c-4aeb-8073-01c11b1058d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025453645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3025453645 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2590859460 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 722525831 ps |
| CPU time | 4.92 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:29:57 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-df83fd37-9134-48ad-893e-a09fffd751c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2590859460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2590859460 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2117523690 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 26948205 ps |
| CPU time | 1.2 seconds |
| Started | May 12 12:29:52 PM PDT 24 |
| Finished | May 12 12:29:55 PM PDT 24 |
| Peak memory | 201756 kb |
| Host | smart-15f5c353-8754-435a-a291-4aaa3b3e0016 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117523690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2117523690 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1156310328 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 673781685 ps |
| CPU time | 12.42 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-e79eff78-5eaf-4108-bace-ce3431ca6430 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1156310328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1156310328 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1949719989 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 66261197 ps |
| CPU time | 5.27 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:29:57 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-d9d8f39a-9bd6-4cd6-ba6d-cbdb600e145d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949719989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1949719989 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1590208645 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 281148547 ps |
| CPU time | 51.41 seconds |
| Started | May 12 12:29:53 PM PDT 24 |
| Finished | May 12 12:30:45 PM PDT 24 |
| Peak memory | 203880 kb |
| Host | smart-9031bd71-a6fd-4efe-afd9-2f3e98dae79c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590208645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1590208645 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.630788264 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4355791789 ps |
| CPU time | 155.33 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:32:27 PM PDT 24 |
| Peak memory | 207288 kb |
| Host | smart-92a32503-1811-4f15-a0b6-a221428a34f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=630788264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.630788264 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2448083561 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 92157076 ps |
| CPU time | 6.74 seconds |
| Started | May 12 12:30:18 PM PDT 24 |
| Finished | May 12 12:30:25 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-897bada0-9a92-4a3d-9b5d-3926cb96e603 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2448083561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2448083561 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.4104290657 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 15421071 ps |
| CPU time | 2.09 seconds |
| Started | May 12 12:29:50 PM PDT 24 |
| Finished | May 12 12:29:54 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-f492d816-fb30-4f5a-acee-34083fbbdfd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4104290657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4104290657 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.4203865098 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 13069269025 ps |
| CPU time | 59.12 seconds |
| Started | May 12 12:29:51 PM PDT 24 |
| Finished | May 12 12:30:52 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-49a7f5d2-c870-45f0-9d3b-8b60af00f4d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4203865098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.4203865098 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4164663143 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 373776038 ps |
| CPU time | 2.96 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:01 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-834d6b89-2303-4187-94b8-dc7637d0377e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4164663143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4164663143 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.2587682211 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1482057401 ps |
| CPU time | 8.83 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-84d783d0-401b-4959-8ba5-ac8dcdc43cfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2587682211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2587682211 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.3179973244 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 73620341 ps |
| CPU time | 4.14 seconds |
| Started | May 12 12:30:18 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-b735068d-ac7d-49c3-8b61-c3b919f279f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3179973244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3179973244 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.653974027 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 67272493441 ps |
| CPU time | 107.06 seconds |
| Started | May 12 12:29:54 PM PDT 24 |
| Finished | May 12 12:31:42 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-c48418f7-9a04-4823-afa1-e6500a652fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=653974027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.653974027 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3597588550 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 78578390725 ps |
| CPU time | 151.58 seconds |
| Started | May 12 12:29:55 PM PDT 24 |
| Finished | May 12 12:32:28 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-283a8562-250e-45f1-99d8-370f5ce1a117 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3597588550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3597588550 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1698047094 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 83051226 ps |
| CPU time | 5.9 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:30:03 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-18382301-d82c-4d97-95b9-06f950d7fc77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698047094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1698047094 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.105750770 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 108748494 ps |
| CPU time | 3.52 seconds |
| Started | May 12 12:29:54 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-4d72c560-b782-4269-a62f-758d5ea0296c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=105750770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.105750770 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.946698238 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 117806871 ps |
| CPU time | 1.35 seconds |
| Started | May 12 12:29:54 PM PDT 24 |
| Finished | May 12 12:29:56 PM PDT 24 |
| Peak memory | 201760 kb |
| Host | smart-78f2ffff-66ef-4cae-98c9-a083cffa8dbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946698238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.946698238 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2484892718 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2676545127 ps |
| CPU time | 11.17 seconds |
| Started | May 12 12:29:52 PM PDT 24 |
| Finished | May 12 12:30:05 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-de974729-99d5-4a47-b958-3d2137879092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484892718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2484892718 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4188925775 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1559635774 ps |
| CPU time | 5.96 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:30:03 PM PDT 24 |
| Peak memory | 201712 kb |
| Host | smart-297b8d23-1c4d-4a9c-8c20-fba59b1594ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4188925775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4188925775 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2974319349 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 11864650 ps |
| CPU time | 1.18 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:29:52 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-d8c3abb2-7142-4087-bcec-4057241cfc03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974319349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2974319349 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.2149910256 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 150468845 ps |
| CPU time | 22.03 seconds |
| Started | May 12 12:29:49 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 202872 kb |
| Host | smart-b6e286a3-9312-4965-a8e7-2e00b9c37be7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149910256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2149910256 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1373777994 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 12633445440 ps |
| CPU time | 59.12 seconds |
| Started | May 12 12:29:52 PM PDT 24 |
| Finished | May 12 12:30:52 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-a7d0913d-a0d8-4f98-bb79-e1e32a242456 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1373777994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1373777994 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.651227602 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 6109691063 ps |
| CPU time | 107.49 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:31:49 PM PDT 24 |
| Peak memory | 204396 kb |
| Host | smart-5f073d72-d048-4687-9ed7-103f9a05c86a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=651227602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.651227602 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3432289885 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 64676430 ps |
| CPU time | 2.24 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:30:07 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-412af367-5677-48ae-94bf-e22b539e3df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3432289885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.3432289885 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.123682559 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 67056541 ps |
| CPU time | 5.5 seconds |
| Started | May 12 12:29:55 PM PDT 24 |
| Finished | May 12 12:30:01 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-17eb6cad-0c04-4d42-b4e1-6b1e66b4d1d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=123682559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.123682559 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3550991229 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1221293073 ps |
| CPU time | 16.71 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:15 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-6c439713-0c68-48c6-ae3d-638f00ef8b5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550991229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3550991229 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1920204608 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 55564294721 ps |
| CPU time | 84.79 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:31:24 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-f22146e7-d045-4d3a-922d-11f297ab925e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1920204608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.1920204608 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2148439185 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 8222348 ps |
| CPU time | 1.07 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-cac4d94a-b810-457d-8f03-f62ddd6fb91f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2148439185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2148439185 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.3111095699 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 51244927 ps |
| CPU time | 4.79 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:30:09 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-4ef0125b-e590-4ef5-bccd-6972942d8e24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3111095699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3111095699 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.1872105952 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1513164150 ps |
| CPU time | 10.91 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:09 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-d2ca93bd-fa18-4910-96a5-74eccef29a4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1872105952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1872105952 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1506843325 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 9297421078 ps |
| CPU time | 33.61 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:30:31 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-949a6394-9523-4d2e-9b4e-363953ea77e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506843325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1506843325 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1415987841 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 22686786428 ps |
| CPU time | 117.96 seconds |
| Started | May 12 12:30:07 PM PDT 24 |
| Finished | May 12 12:32:05 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-61d35f35-205b-41f2-9645-c5ce28d27b2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1415987841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1415987841 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3255220019 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 181437757 ps |
| CPU time | 6.31 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-9fc97b4c-61dd-4153-96a8-96fa8d3f4339 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255220019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3255220019 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3312844790 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 503486987 ps |
| CPU time | 2.11 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:30:01 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-bf1b0453-f73c-47f9-b067-38d57c0bf835 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3312844790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3312844790 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.3833473909 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 126426165 ps |
| CPU time | 1.49 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 201688 kb |
| Host | smart-9a80d7bb-4a5a-4ff8-922e-90c6b41ae5fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3833473909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3833473909 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1216600431 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 6421550931 ps |
| CPU time | 9.94 seconds |
| Started | May 12 12:29:54 PM PDT 24 |
| Finished | May 12 12:30:05 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-088922e7-de5e-42fc-aaab-58552fff9582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216600431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1216600431 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2269461761 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1047119994 ps |
| CPU time | 7.26 seconds |
| Started | May 12 12:29:55 PM PDT 24 |
| Finished | May 12 12:30:03 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-64bd2999-3489-4826-b77f-4173a464e3c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2269461761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2269461761 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1004140855 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 27942390 ps |
| CPU time | 1.38 seconds |
| Started | May 12 12:30:21 PM PDT 24 |
| Finished | May 12 12:30:23 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-bf567cf3-b693-4d41-aff4-a92997303db8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004140855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1004140855 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4234258335 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 6165397220 ps |
| CPU time | 52.49 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:30:53 PM PDT 24 |
| Peak memory | 202924 kb |
| Host | smart-fb91c36d-7592-40a4-b083-020697d12208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234258335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4234258335 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1702576727 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15552103739 ps |
| CPU time | 91.53 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:31:32 PM PDT 24 |
| Peak memory | 203260 kb |
| Host | smart-86a7750e-a397-4937-be73-549b3f2dade3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1702576727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1702576727 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3253274516 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 780972010 ps |
| CPU time | 84.65 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:31:25 PM PDT 24 |
| Peak memory | 203672 kb |
| Host | smart-3c73e884-58aa-47b3-94c5-10923f55c5b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253274516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3253274516 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.720594385 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 92771026 ps |
| CPU time | 6.2 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-e8cf3d14-424d-41fa-98a6-25d8a6070e52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=720594385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.720594385 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.353867497 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 962209587 ps |
| CPU time | 5.61 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:30:05 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-8daae49b-4a9a-4653-9c9e-97ff64e1ff5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353867497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.353867497 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.478069792 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 118100456645 ps |
| CPU time | 188.71 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:33:09 PM PDT 24 |
| Peak memory | 202852 kb |
| Host | smart-8c2d28e7-f5c0-48d6-b868-06b4349f9236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=478069792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.478069792 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2475604723 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 15517609 ps |
| CPU time | 0.99 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-709b68f4-657d-48d5-af13-21c3d7ad050b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2475604723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2475604723 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.4101445050 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 124429492 ps |
| CPU time | 2.15 seconds |
| Started | May 12 12:30:04 PM PDT 24 |
| Finished | May 12 12:30:07 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-708bed3d-5ca4-4a08-b793-41791f6c7042 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4101445050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4101445050 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.424079459 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 25115769 ps |
| CPU time | 2.06 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:30:01 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-a6e4ce4d-03bf-4869-a9ee-9472b3b81eb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424079459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.424079459 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2294277348 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 20361088365 ps |
| CPU time | 69.9 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:31:10 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-84ca1b5d-b5f8-49a1-a385-10da09727e29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294277348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2294277348 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4065237662 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 105075391523 ps |
| CPU time | 94.93 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:31:39 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-9b5da6e8-74b2-4a18-a8cf-c93c8d5288b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4065237662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4065237662 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3027598571 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 30574276 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-927892dd-bbaf-48fc-bd65-44d694aeac1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027598571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3027598571 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.647322277 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 751538784 ps |
| CPU time | 8.78 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:30:09 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-236bf581-6416-4dca-8dde-d4fe0019dae9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647322277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.647322277 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3341470661 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 13267476 ps |
| CPU time | 1.17 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:29:59 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-4679af70-1082-488f-84d0-1a743c56e422 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3341470661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3341470661 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.443223761 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7314120753 ps |
| CPU time | 7.17 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:30:07 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-2cc6272f-4358-40fc-8bab-12e2db39ef2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=443223761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.443223761 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3060876463 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 10566629780 ps |
| CPU time | 12.03 seconds |
| Started | May 12 12:29:56 PM PDT 24 |
| Finished | May 12 12:30:09 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-988cf34f-254c-43ed-b37a-aaf2ff322a99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3060876463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3060876463 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.828069875 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 17528435 ps |
| CPU time | 1.19 seconds |
| Started | May 12 12:29:58 PM PDT 24 |
| Finished | May 12 12:30:00 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-d7f8265a-4e5a-45c7-926a-3c31e1f50497 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828069875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.828069875 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2573075223 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 13921616066 ps |
| CPU time | 95.58 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:31:34 PM PDT 24 |
| Peak memory | 203308 kb |
| Host | smart-5a8a7acd-948a-4ad6-af4c-63415c02cc85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573075223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2573075223 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2291614362 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 279582447 ps |
| CPU time | 29.78 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:30:31 PM PDT 24 |
| Peak memory | 202384 kb |
| Host | smart-fd5d9068-912b-4076-8088-e002466130c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291614362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2291614362 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3712009411 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 225877630 ps |
| CPU time | 28.46 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:30:29 PM PDT 24 |
| Peak memory | 203896 kb |
| Host | smart-eefad5a2-94dd-408e-b9de-0f9cdc1f9e67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3712009411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3712009411 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.676226562 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 11766785585 ps |
| CPU time | 141.47 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:32:25 PM PDT 24 |
| Peak memory | 208096 kb |
| Host | smart-db8ececc-7e02-46b4-9823-88fd90b861b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=676226562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res et_error.676226562 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3454907715 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 526151164 ps |
| CPU time | 7.9 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:15 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-d562420b-dbab-45c2-89be-758260b4168a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3454907715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3454907715 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1628130279 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 48154954 ps |
| CPU time | 7.45 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:30:12 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-078d524f-1622-40c8-9e15-973d77474d60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1628130279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1628130279 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2630480326 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 146738298021 ps |
| CPU time | 283.42 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:34:45 PM PDT 24 |
| Peak memory | 203212 kb |
| Host | smart-bb66045c-a114-4559-8234-f20424efe326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2630480326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2630480326 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1808091199 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 815659979 ps |
| CPU time | 5.23 seconds |
| Started | May 12 12:30:13 PM PDT 24 |
| Finished | May 12 12:30:19 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-01ac4698-dfd3-4e92-b848-e57bbd2889f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808091199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1808091199 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1839903188 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 63133131 ps |
| CPU time | 6.39 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-0c7edea8-2a04-4bfc-8f1a-f8b80d0995c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1839903188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1839903188 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.1588944060 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 53450795 ps |
| CPU time | 5.79 seconds |
| Started | May 12 12:29:57 PM PDT 24 |
| Finished | May 12 12:30:04 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-7943a3ce-4fa1-4b7e-8910-cec579219ee0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1588944060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1588944060 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.247595891 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 27653211104 ps |
| CPU time | 116.78 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:32:01 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-1d886bec-8ba2-4f79-8f40-5f425b5d294c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=247595891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.247595891 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4232790547 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 47970241211 ps |
| CPU time | 51.32 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:58 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-fade17bf-d9b3-4cb2-b7d8-ccef50252df0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4232790547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4232790547 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.849759748 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 52072417 ps |
| CPU time | 4.38 seconds |
| Started | May 12 12:30:00 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-44241e9e-81ed-4b3f-b220-a09859bb064f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849759748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.849759748 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3961471494 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 235445632 ps |
| CPU time | 4.47 seconds |
| Started | May 12 12:30:07 PM PDT 24 |
| Finished | May 12 12:30:12 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-abdfd00a-9048-481c-ae4d-f6c2d0104f74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961471494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3961471494 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1649239609 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 8540683 ps |
| CPU time | 1.07 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-3a6e3157-40fb-4bd7-91bf-b1d4935d0266 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1649239609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1649239609 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.738723823 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1688754654 ps |
| CPU time | 6.9 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:20 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-e9bfe875-d52e-4806-bde7-bfc404f0d7d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=738723823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.738723823 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.971517095 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 6650690591 ps |
| CPU time | 8.45 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:16 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-89263293-ed5e-4eb1-97b2-9b1178ba96fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=971517095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.971517095 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3314910656 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15302237 ps |
| CPU time | 1.19 seconds |
| Started | May 12 12:30:04 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-f1fafb5e-adcb-480d-ba78-05e5c209324d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314910656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3314910656 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.4234442565 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2283892122 ps |
| CPU time | 37.05 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:40 PM PDT 24 |
| Peak memory | 202876 kb |
| Host | smart-ecf3c95e-aa29-4e40-8172-5d828a69e1e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234442565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4234442565 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2935001400 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 489907820 ps |
| CPU time | 23.47 seconds |
| Started | May 12 12:30:01 PM PDT 24 |
| Finished | May 12 12:30:25 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-73cf5e13-b821-4254-94b3-f9ba43f0d699 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2935001400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2935001400 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.128498223 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1716348401 ps |
| CPU time | 161.47 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:32:53 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-da3a4a07-1b03-4a91-9666-891242d605b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=128498223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.128498223 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3084075617 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 80952119 ps |
| CPU time | 18.02 seconds |
| Started | May 12 12:30:04 PM PDT 24 |
| Finished | May 12 12:30:23 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-7f835c7c-de02-4c75-87c6-161f997fc04d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3084075617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.3084075617 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2062913692 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 299611921 ps |
| CPU time | 5.7 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 201740 kb |
| Host | smart-3eefbb86-50e0-4e3e-ae78-6127cc756731 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2062913692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2062913692 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.172559484 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 16563859 ps |
| CPU time | 1.85 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-1b7fec53-c632-4c70-9f32-ac590169ec8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=172559484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.172559484 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.329142077 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2559689685 ps |
| CPU time | 7.8 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:17 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-9e9c9ac1-1922-48d3-b420-ec87414c9c47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=329142077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.329142077 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2813443187 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 303257245 ps |
| CPU time | 2.24 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:05 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-035b9798-14ab-470c-85a6-e320101f3036 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2813443187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2813443187 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3330112512 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 46437605 ps |
| CPU time | 6.44 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:18 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-5397c2e5-5b97-48a0-ae7f-4fa358f283eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3330112512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3330112512 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2700901985 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 10718290888 ps |
| CPU time | 46.34 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:58 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-d4268718-62da-4662-a776-5deecba19ae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700901985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2700901985 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1211423681 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5065310726 ps |
| CPU time | 20.42 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:30:24 PM PDT 24 |
| Peak memory | 201920 kb |
| Host | smart-4441acd1-95cc-4723-9354-8bc08e48325b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1211423681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1211423681 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.636101266 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 60131080 ps |
| CPU time | 5.55 seconds |
| Started | May 12 12:30:03 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-6fccb47d-dbc9-4878-a8be-6faa2cd68edc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636101266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.636101266 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.582623903 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 125070876 ps |
| CPU time | 4.58 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-5b91bac3-5cce-4ee0-bf29-0a2243444817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=582623903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.582623903 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.1735015592 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 9586352 ps |
| CPU time | 1.12 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-b3cb8d97-3658-4e3f-bd00-a461c5980876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1735015592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1735015592 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3106837552 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2419733304 ps |
| CPU time | 10.31 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:17 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-1ac66b18-7504-4686-8bea-d3fa9f619792 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106837552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3106837552 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1906372327 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1900783908 ps |
| CPU time | 7.63 seconds |
| Started | May 12 12:29:59 PM PDT 24 |
| Finished | May 12 12:30:08 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-cab254c0-6341-4979-91a9-e94af2879e07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1906372327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1906372327 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.482888899 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 9871376 ps |
| CPU time | 1.12 seconds |
| Started | May 12 12:30:04 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-4914373a-012e-477b-bf66-d33a814c0c6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482888899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.482888899 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1031826947 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2823572651 ps |
| CPU time | 24.23 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:35 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-ab6efe4b-51be-48c8-9c2c-e95060f733be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1031826947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1031826947 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2370527263 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 506747030 ps |
| CPU time | 7.41 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:19 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-db6f841c-35c0-464c-881c-520bf5988bdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2370527263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2370527263 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4192517150 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 185341423 ps |
| CPU time | 18.26 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 203640 kb |
| Host | smart-6a86d64e-88f7-47f3-9a87-369c419b55f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4192517150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.4192517150 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3381764395 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 450897051 ps |
| CPU time | 34.48 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:45 PM PDT 24 |
| Peak memory | 203404 kb |
| Host | smart-a99cef8f-2893-4f94-8f31-801ad9048531 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381764395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3381764395 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.348769141 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 27682757 ps |
| CPU time | 2.95 seconds |
| Started | May 12 12:30:02 PM PDT 24 |
| Finished | May 12 12:30:06 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-e5a53091-fc10-4c8d-bb7f-83dc99274f1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=348769141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.348769141 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.237095591 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 37338397 ps |
| CPU time | 2.55 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-2c661aa1-eac3-4a6b-9198-16ae60f6c7c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237095591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.237095591 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2796613134 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 50623806681 ps |
| CPU time | 286.23 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:34:55 PM PDT 24 |
| Peak memory | 203556 kb |
| Host | smart-8a061706-8e65-4997-ad5f-59831a61ddc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2796613134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2796613134 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3003912394 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 281309969 ps |
| CPU time | 5.53 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 201820 kb |
| Host | smart-9c1f79d1-4c66-4f15-ad58-4b22cf895d12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003912394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3003912394 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.427966199 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1033433560 ps |
| CPU time | 8.21 seconds |
| Started | May 12 12:30:22 PM PDT 24 |
| Finished | May 12 12:30:31 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-8fd98abc-8952-4e61-a808-c2188a302cb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=427966199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.427966199 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.2536003559 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 507890696 ps |
| CPU time | 6.7 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:18 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-4d43253e-96d4-48de-b3fa-5fdf80197db1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2536003559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2536003559 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3755908571 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 20607989866 ps |
| CPU time | 64.48 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:31:16 PM PDT 24 |
| Peak memory | 201956 kb |
| Host | smart-7c8a64e3-dd84-4f44-b1f1-3d797f5206f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755908571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3755908571 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2196658135 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4404372365 ps |
| CPU time | 26.23 seconds |
| Started | May 12 12:30:07 PM PDT 24 |
| Finished | May 12 12:30:34 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-54e9173b-184b-40b3-b7b7-6db2901b460e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2196658135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2196658135 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3763838741 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 41308270 ps |
| CPU time | 4.26 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:17 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-ef45914e-94b4-4858-bd1a-b3c3dabcd5bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763838741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3763838741 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1279464141 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 275939682 ps |
| CPU time | 5.51 seconds |
| Started | May 12 12:30:13 PM PDT 24 |
| Finished | May 12 12:30:20 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-e5e5aaac-6a8c-465e-8cda-016f6ce6257b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279464141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1279464141 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.354033907 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 78767442 ps |
| CPU time | 1.23 seconds |
| Started | May 12 12:30:05 PM PDT 24 |
| Finished | May 12 12:30:07 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-7d103026-261e-4268-a05d-41a02e0479f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354033907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.354033907 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3364081989 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 5520562571 ps |
| CPU time | 13.77 seconds |
| Started | May 12 12:30:23 PM PDT 24 |
| Finished | May 12 12:30:37 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-f34af8bf-88f3-4ced-8872-a35b7fe9924d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364081989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3364081989 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.668651025 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8505021367 ps |
| CPU time | 11.3 seconds |
| Started | May 12 12:30:07 PM PDT 24 |
| Finished | May 12 12:30:19 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-565b3ea3-8322-4a55-8219-543fd985e361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=668651025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.668651025 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3100780956 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 9542325 ps |
| CPU time | 1.36 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-3f48d0c1-97eb-4be9-a8a2-262ace4c1204 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100780956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3100780956 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3769791154 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 429649992 ps |
| CPU time | 26.06 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:34 PM PDT 24 |
| Peak memory | 202840 kb |
| Host | smart-7e0b21f5-4ee5-4d53-b094-bb92ac804829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769791154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3769791154 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1770006980 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7423359919 ps |
| CPU time | 80.45 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:31:29 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-d714efa1-c26c-4f71-9383-4a7c7be4f2d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1770006980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1770006980 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2012528764 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 581750647 ps |
| CPU time | 9.83 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:30:23 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-8ae7074b-faf5-457a-9007-d2cf5049c036 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2012528764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2012528764 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1936670320 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 451841114 ps |
| CPU time | 8.87 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-7fc26d2c-c8ea-476d-8c96-7dad4af637ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1936670320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1936670320 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1420233021 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 31483582777 ps |
| CPU time | 226.57 seconds |
| Started | May 12 12:30:17 PM PDT 24 |
| Finished | May 12 12:34:04 PM PDT 24 |
| Peak memory | 202916 kb |
| Host | smart-2ea63ead-d322-4435-84bb-f658ca5ce29e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1420233021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1420233021 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2370693245 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 318861429 ps |
| CPU time | 4.76 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:16 PM PDT 24 |
| Peak memory | 201908 kb |
| Host | smart-64267b59-2a42-43a8-8e9f-bf94f6e8b86f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2370693245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2370693245 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2353174863 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2598283483 ps |
| CPU time | 11.42 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:24 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-b7f331bf-e6a1-4aad-94f8-cdbcaf10869b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2353174863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2353174863 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2606438067 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 828236181 ps |
| CPU time | 13.04 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-610bede0-d2ed-4b34-8801-f1e844a8e93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2606438067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2606438067 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1507156888 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 75774718151 ps |
| CPU time | 134.95 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:32:26 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-e9b73edc-f9a2-4c44-a475-b2d4d53a04aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507156888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1507156888 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2791037826 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 42274095342 ps |
| CPU time | 120.93 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:32:08 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-55d28360-88ac-4c12-9f07-e352a8d15d2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2791037826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2791037826 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3316506287 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 218420074 ps |
| CPU time | 5.41 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-0449395c-7886-4d15-9625-7c9f3f888369 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316506287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3316506287 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.607395978 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 483936570 ps |
| CPU time | 5.9 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:17 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-e1abacf3-8d77-4db2-8da2-b2017d386bb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=607395978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.607395978 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.1976311519 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 159466880 ps |
| CPU time | 1.55 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-3bd4cca2-85be-4a09-94ce-3d8a1b3f3590 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976311519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1976311519 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1830340071 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3373690938 ps |
| CPU time | 6.11 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:18 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-a939585d-d914-4fab-84b4-0464c1233b70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830340071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1830340071 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1221358345 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5146841283 ps |
| CPU time | 10.68 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:30:18 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-59672afc-0a21-4d09-b6a1-a217b32888d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1221358345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1221358345 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1403448756 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 15072502 ps |
| CPU time | 1.19 seconds |
| Started | May 12 12:30:08 PM PDT 24 |
| Finished | May 12 12:30:10 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-120b1a85-298f-48c8-9e75-76de4432f5c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403448756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1403448756 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.625802272 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 374464427 ps |
| CPU time | 19.88 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:30 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-b2d85a80-e44a-4007-87ab-0f0ed169dcb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=625802272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.625802272 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1569012197 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 202363156 ps |
| CPU time | 13.21 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:25 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-e2db5d5c-e910-45ad-9340-abcddf9ee93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1569012197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1569012197 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3860916461 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 11972832041 ps |
| CPU time | 185.1 seconds |
| Started | May 12 12:30:06 PM PDT 24 |
| Finished | May 12 12:33:12 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-62e887b0-ac85-413b-838d-62201edd6d7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3860916461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3860916461 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1072963374 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 518360403 ps |
| CPU time | 42.29 seconds |
| Started | May 12 12:30:05 PM PDT 24 |
| Finished | May 12 12:30:48 PM PDT 24 |
| Peak memory | 204048 kb |
| Host | smart-baa4eebf-554b-45da-98b5-3caf403d09df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1072963374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1072963374 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1473384375 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 559239931 ps |
| CPU time | 4.07 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:16 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-59e44ce0-2064-4996-bbc4-ec9acb8aa3aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1473384375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1473384375 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2587410074 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 55953942 ps |
| CPU time | 8.37 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:20 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-189fc132-0a99-48d1-bbde-fc99aeb44668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2587410074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2587410074 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.293171735 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 39033095754 ps |
| CPU time | 270.35 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:34:41 PM PDT 24 |
| Peak memory | 202860 kb |
| Host | smart-bcb13741-a977-43dc-99ca-d4d6b184e844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=293171735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.293171735 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.466135749 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 532548428 ps |
| CPU time | 6.76 seconds |
| Started | May 12 12:30:13 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-4f85fc62-cb99-484c-b5ce-f4088b069173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=466135749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.466135749 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.765618404 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 799840884 ps |
| CPU time | 3.75 seconds |
| Started | May 12 12:30:16 PM PDT 24 |
| Finished | May 12 12:30:20 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-04a59b92-9460-46d8-9e49-8f85fdbc0f04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=765618404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.765618404 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.2954011575 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 104077312 ps |
| CPU time | 8.88 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:20 PM PDT 24 |
| Peak memory | 201816 kb |
| Host | smart-5a4cfbc6-584f-4031-8a64-d3115e0dc217 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2954011575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2954011575 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.664249198 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 89813569328 ps |
| CPU time | 62.2 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:31:13 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-67a7ac0e-7b13-46c5-b29f-80f7f775d8cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=664249198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.664249198 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3703959323 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 32101474283 ps |
| CPU time | 59.07 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:31:10 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-0d76f2ec-7be9-497a-9438-2a2e550b1aa2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3703959323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3703959323 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.146124310 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 23419826 ps |
| CPU time | 2.52 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:14 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-982eadc8-3b09-4799-ab2b-c9d0c2257bf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146124310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.146124310 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.2287807072 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3721208784 ps |
| CPU time | 8.52 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201972 kb |
| Host | smart-c44b79ae-4e79-4e66-ae87-55993058af01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2287807072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2287807072 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.4000788740 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 192857145 ps |
| CPU time | 1.61 seconds |
| Started | May 12 12:30:09 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-9eb7b367-7495-45fa-8c8d-cbf8e2ae4829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000788740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.4000788740 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.932566711 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 2379552344 ps |
| CPU time | 10.07 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201880 kb |
| Host | smart-1cc72b04-620c-4e9e-9b51-f4bf6dd9070a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=932566711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.932566711 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3393758535 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1847845986 ps |
| CPU time | 9.98 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-71dcf61f-52ce-4600-af63-1ec00ea31c36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3393758535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3393758535 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.977737535 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 17781733 ps |
| CPU time | 1.26 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:30:13 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-ae5480c2-4df8-4faa-9cf2-b69774e9abdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977737535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.977737535 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.437505195 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 377425821 ps |
| CPU time | 13.37 seconds |
| Started | May 12 12:30:11 PM PDT 24 |
| Finished | May 12 12:30:26 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-65d78733-de66-42f2-a49d-e8a6743c9f3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=437505195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.437505195 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1903347889 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 13938405588 ps |
| CPU time | 88.3 seconds |
| Started | May 12 12:30:22 PM PDT 24 |
| Finished | May 12 12:31:51 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-09f4de0f-0227-4477-8c89-8a51397979e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1903347889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1903347889 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.177569551 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 644468614 ps |
| CPU time | 75.74 seconds |
| Started | May 12 12:30:10 PM PDT 24 |
| Finished | May 12 12:31:28 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-943dd063-df90-4b47-88ee-e5072a91f822 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177569551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand _reset.177569551 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4032461475 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 149978382 ps |
| CPU time | 4.71 seconds |
| Started | May 12 12:30:17 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-33e425fd-8902-447d-84f1-8b87f457b723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4032461475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.4032461475 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3107902772 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 19150904 ps |
| CPU time | 2.14 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:30:16 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-58763b0b-f64c-489b-8f82-e1dca3b4fbd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107902772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3107902772 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.3615912065 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 375847435 ps |
| CPU time | 6.64 seconds |
| Started | May 12 12:30:13 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-3bc6a083-cbab-4a40-979b-1a4d48ee5b18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3615912065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3615912065 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3717747603 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 46160969605 ps |
| CPU time | 184.74 seconds |
| Started | May 12 12:30:13 PM PDT 24 |
| Finished | May 12 12:33:19 PM PDT 24 |
| Peak memory | 202908 kb |
| Host | smart-b184772d-66ff-4844-a2c0-b2b35cd84030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3717747603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3717747603 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.57094131 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 64355169 ps |
| CPU time | 6.74 seconds |
| Started | May 12 12:30:15 PM PDT 24 |
| Finished | May 12 12:30:22 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-05b3cfd8-a029-4871-9e18-56b06d908416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=57094131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.57094131 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.3127923514 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 189637351 ps |
| CPU time | 2.93 seconds |
| Started | May 12 12:30:17 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 201728 kb |
| Host | smart-f62b1c63-efc5-4078-8aa5-916ac1f9c6b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127923514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3127923514 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1326933728 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4960651702 ps |
| CPU time | 14.51 seconds |
| Started | May 12 12:30:15 PM PDT 24 |
| Finished | May 12 12:30:30 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-1f71633f-75cc-407a-8ae2-745eacebb024 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1326933728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1326933728 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3260248737 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 51567292630 ps |
| CPU time | 134.03 seconds |
| Started | May 12 12:30:20 PM PDT 24 |
| Finished | May 12 12:32:35 PM PDT 24 |
| Peak memory | 201812 kb |
| Host | smart-3bf7ba30-0c37-428a-ad02-0c9154ca33fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260248737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3260248737 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.360185748 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 7888787529 ps |
| CPU time | 28.41 seconds |
| Started | May 12 12:30:16 PM PDT 24 |
| Finished | May 12 12:30:45 PM PDT 24 |
| Peak memory | 201892 kb |
| Host | smart-b44beac0-404f-4d85-b0b9-8a676c9f698c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=360185748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.360185748 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1724877493 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 25292276 ps |
| CPU time | 2.88 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:30:16 PM PDT 24 |
| Peak memory | 201836 kb |
| Host | smart-236039f3-e4a4-433b-b145-57833fd0e4bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724877493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1724877493 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1684395509 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1639658149 ps |
| CPU time | 9.2 seconds |
| Started | May 12 12:30:16 PM PDT 24 |
| Finished | May 12 12:30:26 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-c36ad4dd-5374-4e13-8f5a-85f937cb750c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1684395509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1684395509 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.2074689473 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 104758737 ps |
| CPU time | 1.34 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:30:15 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-6c93818d-4aec-4121-87f0-6b12a19ae2a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2074689473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2074689473 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2302464394 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 14076386087 ps |
| CPU time | 8.41 seconds |
| Started | May 12 12:30:21 PM PDT 24 |
| Finished | May 12 12:30:30 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-ae4fd127-0a7b-41ee-81a6-af9a54f2ca70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302464394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2302464394 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3192641174 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3926491595 ps |
| CPU time | 13.4 seconds |
| Started | May 12 12:30:15 PM PDT 24 |
| Finished | May 12 12:30:29 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-9d1d354a-6b67-416f-81e2-7c65a20a4cbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3192641174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3192641174 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.90447224 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8457275 ps |
| CPU time | 1.11 seconds |
| Started | May 12 12:30:15 PM PDT 24 |
| Finished | May 12 12:30:17 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-123dd5a4-92be-46c4-b3ed-2ffbc2dbebc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90447224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.90447224 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1379650292 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 13135787570 ps |
| CPU time | 45.73 seconds |
| Started | May 12 12:30:18 PM PDT 24 |
| Finished | May 12 12:31:04 PM PDT 24 |
| Peak memory | 203036 kb |
| Host | smart-2954d668-b165-472f-9f5d-500d23b7d2f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379650292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1379650292 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.433627874 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 8424076689 ps |
| CPU time | 57.99 seconds |
| Started | May 12 12:30:22 PM PDT 24 |
| Finished | May 12 12:31:21 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-e0a9215c-6680-478d-90a3-7f9d5dd27b3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=433627874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.433627874 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.41739344 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1365520991 ps |
| CPU time | 134.69 seconds |
| Started | May 12 12:30:16 PM PDT 24 |
| Finished | May 12 12:32:31 PM PDT 24 |
| Peak memory | 205520 kb |
| Host | smart-c6992e06-3af8-4849-a0f8-f304f830cdfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41739344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_ reset.41739344 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.399708939 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5717488679 ps |
| CPU time | 105.43 seconds |
| Started | May 12 12:30:12 PM PDT 24 |
| Finished | May 12 12:31:59 PM PDT 24 |
| Peak memory | 206136 kb |
| Host | smart-a16917bb-0c70-4e82-9452-acaa46677775 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=399708939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res et_error.399708939 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2819958889 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 510470194 ps |
| CPU time | 9.79 seconds |
| Started | May 12 12:30:15 PM PDT 24 |
| Finished | May 12 12:30:25 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-60152f99-34d1-4d4b-9ef3-679ddcb14348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2819958889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2819958889 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1685207153 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 180842926 ps |
| CPU time | 3.35 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:28:06 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-6e8989c5-6bde-4262-849b-01bd5c05a2bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1685207153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1685207153 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.887951656 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 22884580 ps |
| CPU time | 2.42 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-f5fcb589-3e78-4e6f-9fe2-7fc1dc13d0a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=887951656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.887951656 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.1972944899 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 53678991 ps |
| CPU time | 3.76 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:08 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-ea3643dc-ff1f-4e94-9061-8be2cde86942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1972944899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1972944899 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2534936636 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 726210419 ps |
| CPU time | 7.15 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:28:17 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-6a7493e3-4e7e-4a72-9a3f-1bcce0febeb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534936636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2534936636 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1833864589 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 26876464942 ps |
| CPU time | 118.92 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:30:09 PM PDT 24 |
| Peak memory | 201912 kb |
| Host | smart-8e22eb61-e0a2-4844-a62e-62e0ffb9f840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833864589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1833864589 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.460398460 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5122507068 ps |
| CPU time | 14.45 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:28:17 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-b5a5d74c-7f3a-495b-990d-0fd4d9c27743 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=460398460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.460398460 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1292904296 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 76925356 ps |
| CPU time | 7 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-d028f9c3-57b8-4ba6-8147-514cac65b942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292904296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1292904296 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.3775796569 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 599982776 ps |
| CPU time | 8.64 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:21 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-a00a5b31-5519-429d-9d08-b3f08c2c5a4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775796569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3775796569 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2853384687 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 13426000 ps |
| CPU time | 1.31 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:01 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-bcdd1d19-dcf6-4f92-b234-adb080c3be76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853384687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2853384687 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.300884464 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1550545913 ps |
| CPU time | 8.27 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201848 kb |
| Host | smart-95889089-8d44-4063-aef9-efac90b3f54b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=300884464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.300884464 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3849177938 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 10130392306 ps |
| CPU time | 14.31 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-504725e0-1d73-4e50-a5de-59748f348e28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3849177938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3849177938 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4189712448 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11594443 ps |
| CPU time | 1.2 seconds |
| Started | May 12 12:28:04 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-7b0e52a7-6acf-4316-a730-a698a051fcdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189712448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4189712448 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3047403989 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2618116943 ps |
| CPU time | 42.59 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:44 PM PDT 24 |
| Peak memory | 203164 kb |
| Host | smart-c226b121-92df-4094-8cf6-ee726c8b97d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3047403989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3047403989 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1317040138 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 7435209551 ps |
| CPU time | 53.12 seconds |
| Started | May 12 12:28:01 PM PDT 24 |
| Finished | May 12 12:28:56 PM PDT 24 |
| Peak memory | 203868 kb |
| Host | smart-9fcfce3d-cef6-4975-9daf-cabdcd449089 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1317040138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1317040138 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.863416172 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 9285646659 ps |
| CPU time | 71.95 seconds |
| Started | May 12 12:28:01 PM PDT 24 |
| Finished | May 12 12:29:15 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-7125d892-e66a-4b41-a851-49035fe4cee8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863416172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.863416172 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.853014049 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 48668878 ps |
| CPU time | 4.42 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-5ee1aae1-8223-4e18-a560-f1693c9e3f0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=853014049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.853014049 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1551522775 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 325981601 ps |
| CPU time | 6.96 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201828 kb |
| Host | smart-5749c2c6-6c57-4ea1-8ace-420d09967436 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1551522775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1551522775 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3176218728 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3084941219 ps |
| CPU time | 14.37 seconds |
| Started | May 12 12:28:09 PM PDT 24 |
| Finished | May 12 12:28:25 PM PDT 24 |
| Peak memory | 201876 kb |
| Host | smart-020ac53a-7a8f-47a1-ad73-f2326c0a0479 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3176218728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3176218728 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1228795567 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 83230897 ps |
| CPU time | 3 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:09 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-0b7836c6-7082-43a5-990d-f9d27b5c4d91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228795567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1228795567 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.4033348575 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 188624130 ps |
| CPU time | 4.89 seconds |
| Started | May 12 12:28:04 PM PDT 24 |
| Finished | May 12 12:28:11 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-21a5a41b-f147-4319-ac7c-c6c8f570fedc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4033348575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.4033348575 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.4153956908 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 23890660 ps |
| CPU time | 2.68 seconds |
| Started | May 12 12:27:59 PM PDT 24 |
| Finished | May 12 12:28:04 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-92ce3805-6efd-4843-a875-f21f47ce7edf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4153956908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.4153956908 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.445216289 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 17653347805 ps |
| CPU time | 39.25 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:43 PM PDT 24 |
| Peak memory | 201868 kb |
| Host | smart-2db1f02f-5280-41b9-81cf-90bf884dc53d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=445216289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.445216289 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2330849044 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 6811201575 ps |
| CPU time | 15.45 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201888 kb |
| Host | smart-b3628ffb-b0e4-4a1e-8669-6ff76a57c66f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2330849044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2330849044 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.968115408 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 13341403 ps |
| CPU time | 1.43 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:28:04 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-db35b7d6-285a-405f-8483-099e834d36df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968115408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.968115408 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3447648067 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 829142058 ps |
| CPU time | 6.15 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:28:17 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-760717db-b980-4339-899b-e1bb979f6aaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3447648067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3447648067 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.1988893539 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 12274351 ps |
| CPU time | 1.14 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:02 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-7ebcd7e1-f937-493b-8be5-0f0431e492e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1988893539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1988893539 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.481389844 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 23524640299 ps |
| CPU time | 12.72 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-721946ef-9928-4629-96dd-90388447a5d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=481389844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.481389844 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.4187362405 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4545636488 ps |
| CPU time | 7.65 seconds |
| Started | May 12 12:27:57 PM PDT 24 |
| Finished | May 12 12:28:06 PM PDT 24 |
| Peak memory | 201904 kb |
| Host | smart-518bf816-0310-4ec0-9d17-688003d1fee1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4187362405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.4187362405 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3372383928 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 10162339 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:02 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-62f14ced-6552-4f58-b8d5-1c2f5bcd7f57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372383928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3372383928 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1081204901 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 30658819897 ps |
| CPU time | 68.06 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:29:14 PM PDT 24 |
| Peak memory | 202840 kb |
| Host | smart-a79b55ac-c52c-437b-9d90-96ca3e58df35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1081204901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1081204901 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3859727125 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5153145336 ps |
| CPU time | 73.65 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:29:18 PM PDT 24 |
| Peak memory | 202876 kb |
| Host | smart-a021c83d-9365-438f-89e2-9d33ddbf0b02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859727125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3859727125 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.683297007 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 613810863 ps |
| CPU time | 52.74 seconds |
| Started | May 12 12:28:04 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-9491c926-c7e3-44ba-9a88-59061b1218c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=683297007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.683297007 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2658293407 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 9565834860 ps |
| CPU time | 159.42 seconds |
| Started | May 12 12:28:01 PM PDT 24 |
| Finished | May 12 12:30:43 PM PDT 24 |
| Peak memory | 209076 kb |
| Host | smart-ac37a005-cbdd-4671-998a-033e89f9cd4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2658293407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2658293407 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.654474112 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 111150153 ps |
| CPU time | 2.6 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:28:14 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-6c9c6412-952c-4f29-a244-822885d2f043 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=654474112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.654474112 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2383090823 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 260846576 ps |
| CPU time | 10.84 seconds |
| Started | May 12 12:28:06 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-f7f63727-81a5-4ab2-bc0c-5cc30afe09d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2383090823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2383090823 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3605470555 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 66072570382 ps |
| CPU time | 226.58 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:31:51 PM PDT 24 |
| Peak memory | 202884 kb |
| Host | smart-14f58fd7-d888-4090-8e0a-d703ff9d3416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3605470555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3605470555 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3404971579 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 101704574 ps |
| CPU time | 2.44 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:28:12 PM PDT 24 |
| Peak memory | 201840 kb |
| Host | smart-6141bc08-5076-4b95-a628-a16b2a6b181a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3404971579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3404971579 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2620246207 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1344550844 ps |
| CPU time | 10.71 seconds |
| Started | May 12 12:28:09 PM PDT 24 |
| Finished | May 12 12:28:21 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-59058012-fbac-42e8-a7fc-02667d29bb12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2620246207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2620246207 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.4192238249 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 316347049 ps |
| CPU time | 6.83 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:07 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-89453942-e9eb-4594-b528-01d3daf85525 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4192238249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4192238249 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.912974930 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4067065973 ps |
| CPU time | 14.15 seconds |
| Started | May 12 12:28:09 PM PDT 24 |
| Finished | May 12 12:28:25 PM PDT 24 |
| Peak memory | 201872 kb |
| Host | smart-f79522e5-a450-4d16-ad26-b50dee320e26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=912974930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.912974930 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2815931705 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 17771176868 ps |
| CPU time | 106.14 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:29:50 PM PDT 24 |
| Peak memory | 201856 kb |
| Host | smart-8bb45b8c-6a0a-4f6d-9c9e-2aabf97c8ee7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2815931705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2815931705 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2237880938 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 9193780 ps |
| CPU time | 1.02 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:28:06 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-38e678ef-668d-441e-8bce-4737790bf1dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237880938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2237880938 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1775476451 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 22590510 ps |
| CPU time | 2.01 seconds |
| Started | May 12 12:28:09 PM PDT 24 |
| Finished | May 12 12:28:13 PM PDT 24 |
| Peak memory | 201764 kb |
| Host | smart-a3398d81-0e6c-4c63-b3ed-35d3bb58e261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1775476451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1775476451 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.608144571 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 9966647 ps |
| CPU time | 1.02 seconds |
| Started | May 12 12:28:22 PM PDT 24 |
| Finished | May 12 12:28:24 PM PDT 24 |
| Peak memory | 201740 kb |
| Host | smart-44b7773a-e1d8-4d8b-81b5-e2a9a9efb11e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=608144571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.608144571 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.84831269 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1280984396 ps |
| CPU time | 7.06 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:28:11 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-ce818766-4720-451b-b41e-b57aa2d4ae7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=84831269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.84831269 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2891837494 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3201958939 ps |
| CPU time | 12.86 seconds |
| Started | May 12 12:28:24 PM PDT 24 |
| Finished | May 12 12:28:37 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-169f8c34-bb5f-4b5d-b211-3e467d64b9c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2891837494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2891837494 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3016445168 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 12304865 ps |
| CPU time | 1.31 seconds |
| Started | May 12 12:27:58 PM PDT 24 |
| Finished | May 12 12:28:02 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-891beda0-4ae1-4d0b-b567-84bedf002e77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016445168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3016445168 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.4024658032 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 24710934855 ps |
| CPU time | 56.14 seconds |
| Started | May 12 12:28:00 PM PDT 24 |
| Finished | May 12 12:28:59 PM PDT 24 |
| Peak memory | 202888 kb |
| Host | smart-16caf2c6-adf6-4535-bf0c-4dd1b1b7dc1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4024658032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4024658032 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3180420626 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5035535330 ps |
| CPU time | 84.02 seconds |
| Started | May 12 12:28:02 PM PDT 24 |
| Finished | May 12 12:29:28 PM PDT 24 |
| Peak memory | 203252 kb |
| Host | smart-f7c27ca1-f6bf-4e32-982e-c934fa99cccc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180420626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3180420626 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1322416545 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 172955703 ps |
| CPU time | 20.43 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:28:33 PM PDT 24 |
| Peak memory | 204056 kb |
| Host | smart-82e26150-9f09-4d52-9cb3-994a186b5005 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322416545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1322416545 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1853990068 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 896680313 ps |
| CPU time | 24.22 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:38 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-c10c80db-419c-4e07-899e-8967c9ef3fe0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1853990068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1853990068 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3151715819 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 997845612 ps |
| CPU time | 11.36 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:28 PM PDT 24 |
| Peak memory | 201772 kb |
| Host | smart-ac7dea84-badc-4913-9fa8-ceda929ce5ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151715819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3151715819 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.4294724727 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 515093442 ps |
| CPU time | 6.13 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:20 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-a65401a2-0832-4063-bb41-575ae7b35d66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4294724727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.4294724727 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.174365315 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 45897159119 ps |
| CPU time | 350.48 seconds |
| Started | May 12 12:28:03 PM PDT 24 |
| Finished | May 12 12:33:56 PM PDT 24 |
| Peak memory | 203936 kb |
| Host | smart-705a15d5-4d63-470c-904e-28b475a2e4ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=174365315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.174365315 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1973064987 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1858674560 ps |
| CPU time | 8.17 seconds |
| Started | May 12 12:28:29 PM PDT 24 |
| Finished | May 12 12:28:37 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-4331445a-6eac-46cb-bf6a-917e637c9056 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1973064987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1973064987 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2077931515 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 77017826 ps |
| CPU time | 6.99 seconds |
| Started | May 12 12:28:06 PM PDT 24 |
| Finished | May 12 12:28:14 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-6bc14fff-ace2-43ca-b30b-a26aebf9e45c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2077931515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2077931515 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.336576684 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 13716642 ps |
| CPU time | 1.25 seconds |
| Started | May 12 12:28:01 PM PDT 24 |
| Finished | May 12 12:28:05 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-ed181a77-96fd-4355-94b2-34f89b29edb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=336576684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.336576684 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1415437082 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 17822359877 ps |
| CPU time | 68.29 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:29:23 PM PDT 24 |
| Peak memory | 201804 kb |
| Host | smart-d6799aa9-c920-4111-9e6b-b6001c8bf44d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415437082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1415437082 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1506650727 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 27035554370 ps |
| CPU time | 87.09 seconds |
| Started | May 12 12:28:01 PM PDT 24 |
| Finished | May 12 12:29:30 PM PDT 24 |
| Peak memory | 201864 kb |
| Host | smart-b4a85364-13df-48f9-b512-abc1fe008e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1506650727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1506650727 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1937383225 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 240000693 ps |
| CPU time | 5.23 seconds |
| Started | May 12 12:28:10 PM PDT 24 |
| Finished | May 12 12:28:17 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-b3708870-87e0-488f-8d1e-82eb3d2dd89a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937383225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1937383225 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.3537001100 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 13291771 ps |
| CPU time | 1.63 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:15 PM PDT 24 |
| Peak memory | 201796 kb |
| Host | smart-d7941049-b1a8-4ccf-8b01-2e3eb185add6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3537001100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3537001100 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.950504532 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 111828967 ps |
| CPU time | 1.49 seconds |
| Started | May 12 12:28:06 PM PDT 24 |
| Finished | May 12 12:28:09 PM PDT 24 |
| Peak memory | 201824 kb |
| Host | smart-3702400c-e7ed-4933-82bf-a6b015bfa180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=950504532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.950504532 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.195956748 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4525245458 ps |
| CPU time | 11.87 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:24 PM PDT 24 |
| Peak memory | 201860 kb |
| Host | smart-816cea78-f58b-4427-be85-ff19a1ac3eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=195956748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.195956748 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2201245947 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 670695538 ps |
| CPU time | 5.33 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-b3e7cd8f-0651-4f5a-93f8-c01442e633b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2201245947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2201245947 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2695350269 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 8974532 ps |
| CPU time | 1.35 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:15 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-af024dcb-2f0c-4fe9-a491-6eab8db8669d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695350269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2695350269 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1130473102 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 165671445 ps |
| CPU time | 12.67 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:26 PM PDT 24 |
| Peak memory | 201780 kb |
| Host | smart-b987487b-fa7e-4dd4-8c02-50c80fbff11d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1130473102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1130473102 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.699110705 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 12640578927 ps |
| CPU time | 79.16 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:29:36 PM PDT 24 |
| Peak memory | 201896 kb |
| Host | smart-dcc68452-4ad5-41b5-a8bf-565421029e76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=699110705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.699110705 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2442635825 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 17020774843 ps |
| CPU time | 78.88 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:29:32 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-7c3377dd-64f9-4dd4-8f97-b93497511b42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2442635825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2442635825 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2669459454 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 425802239 ps |
| CPU time | 8.63 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:22 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-be693ec3-a207-4eb5-b204-18ffcef6aabd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2669459454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2669459454 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3531502005 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 163318005 ps |
| CPU time | 2.81 seconds |
| Started | May 12 12:28:20 PM PDT 24 |
| Finished | May 12 12:28:23 PM PDT 24 |
| Peak memory | 201784 kb |
| Host | smart-f8e0b189-6583-4eeb-b95a-b3274c405ec7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3531502005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3531502005 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.971854253 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 18168906361 ps |
| CPU time | 126.98 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:30:21 PM PDT 24 |
| Peak memory | 202912 kb |
| Host | smart-d224f32a-cb3f-4554-864e-6e392f45894c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=971854253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow _rsp.971854253 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1792552089 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 34019392 ps |
| CPU time | 1.8 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201792 kb |
| Host | smart-7448f857-0c80-45be-8230-895a6caa44ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1792552089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1792552089 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1745251738 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 234027538 ps |
| CPU time | 5.12 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:20 PM PDT 24 |
| Peak memory | 201808 kb |
| Host | smart-87749748-5cbb-4d36-9ad5-8910c34989a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1745251738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1745251738 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.818968840 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 25675849 ps |
| CPU time | 3.05 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:16 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-c3dc1823-0a05-4c4e-8291-28b0d5421f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=818968840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.818968840 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.507838342 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 11766293771 ps |
| CPU time | 23.19 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:28:37 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-5a7721b0-651b-485d-b28f-cf12e94b6d71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=507838342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.507838342 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2935019904 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 13088110049 ps |
| CPU time | 75.75 seconds |
| Started | May 12 12:28:04 PM PDT 24 |
| Finished | May 12 12:29:22 PM PDT 24 |
| Peak memory | 201844 kb |
| Host | smart-dd49c242-0d9f-4223-bcec-b94341b36a30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2935019904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2935019904 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3561401453 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 14347805 ps |
| CPU time | 1.15 seconds |
| Started | May 12 12:28:16 PM PDT 24 |
| Finished | May 12 12:28:18 PM PDT 24 |
| Peak memory | 201688 kb |
| Host | smart-e92bb1a8-bdb3-4672-8c4c-f83114b7d4c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561401453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3561401453 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3585141451 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 12543035 ps |
| CPU time | 1.26 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:15 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-bcbdedfc-11d5-47ff-8426-64aad5acc5db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3585141451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3585141451 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.1084478456 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 13665925 ps |
| CPU time | 1.24 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:28:14 PM PDT 24 |
| Peak memory | 201788 kb |
| Host | smart-ea36c9a6-75e7-4b76-afe6-b2f342c391d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1084478456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1084478456 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.375942254 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1415302222 ps |
| CPU time | 6.38 seconds |
| Started | May 12 12:28:15 PM PDT 24 |
| Finished | May 12 12:28:22 PM PDT 24 |
| Peak memory | 201832 kb |
| Host | smart-1e441c0f-e409-41fb-adbe-f3bc07a75d65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=375942254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.375942254 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1436715123 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2019292204 ps |
| CPU time | 12.57 seconds |
| Started | May 12 12:28:08 PM PDT 24 |
| Finished | May 12 12:28:21 PM PDT 24 |
| Peak memory | 201800 kb |
| Host | smart-fe817005-4592-4ea3-9e4a-a5ab3e15b18e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1436715123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1436715123 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.137822047 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 8613443 ps |
| CPU time | 1.02 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:15 PM PDT 24 |
| Peak memory | 201916 kb |
| Host | smart-d627deef-c7b1-4772-9f8b-c156ff7e5dd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137822047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.137822047 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.239759438 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1807685508 ps |
| CPU time | 20.57 seconds |
| Started | May 12 12:28:18 PM PDT 24 |
| Finished | May 12 12:28:39 PM PDT 24 |
| Peak memory | 202840 kb |
| Host | smart-10f37344-264d-45c3-92dd-6de09182f061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=239759438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.239759438 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.742131321 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5537736712 ps |
| CPU time | 66.01 seconds |
| Started | May 12 12:28:11 PM PDT 24 |
| Finished | May 12 12:29:19 PM PDT 24 |
| Peak memory | 203916 kb |
| Host | smart-8cdfd1fd-09a4-42d0-b3dc-fc87142b3945 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742131321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.742131321 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.928463499 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 718591947 ps |
| CPU time | 72.61 seconds |
| Started | May 12 12:28:05 PM PDT 24 |
| Finished | May 12 12:29:20 PM PDT 24 |
| Peak memory | 203948 kb |
| Host | smart-02806f43-5844-4bfc-9370-2ad11f35a5df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=928463499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.928463499 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.128000669 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 791004293 ps |
| CPU time | 95.89 seconds |
| Started | May 12 12:28:13 PM PDT 24 |
| Finished | May 12 12:29:50 PM PDT 24 |
| Peak memory | 206492 kb |
| Host | smart-7bbdb0c3-bd5b-49ff-b70e-54459605e741 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=128000669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.128000669 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.839993589 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 994831299 ps |
| CPU time | 11.72 seconds |
| Started | May 12 12:28:12 PM PDT 24 |
| Finished | May 12 12:28:25 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-ea1699d6-e727-42d4-8a7a-d60581dd7ca4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=839993589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.839993589 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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