Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	409	1			T2	1		T22	1		T40	8
all_values[1]	403	1			T20	1		T38	1		T140	1
all_values[2]	405	1			T3	1		T20	1		T140	1
all_values[3]	440	1			T20	1		T38	1		T40	5
all_values[4]	394	1			T19	1		T38	1		T40	5
all_values[5]	431	1			T2	1		T3	1		T19	1
all_values[6]	426	1			T2	2		T149	1		T40	4
all_values[7]	421	1			T3	1		T38	1		T40	2
all_values[8]	407	1			T20	1		T38	1		T40	5
all_values[9]	405	1			T3	1		T19	1		T20	1
all_values[10]	416	1			T3	1		T38	1		T140	1
all_values[11]	397	1			T2	1		T22	1		T40	4
all_values[12]	416	1			T2	1		T38	1		T140	1
all_values[13]	420	1			T3	1		T19	1		T22	1
all_values[14]	405	1			T40	6		T87	3		T43	5
all_values[15]	434	1			T38	1		T40	6		T87	3
all_values[16]	459	1			T19	2		T149	1		T40	7
all_values[17]	370	1			T19	1		T22	2		T40	7
all_values[18]	401	1			T2	1		T38	1		T40	4
all_values[19]	420	1			T19	1		T20	2		T149	1
all_values[20]	421	1			T3	1		T20	1		T38	2
all_values[21]	430	1			T20	2		T40	7		T87	3
all_values[22]	434	1			T19	1		T20	1		T40	4
all_values[23]	403	1			T19	2		T40	5		T87	5
all_values[24]	411	1			T19	1		T149	1		T40	7
all_values[25]	419	1			T2	1		T22	1		T40	6
all_values[26]	403	1			T3	1		T20	1		T38	1