Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 436 1 T1 1 T10 2 T12 5
all_values[1] 433 1 T1 2 T10 3 T12 8
all_values[2] 412 1 T1 1 T12 5 T25 4
all_values[3] 415 1 T1 2 T10 3 T12 1
all_values[4] 440 1 T1 1 T12 1 T25 3
all_values[5] 446 1 T1 2 T10 1 T12 5
all_values[6] 451 1 T1 2 T10 2 T12 3
all_values[7] 454 1 T1 1 T10 1 T12 7
all_values[8] 459 1 T1 1 T10 1 T12 5
all_values[9] 442 1 T10 2 T12 6 T25 2
all_values[10] 491 1 T1 1 T10 1 T12 10
all_values[11] 446 1 T1 1 T10 1 T12 5
all_values[12] 442 1 T1 2 T10 1 T12 2
all_values[13] 453 1 T1 3 T10 1 T12 7
all_values[14] 460 1 T1 2 T12 4 T25 2
all_values[15] 439 1 T1 1 T12 3 T25 1
all_values[16] 433 1 T1 2 T10 1 T12 4
all_values[17] 420 1 T1 1 T10 2 T12 6
all_values[18] 416 1 T12 7 T41 6 T11 1
all_values[19] 462 1 T1 1 T10 1 T12 4
all_values[20] 438 1 T1 3 T10 6 T12 2
all_values[21] 456 1 T1 2 T10 1 T12 2
all_values[22] 466 1 T1 3 T10 1 T12 9
all_values[23] 458 1 T1 2 T10 1 T12 4
all_values[24] 446 1 T1 1 T10 4 T12 3
all_values[25] 442 1 T1 3 T12 4 T25 5
all_values[26] 429 1 T10 3 T12 2 T25 3

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