| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.30 | 100.00 | 95.80 | 100.00 | 100.00 | 100.00 | 100.00 |
| T759 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3298810136 | May 21 02:33:49 PM PDT 24 | May 21 02:34:15 PM PDT 24 | 2353207361 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1432226215 | May 21 02:37:17 PM PDT 24 | May 21 02:37:43 PM PDT 24 | 676988444 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2506063531 | May 21 02:35:14 PM PDT 24 | May 21 02:35:36 PM PDT 24 | 93220839 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3342308072 | May 21 02:35:06 PM PDT 24 | May 21 02:35:29 PM PDT 24 | 37368544 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.335624040 | May 21 02:33:44 PM PDT 24 | May 21 02:34:55 PM PDT 24 | 9295005376 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1515764041 | May 21 02:36:38 PM PDT 24 | May 21 02:38:22 PM PDT 24 | 482423055 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1708890080 | May 21 02:35:13 PM PDT 24 | May 21 02:35:58 PM PDT 24 | 10983576933 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.203646939 | May 21 02:36:36 PM PDT 24 | May 21 02:37:50 PM PDT 24 | 532504597 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/36.xbar_same_source.1336888082 | May 21 02:36:19 PM PDT 24 | May 21 02:36:44 PM PDT 24 | 1091280398 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2629090411 | May 21 02:34:16 PM PDT 24 | May 21 02:34:39 PM PDT 24 | 1001984627 ps | ||
| T116 | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1433357386 | May 21 02:33:13 PM PDT 24 | May 21 02:34:35 PM PDT 24 | 9031779535 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2307093336 | May 21 02:35:25 PM PDT 24 | May 21 02:35:56 PM PDT 24 | 2326869517 ps | ||
| T35 | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2289145370 | May 21 02:37:25 PM PDT 24 | May 21 02:37:56 PM PDT 24 | 431079632 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1968180535 | May 21 02:34:35 PM PDT 24 | May 21 02:34:51 PM PDT 24 | 242015570 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1923580408 | May 21 02:36:53 PM PDT 24 | May 21 02:37:13 PM PDT 24 | 51054160 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1179249607 | May 21 02:33:26 PM PDT 24 | May 21 02:33:44 PM PDT 24 | 27619973 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.452150131 | May 21 02:34:28 PM PDT 24 | May 21 02:34:45 PM PDT 24 | 48508917 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3933149813 | May 21 02:33:03 PM PDT 24 | May 21 02:33:25 PM PDT 24 | 27284336 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3524598645 | May 21 02:36:03 PM PDT 24 | May 21 02:36:25 PM PDT 24 | 618255566 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2801359929 | May 21 02:33:24 PM PDT 24 | May 21 02:33:47 PM PDT 24 | 119799715 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.397959563 | May 21 02:35:37 PM PDT 24 | May 21 02:37:23 PM PDT 24 | 52067901102 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.898383795 | May 21 02:33:26 PM PDT 24 | May 21 02:33:48 PM PDT 24 | 4565210392 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/23.xbar_random.1561874276 | May 21 02:35:01 PM PDT 24 | May 21 02:35:33 PM PDT 24 | 847194062 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1142036459 | May 21 02:34:58 PM PDT 24 | May 21 02:35:15 PM PDT 24 | 27372587 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1037998081 | May 21 02:36:22 PM PDT 24 | May 21 02:37:09 PM PDT 24 | 442124043 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2399928689 | May 21 02:33:13 PM PDT 24 | May 21 02:33:39 PM PDT 24 | 537428420 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4243937227 | May 21 02:36:53 PM PDT 24 | May 21 02:37:11 PM PDT 24 | 191462801 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.357757447 | May 21 02:32:53 PM PDT 24 | May 21 02:36:11 PM PDT 24 | 281229539783 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.632016685 | May 21 02:33:25 PM PDT 24 | May 21 02:33:49 PM PDT 24 | 2078524147 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/34.xbar_error_random.929592428 | May 21 02:36:08 PM PDT 24 | May 21 02:36:33 PM PDT 24 | 2241171110 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.518939222 | May 21 02:34:05 PM PDT 24 | May 21 02:35:19 PM PDT 24 | 3782364119 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.151413838 | May 21 02:35:19 PM PDT 24 | May 21 02:37:13 PM PDT 24 | 4121244608 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/22.xbar_same_source.674571515 | May 21 02:35:02 PM PDT 24 | May 21 02:35:22 PM PDT 24 | 21244279 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/47.xbar_smoke.885249786 | May 21 02:37:16 PM PDT 24 | May 21 02:37:37 PM PDT 24 | 9150776 ps | ||
| T11 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2637436317 | May 21 02:35:15 PM PDT 24 | May 21 02:37:25 PM PDT 24 | 43910042654 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3144857370 | May 21 02:36:07 PM PDT 24 | May 21 02:36:21 PM PDT 24 | 37431874 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2726482774 | May 21 02:36:57 PM PDT 24 | May 21 02:37:14 PM PDT 24 | 26916155 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/45.xbar_error_random.56256425 | May 21 02:37:09 PM PDT 24 | May 21 02:37:40 PM PDT 24 | 2484526958 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1267441885 | May 21 02:34:42 PM PDT 24 | May 21 02:35:01 PM PDT 24 | 1566648306 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4015570217 | May 21 02:36:50 PM PDT 24 | May 21 02:37:10 PM PDT 24 | 1645430857 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2059561551 | May 21 02:34:23 PM PDT 24 | May 21 02:34:51 PM PDT 24 | 2156624651 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3445741276 | May 21 02:36:52 PM PDT 24 | May 21 02:37:26 PM PDT 24 | 114163586 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3075852108 | May 21 02:33:11 PM PDT 24 | May 21 02:33:44 PM PDT 24 | 126838135 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1023114819 | May 21 02:34:10 PM PDT 24 | May 21 02:34:38 PM PDT 24 | 11726195451 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/27.xbar_random.1096670712 | May 21 02:35:21 PM PDT 24 | May 21 02:36:01 PM PDT 24 | 5350000747 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4091888495 | May 21 02:33:12 PM PDT 24 | May 21 02:33:46 PM PDT 24 | 95980592 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2962483217 | May 21 02:34:23 PM PDT 24 | May 21 02:34:42 PM PDT 24 | 2030761179 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3328548860 | May 21 02:36:14 PM PDT 24 | May 21 02:36:37 PM PDT 24 | 10394626911 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1516893677 | May 21 02:35:08 PM PDT 24 | May 21 02:36:47 PM PDT 24 | 2333723771 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1558757798 | May 21 02:33:10 PM PDT 24 | May 21 02:33:30 PM PDT 24 | 10854885 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.697764620 | May 21 02:37:33 PM PDT 24 | May 21 02:38:24 PM PDT 24 | 466264086 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2101076960 | May 21 02:36:21 PM PDT 24 | May 21 02:37:09 PM PDT 24 | 438477956 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2924840090 | May 21 02:36:56 PM PDT 24 | May 21 02:37:20 PM PDT 24 | 2686242963 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4105980342 | May 21 02:34:01 PM PDT 24 | May 21 02:34:23 PM PDT 24 | 1304636964 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.771264241 | May 21 02:36:38 PM PDT 24 | May 21 02:37:03 PM PDT 24 | 1527383836 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2668714456 | May 21 02:35:31 PM PDT 24 | May 21 02:35:57 PM PDT 24 | 341280745 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/28.xbar_error_random.4203668310 | May 21 02:35:27 PM PDT 24 | May 21 02:35:55 PM PDT 24 | 757214264 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2533486410 | May 21 02:35:54 PM PDT 24 | May 21 02:36:10 PM PDT 24 | 10870553 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.784210143 | May 21 02:34:03 PM PDT 24 | May 21 02:34:21 PM PDT 24 | 76121594 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2990838907 | May 21 02:33:17 PM PDT 24 | May 21 02:36:35 PM PDT 24 | 73103303381 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1111532776 | May 21 02:34:56 PM PDT 24 | May 21 02:35:59 PM PDT 24 | 329590812 ps | ||
| T109 | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2376711000 | May 21 02:36:53 PM PDT 24 | May 21 02:37:14 PM PDT 24 | 301278814 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.836677287 | May 21 02:36:59 PM PDT 24 | May 21 02:37:15 PM PDT 24 | 10759446 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.23709922 | May 21 02:33:24 PM PDT 24 | May 21 02:33:47 PM PDT 24 | 57202026 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2621778290 | May 21 02:36:11 PM PDT 24 | May 21 02:36:37 PM PDT 24 | 16596106595 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1596393254 | May 21 02:37:04 PM PDT 24 | May 21 02:37:28 PM PDT 24 | 109969488 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.554164947 | May 21 02:33:14 PM PDT 24 | May 21 02:33:42 PM PDT 24 | 4542238863 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.5928556 | May 21 02:35:19 PM PDT 24 | May 21 02:35:49 PM PDT 24 | 476290612 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/30.xbar_random.655576590 | May 21 02:35:41 PM PDT 24 | May 21 02:36:08 PM PDT 24 | 121884418 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.20261865 | May 21 02:37:02 PM PDT 24 | May 21 02:37:19 PM PDT 24 | 9442825 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/13.xbar_same_source.4271627372 | May 21 02:34:05 PM PDT 24 | May 21 02:34:22 PM PDT 24 | 17451935 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4043740835 | May 21 02:37:09 PM PDT 24 | May 21 02:37:38 PM PDT 24 | 17308645938 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.194735563 | May 21 02:36:21 PM PDT 24 | May 21 02:36:40 PM PDT 24 | 56109437 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1171993360 | May 21 02:35:13 PM PDT 24 | May 21 02:35:35 PM PDT 24 | 10700130 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.518370979 | May 21 02:33:17 PM PDT 24 | May 21 02:33:49 PM PDT 24 | 1435376497 ps | ||
| T189 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1562029980 | May 21 02:35:20 PM PDT 24 | May 21 02:36:01 PM PDT 24 | 2762605179 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2510825692 | May 21 02:34:03 PM PDT 24 | May 21 02:34:25 PM PDT 24 | 2552592849 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1277418095 | May 21 02:35:19 PM PDT 24 | May 21 02:35:42 PM PDT 24 | 19509190 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/19.xbar_smoke.1497561879 | May 21 02:34:27 PM PDT 24 | May 21 02:34:42 PM PDT 24 | 150806524 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1586644457 | May 21 02:36:57 PM PDT 24 | May 21 02:37:13 PM PDT 24 | 10922166 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2869990444 | May 21 02:37:36 PM PDT 24 | May 21 02:38:41 PM PDT 24 | 4103489586 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1907045947 | May 21 02:35:57 PM PDT 24 | May 21 02:36:42 PM PDT 24 | 4788600851 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1531053207 | May 21 02:35:19 PM PDT 24 | May 21 02:37:07 PM PDT 24 | 20925709002 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3418514433 | May 21 02:33:28 PM PDT 24 | May 21 02:33:51 PM PDT 24 | 7461277481 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.21037616 | May 21 02:34:21 PM PDT 24 | May 21 02:34:41 PM PDT 24 | 50320334 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2215476126 | May 21 02:33:28 PM PDT 24 | May 21 02:36:44 PM PDT 24 | 24911504930 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.643950499 | May 21 02:33:26 PM PDT 24 | May 21 02:35:25 PM PDT 24 | 20960133372 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4216005998 | May 21 02:36:36 PM PDT 24 | May 21 02:37:18 PM PDT 24 | 27835746481 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.4054551710 | May 21 02:34:23 PM PDT 24 | May 21 02:35:26 PM PDT 24 | 383074574 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4128012123 | May 21 02:33:29 PM PDT 24 | May 21 02:35:11 PM PDT 24 | 8618660189 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2944861792 | May 21 02:34:54 PM PDT 24 | May 21 02:35:50 PM PDT 24 | 1612811947 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2949788637 | May 21 02:37:23 PM PDT 24 | May 21 02:37:43 PM PDT 24 | 10840608 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2024998005 | May 21 02:32:50 PM PDT 24 | May 21 02:34:38 PM PDT 24 | 47433779141 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3334501071 | May 21 02:33:12 PM PDT 24 | May 21 02:33:43 PM PDT 24 | 182725783 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.991594379 | May 21 02:35:44 PM PDT 24 | May 21 02:36:14 PM PDT 24 | 2252889372 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1103285169 | May 21 02:37:00 PM PDT 24 | May 21 02:37:19 PM PDT 24 | 1768797804 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3567481662 | May 21 02:34:15 PM PDT 24 | May 21 02:34:30 PM PDT 24 | 8786122 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2075032269 | May 21 02:34:25 PM PDT 24 | May 21 02:34:39 PM PDT 24 | 9713165 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/21.xbar_smoke.1149993773 | May 21 02:34:49 PM PDT 24 | May 21 02:35:02 PM PDT 24 | 8779702 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1143696925 | May 21 02:36:09 PM PDT 24 | May 21 02:36:24 PM PDT 24 | 74568667 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.208480057 | May 21 02:33:02 PM PDT 24 | May 21 02:34:02 PM PDT 24 | 254993131 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3957806698 | May 21 02:34:31 PM PDT 24 | May 21 02:34:50 PM PDT 24 | 9761754652 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1055722326 | May 21 02:33:02 PM PDT 24 | May 21 02:33:25 PM PDT 24 | 142792743 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.718715711 | May 21 02:35:01 PM PDT 24 | May 21 02:37:24 PM PDT 24 | 1651947741 ps | ||
| T120 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.4139547443 | May 21 02:34:11 PM PDT 24 | May 21 02:34:31 PM PDT 24 | 251655852 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.742158010 | May 21 02:35:19 PM PDT 24 | May 21 02:38:15 PM PDT 24 | 8566837272 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3511342810 | May 21 02:34:09 PM PDT 24 | May 21 02:34:27 PM PDT 24 | 67183392 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3892449553 | May 21 02:33:39 PM PDT 24 | May 21 02:34:02 PM PDT 24 | 64543245 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2951696792 | May 21 02:33:39 PM PDT 24 | May 21 02:34:30 PM PDT 24 | 276718654 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3880456116 | May 21 02:35:42 PM PDT 24 | May 21 02:36:02 PM PDT 24 | 18768985 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3359588346 | May 21 02:35:08 PM PDT 24 | May 21 02:37:20 PM PDT 24 | 42454667391 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.628616810 | May 21 02:33:16 PM PDT 24 | May 21 02:33:47 PM PDT 24 | 7158638326 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3008317580 | May 21 02:34:24 PM PDT 24 | May 21 02:34:47 PM PDT 24 | 1836787751 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4219258660 | May 21 02:36:14 PM PDT 24 | May 21 02:36:29 PM PDT 24 | 8307266 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/5.xbar_same_source.171102936 | May 21 02:33:11 PM PDT 24 | May 21 02:33:39 PM PDT 24 | 773152622 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.729616933 | May 21 02:36:41 PM PDT 24 | May 21 02:37:58 PM PDT 24 | 11312474407 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3142791776 | May 21 02:35:13 PM PDT 24 | May 21 02:36:11 PM PDT 24 | 2661830516 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1707835640 | May 21 02:33:02 PM PDT 24 | May 21 02:33:51 PM PDT 24 | 4811388722 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3269244120 | May 21 02:33:09 PM PDT 24 | May 21 02:33:29 PM PDT 24 | 327678478 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3931411996 | May 21 02:37:16 PM PDT 24 | May 21 02:38:00 PM PDT 24 | 5966309409 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/40.xbar_random.3555926213 | May 21 02:36:40 PM PDT 24 | May 21 02:37:13 PM PDT 24 | 883388123 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2277123671 | May 21 02:37:23 PM PDT 24 | May 21 02:38:09 PM PDT 24 | 4700582500 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.769481913 | May 21 02:33:39 PM PDT 24 | May 21 02:34:31 PM PDT 24 | 21384314605 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1893426279 | May 21 02:35:56 PM PDT 24 | May 21 02:36:14 PM PDT 24 | 110608715 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3985811487 | May 21 02:33:39 PM PDT 24 | May 21 02:38:50 PM PDT 24 | 129975463103 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1184043719 | May 21 02:36:31 PM PDT 24 | May 21 02:36:47 PM PDT 24 | 31990407 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2709224873 | May 21 02:35:29 PM PDT 24 | May 21 02:35:53 PM PDT 24 | 66322039 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3996937317 | May 21 02:35:26 PM PDT 24 | May 21 02:37:53 PM PDT 24 | 86138542344 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/23.xbar_smoke.4291688615 | May 21 02:35:03 PM PDT 24 | May 21 02:35:23 PM PDT 24 | 81094891 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2152681604 | May 21 02:33:11 PM PDT 24 | May 21 02:34:27 PM PDT 24 | 16104418877 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1996557062 | May 21 02:33:58 PM PDT 24 | May 21 02:34:15 PM PDT 24 | 68909167 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3029397218 | May 21 02:36:28 PM PDT 24 | May 21 02:36:49 PM PDT 24 | 43277457 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.4292373801 | May 21 02:35:37 PM PDT 24 | May 21 02:35:59 PM PDT 24 | 8783525 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/15.xbar_random.4286067743 | May 21 02:34:10 PM PDT 24 | May 21 02:34:31 PM PDT 24 | 445813249 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3617600497 | May 21 02:34:15 PM PDT 24 | May 21 02:35:02 PM PDT 24 | 390836914 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4249975756 | May 21 02:36:52 PM PDT 24 | May 21 02:39:09 PM PDT 24 | 36830590019 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1093332942 | May 21 02:33:26 PM PDT 24 | May 21 02:34:19 PM PDT 24 | 529211315 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3148884618 | May 21 02:36:05 PM PDT 24 | May 21 02:37:29 PM PDT 24 | 1678594895 ps | ||
| T110 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3510411462 | May 21 02:37:16 PM PDT 24 | May 21 02:37:52 PM PDT 24 | 728363882 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2426055533 | May 21 02:33:07 PM PDT 24 | May 21 02:33:26 PM PDT 24 | 10820822 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/38.xbar_random.454892652 | May 21 02:36:37 PM PDT 24 | May 21 02:37:03 PM PDT 24 | 276938051 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3177568398 | May 21 02:34:19 PM PDT 24 | May 21 02:35:20 PM PDT 24 | 1337626541 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.734794837 | May 21 02:37:04 PM PDT 24 | May 21 02:37:25 PM PDT 24 | 53462923 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2622287369 | May 21 02:35:56 PM PDT 24 | May 21 02:36:19 PM PDT 24 | 9174047501 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1279939688 | May 21 02:36:15 PM PDT 24 | May 21 02:36:42 PM PDT 24 | 3556185805 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.490995124 | May 21 02:33:01 PM PDT 24 | May 21 02:33:40 PM PDT 24 | 2602784436 ps | ||
| T216 | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1409977546 | May 21 02:35:01 PM PDT 24 | May 21 02:35:24 PM PDT 24 | 476160877 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3507186603 | May 21 02:36:18 PM PDT 24 | May 21 02:36:35 PM PDT 24 | 1034869991 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1554132553 | May 21 02:37:27 PM PDT 24 | May 21 02:37:51 PM PDT 24 | 45668697 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2552558392 | May 21 02:33:11 PM PDT 24 | May 21 02:33:31 PM PDT 24 | 10741980 ps |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4128410197 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6893439564 ps |
| CPU time | 46.11 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:38:06 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-96e558b5-2357-4902-a2e2-c208b7b82239 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4128410197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4128410197 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2759382099 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 287454685874 ps |
| CPU time | 325.51 seconds |
| Started | May 21 02:34:42 PM PDT 24 |
| Finished | May 21 02:40:18 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-aa7f293a-66aa-4ff8-b0df-013855b1d289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2759382099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2759382099 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.89093811 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 61874415049 ps |
| CPU time | 349.92 seconds |
| Started | May 21 02:37:06 PM PDT 24 |
| Finished | May 21 02:43:14 PM PDT 24 |
| Peak memory | 204004 kb |
| Host | smart-e0acf645-0b66-48f8-acaf-cbde34fc3caf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=89093811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow _rsp.89093811 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1765623103 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 86673658020 ps |
| CPU time | 174.29 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:39:44 PM PDT 24 |
| Peak memory | 203284 kb |
| Host | smart-54532130-5dc8-4615-ae57-3232aa6c889c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1765623103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1765623103 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1038628500 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 332778220 ps |
| CPU time | 36.43 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:43 PM PDT 24 |
| Peak memory | 203656 kb |
| Host | smart-ace966b8-9599-4e3a-abf5-38be9781bbbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1038628500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1038628500 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.804551603 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 42920331998 ps |
| CPU time | 331.44 seconds |
| Started | May 21 02:36:11 PM PDT 24 |
| Finished | May 21 02:41:55 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-05d7300a-ec06-45ae-a408-7be704f7fe5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=804551603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.804551603 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.603367094 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4043499927 ps |
| CPU time | 107.02 seconds |
| Started | May 21 02:36:50 PM PDT 24 |
| Finished | May 21 02:38:52 PM PDT 24 |
| Peak memory | 204788 kb |
| Host | smart-1a0f92bd-1b86-4ae5-9f17-80ce521aa18d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=603367094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.603367094 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2075264140 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 127542615721 ps |
| CPU time | 275.07 seconds |
| Started | May 21 02:34:36 PM PDT 24 |
| Finished | May 21 02:39:23 PM PDT 24 |
| Peak memory | 203296 kb |
| Host | smart-e5e754ec-9d23-45a3-9b12-6fb7e0c8bc59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2075264140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2075264140 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3231560812 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5303420351 ps |
| CPU time | 136.56 seconds |
| Started | May 21 02:34:41 PM PDT 24 |
| Finished | May 21 02:37:09 PM PDT 24 |
| Peak memory | 205228 kb |
| Host | smart-cb4932fa-1d7d-43c2-a294-eaac85bfa717 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231560812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3231560812 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1958445699 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 36331499349 ps |
| CPU time | 71.2 seconds |
| Started | May 21 02:33:01 PM PDT 24 |
| Finished | May 21 02:34:32 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-8f5e3f09-4929-4d1c-9a35-d04838211980 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958445699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1958445699 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.298204060 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 898013512 ps |
| CPU time | 130.02 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:37:51 PM PDT 24 |
| Peak memory | 206136 kb |
| Host | smart-e6b0a9af-00ee-4d8b-8f00-0ca2572412fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=298204060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.298204060 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3829977421 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 63669184247 ps |
| CPU time | 211.74 seconds |
| Started | May 21 02:33:24 PM PDT 24 |
| Finished | May 21 02:37:12 PM PDT 24 |
| Peak memory | 203308 kb |
| Host | smart-d10fb56e-1000-43a9-b78f-be35c176083f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3829977421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3829977421 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2425266493 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 55583723628 ps |
| CPU time | 283.98 seconds |
| Started | May 21 02:32:57 PM PDT 24 |
| Finished | May 21 02:38:00 PM PDT 24 |
| Peak memory | 205340 kb |
| Host | smart-3a84a5f5-3c86-495d-ba84-4437d82881ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2425266493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2425266493 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.481307478 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 820978973 ps |
| CPU time | 15.12 seconds |
| Started | May 21 02:37:09 PM PDT 24 |
| Finished | May 21 02:37:42 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-bce0b878-42b2-47dd-abdb-579bc7b619d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=481307478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.481307478 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3165832427 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4878530757 ps |
| CPU time | 115.7 seconds |
| Started | May 21 02:33:21 PM PDT 24 |
| Finished | May 21 02:35:33 PM PDT 24 |
| Peak memory | 207636 kb |
| Host | smart-6e1444a2-765b-4055-9f99-19bfae4ec0c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3165832427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.3165832427 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1561713884 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 61327340237 ps |
| CPU time | 298.28 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:40:25 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-28ea880b-3084-4b55-9dae-be998e1b654c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1561713884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.1561713884 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.4087873275 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8822356545 ps |
| CPU time | 204.23 seconds |
| Started | May 21 02:33:18 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 207828 kb |
| Host | smart-bf6457ad-bfb9-4761-a51d-19522387a72b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4087873275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.4087873275 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.723588566 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 7816892326 ps |
| CPU time | 47.98 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:38:30 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-b0457ec6-98d7-4ef1-a5a5-aaa5044072d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=723588566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.723588566 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.918427228 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 746082408 ps |
| CPU time | 61.97 seconds |
| Started | May 21 02:36:07 PM PDT 24 |
| Finished | May 21 02:37:23 PM PDT 24 |
| Peak memory | 204696 kb |
| Host | smart-cc91d891-92c8-4632-8318-474768346f28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=918427228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res et_error.918427228 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3392220973 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 5411853152 ps |
| CPU time | 16.09 seconds |
| Started | May 21 02:34:00 PM PDT 24 |
| Finished | May 21 02:34:31 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-fdc93296-7dab-437f-842d-73633491bd40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3392220973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3392220973 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3854071355 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 932794293 ps |
| CPU time | 112.35 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:38:59 PM PDT 24 |
| Peak memory | 206392 kb |
| Host | smart-c65a19d4-62fd-4ff9-bdcd-ed5bbed68235 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3854071355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3854071355 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2445121789 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 37210721506 ps |
| CPU time | 214.21 seconds |
| Started | May 21 02:33:04 PM PDT 24 |
| Finished | May 21 02:36:57 PM PDT 24 |
| Peak memory | 203648 kb |
| Host | smart-d47bdfde-ed70-474d-9e82-f5035c4f4fab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2445121789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2445121789 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3844986866 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 170089439151 ps |
| CPU time | 312.42 seconds |
| Started | May 21 02:33:57 PM PDT 24 |
| Finished | May 21 02:39:25 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-25a3d738-1d88-4702-98bb-2c9f9997054b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3844986866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.3844986866 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3448295704 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 649947663 ps |
| CPU time | 61.63 seconds |
| Started | May 21 02:34:49 PM PDT 24 |
| Finished | May 21 02:36:02 PM PDT 24 |
| Peak memory | 205044 kb |
| Host | smart-7cfff9d4-33b9-4923-bda0-e151f188fbfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3448295704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.3448295704 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2093292036 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 25656391 ps |
| CPU time | 2.05 seconds |
| Started | May 21 02:32:53 PM PDT 24 |
| Finished | May 21 02:33:14 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-13c97727-b208-4929-b948-8fb272239e09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093292036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2093292036 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2024998005 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 47433779141 ps |
| CPU time | 90.79 seconds |
| Started | May 21 02:32:50 PM PDT 24 |
| Finished | May 21 02:34:38 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-767360b3-c1d5-4f27-ba7e-c9c2f5b26142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2024998005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2024998005 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.188593320 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 57550251 ps |
| CPU time | 5.61 seconds |
| Started | May 21 02:32:57 PM PDT 24 |
| Finished | May 21 02:33:22 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-5f1b87a4-933e-4edb-bb24-e244a0ae93df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=188593320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.188593320 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.1373992766 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 13248469 ps |
| CPU time | 1.07 seconds |
| Started | May 21 02:32:53 PM PDT 24 |
| Finished | May 21 02:33:13 PM PDT 24 |
| Peak memory | 201756 kb |
| Host | smart-4cb4dfee-39e5-45a1-84c3-afce70d93498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1373992766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1373992766 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.458218153 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 826935540 ps |
| CPU time | 12.9 seconds |
| Started | May 21 02:32:53 PM PDT 24 |
| Finished | May 21 02:33:24 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-7ffd9d9f-5f72-4d38-bec6-2073a8f0b904 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=458218153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.458218153 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.357757447 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 281229539783 ps |
| CPU time | 179.18 seconds |
| Started | May 21 02:32:53 PM PDT 24 |
| Finished | May 21 02:36:11 PM PDT 24 |
| Peak memory | 201776 kb |
| Host | smart-afd0567c-7dad-4b38-8ef5-e97d55df2937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=357757447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.357757447 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3418725750 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 64439498384 ps |
| CPU time | 117.13 seconds |
| Started | May 21 02:32:52 PM PDT 24 |
| Finished | May 21 02:35:08 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-ee161626-2bb5-4e83-a1e2-881976a28997 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3418725750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3418725750 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.4239790354 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 61892760 ps |
| CPU time | 5.59 seconds |
| Started | May 21 02:32:52 PM PDT 24 |
| Finished | May 21 02:33:16 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-b3524472-9e5e-45c9-9f4c-dbd6b7b70697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239790354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.4239790354 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3636142673 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 59722797 ps |
| CPU time | 2.84 seconds |
| Started | May 21 02:32:55 PM PDT 24 |
| Finished | May 21 02:33:17 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-82982e74-a54c-4479-b303-a384e76131e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3636142673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3636142673 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.1063024012 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 122701373 ps |
| CPU time | 1.42 seconds |
| Started | May 21 02:32:52 PM PDT 24 |
| Finished | May 21 02:33:12 PM PDT 24 |
| Peak memory | 202384 kb |
| Host | smart-18dc0bac-0308-46cc-8e81-bfc730c7dc41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1063024012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1063024012 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3887180224 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2154018785 ps |
| CPU time | 7.75 seconds |
| Started | May 21 02:32:52 PM PDT 24 |
| Finished | May 21 02:33:19 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-889fd7bd-f1ae-4d7d-8c64-39a28c9ad880 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887180224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3887180224 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.389274639 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1207596968 ps |
| CPU time | 7.95 seconds |
| Started | May 21 02:32:51 PM PDT 24 |
| Finished | May 21 02:33:18 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-a4bf11ee-b3a0-4739-8203-901b665ad17b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=389274639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.389274639 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2478577164 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 11551306 ps |
| CPU time | 1.04 seconds |
| Started | May 21 02:32:56 PM PDT 24 |
| Finished | May 21 02:33:16 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-611c3d22-861f-47aa-9ae2-3a76d29f87e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478577164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2478577164 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3765073403 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2706594787 ps |
| CPU time | 41.86 seconds |
| Started | May 21 02:32:59 PM PDT 24 |
| Finished | May 21 02:34:00 PM PDT 24 |
| Peak memory | 202352 kb |
| Host | smart-9b5fa800-6a35-446f-8d84-990b4265e856 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3765073403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3765073403 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1286833347 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1386250265 ps |
| CPU time | 34.05 seconds |
| Started | May 21 02:32:59 PM PDT 24 |
| Finished | May 21 02:33:52 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-49b45ca1-a6c2-48c9-973f-68c6905c05ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1286833347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1286833347 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1788223801 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 155656085 ps |
| CPU time | 15.85 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:33 PM PDT 24 |
| Peak memory | 204272 kb |
| Host | smart-2b89d6fb-8a31-478a-a59e-5717ac661347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1788223801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1788223801 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.177330575 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 384613542 ps |
| CPU time | 82.49 seconds |
| Started | May 21 02:33:01 PM PDT 24 |
| Finished | May 21 02:34:43 PM PDT 24 |
| Peak memory | 206384 kb |
| Host | smart-3b3f0bd7-6322-4abb-99f6-209b36bb65cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177330575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.177330575 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3545525024 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 161891469 ps |
| CPU time | 2.11 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:19 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-00ca41a4-7f5d-446b-bb2b-223d39e408a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3545525024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3545525024 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.490995124 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2602784436 ps |
| CPU time | 19.47 seconds |
| Started | May 21 02:33:01 PM PDT 24 |
| Finished | May 21 02:33:40 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-1f4c138d-feeb-4c8d-b891-a9d008a0ba9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=490995124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.490995124 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.572361954 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 79760614 ps |
| CPU time | 6.19 seconds |
| Started | May 21 02:32:59 PM PDT 24 |
| Finished | May 21 02:33:24 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-2ff71405-5e28-4c8f-9246-316f7c18d14f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572361954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.572361954 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.1150344432 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 61917289 ps |
| CPU time | 5.52 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:23 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-aecd4d65-e3ce-4f55-babb-ff65e332268f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1150344432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1150344432 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2057478611 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 519883480 ps |
| CPU time | 6.14 seconds |
| Started | May 21 02:32:57 PM PDT 24 |
| Finished | May 21 02:33:23 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-8361e814-8c98-4704-b9d6-5da55a61f897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2057478611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2057478611 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1707835640 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4811388722 ps |
| CPU time | 29.87 seconds |
| Started | May 21 02:33:02 PM PDT 24 |
| Finished | May 21 02:33:51 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-dc073d13-8ad4-427a-bcc1-a303db9237ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1707835640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1707835640 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2812859306 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10431488 ps |
| CPU time | 1.06 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:19 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-e09197b2-2f99-4c57-bc97-e05cc114173b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812859306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2812859306 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.268360133 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 59895801 ps |
| CPU time | 4.46 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:22 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-c50d82dd-b8d5-40cd-8e87-e5feac707164 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=268360133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.268360133 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.723812458 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 132019763 ps |
| CPU time | 1.63 seconds |
| Started | May 21 02:33:00 PM PDT 24 |
| Finished | May 21 02:33:21 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-14b72c41-b42e-405e-9d2f-819d285cc96d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723812458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.723812458 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2474145352 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3522545297 ps |
| CPU time | 8.96 seconds |
| Started | May 21 02:32:59 PM PDT 24 |
| Finished | May 21 02:33:27 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-62647146-2054-40d3-a21a-5b254063c723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474145352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2474145352 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3745904006 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1988497185 ps |
| CPU time | 8.45 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:26 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-0cb402b9-7d8f-42d4-b0dc-6a778b287bb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3745904006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3745904006 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2717581969 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 9403384 ps |
| CPU time | 1.03 seconds |
| Started | May 21 02:33:01 PM PDT 24 |
| Finished | May 21 02:33:22 PM PDT 24 |
| Peak memory | 202392 kb |
| Host | smart-7111070b-df64-426e-90c7-e2be316da7db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717581969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2717581969 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1898529035 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 5911185235 ps |
| CPU time | 83.84 seconds |
| Started | May 21 02:32:57 PM PDT 24 |
| Finished | May 21 02:34:41 PM PDT 24 |
| Peak memory | 203280 kb |
| Host | smart-ff8b0f2e-bc12-4093-af50-94703dcff6c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1898529035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1898529035 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1753357099 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1735347491 ps |
| CPU time | 30.6 seconds |
| Started | May 21 02:32:57 PM PDT 24 |
| Finished | May 21 02:33:47 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-1d8bc3c5-d128-4106-b09d-ac9ad7cca028 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1753357099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1753357099 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.766470486 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 162666617 ps |
| CPU time | 18.49 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-333eeb14-95e0-4408-af79-ead402f0becd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=766470486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.766470486 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.238028008 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 240070027 ps |
| CPU time | 17.69 seconds |
| Started | May 21 02:33:00 PM PDT 24 |
| Finished | May 21 02:33:38 PM PDT 24 |
| Peak memory | 203252 kb |
| Host | smart-b1d81f41-dbf1-43b8-beaf-66f0c01e991f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=238028008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.238028008 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1055722326 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 142792743 ps |
| CPU time | 3.88 seconds |
| Started | May 21 02:33:02 PM PDT 24 |
| Finished | May 21 02:33:25 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-83f160a8-a619-4aef-8eca-a90dd38c740c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055722326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1055722326 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1900130330 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 91880273 ps |
| CPU time | 2.02 seconds |
| Started | May 21 02:33:38 PM PDT 24 |
| Finished | May 21 02:33:58 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-82aa74dc-ce84-4275-b774-fc40b356782e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1900130330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1900130330 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3985811487 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 129975463103 ps |
| CPU time | 293.43 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:38:50 PM PDT 24 |
| Peak memory | 203356 kb |
| Host | smart-027ff1d5-1996-4aa8-9985-ab218fdbaf30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3985811487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.3985811487 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2068213203 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 11812292 ps |
| CPU time | 1.29 seconds |
| Started | May 21 02:33:38 PM PDT 24 |
| Finished | May 21 02:33:56 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-69a72746-02b7-4de1-a9de-0f1d977752e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2068213203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2068213203 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.3107903284 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2347948970 ps |
| CPU time | 12.17 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:08 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-4bdfd1f9-1c9a-4ce3-bf68-daf3104acf73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107903284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3107903284 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.1331633423 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1982126913 ps |
| CPU time | 14.11 seconds |
| Started | May 21 02:33:38 PM PDT 24 |
| Finished | May 21 02:34:10 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-5b926d56-d684-48ee-afa5-3209a57b86ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1331633423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1331633423 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.769481913 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 21384314605 ps |
| CPU time | 34.12 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:31 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-26d430d0-12f3-4302-80c0-f52f3e4f7473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=769481913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.769481913 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.4003414353 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 14064786643 ps |
| CPU time | 27.3 seconds |
| Started | May 21 02:33:40 PM PDT 24 |
| Finished | May 21 02:34:25 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-2993c3e5-65d9-41c6-a8b0-715fe254218d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4003414353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.4003414353 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2228246119 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 53393094 ps |
| CPU time | 4.19 seconds |
| Started | May 21 02:33:43 PM PDT 24 |
| Finished | May 21 02:34:05 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-a74f5c3c-7dd1-4877-8553-ba9e111ad5da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228246119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2228246119 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3892449553 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 64543245 ps |
| CPU time | 4.71 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:02 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-0e0f563a-d891-4760-b8eb-0482e7f61562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3892449553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3892449553 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.4180158394 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 40481449 ps |
| CPU time | 1.32 seconds |
| Started | May 21 02:33:37 PM PDT 24 |
| Finished | May 21 02:33:54 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-93622aa3-5af4-41ca-a74c-c98d14035169 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4180158394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4180158394 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1886394186 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3387546724 ps |
| CPU time | 12.37 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:09 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-0ff1d773-15ff-4916-bd63-5114cd892384 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886394186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1886394186 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2467599910 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1703163094 ps |
| CPU time | 7.17 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:05 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-0821cbbd-9e67-4d8e-8ebc-43531ae03ab7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2467599910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2467599910 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.546283230 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 12541544 ps |
| CPU time | 1.06 seconds |
| Started | May 21 02:33:38 PM PDT 24 |
| Finished | May 21 02:33:56 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-af3c6092-dfa9-4254-bb1b-b10c59f594ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546283230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.546283230 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3569826703 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 6971584537 ps |
| CPU time | 47.05 seconds |
| Started | May 21 02:33:43 PM PDT 24 |
| Finished | May 21 02:34:48 PM PDT 24 |
| Peak memory | 203304 kb |
| Host | smart-76c394ca-9662-41a7-b52c-2b991a349bc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569826703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3569826703 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1819599166 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 229917324 ps |
| CPU time | 15.8 seconds |
| Started | May 21 02:33:47 PM PDT 24 |
| Finished | May 21 02:34:20 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-807aee60-0735-400e-8757-5bff2b6ba0ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1819599166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1819599166 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3920466659 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 122114444 ps |
| CPU time | 31.87 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:28 PM PDT 24 |
| Peak memory | 204448 kb |
| Host | smart-1d1ea305-7b4a-4b71-8e63-1e5b7c8ec11a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3920466659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3920466659 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1644772601 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 175746466 ps |
| CPU time | 10.39 seconds |
| Started | May 21 02:34:01 PM PDT 24 |
| Finished | May 21 02:34:26 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-902e06bb-4823-42d3-823a-26398747bdb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1644772601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1644772601 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1624829917 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 81241565 ps |
| CPU time | 7.62 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:05 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-719b0d12-198a-4d51-8890-783233f9dd2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1624829917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1624829917 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1405846931 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 243870731 ps |
| CPU time | 7.53 seconds |
| Started | May 21 02:33:53 PM PDT 24 |
| Finished | May 21 02:34:18 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-e943b120-0dd7-4c1d-bcac-6ff54edd8667 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1405846931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1405846931 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3266983627 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 77898483349 ps |
| CPU time | 245.21 seconds |
| Started | May 21 02:33:52 PM PDT 24 |
| Finished | May 21 02:38:14 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-da7428bf-ad7c-4e6a-aa10-f229bc9e4bea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3266983627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3266983627 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4105980342 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1304636964 ps |
| CPU time | 7.66 seconds |
| Started | May 21 02:34:01 PM PDT 24 |
| Finished | May 21 02:34:23 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-641694c1-5260-4e1c-9f81-bae54bd11092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4105980342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4105980342 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2901184065 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1601523540 ps |
| CPU time | 7.92 seconds |
| Started | May 21 02:33:52 PM PDT 24 |
| Finished | May 21 02:34:17 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-aaceff9f-9acb-47f0-896e-4d6b1e5f2702 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2901184065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2901184065 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.741775903 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 704595305 ps |
| CPU time | 4.62 seconds |
| Started | May 21 02:33:47 PM PDT 24 |
| Finished | May 21 02:34:09 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-1eb19898-368d-4536-a856-7358bcd63ed1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=741775903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.741775903 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2389939212 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 23931331869 ps |
| CPU time | 56.77 seconds |
| Started | May 21 02:33:43 PM PDT 24 |
| Finished | May 21 02:34:58 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-9d332300-d973-4323-8027-274440c70a53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389939212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2389939212 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.335624040 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 9295005376 ps |
| CPU time | 53.76 seconds |
| Started | May 21 02:33:44 PM PDT 24 |
| Finished | May 21 02:34:55 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-e60267de-3c41-42b1-9bdd-937f4cf5d2c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=335624040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.335624040 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1616190047 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 66710925 ps |
| CPU time | 3.28 seconds |
| Started | May 21 02:33:47 PM PDT 24 |
| Finished | May 21 02:34:08 PM PDT 24 |
| Peak memory | 202396 kb |
| Host | smart-65112664-d8e6-459e-aac5-419d3e144dfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616190047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1616190047 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3333741048 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1245254058 ps |
| CPU time | 12.19 seconds |
| Started | May 21 02:33:54 PM PDT 24 |
| Finished | May 21 02:34:23 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-711f35b7-3d6d-4df3-9f80-93091644257e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333741048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3333741048 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3021885245 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 74976383 ps |
| CPU time | 1.88 seconds |
| Started | May 21 02:33:45 PM PDT 24 |
| Finished | May 21 02:34:05 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-793f4ccc-2da2-4d33-9352-06029927fe9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3021885245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3021885245 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3298810136 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 2353207361 ps |
| CPU time | 9.49 seconds |
| Started | May 21 02:33:49 PM PDT 24 |
| Finished | May 21 02:34:15 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-501b0b9b-d265-45f7-a3bf-0d10b1ad58e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298810136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3298810136 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2968050454 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3741232325 ps |
| CPU time | 9.12 seconds |
| Started | May 21 02:33:47 PM PDT 24 |
| Finished | May 21 02:34:14 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-1717b4b7-5058-4353-be17-141a66bad6ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2968050454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2968050454 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2768458769 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 14305925 ps |
| CPU time | 1.08 seconds |
| Started | May 21 02:33:46 PM PDT 24 |
| Finished | May 21 02:34:05 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-f006e383-9dd2-4ada-a0a6-bc57fae0ce3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768458769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2768458769 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1913953713 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1186765075 ps |
| CPU time | 49.75 seconds |
| Started | May 21 02:33:52 PM PDT 24 |
| Finished | May 21 02:34:59 PM PDT 24 |
| Peak memory | 203412 kb |
| Host | smart-7fbc2569-35b6-4bcd-a4f3-b4e26540a4dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1913953713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1913953713 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3282760326 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 4745922921 ps |
| CPU time | 60.44 seconds |
| Started | May 21 02:33:51 PM PDT 24 |
| Finished | May 21 02:35:09 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-20fd5703-a417-4812-93cd-1ad594cfface |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3282760326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3282760326 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.4081818506 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1452178404 ps |
| CPU time | 211.93 seconds |
| Started | May 21 02:33:51 PM PDT 24 |
| Finished | May 21 02:37:40 PM PDT 24 |
| Peak memory | 207092 kb |
| Host | smart-d8e46481-0a96-4d0a-b440-a5bae076d2bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4081818506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.4081818506 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1551594296 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 359418305 ps |
| CPU time | 35.19 seconds |
| Started | May 21 02:33:51 PM PDT 24 |
| Finished | May 21 02:34:44 PM PDT 24 |
| Peak memory | 204256 kb |
| Host | smart-5cbe68ba-98da-4304-8903-36a9fb69beec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1551594296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1551594296 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3382717081 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 192031963 ps |
| CPU time | 3.24 seconds |
| Started | May 21 02:33:53 PM PDT 24 |
| Finished | May 21 02:34:14 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-19682b12-3ee9-419e-805d-7e8ab4dc170d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3382717081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3382717081 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2744474873 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 28207893 ps |
| CPU time | 1.98 seconds |
| Started | May 21 02:33:59 PM PDT 24 |
| Finished | May 21 02:34:16 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-0b1295d7-9f28-4710-8167-5600dbcbab8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2744474873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2744474873 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.4215898969 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 94595849 ps |
| CPU time | 6.44 seconds |
| Started | May 21 02:33:57 PM PDT 24 |
| Finished | May 21 02:34:19 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-0cfdc4da-25e0-4622-898f-55bfe6c1836c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215898969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4215898969 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3755428921 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 36654136 ps |
| CPU time | 3.52 seconds |
| Started | May 21 02:33:51 PM PDT 24 |
| Finished | May 21 02:34:11 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-e4d838a9-4c16-4106-9581-0abc1c78fb72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3755428921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3755428921 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.855191427 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 18565151640 ps |
| CPU time | 81.65 seconds |
| Started | May 21 02:33:51 PM PDT 24 |
| Finished | May 21 02:35:29 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-51ccaedb-b7f5-437a-a4d2-0d0b4d3d54f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=855191427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.855191427 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3727300450 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 6369452569 ps |
| CPU time | 46.74 seconds |
| Started | May 21 02:34:01 PM PDT 24 |
| Finished | May 21 02:35:02 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-11dbe030-7f8e-41ee-87a0-82ca60316443 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3727300450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3727300450 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.192652050 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 380837836 ps |
| CPU time | 5.89 seconds |
| Started | May 21 02:33:51 PM PDT 24 |
| Finished | May 21 02:34:14 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-d23a1b98-1745-43fb-80ff-6a59230396e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192652050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.192652050 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.3714517044 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1173496219 ps |
| CPU time | 13.79 seconds |
| Started | May 21 02:33:59 PM PDT 24 |
| Finished | May 21 02:34:28 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-e1281e71-ae3f-4405-9815-0e153b675955 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3714517044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3714517044 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2730088043 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 343165564 ps |
| CPU time | 1.77 seconds |
| Started | May 21 02:33:53 PM PDT 24 |
| Finished | May 21 02:34:12 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-dc9ff1ed-80b4-476f-ab1c-a72f937ec4ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730088043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2730088043 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2009978810 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2367938007 ps |
| CPU time | 9.02 seconds |
| Started | May 21 02:33:52 PM PDT 24 |
| Finished | May 21 02:34:18 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-d69eb1a3-c465-4f1f-916b-97211098c692 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009978810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2009978810 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.921537573 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1044680122 ps |
| CPU time | 5.98 seconds |
| Started | May 21 02:33:50 PM PDT 24 |
| Finished | May 21 02:34:13 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-d42d5015-7518-4b33-9b0c-9dce18eb25e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=921537573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.921537573 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2103358607 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 27684709 ps |
| CPU time | 1.03 seconds |
| Started | May 21 02:33:52 PM PDT 24 |
| Finished | May 21 02:34:10 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-dfcf6dd6-3fb9-4c55-bf5b-1d3724e7f0fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103358607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2103358607 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1828180201 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6936397536 ps |
| CPU time | 24.98 seconds |
| Started | May 21 02:34:05 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-a59d3a69-705b-4809-89f0-b1bada2e2327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1828180201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1828180201 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2982379472 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 7400783184 ps |
| CPU time | 18.56 seconds |
| Started | May 21 02:34:00 PM PDT 24 |
| Finished | May 21 02:34:33 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-d95e1488-0369-4681-a6b6-7005e4dfe85b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2982379472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2982379472 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.762540583 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3153895357 ps |
| CPU time | 106.56 seconds |
| Started | May 21 02:34:01 PM PDT 24 |
| Finished | May 21 02:36:02 PM PDT 24 |
| Peak memory | 204944 kb |
| Host | smart-3bd989a6-76b4-4b3d-8728-993ed6d74c77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762540583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand _reset.762540583 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.946582874 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 10042035902 ps |
| CPU time | 65.41 seconds |
| Started | May 21 02:33:59 PM PDT 24 |
| Finished | May 21 02:35:20 PM PDT 24 |
| Peak memory | 205612 kb |
| Host | smart-bdf0621b-6534-4214-9ce0-9be28b1b88af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946582874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.946582874 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.24702874 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 38651883 ps |
| CPU time | 4.5 seconds |
| Started | May 21 02:34:01 PM PDT 24 |
| Finished | May 21 02:34:20 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-c1a928cb-55a2-4699-81ba-9e25d11cc9d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24702874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.24702874 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.977785730 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 166824122 ps |
| CPU time | 8.62 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:34:27 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-7dfeb0c6-add9-4686-9912-291bd6a7de28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=977785730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.977785730 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1323963894 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 135141416612 ps |
| CPU time | 343.39 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:40:02 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-1986c575-2fb5-4218-8503-f664e28bcae9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1323963894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1323963894 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.784210143 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 76121594 ps |
| CPU time | 3.82 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:34:21 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-61e79ab4-f50f-43aa-bde1-e764075cf4e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=784210143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.784210143 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.827547131 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 590953044 ps |
| CPU time | 6.75 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:34:24 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-ddabafed-9562-48ef-9add-3d3396a84e0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827547131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.827547131 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.139586361 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 966469065 ps |
| CPU time | 11.4 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:34:28 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-51273052-117d-4660-8835-f0f762004319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=139586361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.139586361 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.222785286 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 33593230308 ps |
| CPU time | 114.65 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:36:13 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-e5947476-fb22-4545-8b23-a4abc1aff439 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=222785286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.222785286 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2931036006 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 127400975904 ps |
| CPU time | 188.07 seconds |
| Started | May 21 02:34:06 PM PDT 24 |
| Finished | May 21 02:37:28 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-fa04d63d-315f-4525-8bed-23185fe1fa7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2931036006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2931036006 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.377108112 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 54164478 ps |
| CPU time | 5.9 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:34:23 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-4800db7e-66db-409d-9294-46e6a9c1b2b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377108112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.377108112 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.4271627372 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 17451935 ps |
| CPU time | 1.87 seconds |
| Started | May 21 02:34:05 PM PDT 24 |
| Finished | May 21 02:34:22 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-908373f6-018c-4d64-92a5-d965ba65eebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271627372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4271627372 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1996557062 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 68909167 ps |
| CPU time | 1.3 seconds |
| Started | May 21 02:33:58 PM PDT 24 |
| Finished | May 21 02:34:15 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-f7d2c2f5-ac4e-41a4-958f-baebb50a9259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996557062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1996557062 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.129143484 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1585071036 ps |
| CPU time | 6.85 seconds |
| Started | May 21 02:33:59 PM PDT 24 |
| Finished | May 21 02:34:21 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-7ec2ed7c-4986-418b-895f-9c455bc8187a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=129143484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.129143484 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2778282084 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1674051821 ps |
| CPU time | 7.71 seconds |
| Started | May 21 02:33:58 PM PDT 24 |
| Finished | May 21 02:34:21 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-621902dc-d849-4e80-89ff-a9ba2983933a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2778282084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2778282084 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2381582268 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 10411703 ps |
| CPU time | 1.02 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:34:18 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-4273e92b-54ee-43c6-a3b4-32c8609e2be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381582268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2381582268 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2113492956 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 5277315905 ps |
| CPU time | 86.67 seconds |
| Started | May 21 02:34:05 PM PDT 24 |
| Finished | May 21 02:35:47 PM PDT 24 |
| Peak memory | 205004 kb |
| Host | smart-c78eb6b6-d509-4eb5-a78c-db104d30fe5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2113492956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2113492956 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3851138553 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 778264877 ps |
| CPU time | 39.05 seconds |
| Started | May 21 02:34:05 PM PDT 24 |
| Finished | May 21 02:34:59 PM PDT 24 |
| Peak memory | 203312 kb |
| Host | smart-933bfb93-f45f-491a-88a1-fdc0c173166d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3851138553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3851138553 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.518939222 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3782364119 ps |
| CPU time | 59.58 seconds |
| Started | May 21 02:34:05 PM PDT 24 |
| Finished | May 21 02:35:19 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-a0ca7e8c-639b-425f-b156-89e397e1f090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518939222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.518939222 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.973458244 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 517150407 ps |
| CPU time | 62.16 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:35:19 PM PDT 24 |
| Peak memory | 205548 kb |
| Host | smart-c0164d61-40f0-4d76-a3a0-e275ee18cadf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973458244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.973458244 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.273377706 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1105028372 ps |
| CPU time | 12.48 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:34:30 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-219bf644-5b18-4b1c-a07b-d98835328353 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273377706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.273377706 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.4139547443 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 251655852 ps |
| CPU time | 5.57 seconds |
| Started | May 21 02:34:11 PM PDT 24 |
| Finished | May 21 02:34:31 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-b4a66ffe-9f94-46b8-b6ee-8926f37aaabc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4139547443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.4139547443 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1370136109 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2003652655 ps |
| CPU time | 16.4 seconds |
| Started | May 21 02:34:12 PM PDT 24 |
| Finished | May 21 02:34:43 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-c1394581-4b03-4705-a5ba-57386698150f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1370136109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1370136109 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.4094595490 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 121774114 ps |
| CPU time | 2.91 seconds |
| Started | May 21 02:34:11 PM PDT 24 |
| Finished | May 21 02:34:28 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-ea2ddc87-54ff-4bff-aa46-ff450696502c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4094595490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.4094595490 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.893910676 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1270700384 ps |
| CPU time | 6.3 seconds |
| Started | May 21 02:34:14 PM PDT 24 |
| Finished | May 21 02:34:34 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-8aaf2c28-2896-4a83-a6f9-0b33f19a36c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893910676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.893910676 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.394663001 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 29213435 ps |
| CPU time | 3.71 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:40 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-b0e112d4-eed9-4332-a7e4-fa75cf4b13e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=394663001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.394663001 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3894622446 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5257747863 ps |
| CPU time | 24.7 seconds |
| Started | May 21 02:34:06 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-faeb6831-c0f8-40fc-b474-b54c5f38d568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894622446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3894622446 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.848998909 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 45876438926 ps |
| CPU time | 131 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:36:35 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-dab18641-221a-42ff-80db-091a619d7760 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=848998909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.848998909 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.926106942 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 34879688 ps |
| CPU time | 3.63 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:34:22 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-ba583ee5-00d0-42b2-bf28-1f5a572722d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926106942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.926106942 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.2200538608 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 57413963 ps |
| CPU time | 5.2 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:34:30 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-026a9a09-45e4-4a17-bbaa-adcee368d89a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200538608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2200538608 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.620202222 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 48964728 ps |
| CPU time | 1.47 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:34:19 PM PDT 24 |
| Peak memory | 202384 kb |
| Host | smart-abb235bc-bade-492e-89d9-874c5fafae5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=620202222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.620202222 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2510825692 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2552592849 ps |
| CPU time | 8.28 seconds |
| Started | May 21 02:34:03 PM PDT 24 |
| Finished | May 21 02:34:25 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-f127a7e5-0a75-4fcb-980a-72788c4fdbb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510825692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2510825692 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3881820432 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1583157058 ps |
| CPU time | 6.31 seconds |
| Started | May 21 02:34:04 PM PDT 24 |
| Finished | May 21 02:34:24 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-41f0d7ca-2eb4-4f3b-b8ff-889a0e7cd13b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3881820432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3881820432 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1284172618 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 30156769 ps |
| CPU time | 1.07 seconds |
| Started | May 21 02:34:05 PM PDT 24 |
| Finished | May 21 02:34:21 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-94dbf19b-990a-476c-8e73-4160555c2ac4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284172618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1284172618 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.4054551710 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 383074574 ps |
| CPU time | 49.03 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:35:26 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-bcd3c02d-2358-433d-8083-e26d28e00327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4054551710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4054551710 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.902285771 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 24082256020 ps |
| CPU time | 41.49 seconds |
| Started | May 21 02:34:09 PM PDT 24 |
| Finished | May 21 02:35:04 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-4d0eb248-59da-47ed-a53b-6e52c9cb72ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=902285771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.902285771 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.576219164 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 471027331 ps |
| CPU time | 91.38 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:35:56 PM PDT 24 |
| Peak memory | 205008 kb |
| Host | smart-e79e3479-e656-4329-93db-4bdd9d3b00d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576219164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.576219164 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.518925172 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2307810689 ps |
| CPU time | 46.57 seconds |
| Started | May 21 02:34:09 PM PDT 24 |
| Finished | May 21 02:35:10 PM PDT 24 |
| Peak memory | 203864 kb |
| Host | smart-4498c79a-6914-4ae3-b317-ea2f2f66cec1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518925172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.518925172 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.901300613 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 67102240 ps |
| CPU time | 1.88 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:34:27 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-f43d8223-4671-4e0e-b599-3c6c8bcd19d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=901300613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.901300613 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3118338562 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1400412873 ps |
| CPU time | 9.67 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:40 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-1f9310bd-111f-42c0-83d0-72efd9f8c350 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118338562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3118338562 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.246005255 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 55977824474 ps |
| CPU time | 291.34 seconds |
| Started | May 21 02:34:18 PM PDT 24 |
| Finished | May 21 02:39:24 PM PDT 24 |
| Peak memory | 203256 kb |
| Host | smart-9be2af4b-972d-464a-ae5a-1fc1444a77f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=246005255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo w_rsp.246005255 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2348261871 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 76166035 ps |
| CPU time | 2.14 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:34:34 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-170b0567-9a0e-4b31-903c-2486128050be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348261871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2348261871 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2281162731 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 599851676 ps |
| CPU time | 7.87 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:38 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-55c38680-d006-4a39-a38c-ca9efc0b31c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2281162731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2281162731 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.4286067743 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 445813249 ps |
| CPU time | 6.46 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:34:31 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-c330c9c6-2dd9-4ef2-9a2c-df1d8dd494a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4286067743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4286067743 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.423053711 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 32978257700 ps |
| CPU time | 51.94 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:35:16 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-b86a015a-3a3e-4754-aa20-b09e137f23de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=423053711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.423053711 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1023114819 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 11726195451 ps |
| CPU time | 13.45 seconds |
| Started | May 21 02:34:10 PM PDT 24 |
| Finished | May 21 02:34:38 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-f1337a12-fd16-4f43-81a3-030ad2abd6b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1023114819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1023114819 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3511342810 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 67183392 ps |
| CPU time | 3.83 seconds |
| Started | May 21 02:34:09 PM PDT 24 |
| Finished | May 21 02:34:27 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-4ba32c08-e24e-4247-b156-6597da62b89a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511342810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3511342810 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.752170145 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 97303144 ps |
| CPU time | 4.63 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:35 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-a77b1da0-b032-41aa-bf7d-5b583b9ad26d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=752170145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.752170145 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.2815964179 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 39444823 ps |
| CPU time | 1.45 seconds |
| Started | May 21 02:34:13 PM PDT 24 |
| Finished | May 21 02:34:29 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-de4873b7-a27a-47e8-895d-1381be447aba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2815964179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2815964179 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1459957543 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 11490569792 ps |
| CPU time | 8.16 seconds |
| Started | May 21 02:34:11 PM PDT 24 |
| Finished | May 21 02:34:33 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-dcac8b59-302b-4fa4-bb7c-dbd0a7146ac8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459957543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1459957543 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2610389598 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2959877385 ps |
| CPU time | 10.47 seconds |
| Started | May 21 02:34:14 PM PDT 24 |
| Finished | May 21 02:34:38 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-ee0eb316-b911-4ebd-b777-e44e0bb9adb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2610389598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2610389598 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1587598734 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 20438139 ps |
| CPU time | 1.16 seconds |
| Started | May 21 02:34:12 PM PDT 24 |
| Finished | May 21 02:34:27 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-4bdf24f7-647b-49e3-966c-81f7649f0a2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587598734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1587598734 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1112081389 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 6095919152 ps |
| CPU time | 104.32 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:36:16 PM PDT 24 |
| Peak memory | 204712 kb |
| Host | smart-6ac6f0ab-f70d-4cb9-afcc-34279401d9b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1112081389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1112081389 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3177568398 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1337626541 ps |
| CPU time | 47.22 seconds |
| Started | May 21 02:34:19 PM PDT 24 |
| Finished | May 21 02:35:20 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-1f239e08-35af-441a-8c78-967c76dcabbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3177568398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3177568398 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3617600497 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 390836914 ps |
| CPU time | 32.17 seconds |
| Started | May 21 02:34:15 PM PDT 24 |
| Finished | May 21 02:35:02 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-aaa7a24a-2bf7-49fd-a0b4-dff4d731ddc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3617600497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3617600497 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1897919363 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 52067236 ps |
| CPU time | 8.13 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:34:39 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-9893c3ce-1f1b-440a-9c0b-5ac2b2a4ef47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897919363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1897919363 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2571827687 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 197370976 ps |
| CPU time | 6.9 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:43 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-b6f83fd1-63bf-4ef1-b2f8-63d9f0048775 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2571827687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2571827687 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2897821715 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 123957069 ps |
| CPU time | 1.98 seconds |
| Started | May 21 02:34:15 PM PDT 24 |
| Finished | May 21 02:34:31 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-914e9f34-1308-4896-b96e-cf3d21eee0e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2897821715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2897821715 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3598952792 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 20952588592 ps |
| CPU time | 112.75 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:36:24 PM PDT 24 |
| Peak memory | 203296 kb |
| Host | smart-e7b09cdd-52c6-440c-8257-7fe7dd279a00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3598952792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3598952792 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1292410673 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 754866029 ps |
| CPU time | 7.32 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:34:39 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-29cc8f21-3fb8-48ee-8bd2-095dbf7b560c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1292410673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1292410673 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.234261342 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 387798148 ps |
| CPU time | 6.74 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:37 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-7a3a5887-2fb3-42a4-b4d3-7cc582689ea3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=234261342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.234261342 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.4115680418 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 50082838 ps |
| CPU time | 8.3 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:39 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-c2f9589b-9947-4ff1-a0a5-024b584072cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4115680418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4115680418 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2833433831 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 25384948379 ps |
| CPU time | 120.12 seconds |
| Started | May 21 02:34:14 PM PDT 24 |
| Finished | May 21 02:36:29 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-9182c2c5-9620-4fb4-8381-8581f1335b46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833433831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2833433831 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.112311553 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 111599867796 ps |
| CPU time | 102.18 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:36:13 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-5f6557fd-9d46-421e-82e0-2f83062d8f79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=112311553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.112311553 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3011977731 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 286784238 ps |
| CPU time | 7.15 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:37 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-3979a4f2-2719-42cf-b2df-3b78fdede735 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011977731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3011977731 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.3520953083 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 103953217 ps |
| CPU time | 5.47 seconds |
| Started | May 21 02:34:15 PM PDT 24 |
| Finished | May 21 02:34:34 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-9aa1bbbd-8a0c-4b32-9f52-229bd898ad8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3520953083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3520953083 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1840295015 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 8379450 ps |
| CPU time | 1.02 seconds |
| Started | May 21 02:34:19 PM PDT 24 |
| Finished | May 21 02:34:33 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-1f46cad0-2e40-44bf-9af5-b7284da1990a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840295015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1840295015 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1155420802 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3628790514 ps |
| CPU time | 5.83 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:34:37 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-ddcc2137-117b-43ae-af59-d14d4a812bfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155420802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1155420802 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.780296709 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1248645393 ps |
| CPU time | 9.49 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:34:41 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-3b5ed999-b003-4a26-91c1-a79300445263 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=780296709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.780296709 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3567481662 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 8786122 ps |
| CPU time | 1.01 seconds |
| Started | May 21 02:34:15 PM PDT 24 |
| Finished | May 21 02:34:30 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-4963406b-69fc-4b5f-8c90-878430e73256 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567481662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3567481662 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3309364083 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 7859285095 ps |
| CPU time | 67.48 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:35:39 PM PDT 24 |
| Peak memory | 204044 kb |
| Host | smart-2e59b549-12fd-412c-9a7c-5826c4e32eff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3309364083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3309364083 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2629090411 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1001984627 ps |
| CPU time | 9.22 seconds |
| Started | May 21 02:34:16 PM PDT 24 |
| Finished | May 21 02:34:39 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-e3ced8af-a5a3-407c-bb40-2cbfad512e67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2629090411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2629090411 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.870665354 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1964392010 ps |
| CPU time | 173.43 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:37:25 PM PDT 24 |
| Peak memory | 208364 kb |
| Host | smart-4ad35573-52b5-4cbe-b035-cb32d45af9fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=870665354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.870665354 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4063535550 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3879139185 ps |
| CPU time | 113.67 seconds |
| Started | May 21 02:34:15 PM PDT 24 |
| Finished | May 21 02:36:23 PM PDT 24 |
| Peak memory | 206224 kb |
| Host | smart-6ac543a7-242b-4dd1-baf0-5278fa027786 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063535550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.4063535550 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2322774508 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 75686553 ps |
| CPU time | 3.8 seconds |
| Started | May 21 02:34:17 PM PDT 24 |
| Finished | May 21 02:34:36 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-4bae03df-4fbf-4b07-9432-595687c6b766 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322774508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2322774508 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3008317580 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1836787751 ps |
| CPU time | 9.72 seconds |
| Started | May 21 02:34:24 PM PDT 24 |
| Finished | May 21 02:34:47 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-31111241-afc0-459d-b800-3fd7ae69fb32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008317580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3008317580 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.666133432 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 18617120491 ps |
| CPU time | 89.25 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:36:06 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-4df0b145-c984-4e84-afd6-75e94f55782a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=666133432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slo w_rsp.666133432 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2831958229 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 417215986 ps |
| CPU time | 3.22 seconds |
| Started | May 21 02:34:21 PM PDT 24 |
| Finished | May 21 02:34:39 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-0f395fc0-ccde-4099-8d4a-674db4d8d4d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2831958229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2831958229 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2075032269 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 9713165 ps |
| CPU time | 1.2 seconds |
| Started | May 21 02:34:25 PM PDT 24 |
| Finished | May 21 02:34:39 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-95397621-d333-4668-af8f-7c997021ad5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2075032269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2075032269 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.739550037 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 60751927 ps |
| CPU time | 3.55 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:40 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-f7bb6901-7834-41ac-ae74-6da8611ee4bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=739550037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.739550037 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3699365246 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 27292290452 ps |
| CPU time | 83.55 seconds |
| Started | May 21 02:34:21 PM PDT 24 |
| Finished | May 21 02:35:58 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-1c24bb22-9f79-479b-b4e1-7c4e171de555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699365246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3699365246 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2962483217 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2030761179 ps |
| CPU time | 5.75 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:42 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-1feba6b3-dc1d-4834-a773-18cadad60e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2962483217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2962483217 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.21037616 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 50320334 ps |
| CPU time | 5.91 seconds |
| Started | May 21 02:34:21 PM PDT 24 |
| Finished | May 21 02:34:41 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-279ddc53-8aa4-4b93-bcd6-75d63057ad6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21037616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.21037616 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.4041975646 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 73266994 ps |
| CPU time | 5.16 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:42 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-316de510-8b95-4514-ad5f-cd50464c9b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041975646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4041975646 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.2273602077 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 10040391 ps |
| CPU time | 1.26 seconds |
| Started | May 21 02:34:18 PM PDT 24 |
| Finished | May 21 02:34:34 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-318b9648-1cd0-4569-9b1d-00a797bd3ca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2273602077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2273602077 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.986163380 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3138028279 ps |
| CPU time | 9.93 seconds |
| Started | May 21 02:34:22 PM PDT 24 |
| Finished | May 21 02:34:46 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-6aed8bd6-3e9b-4031-a130-b1048db10a67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=986163380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.986163380 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1313054170 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1711661809 ps |
| CPU time | 7.42 seconds |
| Started | May 21 02:34:22 PM PDT 24 |
| Finished | May 21 02:34:44 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-e33d0692-05b9-4178-b76c-fdd41303a74a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1313054170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1313054170 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1425645680 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 12209596 ps |
| CPU time | 1.08 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:38 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-2e28fc20-920c-45a5-951c-8732f21dcad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425645680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1425645680 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3186034996 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3534042373 ps |
| CPU time | 46.6 seconds |
| Started | May 21 02:34:25 PM PDT 24 |
| Finished | May 21 02:35:25 PM PDT 24 |
| Peak memory | 203236 kb |
| Host | smart-0232da23-b71f-4ca1-895f-28d66b3aca56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3186034996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3186034996 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.970201620 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 4010529246 ps |
| CPU time | 25.71 seconds |
| Started | May 21 02:34:22 PM PDT 24 |
| Finished | May 21 02:35:02 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-e30f274b-798f-41b0-b6b0-7c62112cf762 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=970201620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.970201620 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.895884280 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 9368407410 ps |
| CPU time | 108.71 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:36:26 PM PDT 24 |
| Peak memory | 206176 kb |
| Host | smart-4d49d8b7-305e-46f6-8d01-ade93bceb190 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=895884280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.895884280 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.694666192 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1313734896 ps |
| CPU time | 68.27 seconds |
| Started | May 21 02:34:22 PM PDT 24 |
| Finished | May 21 02:35:45 PM PDT 24 |
| Peak memory | 205544 kb |
| Host | smart-194227c8-422e-4bf3-8cc1-923abe2a3add |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=694666192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.694666192 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3257333299 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 604361559 ps |
| CPU time | 4.84 seconds |
| Started | May 21 02:34:21 PM PDT 24 |
| Finished | May 21 02:34:40 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-e00f56eb-825b-4df3-b1cb-c30de4f98a0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3257333299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3257333299 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.4261872641 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1098080582 ps |
| CPU time | 13.94 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:51 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-3789d279-53ea-47ef-bbbf-c2a9fd3c914c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4261872641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.4261872641 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.11459934 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 18105132419 ps |
| CPU time | 40.61 seconds |
| Started | May 21 02:34:28 PM PDT 24 |
| Finished | May 21 02:35:21 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-6d0074d2-b8f8-4b8c-a2ea-845a253863ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=11459934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow _rsp.11459934 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3768386922 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 503692094 ps |
| CPU time | 9.96 seconds |
| Started | May 21 02:34:31 PM PDT 24 |
| Finished | May 21 02:34:54 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-a806c040-1437-4d2f-93d3-8636c5a2b126 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3768386922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3768386922 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1950150554 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1062619543 ps |
| CPU time | 4.28 seconds |
| Started | May 21 02:34:28 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-2c0734a2-8950-4d9b-aa00-4d6e29286316 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1950150554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1950150554 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.3036720177 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 60502501 ps |
| CPU time | 5.07 seconds |
| Started | May 21 02:34:27 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-0e5e44a5-bc0a-48f0-b719-7c64f09948cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3036720177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3036720177 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.4056070707 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 25117536625 ps |
| CPU time | 60.08 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:35:37 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-65cfff3b-0551-45bd-919c-343d3fed135a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056070707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4056070707 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2820347946 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 45908491710 ps |
| CPU time | 140.38 seconds |
| Started | May 21 02:34:24 PM PDT 24 |
| Finished | May 21 02:36:57 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-ce3c0783-356d-43eb-b22f-0c4f3f26b5a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2820347946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2820347946 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.243497398 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 45519399 ps |
| CPU time | 3.12 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:40 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-c12f3b42-b910-4a80-9f8a-a79bb3e5b06a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243497398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.243497398 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.371632535 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1148963810 ps |
| CPU time | 10.92 seconds |
| Started | May 21 02:34:29 PM PDT 24 |
| Finished | May 21 02:34:53 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-5bbb2459-9b92-4afc-bbbc-f79c1b5e091b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371632535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.371632535 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.123416308 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 59067734 ps |
| CPU time | 1.4 seconds |
| Started | May 21 02:34:27 PM PDT 24 |
| Finished | May 21 02:34:41 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-31d7bb96-94e0-4f81-9755-272f6bd4c404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=123416308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.123416308 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2120435636 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3938978433 ps |
| CPU time | 9.01 seconds |
| Started | May 21 02:34:27 PM PDT 24 |
| Finished | May 21 02:34:49 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-4961be9e-7a63-4628-a716-33522d6f2db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120435636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2120435636 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2059561551 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 2156624651 ps |
| CPU time | 14.27 seconds |
| Started | May 21 02:34:23 PM PDT 24 |
| Finished | May 21 02:34:51 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-1c407a17-7e5b-4f1a-9b12-f86770fec9a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2059561551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2059561551 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.618051819 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 10272679 ps |
| CPU time | 1.4 seconds |
| Started | May 21 02:34:22 PM PDT 24 |
| Finished | May 21 02:34:38 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-3785c454-eb76-44f8-9211-74d9a27342f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618051819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.618051819 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3629448454 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 33771881 ps |
| CPU time | 3.33 seconds |
| Started | May 21 02:34:27 PM PDT 24 |
| Finished | May 21 02:34:43 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-3e9b04d6-2594-45fe-910b-adff8b30d5b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3629448454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3629448454 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.511367942 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3596747709 ps |
| CPU time | 64.79 seconds |
| Started | May 21 02:34:31 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-1c31a3e9-a079-465f-80b7-66e0791cc36c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=511367942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.511367942 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3248703964 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 6518861856 ps |
| CPU time | 151.35 seconds |
| Started | May 21 02:34:30 PM PDT 24 |
| Finished | May 21 02:37:15 PM PDT 24 |
| Peak memory | 206132 kb |
| Host | smart-5050203e-039a-46cc-a9cc-e486cb683f44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3248703964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3248703964 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2048029267 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 114318832 ps |
| CPU time | 16.19 seconds |
| Started | May 21 02:34:31 PM PDT 24 |
| Finished | May 21 02:35:00 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-95fea3fd-93fc-4da2-b7be-5ac5e1fd6231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048029267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2048029267 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3859142816 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 753143593 ps |
| CPU time | 10.85 seconds |
| Started | May 21 02:34:28 PM PDT 24 |
| Finished | May 21 02:34:52 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-fce92242-c8bb-4b61-a2e7-b601e61bc3e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859142816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3859142816 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1968180535 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 242015570 ps |
| CPU time | 3.97 seconds |
| Started | May 21 02:34:35 PM PDT 24 |
| Finished | May 21 02:34:51 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-0b87baaf-2485-4bb1-aafd-880525b9bf06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1968180535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1968180535 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3484074139 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 77708338 ps |
| CPU time | 4.14 seconds |
| Started | May 21 02:34:39 PM PDT 24 |
| Finished | May 21 02:34:54 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-154c8879-2f5f-4c2a-b80f-7cc0ab645771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484074139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3484074139 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.734236030 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2216106687 ps |
| CPU time | 13.1 seconds |
| Started | May 21 02:34:36 PM PDT 24 |
| Finished | May 21 02:35:01 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-39c450e9-7395-4c9a-b819-e3db785d5fbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734236030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.734236030 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.253616989 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 753488687 ps |
| CPU time | 14.83 seconds |
| Started | May 21 02:34:31 PM PDT 24 |
| Finished | May 21 02:34:59 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-280047d3-97b7-41ed-9bb8-c114fc7d6ea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=253616989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.253616989 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.3491549739 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 126166331606 ps |
| CPU time | 107.72 seconds |
| Started | May 21 02:34:35 PM PDT 24 |
| Finished | May 21 02:36:35 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-51746b5c-afbd-4c8d-ae0e-973e3297bb27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491549739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3491549739 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.758014988 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 24900549541 ps |
| CPU time | 84.05 seconds |
| Started | May 21 02:34:37 PM PDT 24 |
| Finished | May 21 02:36:13 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-3e86932a-c645-4432-ad22-e49beb23ad56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=758014988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.758014988 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.452150131 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 48508917 ps |
| CPU time | 4.32 seconds |
| Started | May 21 02:34:28 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-6384527b-be55-45ab-905a-179c3592cd93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452150131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.452150131 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.2173056432 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 175230571 ps |
| CPU time | 1.79 seconds |
| Started | May 21 02:34:35 PM PDT 24 |
| Finished | May 21 02:34:49 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-9f5dbb9c-f626-4b07-8677-a64979fdf771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2173056432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2173056432 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.1497561879 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 150806524 ps |
| CPU time | 1.41 seconds |
| Started | May 21 02:34:27 PM PDT 24 |
| Finished | May 21 02:34:42 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-ae656c2a-8d48-4829-a41c-2ce79b4536a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1497561879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1497561879 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3957806698 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 9761754652 ps |
| CPU time | 6.41 seconds |
| Started | May 21 02:34:31 PM PDT 24 |
| Finished | May 21 02:34:50 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-07427183-8231-485e-9512-6e0a334bd746 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957806698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3957806698 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1811579262 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4093664035 ps |
| CPU time | 5.04 seconds |
| Started | May 21 02:34:27 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-a178d374-f75c-4879-9ba4-e0d28d45ed93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1811579262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1811579262 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1529144101 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 14476134 ps |
| CPU time | 1.04 seconds |
| Started | May 21 02:34:31 PM PDT 24 |
| Finished | May 21 02:34:45 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-156e0d89-b757-49c7-ac52-0b76e90a79be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529144101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1529144101 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.2415774063 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6970926139 ps |
| CPU time | 79.19 seconds |
| Started | May 21 02:34:33 PM PDT 24 |
| Finished | May 21 02:36:05 PM PDT 24 |
| Peak memory | 203232 kb |
| Host | smart-7b68b6bf-ac59-4e0d-8c72-9682267333c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2415774063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2415774063 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.819366348 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 4477655839 ps |
| CPU time | 61.86 seconds |
| Started | May 21 02:34:35 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 203260 kb |
| Host | smart-bd79e304-84db-44b0-848b-5dfad8329679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=819366348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.819366348 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3980818231 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5623415165 ps |
| CPU time | 87.74 seconds |
| Started | May 21 02:34:38 PM PDT 24 |
| Finished | May 21 02:36:18 PM PDT 24 |
| Peak memory | 205464 kb |
| Host | smart-6c4d93ad-9b2e-42e8-a30c-3c2298c8ddfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3980818231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3980818231 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.203522473 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 498254944 ps |
| CPU time | 8.12 seconds |
| Started | May 21 02:34:33 PM PDT 24 |
| Finished | May 21 02:34:53 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-660fbdc0-680f-44ea-b3f7-b4cfff5c484d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=203522473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.203522473 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2980379658 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 209001748 ps |
| CPU time | 4.89 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:28 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-d499bf6a-dc60-4b4e-9644-af047b12aa89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2980379658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2980379658 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2282701354 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 47421747 ps |
| CPU time | 4.82 seconds |
| Started | May 21 02:33:04 PM PDT 24 |
| Finished | May 21 02:33:28 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-90b0f27f-8490-4d47-b533-af7157fd21b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282701354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2282701354 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.1971272156 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 24390225 ps |
| CPU time | 2.02 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:33 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-b5de80e0-92d8-4bcd-a6aa-af4ab98133cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1971272156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1971272156 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.2387456271 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 70864118 ps |
| CPU time | 3.58 seconds |
| Started | May 21 02:32:57 PM PDT 24 |
| Finished | May 21 02:33:20 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-983b743a-9caf-498f-a8b0-2c71b234d95a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2387456271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2387456271 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1797320883 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6277969584 ps |
| CPU time | 17.96 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-e9f2991e-b407-4d62-9264-5e8d72aa408e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797320883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1797320883 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1755097951 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 14731259609 ps |
| CPU time | 105.09 seconds |
| Started | May 21 02:33:06 PM PDT 24 |
| Finished | May 21 02:35:09 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-22c76827-e137-4428-a756-97ceb812dc2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1755097951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1755097951 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3171428623 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 26554016 ps |
| CPU time | 2.91 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:20 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-b51a4189-c5be-4dc7-b7fd-fc5d4dcd7de2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171428623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3171428623 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.2165664887 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 66088539 ps |
| CPU time | 2.73 seconds |
| Started | May 21 02:33:05 PM PDT 24 |
| Finished | May 21 02:33:26 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-91525101-130c-4ce9-8870-b737f6f44894 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2165664887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2165664887 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2693482429 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 10076672 ps |
| CPU time | 1.22 seconds |
| Started | May 21 02:33:01 PM PDT 24 |
| Finished | May 21 02:33:23 PM PDT 24 |
| Peak memory | 202380 kb |
| Host | smart-40d84679-637c-4fe8-b2ba-74ff7569d272 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693482429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2693482429 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.428525643 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 2272474602 ps |
| CPU time | 6.72 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:24 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-a6385343-3afc-4dcf-b342-17a1707668bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=428525643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.428525643 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2642363900 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2259458050 ps |
| CPU time | 11.11 seconds |
| Started | May 21 02:32:58 PM PDT 24 |
| Finished | May 21 02:33:28 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-545f3b73-d480-4442-ac65-358fd3c65e08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2642363900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2642363900 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1006641665 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 22618666 ps |
| CPU time | 1.25 seconds |
| Started | May 21 02:33:02 PM PDT 24 |
| Finished | May 21 02:33:23 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-ebfb8ec1-3114-4746-8c43-fcc83c47ce02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006641665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1006641665 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3690841202 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2040184502 ps |
| CPU time | 29.71 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:52 PM PDT 24 |
| Peak memory | 203256 kb |
| Host | smart-1a43eabd-d190-4858-95cb-1fb76c4e2398 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3690841202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3690841202 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.383381894 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 277366244 ps |
| CPU time | 18.17 seconds |
| Started | May 21 02:33:04 PM PDT 24 |
| Finished | May 21 02:33:41 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-0751eba2-2c23-4e04-b8c7-d2a1fefec7a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=383381894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.383381894 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.32507500 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 709328254 ps |
| CPU time | 99.29 seconds |
| Started | May 21 02:33:08 PM PDT 24 |
| Finished | May 21 02:35:06 PM PDT 24 |
| Peak memory | 206268 kb |
| Host | smart-0493f3a1-a269-49e5-8150-507771c17de0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=32507500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_r eset.32507500 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3080422673 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1830508521 ps |
| CPU time | 121.97 seconds |
| Started | May 21 02:33:09 PM PDT 24 |
| Finished | May 21 02:35:29 PM PDT 24 |
| Peak memory | 207160 kb |
| Host | smart-14832a1b-dfb4-4575-8600-7701fbfebdcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080422673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3080422673 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3933149813 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 27284336 ps |
| CPU time | 2.57 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:25 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-ea666512-a660-425a-923b-2f951cab62ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3933149813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3933149813 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2298717553 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 11791822 ps |
| CPU time | 1.42 seconds |
| Started | May 21 02:34:40 PM PDT 24 |
| Finished | May 21 02:34:53 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-4e02773f-e9cc-4270-acf8-3fc2655999d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2298717553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2298717553 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.893805081 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 119502078 ps |
| CPU time | 3.08 seconds |
| Started | May 21 02:34:41 PM PDT 24 |
| Finished | May 21 02:34:56 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-d34748b8-682b-4323-bae2-35c6458cfbab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893805081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.893805081 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3319652714 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 109698287 ps |
| CPU time | 7.12 seconds |
| Started | May 21 02:34:40 PM PDT 24 |
| Finished | May 21 02:34:58 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-34443399-579b-4885-804a-15f7a8128294 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3319652714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3319652714 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.2170723977 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 82597082 ps |
| CPU time | 2.4 seconds |
| Started | May 21 02:34:43 PM PDT 24 |
| Finished | May 21 02:34:56 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-d1ea418f-8346-4573-b095-b90ac0ffc7d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2170723977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2170723977 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.508196877 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 31524868209 ps |
| CPU time | 64.31 seconds |
| Started | May 21 02:34:40 PM PDT 24 |
| Finished | May 21 02:35:56 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-05afd9dc-c49f-48b5-8725-53decd20aa54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=508196877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.508196877 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1823988810 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 35665584890 ps |
| CPU time | 104.93 seconds |
| Started | May 21 02:34:40 PM PDT 24 |
| Finished | May 21 02:36:36 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-3b78ab12-7278-4222-a30e-3da7e8db9161 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1823988810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1823988810 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.4065350827 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 101591897 ps |
| CPU time | 2.6 seconds |
| Started | May 21 02:34:40 PM PDT 24 |
| Finished | May 21 02:34:54 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-0d6df946-4108-4aba-bfb2-d8476a0a3faf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065350827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.4065350827 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1267441885 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1566648306 ps |
| CPU time | 8.34 seconds |
| Started | May 21 02:34:42 PM PDT 24 |
| Finished | May 21 02:35:01 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-0269baa8-c4b9-48e5-a20c-d862d8be1ac6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1267441885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1267441885 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2443766045 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 10031487 ps |
| CPU time | 1.16 seconds |
| Started | May 21 02:34:45 PM PDT 24 |
| Finished | May 21 02:34:57 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-79b6961d-9cb0-464d-b8c4-2bd97bab0f42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2443766045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2443766045 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.4004143734 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 10175995016 ps |
| CPU time | 11.38 seconds |
| Started | May 21 02:34:39 PM PDT 24 |
| Finished | May 21 02:35:02 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-52c8a6ac-cf03-4072-a515-70a2fd9f9b49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004143734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4004143734 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2943146824 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5280108355 ps |
| CPU time | 6.62 seconds |
| Started | May 21 02:34:42 PM PDT 24 |
| Finished | May 21 02:35:00 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-e8142ef6-94ab-424b-b10b-25ee712b4012 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2943146824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2943146824 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.759792585 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8899828 ps |
| CPU time | 1.12 seconds |
| Started | May 21 02:34:42 PM PDT 24 |
| Finished | May 21 02:34:55 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-45ab14bf-c114-4f1e-83a2-54a3f4eacb1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759792585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.759792585 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.642110345 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 486736571 ps |
| CPU time | 31.34 seconds |
| Started | May 21 02:34:42 PM PDT 24 |
| Finished | May 21 02:35:24 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-bcac1cd7-dfbb-419f-a1e5-a3810c5650a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=642110345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.642110345 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3478955341 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2478959250 ps |
| CPU time | 41.5 seconds |
| Started | May 21 02:34:49 PM PDT 24 |
| Finished | May 21 02:35:42 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-43ae9ae1-97c5-41c3-9a39-81ad4c08ce3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3478955341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3478955341 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2875514278 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 50023059 ps |
| CPU time | 10.69 seconds |
| Started | May 21 02:34:49 PM PDT 24 |
| Finished | May 21 02:35:12 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-294a21b5-c557-44c7-a866-147fb02f82fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2875514278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2875514278 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3245022812 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 11529885 ps |
| CPU time | 1.3 seconds |
| Started | May 21 02:34:38 PM PDT 24 |
| Finished | May 21 02:34:51 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-c8130aba-faf9-4f0e-9e54-4bcb3bcb3124 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3245022812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3245022812 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.4144388735 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2992272083 ps |
| CPU time | 18.03 seconds |
| Started | May 21 02:34:56 PM PDT 24 |
| Finished | May 21 02:35:28 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-450022e2-6280-4e52-9a68-9b68dd24929b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4144388735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.4144388735 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.439389535 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 42707521032 ps |
| CPU time | 206.51 seconds |
| Started | May 21 02:34:52 PM PDT 24 |
| Finished | May 21 02:38:31 PM PDT 24 |
| Peak memory | 203280 kb |
| Host | smart-42618594-2e73-438f-a85f-b95f9784793c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=439389535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slo w_rsp.439389535 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2408120959 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 722096160 ps |
| CPU time | 4.31 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:35:12 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-811a983c-5db3-4ab6-bb64-c3120cbb885f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2408120959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2408120959 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1142036459 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 27372587 ps |
| CPU time | 1.9 seconds |
| Started | May 21 02:34:58 PM PDT 24 |
| Finished | May 21 02:35:15 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-433ce06d-9535-45d5-9989-93e763554434 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142036459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1142036459 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.2357620461 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 601144939 ps |
| CPU time | 5 seconds |
| Started | May 21 02:34:47 PM PDT 24 |
| Finished | May 21 02:35:03 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-286bcd5b-0e2a-49c0-8d2b-aa7aadc3d828 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2357620461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2357620461 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.161706934 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 43039374718 ps |
| CPU time | 182.73 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:38:10 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-00590597-590d-4be8-8d80-78197b5a7672 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=161706934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.161706934 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3987709288 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 47643733225 ps |
| CPU time | 173.72 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:38:02 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-d72c27d0-5866-4187-b811-7b2d8fb01fb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3987709288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3987709288 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1868253336 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 126054416 ps |
| CPU time | 8.36 seconds |
| Started | May 21 02:34:49 PM PDT 24 |
| Finished | May 21 02:35:09 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-71d0e57b-d908-4539-86e6-2c4de6fcf812 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868253336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1868253336 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.4174046639 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 26762773 ps |
| CPU time | 1.87 seconds |
| Started | May 21 02:34:56 PM PDT 24 |
| Finished | May 21 02:35:12 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-aa79f4ab-f5c2-4d1b-8dfa-467032699f3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4174046639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.4174046639 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.1149993773 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 8779702 ps |
| CPU time | 1.19 seconds |
| Started | May 21 02:34:49 PM PDT 24 |
| Finished | May 21 02:35:02 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-3c452b8e-fc80-4b64-8acd-931ea1fffc01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149993773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1149993773 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1003749542 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2787121268 ps |
| CPU time | 8.3 seconds |
| Started | May 21 02:34:47 PM PDT 24 |
| Finished | May 21 02:35:06 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-72843a2b-a0d8-49a4-83c9-ea049a478929 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003749542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1003749542 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.319747559 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2518243392 ps |
| CPU time | 5.41 seconds |
| Started | May 21 02:34:49 PM PDT 24 |
| Finished | May 21 02:35:06 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-4411a71a-55e7-40b8-88fd-b701c54ba688 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=319747559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.319747559 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1277650069 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 10801459 ps |
| CPU time | 1.19 seconds |
| Started | May 21 02:34:50 PM PDT 24 |
| Finished | May 21 02:35:03 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-2b04a180-63d9-42a2-bbb2-853e30a39790 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277650069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1277650069 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2944861792 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1612811947 ps |
| CPU time | 41.84 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:35:50 PM PDT 24 |
| Peak memory | 205112 kb |
| Host | smart-4446f8e6-e450-40f2-9000-7db37319b048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2944861792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2944861792 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3097946768 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1005357582 ps |
| CPU time | 41.66 seconds |
| Started | May 21 02:34:55 PM PDT 24 |
| Finished | May 21 02:35:50 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-7011a1b6-9b70-49f5-a604-9d1b5dc40664 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3097946768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3097946768 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1111532776 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 329590812 ps |
| CPU time | 49.66 seconds |
| Started | May 21 02:34:56 PM PDT 24 |
| Finished | May 21 02:35:59 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-2e5e4db6-973c-4179-990d-7c7e003ecbf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1111532776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.1111532776 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.872911850 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 5485603113 ps |
| CPU time | 82.51 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:36:31 PM PDT 24 |
| Peak memory | 205820 kb |
| Host | smart-a1627fe4-e072-49ea-934d-751cf34ec310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=872911850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_res et_error.872911850 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.141423680 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 20078963 ps |
| CPU time | 1.41 seconds |
| Started | May 21 02:34:53 PM PDT 24 |
| Finished | May 21 02:35:08 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-6f7875c3-2a28-466d-ae2d-53f7bd4dff73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=141423680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.141423680 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.4247186460 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 950788864 ps |
| CPU time | 12.21 seconds |
| Started | May 21 02:34:56 PM PDT 24 |
| Finished | May 21 02:35:22 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-3d268c15-c48c-4c6f-99a9-a67e5b901bdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4247186460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.4247186460 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.317219967 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 26890695843 ps |
| CPU time | 207.64 seconds |
| Started | May 21 02:34:57 PM PDT 24 |
| Finished | May 21 02:38:40 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-6a6566b1-10b9-4832-b799-d5175cdd70ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=317219967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo w_rsp.317219967 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3766732490 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 33733081 ps |
| CPU time | 3.02 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:35:20 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-3e5fde95-4830-407b-8f40-172fe502498b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3766732490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3766732490 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.4000143461 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 158493339 ps |
| CPU time | 2.25 seconds |
| Started | May 21 02:35:00 PM PDT 24 |
| Finished | May 21 02:35:18 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-c7813482-b152-4473-96c7-9d8ce3c585b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000143461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.4000143461 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.3220438678 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 100313347 ps |
| CPU time | 4.09 seconds |
| Started | May 21 02:34:56 PM PDT 24 |
| Finished | May 21 02:35:14 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-88906981-5e14-4df5-a244-347c7573475d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3220438678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3220438678 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3258139387 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 44511130703 ps |
| CPU time | 151.59 seconds |
| Started | May 21 02:34:59 PM PDT 24 |
| Finished | May 21 02:37:47 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-b28b7a35-7ce7-49af-87c1-d1931131770c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258139387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3258139387 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1413622193 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 63695841905 ps |
| CPU time | 142.03 seconds |
| Started | May 21 02:34:55 PM PDT 24 |
| Finished | May 21 02:37:30 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-d6e8ddcb-5bb2-443e-bab9-d55bb77f6691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1413622193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1413622193 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.959878218 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 298417722 ps |
| CPU time | 9.72 seconds |
| Started | May 21 02:34:55 PM PDT 24 |
| Finished | May 21 02:35:18 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-3df11470-24d8-4f00-9042-9f42804944d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959878218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.959878218 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.674571515 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 21244279 ps |
| CPU time | 1.51 seconds |
| Started | May 21 02:35:02 PM PDT 24 |
| Finished | May 21 02:35:22 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-4d487734-1d1f-4c97-b788-97a4c720ad7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=674571515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.674571515 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2597222573 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 152115386 ps |
| CPU time | 1.84 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:35:10 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-6c1cd17d-c464-4619-a522-b7859a990697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2597222573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2597222573 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.297092550 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2912751335 ps |
| CPU time | 8.6 seconds |
| Started | May 21 02:34:55 PM PDT 24 |
| Finished | May 21 02:35:18 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-8628461d-568b-4db3-bcd0-fee1ec9dfa68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=297092550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.297092550 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2357991715 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1536680299 ps |
| CPU time | 5.94 seconds |
| Started | May 21 02:34:54 PM PDT 24 |
| Finished | May 21 02:35:13 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-203bf76c-bf22-4753-b660-e03851a72936 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2357991715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2357991715 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3363913662 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 33709142 ps |
| CPU time | 1.13 seconds |
| Started | May 21 02:34:58 PM PDT 24 |
| Finished | May 21 02:35:14 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-420d70eb-86e0-4bc1-87ae-c2774a92922a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363913662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3363913662 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2701500250 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1088784635 ps |
| CPU time | 44.68 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:36:03 PM PDT 24 |
| Peak memory | 203896 kb |
| Host | smart-b341fb23-7d8f-495b-bbf5-373c407d7096 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2701500250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2701500250 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3444000425 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1434425334 ps |
| CPU time | 22.49 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:35:41 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-a1a9f559-91fb-4802-9b4f-6de6cc9236e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444000425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3444000425 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.881729834 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 7470137 ps |
| CPU time | 3.1 seconds |
| Started | May 21 02:35:00 PM PDT 24 |
| Finished | May 21 02:35:20 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-a74d8a99-891b-4f62-a256-3b3817dcb325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=881729834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.881729834 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.718715711 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1651947741 ps |
| CPU time | 126.62 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:37:24 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-a29c10b0-401d-45b8-9247-a02a42ebef22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=718715711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res et_error.718715711 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1409977546 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 476160877 ps |
| CPU time | 6.05 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:35:24 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-4be357a3-1db2-4d17-893c-c1bb8fd64ba9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1409977546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1409977546 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2725727104 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 78837976 ps |
| CPU time | 8.08 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:35:36 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-c137f1ee-f6a7-427f-870c-58fce76fab0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2725727104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2725727104 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2825424509 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 30180577393 ps |
| CPU time | 211.3 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:38:57 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-8c3ba804-f699-479d-9ff6-06c9e857e052 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2825424509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2825424509 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2268292073 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 58382872 ps |
| CPU time | 5.2 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:35:32 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-637ca4ba-279a-4e90-9347-5a2eb87ce6f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2268292073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2268292073 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2691289320 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 40301471 ps |
| CPU time | 3.44 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:35:32 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-f178a922-4676-4d6f-a1c7-4d3455572f74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2691289320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2691289320 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.1561874276 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 847194062 ps |
| CPU time | 14.85 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:35:33 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-15da7b75-a116-4d64-b261-9130eb9e16e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1561874276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1561874276 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2796947647 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 21619528412 ps |
| CPU time | 79.27 seconds |
| Started | May 21 02:34:59 PM PDT 24 |
| Finished | May 21 02:36:35 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-802c4f9e-5374-4076-bfe3-19ed11192642 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796947647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2796947647 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3604206251 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2340130435 ps |
| CPU time | 7.57 seconds |
| Started | May 21 02:35:06 PM PDT 24 |
| Finished | May 21 02:35:33 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-e8f77f33-73d3-4e98-9308-249506179609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3604206251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3604206251 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2517634841 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 44164099 ps |
| CPU time | 6.26 seconds |
| Started | May 21 02:35:00 PM PDT 24 |
| Finished | May 21 02:35:22 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-b2b0eeeb-6cc0-4f22-bfba-1fe95d51b25d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517634841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2517634841 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.766750517 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 40450707 ps |
| CPU time | 2.87 seconds |
| Started | May 21 02:35:09 PM PDT 24 |
| Finished | May 21 02:35:33 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-88f335c1-7cdf-4d50-a53e-159887d41496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=766750517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.766750517 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.4291688615 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 81094891 ps |
| CPU time | 1.59 seconds |
| Started | May 21 02:35:03 PM PDT 24 |
| Finished | May 21 02:35:23 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-568e7dad-304c-408d-a724-92963ebeb219 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4291688615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4291688615 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1796941361 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2766097147 ps |
| CPU time | 9.15 seconds |
| Started | May 21 02:34:59 PM PDT 24 |
| Finished | May 21 02:35:24 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-7176b35b-455f-4a8c-a842-95097205835b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796941361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1796941361 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1880785239 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2149859994 ps |
| CPU time | 8.51 seconds |
| Started | May 21 02:35:02 PM PDT 24 |
| Finished | May 21 02:35:27 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-9f498d10-aea6-4e36-a25d-4bb9634ffc44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1880785239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1880785239 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3146460263 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8378526 ps |
| CPU time | 1.09 seconds |
| Started | May 21 02:35:01 PM PDT 24 |
| Finished | May 21 02:35:19 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-896b134a-6879-4710-bb95-bc08005052fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146460263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3146460263 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2534128223 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 567914463 ps |
| CPU time | 27.23 seconds |
| Started | May 21 02:35:10 PM PDT 24 |
| Finished | May 21 02:35:58 PM PDT 24 |
| Peak memory | 203200 kb |
| Host | smart-92329bdb-d011-4618-a010-be3cc29b67b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534128223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2534128223 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2997033701 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 3782590818 ps |
| CPU time | 48.26 seconds |
| Started | May 21 02:35:09 PM PDT 24 |
| Finished | May 21 02:36:18 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-2aaf996c-abcc-40c1-bbd7-1228e1f12ee3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2997033701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2997033701 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4018963331 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1165300817 ps |
| CPU time | 147.31 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:37:55 PM PDT 24 |
| Peak memory | 208012 kb |
| Host | smart-349804bc-b571-4c61-8358-5c044626b017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018963331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.4018963331 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1516893677 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2333723771 ps |
| CPU time | 78.51 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:36:47 PM PDT 24 |
| Peak memory | 205196 kb |
| Host | smart-87500bdb-5e8e-46d9-b8bd-d674bb93d215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1516893677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1516893677 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2345818917 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 393178984 ps |
| CPU time | 8.12 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:35:37 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-69bb7095-caf4-499e-ac08-9d150c640c62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345818917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2345818917 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2232408312 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 522405907 ps |
| CPU time | 6.18 seconds |
| Started | May 21 02:35:10 PM PDT 24 |
| Finished | May 21 02:35:37 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-e170e4e8-87f2-48c6-8d54-b09afc3888f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2232408312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2232408312 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2928453390 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 9997207 ps |
| CPU time | 1.04 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:35:29 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-ec12d8ef-a32c-4464-9957-7af641ae5be2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2928453390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2928453390 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.1870608934 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 315825725 ps |
| CPU time | 4.06 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:35:31 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-eb92d033-2b2b-48c8-ba0e-219deb4988c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1870608934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1870608934 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.760263228 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 437326197 ps |
| CPU time | 2.54 seconds |
| Started | May 21 02:35:06 PM PDT 24 |
| Finished | May 21 02:35:28 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-26250c35-120e-4fdc-a9e4-1205b8030a12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760263228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.760263228 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3359588346 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 42454667391 ps |
| CPU time | 112.12 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:37:20 PM PDT 24 |
| Peak memory | 202316 kb |
| Host | smart-3b60eb7a-275b-4ff7-8758-8de8fd14c677 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359588346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3359588346 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3827510370 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 37562866024 ps |
| CPU time | 55.32 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:36:22 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-bd2d2232-e1a5-4762-96e3-5bb875f76679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3827510370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3827510370 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3342308072 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 37368544 ps |
| CPU time | 3.89 seconds |
| Started | May 21 02:35:06 PM PDT 24 |
| Finished | May 21 02:35:29 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-4454c5d0-ef77-4d80-95cd-488c434331a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342308072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3342308072 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.2245166151 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 412419724 ps |
| CPU time | 5.08 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:35:32 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-7dff3816-0f62-4196-b10f-594db6b920a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2245166151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2245166151 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.952576778 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 73470832 ps |
| CPU time | 1.75 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:35:30 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-f92f6544-d95b-4ee3-bef4-93df1ca93f2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=952576778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.952576778 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.4186860881 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1275299154 ps |
| CPU time | 6.69 seconds |
| Started | May 21 02:35:07 PM PDT 24 |
| Finished | May 21 02:35:34 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-f12a3844-79b8-4383-95a5-33100dd8be38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186860881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.4186860881 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2364792835 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1645475633 ps |
| CPU time | 10.85 seconds |
| Started | May 21 02:35:06 PM PDT 24 |
| Finished | May 21 02:35:37 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-91d4bd4a-bae5-4a95-b5db-eb2257ca69f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2364792835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2364792835 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3113811433 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 10017788 ps |
| CPU time | 1.32 seconds |
| Started | May 21 02:35:08 PM PDT 24 |
| Finished | May 21 02:35:29 PM PDT 24 |
| Peak memory | 202116 kb |
| Host | smart-73881d5a-ed47-41fb-8669-45cfd3a9086c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113811433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3113811433 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2506063531 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 93220839 ps |
| CPU time | 1.42 seconds |
| Started | May 21 02:35:14 PM PDT 24 |
| Finished | May 21 02:35:36 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-4e3de9af-86fc-4f7b-8d55-d518131ee48f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2506063531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2506063531 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2637436317 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 43910042654 ps |
| CPU time | 109.25 seconds |
| Started | May 21 02:35:15 PM PDT 24 |
| Finished | May 21 02:37:25 PM PDT 24 |
| Peak memory | 204956 kb |
| Host | smart-3dd6d5aa-9434-44d7-9675-fea6cfef3ea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2637436317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2637436317 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2856022326 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6599510309 ps |
| CPU time | 87.91 seconds |
| Started | May 21 02:35:15 PM PDT 24 |
| Finished | May 21 02:37:04 PM PDT 24 |
| Peak memory | 205000 kb |
| Host | smart-1429adc0-bf6e-44de-9080-21f8f0d896eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856022326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2856022326 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.151413838 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4121244608 ps |
| CPU time | 92.48 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:37:13 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-576ea4da-d31f-41d4-b8dd-6f8503bfef0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=151413838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.151413838 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3770264480 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 276687651 ps |
| CPU time | 4.18 seconds |
| Started | May 21 02:35:06 PM PDT 24 |
| Finished | May 21 02:35:30 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-d3ab90ce-8e88-4a55-90bc-249094056f7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3770264480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3770264480 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1758472308 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 649879670 ps |
| CPU time | 5.6 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:35:40 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-7da84d7f-2afd-45df-be70-87396c36ecaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758472308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1758472308 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.748561425 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 134793995003 ps |
| CPU time | 196.19 seconds |
| Started | May 21 02:35:14 PM PDT 24 |
| Finished | May 21 02:38:51 PM PDT 24 |
| Peak memory | 203296 kb |
| Host | smart-28adef81-cf94-49e1-b2e6-9268ec02398f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=748561425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.748561425 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2394372133 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 493784322 ps |
| CPU time | 6.78 seconds |
| Started | May 21 02:35:15 PM PDT 24 |
| Finished | May 21 02:35:43 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-ef7a1a3f-b45a-47ed-a566-3c0be814cc9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394372133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2394372133 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.413063204 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 298240256 ps |
| CPU time | 4.18 seconds |
| Started | May 21 02:35:14 PM PDT 24 |
| Finished | May 21 02:35:39 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-a7d88d6c-55e7-40bf-ae91-dda7ce7fe41e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413063204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.413063204 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.3126988936 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 266458272 ps |
| CPU time | 5.53 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:35:46 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-4b1bf1c0-f87c-4d14-861e-e03f672890e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3126988936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3126988936 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2161936993 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 22685246571 ps |
| CPU time | 109.99 seconds |
| Started | May 21 02:35:14 PM PDT 24 |
| Finished | May 21 02:37:25 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-15fe60e4-6999-44e1-8662-1c9059cd4df1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161936993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2161936993 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1206804079 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 17947593412 ps |
| CPU time | 82.21 seconds |
| Started | May 21 02:35:17 PM PDT 24 |
| Finished | May 21 02:37:01 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-245ee145-d0a3-4139-b062-36daa0464653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1206804079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1206804079 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1298664930 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 47420534 ps |
| CPU time | 4.26 seconds |
| Started | May 21 02:35:12 PM PDT 24 |
| Finished | May 21 02:35:37 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-d75341cc-26bb-49d0-b18e-a57e481cda94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298664930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1298664930 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.1595625856 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 788948059 ps |
| CPU time | 7.48 seconds |
| Started | May 21 02:35:12 PM PDT 24 |
| Finished | May 21 02:35:40 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-d3ee85e7-3464-4b42-8250-17f29ecf7209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1595625856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1595625856 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3110555572 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 222049155 ps |
| CPU time | 1.77 seconds |
| Started | May 21 02:35:16 PM PDT 24 |
| Finished | May 21 02:35:39 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-aea1693e-f02d-4567-b390-1e6acd327f01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3110555572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3110555572 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1421570449 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1586884174 ps |
| CPU time | 6.55 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:35:41 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-ce7c4fe0-4064-4606-bf8e-86e30641485f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421570449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1421570449 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3889705226 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 4890884645 ps |
| CPU time | 8.49 seconds |
| Started | May 21 02:35:17 PM PDT 24 |
| Finished | May 21 02:35:47 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-d059941e-a1d0-45cb-8402-dc8d2c283621 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3889705226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3889705226 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1989281712 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 11551823 ps |
| CPU time | 1.05 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:35:35 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-39b26ce4-2f4e-481d-b52c-81423038a4e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989281712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1989281712 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3142791776 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2661830516 ps |
| CPU time | 36.74 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:36:11 PM PDT 24 |
| Peak memory | 204288 kb |
| Host | smart-3dc3a216-f516-47b2-a603-e1edd5d8f7ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142791776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3142791776 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1708890080 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 10983576933 ps |
| CPU time | 24.16 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:35:58 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-15581189-2bf3-445d-af12-3a54a1150a8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708890080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1708890080 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.235837058 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 267920156 ps |
| CPU time | 84.24 seconds |
| Started | May 21 02:35:14 PM PDT 24 |
| Finished | May 21 02:36:59 PM PDT 24 |
| Peak memory | 204832 kb |
| Host | smart-4aec901d-48ad-429c-834e-2b729d863003 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=235837058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.235837058 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.916812821 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 72713376 ps |
| CPU time | 8.73 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-74dfd0f4-df2a-449e-9b1c-7624d08d893a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=916812821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.916812821 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.579822465 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 495102137 ps |
| CPU time | 2.6 seconds |
| Started | May 21 02:35:17 PM PDT 24 |
| Finished | May 21 02:35:41 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-b733cad3-23a2-492c-8cd9-b46c19c115b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579822465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.579822465 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3022188117 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2794025506 ps |
| CPU time | 22.35 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:36:03 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-8a054216-a337-4d62-a0c5-c7832c4aebcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3022188117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3022188117 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1562029980 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2762605179 ps |
| CPU time | 19.22 seconds |
| Started | May 21 02:35:20 PM PDT 24 |
| Finished | May 21 02:36:01 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-b5e191b8-3c2c-4209-95b9-1626543e706d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1562029980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1562029980 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.5928556 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 476290612 ps |
| CPU time | 8.31 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-ed554a1f-9181-43d5-8937-07ae11212467 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=5928556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.5928556 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.18353302 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1125977317 ps |
| CPU time | 12.28 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:52 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-2e7dbd8e-e9d3-4769-8829-e6081fd333f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18353302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.18353302 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2865136778 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 920927856 ps |
| CPU time | 8.43 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:47 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-fd3c4acb-b042-445c-b163-7e641885b9cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2865136778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2865136778 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1164355556 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 41076975511 ps |
| CPU time | 132.85 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:37:47 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-9bed33c0-939a-4d83-a94f-fd5e49107849 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164355556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1164355556 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3548281446 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 37435686457 ps |
| CPU time | 143.38 seconds |
| Started | May 21 02:35:20 PM PDT 24 |
| Finished | May 21 02:38:05 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-4c6c76d7-9492-4b72-95b7-a400f4d9e01f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3548281446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3548281446 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.59481008 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 16068305 ps |
| CPU time | 2.26 seconds |
| Started | May 21 02:35:12 PM PDT 24 |
| Finished | May 21 02:35:35 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-510c1859-6053-4a55-8a14-e65e6e389cad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59481008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.59481008 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.1657534160 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 38462900 ps |
| CPU time | 2.11 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:42 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-16d4c237-1748-4587-bd9b-beb6d351a17c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1657534160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1657534160 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1435647743 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 8821819 ps |
| CPU time | 1.09 seconds |
| Started | May 21 02:35:12 PM PDT 24 |
| Finished | May 21 02:35:35 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-60d73a7c-e420-4ea6-87b9-7a058e3bdaca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1435647743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1435647743 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1933626689 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2445764279 ps |
| CPU time | 8.79 seconds |
| Started | May 21 02:35:17 PM PDT 24 |
| Finished | May 21 02:35:47 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-73152e9c-6335-44db-b705-cbbd4965558f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933626689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1933626689 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1592505860 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3706437955 ps |
| CPU time | 11.66 seconds |
| Started | May 21 02:35:12 PM PDT 24 |
| Finished | May 21 02:35:44 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-df7d2d1e-2127-4626-8b69-b2f8df062f4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1592505860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1592505860 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1171993360 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 10700130 ps |
| CPU time | 1.01 seconds |
| Started | May 21 02:35:13 PM PDT 24 |
| Finished | May 21 02:35:35 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-4482a346-8145-471d-8616-d29c897cee54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171993360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1171993360 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3591095777 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 6649678390 ps |
| CPU time | 79.45 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 203296 kb |
| Host | smart-e4c1566b-0841-4e35-aa4a-680fa4a3b67f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3591095777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3591095777 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1892063584 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 323915760 ps |
| CPU time | 5.7 seconds |
| Started | May 21 02:35:20 PM PDT 24 |
| Finished | May 21 02:35:47 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-987becfe-e48a-495c-b40c-4458a4169c2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1892063584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1892063584 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.713831441 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 119425787 ps |
| CPU time | 18.79 seconds |
| Started | May 21 02:35:20 PM PDT 24 |
| Finished | May 21 02:36:01 PM PDT 24 |
| Peak memory | 203244 kb |
| Host | smart-0cf11e11-bf47-4d25-a2ce-5c11fffc5449 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=713831441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.713831441 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.742158010 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 8566837272 ps |
| CPU time | 154.22 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:38:15 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-c3e0d3bb-98e5-44f5-b940-d2791db7881b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742158010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.742158010 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2435726881 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 840170085 ps |
| CPU time | 10.79 seconds |
| Started | May 21 02:35:21 PM PDT 24 |
| Finished | May 21 02:35:53 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-15f73f3d-0f0b-4046-9317-16119eadfaaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2435726881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2435726881 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1277418095 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 19509190 ps |
| CPU time | 1.6 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:35:42 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-c6524b45-dc08-4b60-b1d4-e3e8c4aa9cf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1277418095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1277418095 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1970797074 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 19157331224 ps |
| CPU time | 111.51 seconds |
| Started | May 21 02:35:20 PM PDT 24 |
| Finished | May 21 02:37:33 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-5db715ee-6a02-4a44-8a35-e4be30da37c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1970797074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.1970797074 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4264678186 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 49495336 ps |
| CPU time | 4.79 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:45 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-0ec098d1-980b-43a3-a4bd-2096a526ed6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4264678186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.4264678186 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.1502181324 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 229606334 ps |
| CPU time | 4.64 seconds |
| Started | May 21 02:35:24 PM PDT 24 |
| Finished | May 21 02:35:50 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-8ff544d8-ed0c-4c5a-ab96-8b0ec5b40560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1502181324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1502181324 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.1096670712 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5350000747 ps |
| CPU time | 18.72 seconds |
| Started | May 21 02:35:21 PM PDT 24 |
| Finished | May 21 02:36:01 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-a8619ed3-4054-435c-ba82-c2245fb2e174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1096670712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1096670712 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1531053207 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 20925709002 ps |
| CPU time | 86.27 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:37:07 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-5ed3c586-20f1-40bb-9f9a-2644a8fb7862 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531053207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1531053207 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4252219175 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 8559147541 ps |
| CPU time | 34.74 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:36:15 PM PDT 24 |
| Peak memory | 202312 kb |
| Host | smart-e7486d07-b3b9-46df-affe-49fa2dc448e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4252219175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4252219175 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.285420704 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 12527879 ps |
| CPU time | 1.14 seconds |
| Started | May 21 02:35:19 PM PDT 24 |
| Finished | May 21 02:35:42 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-3dfc385b-875a-4a00-a5f4-65571b22b73c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285420704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.285420704 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.1830337272 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 104670112 ps |
| CPU time | 6.26 seconds |
| Started | May 21 02:35:21 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-bc8b15c3-a029-4983-a621-3fac34c36080 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1830337272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1830337272 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3543556464 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 43533123 ps |
| CPU time | 1.56 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:41 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-1fc3c3d6-3320-4c35-bbab-0499a16ede5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3543556464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3543556464 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.496136281 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5277147310 ps |
| CPU time | 11.83 seconds |
| Started | May 21 02:35:22 PM PDT 24 |
| Finished | May 21 02:35:56 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-b719f377-4daa-4abb-ae9d-04602bbb0c31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=496136281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.496136281 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3012107422 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2712849325 ps |
| CPU time | 8.25 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:48 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-c364716c-b30f-467b-ba56-e6584f505855 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3012107422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3012107422 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1553835800 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 12415883 ps |
| CPU time | 1.12 seconds |
| Started | May 21 02:35:18 PM PDT 24 |
| Finished | May 21 02:35:41 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-2c8bd205-c755-4109-85c8-3f619c7c13e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553835800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1553835800 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.873410111 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3994106151 ps |
| CPU time | 45.27 seconds |
| Started | May 21 02:35:22 PM PDT 24 |
| Finished | May 21 02:36:29 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-269685b0-d82c-436b-a572-314cadce23c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=873410111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.873410111 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3094496718 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 18193805570 ps |
| CPU time | 51.7 seconds |
| Started | May 21 02:35:25 PM PDT 24 |
| Finished | May 21 02:36:38 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-112cbb18-7637-446c-a260-579022023fdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094496718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3094496718 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3365451229 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 572356320 ps |
| CPU time | 46.88 seconds |
| Started | May 21 02:35:27 PM PDT 24 |
| Finished | May 21 02:36:34 PM PDT 24 |
| Peak memory | 204432 kb |
| Host | smart-f5249fba-ed3c-4d4b-a3b7-b9561e02b71b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3365451229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3365451229 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1777005643 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1194146073 ps |
| CPU time | 11.84 seconds |
| Started | May 21 02:35:20 PM PDT 24 |
| Finished | May 21 02:35:53 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-3b340822-a29b-42c7-a4d8-e4a67c62f41c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1777005643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1777005643 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2709224873 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 66322039 ps |
| CPU time | 3.3 seconds |
| Started | May 21 02:35:29 PM PDT 24 |
| Finished | May 21 02:35:53 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-76409a7e-6b35-40ef-b4e5-d2e9b0dcb2ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2709224873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2709224873 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1423020078 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 23895275964 ps |
| CPU time | 176.16 seconds |
| Started | May 21 02:35:26 PM PDT 24 |
| Finished | May 21 02:38:44 PM PDT 24 |
| Peak memory | 203280 kb |
| Host | smart-cf3f2c7d-53b8-4e9a-b9ca-367e4cd85d0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1423020078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.1423020078 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.762125531 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 503026963 ps |
| CPU time | 6.5 seconds |
| Started | May 21 02:35:33 PM PDT 24 |
| Finished | May 21 02:35:59 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-1428e3e3-3c5f-47dd-89ff-c539b01a751d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762125531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.762125531 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.4203668310 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 757214264 ps |
| CPU time | 7.87 seconds |
| Started | May 21 02:35:27 PM PDT 24 |
| Finished | May 21 02:35:55 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-16a2ecfb-3e2a-4b25-a168-b9581f8fe191 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4203668310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4203668310 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.2428946455 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 639442950 ps |
| CPU time | 6.64 seconds |
| Started | May 21 02:35:25 PM PDT 24 |
| Finished | May 21 02:35:53 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-476271f6-54dd-4b2e-9387-0f98781081a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2428946455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2428946455 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3996937317 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 86138542344 ps |
| CPU time | 126.13 seconds |
| Started | May 21 02:35:26 PM PDT 24 |
| Finished | May 21 02:37:53 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-c222f72c-d44e-48f8-b427-5b8f35ea07c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996937317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3996937317 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2835714676 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 9692514886 ps |
| CPU time | 39.49 seconds |
| Started | May 21 02:35:25 PM PDT 24 |
| Finished | May 21 02:36:26 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-8d32ac40-348f-488a-bc2a-252b7d64b132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2835714676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2835714676 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3109637894 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 53872530 ps |
| CPU time | 5.1 seconds |
| Started | May 21 02:35:25 PM PDT 24 |
| Finished | May 21 02:35:51 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-3150a27c-f2c4-4a53-95cb-0757e05dbfb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109637894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3109637894 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3407940579 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 349166258 ps |
| CPU time | 4.2 seconds |
| Started | May 21 02:35:26 PM PDT 24 |
| Finished | May 21 02:35:52 PM PDT 24 |
| Peak memory | 201980 kb |
| Host | smart-74819ffe-9caf-46ce-b9ed-d038a59b31dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3407940579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3407940579 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.3551554310 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 60166179 ps |
| CPU time | 1.76 seconds |
| Started | May 21 02:35:31 PM PDT 24 |
| Finished | May 21 02:35:54 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-b82cd140-b929-43ea-ae28-f9f8f7670aa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3551554310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3551554310 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2307093336 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2326869517 ps |
| CPU time | 9.71 seconds |
| Started | May 21 02:35:25 PM PDT 24 |
| Finished | May 21 02:35:56 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-df2959d3-29bd-446c-9122-a9a927cdba48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307093336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2307093336 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2104782103 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 5829003234 ps |
| CPU time | 12.8 seconds |
| Started | May 21 02:35:26 PM PDT 24 |
| Finished | May 21 02:36:00 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-534b7f82-6b51-4e1a-a5df-1e8756523609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2104782103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2104782103 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.922617689 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 10312274 ps |
| CPU time | 1.16 seconds |
| Started | May 21 02:35:26 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-e365f641-5cbf-40eb-a3c8-0be3bf556cec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922617689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.922617689 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2211109502 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 827048568 ps |
| CPU time | 44.38 seconds |
| Started | May 21 02:35:33 PM PDT 24 |
| Finished | May 21 02:36:37 PM PDT 24 |
| Peak memory | 204020 kb |
| Host | smart-3755ec96-07db-4095-a1b4-827e537cd29c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211109502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2211109502 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.254128837 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 205988304 ps |
| CPU time | 23.34 seconds |
| Started | May 21 02:35:31 PM PDT 24 |
| Finished | May 21 02:36:15 PM PDT 24 |
| Peak memory | 203224 kb |
| Host | smart-38eca2e1-6ffb-4c7b-b651-5f9c228a2656 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=254128837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.254128837 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.938724530 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 319310406 ps |
| CPU time | 37.23 seconds |
| Started | May 21 02:35:32 PM PDT 24 |
| Finished | May 21 02:36:29 PM PDT 24 |
| Peak memory | 204540 kb |
| Host | smart-f3fe65d8-b6ee-4085-bece-3b49e7b5efcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=938724530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.938724530 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1489063510 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 914645491 ps |
| CPU time | 163.64 seconds |
| Started | May 21 02:35:35 PM PDT 24 |
| Finished | May 21 02:38:38 PM PDT 24 |
| Peak memory | 209020 kb |
| Host | smart-554b5741-245c-4d10-8259-aff6cc7c601d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1489063510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1489063510 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2577108596 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 73829488 ps |
| CPU time | 1.13 seconds |
| Started | May 21 02:35:26 PM PDT 24 |
| Finished | May 21 02:35:49 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-9ab8f7b5-7766-4da2-80e5-7edfb9a4f6bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2577108596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2577108596 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2668714456 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 341280745 ps |
| CPU time | 4.99 seconds |
| Started | May 21 02:35:31 PM PDT 24 |
| Finished | May 21 02:35:57 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-20da3caa-4a16-4409-97e4-7f6957d545f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2668714456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2668714456 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1816031055 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 63240359562 ps |
| CPU time | 182.43 seconds |
| Started | May 21 02:35:32 PM PDT 24 |
| Finished | May 21 02:38:55 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-76c809d4-0fe8-491a-bc97-53763119bf28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1816031055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1816031055 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1191458430 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 76340878 ps |
| CPU time | 3.35 seconds |
| Started | May 21 02:36:03 PM PDT 24 |
| Finished | May 21 02:36:19 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-46344bb5-153a-4720-bfbb-eec8745111ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1191458430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1191458430 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.708324383 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 64750526 ps |
| CPU time | 1.35 seconds |
| Started | May 21 02:35:32 PM PDT 24 |
| Finished | May 21 02:35:53 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-b4d4ac9a-abd1-4b3a-ad8b-e626ec1b7c1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708324383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.708324383 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2963731578 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1299230998 ps |
| CPU time | 13.46 seconds |
| Started | May 21 02:35:30 PM PDT 24 |
| Finished | May 21 02:36:04 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-3556bdc7-838b-4438-938c-a3d51188d0f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2963731578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2963731578 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2065151259 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 58755928154 ps |
| CPU time | 154.19 seconds |
| Started | May 21 02:35:30 PM PDT 24 |
| Finished | May 21 02:38:26 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-2ad5bde5-529e-45eb-8c94-8745e424dfb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065151259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2065151259 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1536192172 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 21269370228 ps |
| CPU time | 116.26 seconds |
| Started | May 21 02:35:31 PM PDT 24 |
| Finished | May 21 02:37:48 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-4b90a634-b0fd-4e5b-9fd3-6039cb25a79b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1536192172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1536192172 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3116090167 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 166090738 ps |
| CPU time | 6.2 seconds |
| Started | May 21 02:35:30 PM PDT 24 |
| Finished | May 21 02:35:57 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-b9d2332c-38ce-4184-aa98-2b4df173ee33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116090167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3116090167 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.4192117664 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 149455413 ps |
| CPU time | 2.6 seconds |
| Started | May 21 02:35:31 PM PDT 24 |
| Finished | May 21 02:35:54 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-777a8cd9-b3a7-40fb-81fc-b34e4c984c2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4192117664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4192117664 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3458908661 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 8983339 ps |
| CPU time | 1.1 seconds |
| Started | May 21 02:35:33 PM PDT 24 |
| Finished | May 21 02:35:54 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-96dd0d22-5e44-4adf-b117-e64e8c729118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3458908661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3458908661 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.62516903 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9776391277 ps |
| CPU time | 11.36 seconds |
| Started | May 21 02:35:30 PM PDT 24 |
| Finished | May 21 02:36:02 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-59c0e340-9848-47b1-a0f2-4a92579f320b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=62516903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.62516903 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.8957395 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 998405698 ps |
| CPU time | 6.12 seconds |
| Started | May 21 02:35:30 PM PDT 24 |
| Finished | May 21 02:35:57 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-b987eaee-32be-45b7-ad6c-fc584b9538f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=8957395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.8957395 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3373442329 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 13421268 ps |
| CPU time | 1.21 seconds |
| Started | May 21 02:35:31 PM PDT 24 |
| Finished | May 21 02:35:54 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-095c67ef-b8ac-4ecb-ae52-4232fffc91f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373442329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3373442329 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.4047942256 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 178709816 ps |
| CPU time | 17.14 seconds |
| Started | May 21 02:35:38 PM PDT 24 |
| Finished | May 21 02:36:15 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-9c824fa8-e785-4bb1-8a32-cb5780fdc227 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4047942256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4047942256 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3594669742 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 5672213756 ps |
| CPU time | 79.84 seconds |
| Started | May 21 02:35:36 PM PDT 24 |
| Finished | May 21 02:37:17 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-333be972-78a9-45e9-8953-82c5870ba500 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3594669742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3594669742 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3930824125 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 450823533 ps |
| CPU time | 50.44 seconds |
| Started | May 21 02:35:37 PM PDT 24 |
| Finished | May 21 02:36:48 PM PDT 24 |
| Peak memory | 204788 kb |
| Host | smart-49c39a04-ae67-4dee-b5c1-c4028ee42df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930824125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.3930824125 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.536289258 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 506704682 ps |
| CPU time | 61.03 seconds |
| Started | May 21 02:35:37 PM PDT 24 |
| Finished | May 21 02:36:59 PM PDT 24 |
| Peak memory | 205544 kb |
| Host | smart-78be122f-78d5-4756-8d09-516e6123fd78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=536289258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.536289258 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3549630601 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 65714787 ps |
| CPU time | 7.25 seconds |
| Started | May 21 02:35:30 PM PDT 24 |
| Finished | May 21 02:35:58 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-6f930386-459d-4538-a8b5-c9dae0ad6aad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549630601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3549630601 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3269244120 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 327678478 ps |
| CPU time | 1.73 seconds |
| Started | May 21 02:33:09 PM PDT 24 |
| Finished | May 21 02:33:29 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-399a635e-7135-4883-9eef-c4667dcfe230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3269244120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3269244120 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1473274856 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 57016957436 ps |
| CPU time | 213.62 seconds |
| Started | May 21 02:33:02 PM PDT 24 |
| Finished | May 21 02:36:55 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-acdd7795-eb8c-4178-b13d-d972405e4723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1473274856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1473274856 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2866630840 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 266560779 ps |
| CPU time | 3.49 seconds |
| Started | May 21 02:33:08 PM PDT 24 |
| Finished | May 21 02:33:30 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-2abc91c2-1074-4d99-904d-de743f3753eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866630840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2866630840 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.4078979250 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 683049009 ps |
| CPU time | 9.1 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:41 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-4323f213-b694-4e89-bbf0-dca4b8287b55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078979250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4078979250 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.669765098 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 80183577 ps |
| CPU time | 5.87 seconds |
| Started | May 21 02:33:08 PM PDT 24 |
| Finished | May 21 02:33:32 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-74ba3cc3-40c3-4b4b-b2cd-65773bda97b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=669765098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.669765098 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.4028147246 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 31741428971 ps |
| CPU time | 115.65 seconds |
| Started | May 21 02:33:10 PM PDT 24 |
| Finished | May 21 02:35:24 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-e8f79cf0-1c14-4be4-9766-b73f88cd2d59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028147246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.4028147246 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.585040491 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 105762880082 ps |
| CPU time | 173.23 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:36:16 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-a89b4d09-855a-4b6b-bb6f-33006b69e7f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=585040491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.585040491 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1712318808 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 11634957 ps |
| CPU time | 1.43 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:24 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-f7bcee69-0dfb-476a-b01e-cbfd7b5ae9ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712318808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1712318808 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.1847534157 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 32655120 ps |
| CPU time | 2.18 seconds |
| Started | May 21 02:33:05 PM PDT 24 |
| Finished | May 21 02:33:26 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-8b6abfe2-b41a-410b-acbd-ec1f98ea3569 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847534157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1847534157 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.3386319769 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 8781996 ps |
| CPU time | 1.16 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:24 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-5540ddcc-741c-44b1-bc01-afc2156da9e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386319769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3386319769 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2256406188 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 8752701972 ps |
| CPU time | 7.64 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:30 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-6fa0d704-7b31-4f85-a5b3-918f76d7b7a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256406188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2256406188 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1932296932 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1580607778 ps |
| CPU time | 11.08 seconds |
| Started | May 21 02:33:04 PM PDT 24 |
| Finished | May 21 02:33:35 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-01f83017-6ff5-4c08-aa77-c7756edcfac7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1932296932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1932296932 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2426055533 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 10820822 ps |
| CPU time | 1.21 seconds |
| Started | May 21 02:33:07 PM PDT 24 |
| Finished | May 21 02:33:26 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-72b80969-4cfc-4b0f-929b-16a0b8600e88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426055533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2426055533 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1948690215 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 547661390 ps |
| CPU time | 36.5 seconds |
| Started | May 21 02:33:04 PM PDT 24 |
| Finished | May 21 02:33:59 PM PDT 24 |
| Peak memory | 204196 kb |
| Host | smart-1b0e76c2-3c15-48fc-af08-045c0b5e48f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1948690215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1948690215 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2496607613 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5639812549 ps |
| CPU time | 72.2 seconds |
| Started | May 21 02:33:04 PM PDT 24 |
| Finished | May 21 02:34:36 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-e3bea0ce-2060-489f-80e9-6c5ac0ac7c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496607613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2496607613 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.208480057 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 254993131 ps |
| CPU time | 40.7 seconds |
| Started | May 21 02:33:02 PM PDT 24 |
| Finished | May 21 02:34:02 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-f424af00-e00c-4d75-a861-9354c5f6d7ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=208480057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.208480057 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1947758483 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 448509059 ps |
| CPU time | 41.97 seconds |
| Started | May 21 02:33:14 PM PDT 24 |
| Finished | May 21 02:34:15 PM PDT 24 |
| Peak memory | 204000 kb |
| Host | smart-7d51801d-4824-4c53-a241-1b9ffd4559bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1947758483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1947758483 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2304204196 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 49133942 ps |
| CPU time | 3.37 seconds |
| Started | May 21 02:33:03 PM PDT 24 |
| Finished | May 21 02:33:26 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-bee888f1-93e0-400f-a0a5-526c9ebe80a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304204196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2304204196 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.294421595 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 53597957 ps |
| CPU time | 10.74 seconds |
| Started | May 21 02:35:41 PM PDT 24 |
| Finished | May 21 02:36:10 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-54110cb7-cdb7-4cb0-9bec-441d002ce655 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=294421595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.294421595 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.83670053 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 48900437180 ps |
| CPU time | 331.59 seconds |
| Started | May 21 02:35:36 PM PDT 24 |
| Finished | May 21 02:41:28 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-2a18f37e-ddeb-4143-816d-8e3ab8898a08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=83670053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow _rsp.83670053 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.730288499 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 65508901 ps |
| CPU time | 6.31 seconds |
| Started | May 21 02:35:41 PM PDT 24 |
| Finished | May 21 02:36:06 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-d7771e04-5460-4fb1-955c-213e77cf5508 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=730288499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.730288499 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.977502677 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 136885200 ps |
| CPU time | 2.53 seconds |
| Started | May 21 02:35:36 PM PDT 24 |
| Finished | May 21 02:35:59 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-c59de0c0-cbef-4249-a3d3-66c62cc36516 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=977502677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.977502677 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.655576590 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 121884418 ps |
| CPU time | 8.7 seconds |
| Started | May 21 02:35:41 PM PDT 24 |
| Finished | May 21 02:36:08 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-71d088fe-b899-4ec5-9e75-61aed873c822 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=655576590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.655576590 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.897469159 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 96407517367 ps |
| CPU time | 81.73 seconds |
| Started | May 21 02:35:36 PM PDT 24 |
| Finished | May 21 02:37:18 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-d9f895c0-a415-4b7d-8de5-e7100a480251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=897469159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.897469159 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.397959563 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 52067901102 ps |
| CPU time | 85.69 seconds |
| Started | May 21 02:35:37 PM PDT 24 |
| Finished | May 21 02:37:23 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-a9eb7a28-8ac8-4f94-a38e-a1aabe1e0e28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=397959563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.397959563 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.4292373801 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 8783525 ps |
| CPU time | 1.3 seconds |
| Started | May 21 02:35:37 PM PDT 24 |
| Finished | May 21 02:35:59 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-0cb3b52e-619e-4048-be9d-be9fcda9a616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292373801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.4292373801 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.4235719302 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2399700282 ps |
| CPU time | 14.2 seconds |
| Started | May 21 02:35:38 PM PDT 24 |
| Finished | May 21 02:36:12 PM PDT 24 |
| Peak memory | 202444 kb |
| Host | smart-c771470c-4767-43fa-9508-46268f794a5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4235719302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4235719302 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.486283329 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 80219856 ps |
| CPU time | 1.36 seconds |
| Started | May 21 02:35:37 PM PDT 24 |
| Finished | May 21 02:35:59 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-91dfb869-3ad5-4f6e-9687-c4aaceb2972d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486283329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.486283329 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1570580851 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2204303167 ps |
| CPU time | 7.64 seconds |
| Started | May 21 02:35:36 PM PDT 24 |
| Finished | May 21 02:36:04 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-13f297d6-4c97-440a-9f39-f53930fb765f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570580851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1570580851 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3502059069 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3018434549 ps |
| CPU time | 10.27 seconds |
| Started | May 21 02:35:39 PM PDT 24 |
| Finished | May 21 02:36:08 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-dcaff3d0-f21c-4392-9e4e-1eb672119766 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3502059069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3502059069 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2107377656 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 17452384 ps |
| CPU time | 1.15 seconds |
| Started | May 21 02:35:37 PM PDT 24 |
| Finished | May 21 02:35:58 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-8726426c-1ad5-4a69-adcd-eabd9f5a9c94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107377656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2107377656 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2733621455 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2945969737 ps |
| CPU time | 36.71 seconds |
| Started | May 21 02:35:43 PM PDT 24 |
| Finished | May 21 02:36:38 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-d4df7709-0977-4e84-80f5-8b14979c7e53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2733621455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2733621455 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3202223356 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9828009182 ps |
| CPU time | 56.86 seconds |
| Started | May 21 02:35:44 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-dfddca78-8603-4b0f-bc34-0ce2ffe7b8a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3202223356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3202223356 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2208960477 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3831766818 ps |
| CPU time | 84.42 seconds |
| Started | May 21 02:35:44 PM PDT 24 |
| Finished | May 21 02:37:27 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-0b650777-661d-4398-87ae-29391a73a7c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2208960477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2208960477 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1289311469 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 12002321 ps |
| CPU time | 1.35 seconds |
| Started | May 21 02:35:43 PM PDT 24 |
| Finished | May 21 02:36:04 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-768f6ef0-c104-4bfe-a3f9-71dc45d45b69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289311469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1289311469 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2134265200 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 252818204 ps |
| CPU time | 3.73 seconds |
| Started | May 21 02:35:41 PM PDT 24 |
| Finished | May 21 02:36:03 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-0bcde5d4-74e0-42b7-b459-2283d9f0eb3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2134265200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2134265200 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3927580459 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 28191790 ps |
| CPU time | 3.25 seconds |
| Started | May 21 02:35:53 PM PDT 24 |
| Finished | May 21 02:36:12 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-080f8af2-62b0-429f-b154-f9a0882e56de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3927580459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3927580459 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3598080038 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 7120441357 ps |
| CPU time | 52.13 seconds |
| Started | May 21 02:35:49 PM PDT 24 |
| Finished | May 21 02:36:58 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-634b6292-3323-4096-bad6-ffc29cc74ce3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3598080038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.3598080038 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1295987654 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1196694409 ps |
| CPU time | 7.68 seconds |
| Started | May 21 02:35:50 PM PDT 24 |
| Finished | May 21 02:36:14 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-ca097801-94b4-4568-bd69-0d6ee55473b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1295987654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1295987654 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.1071456140 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 496098739 ps |
| CPU time | 6.01 seconds |
| Started | May 21 02:35:50 PM PDT 24 |
| Finished | May 21 02:36:13 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-e45214ec-b0d8-4e0c-b226-8b51a3c0a4e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1071456140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1071456140 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.1339664451 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 57659358 ps |
| CPU time | 6.53 seconds |
| Started | May 21 02:35:43 PM PDT 24 |
| Finished | May 21 02:36:08 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-afae04df-3db0-4108-9664-7d0f86146db3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1339664451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1339664451 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3156711086 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 7638402609 ps |
| CPU time | 23.57 seconds |
| Started | May 21 02:35:47 PM PDT 24 |
| Finished | May 21 02:36:29 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-eab5798c-e39f-4d71-9e31-a1489c449c24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156711086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3156711086 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.991594379 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2252889372 ps |
| CPU time | 11.87 seconds |
| Started | May 21 02:35:44 PM PDT 24 |
| Finished | May 21 02:36:14 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-cd957d45-0a6f-4fd4-b62a-0dcff86b1c52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=991594379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.991594379 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3944310025 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 203087117 ps |
| CPU time | 6.72 seconds |
| Started | May 21 02:35:43 PM PDT 24 |
| Finished | May 21 02:36:08 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-e0bcea0f-a1de-43d8-a0df-9f3662443e1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944310025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3944310025 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1648449321 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 162128197 ps |
| CPU time | 2.74 seconds |
| Started | May 21 02:35:50 PM PDT 24 |
| Finished | May 21 02:36:10 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-0ba30bf6-1a09-48da-8064-74babd7b33e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1648449321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1648449321 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.3524353170 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 62721460 ps |
| CPU time | 1.31 seconds |
| Started | May 21 02:35:43 PM PDT 24 |
| Finished | May 21 02:36:03 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-7fea9bd1-6b79-4f49-9819-41057fd15d95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524353170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3524353170 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3814306239 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3047352820 ps |
| CPU time | 13.59 seconds |
| Started | May 21 02:35:44 PM PDT 24 |
| Finished | May 21 02:36:17 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-7fc16e75-9bfd-4e74-98dc-e3e1f6a02ce9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814306239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3814306239 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3132729845 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 794125546 ps |
| CPU time | 7.09 seconds |
| Started | May 21 02:35:43 PM PDT 24 |
| Finished | May 21 02:36:09 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-26483a71-b87a-485f-96c4-44a303aebb18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3132729845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3132729845 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3880456116 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 18768985 ps |
| CPU time | 1.16 seconds |
| Started | May 21 02:35:42 PM PDT 24 |
| Finished | May 21 02:36:02 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-c9d78143-a75c-4c9c-873e-68f846902fd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880456116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3880456116 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2841976366 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 6417587296 ps |
| CPU time | 44.06 seconds |
| Started | May 21 02:35:51 PM PDT 24 |
| Finished | May 21 02:36:51 PM PDT 24 |
| Peak memory | 203284 kb |
| Host | smart-1475880c-058b-4115-9598-95cb63ead1b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2841976366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2841976366 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2994768772 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 93265160 ps |
| CPU time | 8.61 seconds |
| Started | May 21 02:35:51 PM PDT 24 |
| Finished | May 21 02:36:16 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-074ec448-4308-40b3-a945-e4a4e9eab085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2994768772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2994768772 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1270772017 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 623172960 ps |
| CPU time | 93.39 seconds |
| Started | May 21 02:35:52 PM PDT 24 |
| Finished | May 21 02:37:42 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-e683ca1d-fb4c-487b-a040-865e46954be1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1270772017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1270772017 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4044188348 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 673800640 ps |
| CPU time | 38.55 seconds |
| Started | May 21 02:35:51 PM PDT 24 |
| Finished | May 21 02:36:46 PM PDT 24 |
| Peak memory | 203672 kb |
| Host | smart-511d354f-fced-4414-9a60-d341862a4306 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4044188348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.4044188348 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2435237388 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 163931774 ps |
| CPU time | 5.22 seconds |
| Started | May 21 02:35:52 PM PDT 24 |
| Finished | May 21 02:36:13 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-a4f4f764-00e1-40d7-9e4a-48f28354047a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2435237388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2435237388 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2971194678 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 119728409 ps |
| CPU time | 2.66 seconds |
| Started | May 21 02:35:59 PM PDT 24 |
| Finished | May 21 02:36:16 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-5f6f3613-03ad-4847-9af8-165ba428d3c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971194678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2971194678 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.284687211 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 91189574297 ps |
| CPU time | 326.63 seconds |
| Started | May 21 02:36:00 PM PDT 24 |
| Finished | May 21 02:41:41 PM PDT 24 |
| Peak memory | 203388 kb |
| Host | smart-33b5cac3-4712-46a9-be0a-f8ceeb1f7a83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=284687211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.284687211 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3693348050 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 15652255 ps |
| CPU time | 1.37 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:36:12 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-76c51f78-3cf0-429e-b0f3-7d7e732fb277 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3693348050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3693348050 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.2028334820 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 484782250 ps |
| CPU time | 8.05 seconds |
| Started | May 21 02:36:00 PM PDT 24 |
| Finished | May 21 02:36:22 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-6609c51b-7e12-4303-b0d1-ba25ff435da4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028334820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2028334820 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.1184998218 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 354753246 ps |
| CPU time | 9.32 seconds |
| Started | May 21 02:35:57 PM PDT 24 |
| Finished | May 21 02:36:20 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-29451890-3153-446c-98ac-f5be8a7f1ef5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184998218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1184998218 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.71150638 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 19977519023 ps |
| CPU time | 100.28 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:37:51 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-288706cb-7d63-4506-9145-3a9484e9ba5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=71150638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.71150638 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1907045947 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4788600851 ps |
| CPU time | 31.34 seconds |
| Started | May 21 02:35:57 PM PDT 24 |
| Finished | May 21 02:36:42 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-0ef9d676-21b4-4078-a68f-f627eca3fa8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1907045947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1907045947 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1893426279 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 110608715 ps |
| CPU time | 3.61 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:36:14 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-9f603a55-3f01-4b95-aabc-43f335d995ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893426279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1893426279 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2074525981 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 283344784 ps |
| CPU time | 4.48 seconds |
| Started | May 21 02:35:57 PM PDT 24 |
| Finished | May 21 02:36:16 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-41404d0c-5993-4bd2-aabe-5a0a47e3029c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2074525981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2074525981 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2533486410 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 10870553 ps |
| CPU time | 1.07 seconds |
| Started | May 21 02:35:54 PM PDT 24 |
| Finished | May 21 02:36:10 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-fc2d18ac-7e0c-498b-80fb-51cf19471f4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2533486410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2533486410 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1470399153 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2362830462 ps |
| CPU time | 8.5 seconds |
| Started | May 21 02:35:51 PM PDT 24 |
| Finished | May 21 02:36:15 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-14e481ec-2e7d-49a6-bbd5-66ba77da5118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470399153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1470399153 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3217591580 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1703753907 ps |
| CPU time | 9.53 seconds |
| Started | May 21 02:35:50 PM PDT 24 |
| Finished | May 21 02:36:17 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-9e42f41c-5a8f-4dee-a96e-4ea00803278a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3217591580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3217591580 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2230035799 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 11008192 ps |
| CPU time | 1.14 seconds |
| Started | May 21 02:35:50 PM PDT 24 |
| Finished | May 21 02:36:08 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-113a62bd-bc0a-4e27-a070-54ca0fe342c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230035799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2230035799 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.830939292 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 537115771 ps |
| CPU time | 37.11 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:36:48 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-d25202fa-b10d-4642-8431-f11138527a7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830939292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.830939292 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1284154870 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1965047913 ps |
| CPU time | 27.66 seconds |
| Started | May 21 02:35:57 PM PDT 24 |
| Finished | May 21 02:36:39 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-e89a343d-87a8-438e-96a5-33cdcee6e70a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1284154870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1284154870 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1307245769 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 154866026 ps |
| CPU time | 9.94 seconds |
| Started | May 21 02:35:55 PM PDT 24 |
| Finished | May 21 02:36:21 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-bd3f9fbd-8f94-4229-ae07-86bc0a68eeee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307245769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.1307245769 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4091372195 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 94130007 ps |
| CPU time | 12.59 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:36:23 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-403f7e77-0ae6-4445-a4ad-980b59a50754 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091372195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.4091372195 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.419297522 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 390409587 ps |
| CPU time | 6.92 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:36:18 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-fb11d495-4502-40c2-9bc4-0be1d1782291 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=419297522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.419297522 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1095224871 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 64647593 ps |
| CPU time | 7.53 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:36:25 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-e9e43add-cf76-4634-b5cd-9068f9a314fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1095224871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1095224871 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4129627414 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 99832285384 ps |
| CPU time | 286.99 seconds |
| Started | May 21 02:36:07 PM PDT 24 |
| Finished | May 21 02:41:07 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-f6684003-01f2-49ac-9b75-c16c963d6231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4129627414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.4129627414 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2552559637 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 71618558 ps |
| CPU time | 3.14 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:36:21 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-88b092f0-e072-4e94-b131-24679b7b7109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2552559637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2552559637 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.4103407983 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 761370864 ps |
| CPU time | 8.98 seconds |
| Started | May 21 02:36:04 PM PDT 24 |
| Finished | May 21 02:36:26 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-e8e3ceb4-a4f9-4e2a-b863-96e0baa99da0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4103407983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4103407983 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2215745963 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1478027010 ps |
| CPU time | 7.29 seconds |
| Started | May 21 02:36:04 PM PDT 24 |
| Finished | May 21 02:36:24 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-4e5b0868-1533-4397-ac4e-33bd514d9ca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2215745963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2215745963 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.197845379 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 8237635486 ps |
| CPU time | 16.91 seconds |
| Started | May 21 02:36:03 PM PDT 24 |
| Finished | May 21 02:36:33 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-f81a29f4-2c3a-40c3-add5-6181858eae59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=197845379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.197845379 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1273704202 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 101761303415 ps |
| CPU time | 179.07 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:39:16 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-e62ac1b5-00e7-4d5c-926b-6e716e5a4e6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1273704202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1273704202 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2586218728 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 146362610 ps |
| CPU time | 9.03 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:36:26 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-e84b6acc-ad5c-4d50-b424-eb40e423f2d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586218728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2586218728 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.3210270773 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 318632091 ps |
| CPU time | 1.58 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:36:19 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-e337655f-9a4b-4c60-81d1-a254fe31ad3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3210270773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3210270773 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1910229618 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 9797562 ps |
| CPU time | 1.05 seconds |
| Started | May 21 02:36:00 PM PDT 24 |
| Finished | May 21 02:36:15 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-cec2418c-ae38-4484-99bc-0543ea5f7434 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1910229618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1910229618 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2622287369 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 9174047501 ps |
| CPU time | 7.89 seconds |
| Started | May 21 02:35:56 PM PDT 24 |
| Finished | May 21 02:36:19 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-ce14bfdc-2c29-4c10-9f37-70f961df7e83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622287369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2622287369 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.621566112 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2154685228 ps |
| CPU time | 9.52 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:36:27 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-59d02477-c838-468d-9470-cf246a758d35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=621566112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.621566112 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.296530424 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 24666416 ps |
| CPU time | 1.2 seconds |
| Started | May 21 02:35:55 PM PDT 24 |
| Finished | May 21 02:36:12 PM PDT 24 |
| Peak memory | 202396 kb |
| Host | smart-496c5e1c-6df0-4a6e-ae57-4ec7b1aa004d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296530424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.296530424 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.648828432 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 596635169 ps |
| CPU time | 55.93 seconds |
| Started | May 21 02:36:06 PM PDT 24 |
| Finished | May 21 02:37:15 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-9de97274-0ce8-4bf6-9c32-72eb2e37dd27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=648828432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.648828432 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1920098571 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 7851088642 ps |
| CPU time | 90.74 seconds |
| Started | May 21 02:36:07 PM PDT 24 |
| Finished | May 21 02:37:51 PM PDT 24 |
| Peak memory | 203308 kb |
| Host | smart-fa473bf8-46dc-42a6-bc0c-1f38e42679ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1920098571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1920098571 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3148884618 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1678594895 ps |
| CPU time | 71.12 seconds |
| Started | May 21 02:36:05 PM PDT 24 |
| Finished | May 21 02:37:29 PM PDT 24 |
| Peak memory | 206072 kb |
| Host | smart-47331b4c-81f0-4792-8946-3e3cb91dd67e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3148884618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3148884618 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3524598645 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 618255566 ps |
| CPU time | 8.88 seconds |
| Started | May 21 02:36:03 PM PDT 24 |
| Finished | May 21 02:36:25 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-59e14b25-dd7b-4454-b84e-31b9fa823a82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524598645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3524598645 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2678286576 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 46293184 ps |
| CPU time | 7.48 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:36:28 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-8668cc3f-6b9d-400f-bdd1-60e14035ccac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2678286576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2678286576 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2197545621 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 82397386 ps |
| CPU time | 1.73 seconds |
| Started | May 21 02:36:06 PM PDT 24 |
| Finished | May 21 02:36:21 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-f8c5236d-f9ea-4d54-b51f-6334241971a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2197545621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2197545621 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.929592428 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2241171110 ps |
| CPU time | 12.2 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:36:33 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-e910800e-8847-4563-9a31-a132fcac37a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=929592428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.929592428 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3184179789 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 99095168 ps |
| CPU time | 7.67 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:36:28 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-139c28a8-38f9-4e6c-aef6-84d093b56a5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184179789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3184179789 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4122133967 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 132150954368 ps |
| CPU time | 120.41 seconds |
| Started | May 21 02:36:09 PM PDT 24 |
| Finished | May 21 02:38:23 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-530eaccb-3b93-48b2-8336-f7625c83b36a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122133967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4122133967 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.739313853 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 22570757139 ps |
| CPU time | 155.73 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:38:57 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-b6c53f63-0797-4044-ae2f-491922981dad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=739313853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.739313853 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.428298378 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 40394158 ps |
| CPU time | 5.71 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:36:27 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-7bdfce77-9744-41eb-9f23-72038e5a861b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428298378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.428298378 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.1919994759 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 194576856 ps |
| CPU time | 3.77 seconds |
| Started | May 21 02:36:07 PM PDT 24 |
| Finished | May 21 02:36:23 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-4969de02-4215-4662-9d0e-f900ab74ced4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1919994759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1919994759 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1143696925 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 74568667 ps |
| CPU time | 1.82 seconds |
| Started | May 21 02:36:09 PM PDT 24 |
| Finished | May 21 02:36:24 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-986c39dd-8d26-472f-b106-011dc06ebf78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1143696925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1143696925 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2621778290 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 16596106595 ps |
| CPU time | 13.12 seconds |
| Started | May 21 02:36:11 PM PDT 24 |
| Finished | May 21 02:36:37 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-0be1ac08-f385-4fec-b4ef-5c28a409fa8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621778290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2621778290 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3533970427 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 728519283 ps |
| CPU time | 5.36 seconds |
| Started | May 21 02:36:07 PM PDT 24 |
| Finished | May 21 02:36:26 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-a250b185-0916-4adb-a28f-ef2f9a9e8ccb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3533970427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3533970427 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3144857370 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 37431874 ps |
| CPU time | 1.17 seconds |
| Started | May 21 02:36:07 PM PDT 24 |
| Finished | May 21 02:36:21 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-1be4d47a-db00-430d-ac49-0e71acad478c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144857370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3144857370 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.313599040 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2944889644 ps |
| CPU time | 62.56 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:37:24 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-402d2fed-9cbf-4257-9106-b10434fff6a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313599040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.313599040 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3991641615 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 7893135709 ps |
| CPU time | 112.58 seconds |
| Started | May 21 02:36:14 PM PDT 24 |
| Finished | May 21 02:38:20 PM PDT 24 |
| Peak memory | 203304 kb |
| Host | smart-a43a49d4-5cd9-4af2-875a-5acbf1e67379 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3991641615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3991641615 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2536043783 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 106257307 ps |
| CPU time | 19.51 seconds |
| Started | May 21 02:36:08 PM PDT 24 |
| Finished | May 21 02:36:41 PM PDT 24 |
| Peak memory | 203260 kb |
| Host | smart-ef162ef2-7a8b-4a71-8305-9e9e54b873a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2536043783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.2536043783 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.367609522 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1005358253 ps |
| CPU time | 13.12 seconds |
| Started | May 21 02:36:13 PM PDT 24 |
| Finished | May 21 02:36:40 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-7ab6ea9e-0206-4741-b494-8b14cc86911e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=367609522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.367609522 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3179554491 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 18014671 ps |
| CPU time | 2.12 seconds |
| Started | May 21 02:36:11 PM PDT 24 |
| Finished | May 21 02:36:26 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-a5eae0ca-f281-41ca-905d-2ed09583fbc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3179554491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3179554491 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3686522120 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1147921168 ps |
| CPU time | 18.29 seconds |
| Started | May 21 02:36:15 PM PDT 24 |
| Finished | May 21 02:36:46 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-29ceb4c0-ff53-4be9-8252-9be83db2b26e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3686522120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3686522120 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.836565398 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 25996267034 ps |
| CPU time | 67.97 seconds |
| Started | May 21 02:36:15 PM PDT 24 |
| Finished | May 21 02:37:36 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-46f81e81-f418-4a78-adb4-e874e924429f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=836565398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.836565398 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.930486511 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 328604870 ps |
| CPU time | 5.44 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:36:39 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-d61da4ad-4d30-4e5c-b0d6-9fcff7abf57b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930486511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.930486511 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.389948494 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 771080407 ps |
| CPU time | 9.1 seconds |
| Started | May 21 02:36:15 PM PDT 24 |
| Finished | May 21 02:36:37 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-4db51b96-5be8-4c1e-a8b3-e3be813db88b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=389948494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.389948494 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.3113089149 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 23148968 ps |
| CPU time | 2.38 seconds |
| Started | May 21 02:36:16 PM PDT 24 |
| Finished | May 21 02:36:32 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-b667e8eb-2005-4b81-8bf4-598ce043d447 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3113089149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3113089149 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2178806654 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 216859428492 ps |
| CPU time | 115.15 seconds |
| Started | May 21 02:36:18 PM PDT 24 |
| Finished | May 21 02:38:26 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-1a73efd3-3dd9-4506-b750-4c088d7b1a4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178806654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2178806654 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2180852865 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 24236369048 ps |
| CPU time | 156.94 seconds |
| Started | May 21 02:36:14 PM PDT 24 |
| Finished | May 21 02:39:05 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-9823188d-77b3-4ada-9172-e572735a0958 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2180852865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2180852865 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2113735351 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 303950510 ps |
| CPU time | 5.7 seconds |
| Started | May 21 02:36:13 PM PDT 24 |
| Finished | May 21 02:36:32 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-0e0098da-f81f-46fc-9a4d-b1b5ac1ebd24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113735351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2113735351 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1279939688 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3556185805 ps |
| CPU time | 13.44 seconds |
| Started | May 21 02:36:15 PM PDT 24 |
| Finished | May 21 02:36:42 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-b54151a0-2953-486b-940e-8a1a100c50a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1279939688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1279939688 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.3461237158 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 209065462 ps |
| CPU time | 1.58 seconds |
| Started | May 21 02:36:15 PM PDT 24 |
| Finished | May 21 02:36:30 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-ffa50428-332a-4521-ad33-ce9cec86632b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3461237158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3461237158 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3328548860 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 10394626911 ps |
| CPU time | 9.65 seconds |
| Started | May 21 02:36:14 PM PDT 24 |
| Finished | May 21 02:36:37 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-be51b2a0-221c-4c7e-8dd9-cd8af17d415e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328548860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3328548860 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3507186603 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1034869991 ps |
| CPU time | 4.43 seconds |
| Started | May 21 02:36:18 PM PDT 24 |
| Finished | May 21 02:36:35 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-70e0f77f-ad96-415e-8bfa-480c2607213b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3507186603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3507186603 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4219258660 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 8307266 ps |
| CPU time | 1.13 seconds |
| Started | May 21 02:36:14 PM PDT 24 |
| Finished | May 21 02:36:29 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-35434e48-e226-447a-9c24-ed3b886e5262 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219258660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4219258660 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2539419574 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 743012228 ps |
| CPU time | 13.9 seconds |
| Started | May 21 02:36:20 PM PDT 24 |
| Finished | May 21 02:36:46 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-c4196c44-2afb-42e1-b218-917535d8a298 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2539419574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2539419574 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3175058882 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3858352792 ps |
| CPU time | 65.22 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:37:39 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-4437d0d9-7196-4bea-aa14-e6a8ac55b5a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175058882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3175058882 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2391658416 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 3340090002 ps |
| CPU time | 27.63 seconds |
| Started | May 21 02:36:20 PM PDT 24 |
| Finished | May 21 02:37:05 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-33fa5ee4-1ba5-48d5-9275-817e5e824bd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2391658416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.2391658416 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.541930460 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 690451014 ps |
| CPU time | 107.14 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:38:20 PM PDT 24 |
| Peak memory | 206208 kb |
| Host | smart-32d60c4c-06cb-4020-a7f7-6b562ffbe451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=541930460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res et_error.541930460 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3630824443 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 28463232 ps |
| CPU time | 2.79 seconds |
| Started | May 21 02:36:16 PM PDT 24 |
| Finished | May 21 02:36:32 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-6d745b09-5231-4619-8429-00403632f52c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3630824443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3630824443 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3793079031 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 39186895 ps |
| CPU time | 6.3 seconds |
| Started | May 21 02:36:19 PM PDT 24 |
| Finished | May 21 02:36:37 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-246b77b8-da96-45d5-b77a-367cefb36017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3793079031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3793079031 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.452656808 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 95803530986 ps |
| CPU time | 343.38 seconds |
| Started | May 21 02:36:20 PM PDT 24 |
| Finished | May 21 02:42:15 PM PDT 24 |
| Peak memory | 204068 kb |
| Host | smart-aa72a27b-2e45-48ab-b640-5426b9460bf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=452656808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.452656808 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3679226115 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 181087548 ps |
| CPU time | 3.19 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:36:37 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-9668c06b-287a-42da-991c-f7046097d337 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679226115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3679226115 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1041750633 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 135021400 ps |
| CPU time | 4.51 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:36:38 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-0003f692-d0e4-405c-9dc2-75a2a1db452f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1041750633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1041750633 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.274106707 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 393376947 ps |
| CPU time | 3.94 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:36:38 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-a8cb9b82-23d0-47fe-abf3-3be621c1b798 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=274106707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.274106707 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2462876623 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 101421387262 ps |
| CPU time | 158.79 seconds |
| Started | May 21 02:36:20 PM PDT 24 |
| Finished | May 21 02:39:11 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-63b34da3-d168-47f5-b2c5-3e35b0d8599c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462876623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2462876623 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1019904134 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 32129154449 ps |
| CPU time | 90.01 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:38:03 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-f1ca195e-05b0-4707-8c18-c40b5ac0ef7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1019904134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1019904134 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.194735563 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 56109437 ps |
| CPU time | 7.04 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:36:40 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-d4a3bfe4-542c-4375-898b-86402cf7c643 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194735563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.194735563 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.1336888082 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 1091280398 ps |
| CPU time | 13.25 seconds |
| Started | May 21 02:36:19 PM PDT 24 |
| Finished | May 21 02:36:44 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-dd6ac41b-aa69-4b23-b775-ffa0f4d131c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1336888082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1336888082 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.476225807 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 8128324 ps |
| CPU time | 1.06 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:36:35 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-f3b6b81c-986f-4dea-9f4c-d8c41f5961f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=476225807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.476225807 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2117871363 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3806990672 ps |
| CPU time | 12.25 seconds |
| Started | May 21 02:36:19 PM PDT 24 |
| Finished | May 21 02:36:43 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-cd1d1353-822a-49f4-b54e-efacde798905 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117871363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2117871363 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1253744675 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1370076089 ps |
| CPU time | 5.55 seconds |
| Started | May 21 02:36:20 PM PDT 24 |
| Finished | May 21 02:36:43 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-9a32f44a-724a-4a7a-9a60-5cd466a71976 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1253744675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1253744675 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1886559907 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 9463130 ps |
| CPU time | 0.98 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:36:34 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-bea8e0c6-4dbf-4a87-b980-13869a1412bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886559907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1886559907 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2101076960 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 438477956 ps |
| CPU time | 36.34 seconds |
| Started | May 21 02:36:21 PM PDT 24 |
| Finished | May 21 02:37:09 PM PDT 24 |
| Peak memory | 202324 kb |
| Host | smart-d948ab3c-b2b9-4867-9d9a-4fa8ebda1f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101076960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2101076960 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1037998081 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 442124043 ps |
| CPU time | 35.53 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:37:09 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-eb797dd7-68ce-4373-93d6-40475fe4bd66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037998081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1037998081 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2596891834 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 37324024 ps |
| CPU time | 11.07 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:36:45 PM PDT 24 |
| Peak memory | 203136 kb |
| Host | smart-ab619d52-57c9-48d2-8448-5356706e1e2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2596891834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2596891834 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3140338513 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 642763130 ps |
| CPU time | 64.87 seconds |
| Started | May 21 02:36:22 PM PDT 24 |
| Finished | May 21 02:37:39 PM PDT 24 |
| Peak memory | 205476 kb |
| Host | smart-3b24307b-2504-48d1-b277-e954ae112cd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3140338513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3140338513 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3092241757 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 39507890 ps |
| CPU time | 3.33 seconds |
| Started | May 21 02:36:23 PM PDT 24 |
| Finished | May 21 02:36:38 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-3624b659-204b-4e90-a872-789eb60c9438 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3092241757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3092241757 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3029397218 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 43277457 ps |
| CPU time | 7.57 seconds |
| Started | May 21 02:36:28 PM PDT 24 |
| Finished | May 21 02:36:49 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-c32c32d4-3a17-4f47-90a3-ed27d9e8b606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3029397218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3029397218 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3638919288 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 56419857299 ps |
| CPU time | 337.01 seconds |
| Started | May 21 02:36:26 PM PDT 24 |
| Finished | May 21 02:42:15 PM PDT 24 |
| Peak memory | 204348 kb |
| Host | smart-b7e428c1-581d-46ed-922c-dc7640116a66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3638919288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3638919288 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2804703406 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 102973597 ps |
| CPU time | 5.31 seconds |
| Started | May 21 02:36:27 PM PDT 24 |
| Finished | May 21 02:36:45 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-148c81f9-ccdd-4d12-b2eb-30df7c90a84e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2804703406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2804703406 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.695053321 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 146134598 ps |
| CPU time | 3.13 seconds |
| Started | May 21 02:36:28 PM PDT 24 |
| Finished | May 21 02:36:44 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-5ac2f741-5541-4499-8823-343b001e2501 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695053321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.695053321 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2487224054 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1032647732 ps |
| CPU time | 12.05 seconds |
| Started | May 21 02:36:26 PM PDT 24 |
| Finished | May 21 02:36:49 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-f530d3c5-5f7b-4ebc-8359-dfc5e7121cca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2487224054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2487224054 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.248893346 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 10075700124 ps |
| CPU time | 30.99 seconds |
| Started | May 21 02:36:28 PM PDT 24 |
| Finished | May 21 02:37:13 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-9ecb07f4-db1e-46e1-8e95-8140978ab5e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=248893346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.248893346 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2393601628 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3783333622 ps |
| CPU time | 25.13 seconds |
| Started | May 21 02:36:30 PM PDT 24 |
| Finished | May 21 02:37:10 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-fdbc6bf1-37d8-483f-9579-2d89ad205ab4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2393601628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2393601628 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1916439149 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 93504591 ps |
| CPU time | 4.83 seconds |
| Started | May 21 02:36:30 PM PDT 24 |
| Finished | May 21 02:36:50 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-6eaa7ca3-0395-4859-8520-0cf8a0e138d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916439149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1916439149 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.1175578968 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 12046160 ps |
| CPU time | 1.2 seconds |
| Started | May 21 02:36:27 PM PDT 24 |
| Finished | May 21 02:36:41 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-0ab09a6d-7a4c-40c1-8460-164a4b2d75c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1175578968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1175578968 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.79670159 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 132006266 ps |
| CPU time | 1.5 seconds |
| Started | May 21 02:36:30 PM PDT 24 |
| Finished | May 21 02:36:47 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-417224d4-ea0a-4630-a3a0-9f3364b11cf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=79670159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.79670159 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3516267290 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 21240635710 ps |
| CPU time | 12.9 seconds |
| Started | May 21 02:36:28 PM PDT 24 |
| Finished | May 21 02:36:55 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-29c43263-9dba-4b79-8e7d-e8391d83b3b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516267290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3516267290 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3230157486 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2124141898 ps |
| CPU time | 9.48 seconds |
| Started | May 21 02:36:28 PM PDT 24 |
| Finished | May 21 02:36:52 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-25817c2c-ac44-4fb4-93f6-c7c450480755 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3230157486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3230157486 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1184043719 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 31990407 ps |
| CPU time | 1.12 seconds |
| Started | May 21 02:36:31 PM PDT 24 |
| Finished | May 21 02:36:47 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-a7fe8527-17d6-415c-af1d-1273df73ca6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184043719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1184043719 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3972417840 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 805501338 ps |
| CPU time | 37.54 seconds |
| Started | May 21 02:36:28 PM PDT 24 |
| Finished | May 21 02:37:19 PM PDT 24 |
| Peak memory | 203316 kb |
| Host | smart-5319cfe0-8fa9-44dc-a0ed-0071781c88bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3972417840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3972417840 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3633488843 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 94521790 ps |
| CPU time | 1.77 seconds |
| Started | May 21 02:36:27 PM PDT 24 |
| Finished | May 21 02:36:42 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-c03e133d-1a7e-485a-b49e-daa9c2550a5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3633488843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3633488843 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1070456591 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 477584249 ps |
| CPU time | 56.35 seconds |
| Started | May 21 02:36:30 PM PDT 24 |
| Finished | May 21 02:37:41 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-01884b92-c5b1-4223-b81d-169b2bfbbad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1070456591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.1070456591 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.557492071 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1092568198 ps |
| CPU time | 120.27 seconds |
| Started | May 21 02:36:27 PM PDT 24 |
| Finished | May 21 02:38:43 PM PDT 24 |
| Peak memory | 207196 kb |
| Host | smart-43c9dbeb-2743-4ed4-a78f-2e8158634478 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=557492071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_res et_error.557492071 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3472585345 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 192356590 ps |
| CPU time | 3.85 seconds |
| Started | May 21 02:36:27 PM PDT 24 |
| Finished | May 21 02:36:44 PM PDT 24 |
| Peak memory | 202380 kb |
| Host | smart-e0903758-2d56-47db-96b9-ad1421bc353a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3472585345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3472585345 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.567928348 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3499922448 ps |
| CPU time | 18.81 seconds |
| Started | May 21 02:36:37 PM PDT 24 |
| Finished | May 21 02:37:12 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-2767f8e5-105a-4534-bf08-714369e2cbc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=567928348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.567928348 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3653226843 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 26496863895 ps |
| CPU time | 141.84 seconds |
| Started | May 21 02:36:35 PM PDT 24 |
| Finished | May 21 02:39:13 PM PDT 24 |
| Peak memory | 202340 kb |
| Host | smart-4e5e3edb-3759-49b1-8b68-5386dec443a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3653226843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3653226843 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1666737523 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 872527186 ps |
| CPU time | 10.06 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-2acdc95f-6982-455a-b4a0-b5c622e5d833 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1666737523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1666737523 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1880367151 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 526567550 ps |
| CPU time | 8.59 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:37:04 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-d213521e-a7e9-4302-bef2-e106286834cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1880367151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1880367151 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.454892652 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 276938051 ps |
| CPU time | 9.52 seconds |
| Started | May 21 02:36:37 PM PDT 24 |
| Finished | May 21 02:37:03 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-2c92ca74-5cdf-4e4b-a191-a98b5a9e670c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=454892652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.454892652 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2846141061 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 45780458285 ps |
| CPU time | 141.97 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:39:14 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-1f1aa305-9944-4897-83eb-34ea31a7558d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846141061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2846141061 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1589120711 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 40417299604 ps |
| CPU time | 64.64 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:37:54 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-3f715a7f-3364-424f-a3dd-77a24f5fc0f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1589120711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1589120711 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1214962923 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 130702540 ps |
| CPU time | 6.91 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:36:59 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-ec26a821-03fc-4ce6-9d6b-20da1784a918 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214962923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1214962923 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.2352272265 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 70478892 ps |
| CPU time | 6.27 seconds |
| Started | May 21 02:36:38 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-7b65cae3-6fea-4c3d-9a27-8a69b7dbd9ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2352272265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2352272265 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.3414709354 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 14113580 ps |
| CPU time | 1.35 seconds |
| Started | May 21 02:36:26 PM PDT 24 |
| Finished | May 21 02:36:39 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-bdb2f871-cd35-4176-9233-bbf63beb0287 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3414709354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3414709354 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.31588352 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3075948283 ps |
| CPU time | 7.41 seconds |
| Started | May 21 02:36:38 PM PDT 24 |
| Finished | May 21 02:37:01 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-12c4c352-b1c6-496c-9abd-a5c2e938df04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.31588352 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.771264241 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1527383836 ps |
| CPU time | 8.72 seconds |
| Started | May 21 02:36:38 PM PDT 24 |
| Finished | May 21 02:37:03 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-3d5c4034-b156-4eb7-b7a2-d6ab8c4b1e68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=771264241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.771264241 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.573347452 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 11701723 ps |
| CPU time | 1.38 seconds |
| Started | May 21 02:36:27 PM PDT 24 |
| Finished | May 21 02:36:42 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-bfd245a6-cc2f-4fbf-95e1-a403dcf57c5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573347452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.573347452 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.74011498 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2072333622 ps |
| CPU time | 38.79 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:37:31 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-bbfacacb-1db9-4d3d-8fa9-5ced0fb0cdac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=74011498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.74011498 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.353624829 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7488745258 ps |
| CPU time | 42.96 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:37:32 PM PDT 24 |
| Peak memory | 202328 kb |
| Host | smart-5bafe982-bda2-4b64-9781-ad30ca4fb07a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353624829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.353624829 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1136318240 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 249297374 ps |
| CPU time | 31.21 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:37:20 PM PDT 24 |
| Peak memory | 204256 kb |
| Host | smart-f135ff04-7add-4338-869f-a252f46e26f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1136318240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1136318240 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.203646939 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 532504597 ps |
| CPU time | 58.1 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:37:50 PM PDT 24 |
| Peak memory | 204324 kb |
| Host | smart-06af7daa-8b7e-4690-8ed1-135e71427ee1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=203646939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res et_error.203646939 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.884141325 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 62745585 ps |
| CPU time | 5.86 seconds |
| Started | May 21 02:36:39 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-c5a74e63-4566-47ae-963d-f84bd8e7b616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=884141325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.884141325 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3307941899 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 831794405 ps |
| CPU time | 11.15 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:37:03 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-ea6fffe3-25c4-4a66-b5b4-8bf14284e7c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3307941899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3307941899 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1528819528 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 696458789 ps |
| CPU time | 8.97 seconds |
| Started | May 21 02:36:39 PM PDT 24 |
| Finished | May 21 02:37:03 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-3af64e19-67e0-4fe1-a8be-eba9be2d0255 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1528819528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1528819528 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.4204844763 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 14718109 ps |
| CPU time | 1.57 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:36:58 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-16670184-ad15-45e3-865b-81a9dcaa8627 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4204844763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4204844763 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1192681446 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 454238377 ps |
| CPU time | 6.59 seconds |
| Started | May 21 02:36:37 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-5ff8f9e1-db64-4ddb-8684-ad032ef2f556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1192681446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1192681446 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.334446311 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 51598641566 ps |
| CPU time | 140.59 seconds |
| Started | May 21 02:36:35 PM PDT 24 |
| Finished | May 21 02:39:12 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-d3610a06-8a7c-4977-b44d-d51767e72567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=334446311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.334446311 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4216005998 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 27835746481 ps |
| CPU time | 26.21 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:37:18 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-10f6fd64-c143-4f0d-bcdf-d8ba9d5d533a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4216005998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4216005998 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.4073127482 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 29600665 ps |
| CPU time | 3.98 seconds |
| Started | May 21 02:36:39 PM PDT 24 |
| Finished | May 21 02:36:59 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-444a93a4-9291-42fa-9283-cbe85edacb40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073127482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.4073127482 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1288165594 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 51481349 ps |
| CPU time | 6.03 seconds |
| Started | May 21 02:36:39 PM PDT 24 |
| Finished | May 21 02:37:01 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-3529af5a-1660-4d91-ae9d-2df6992908d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1288165594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1288165594 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2126524554 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8348085 ps |
| CPU time | 0.96 seconds |
| Started | May 21 02:36:36 PM PDT 24 |
| Finished | May 21 02:36:53 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-6ee173e2-4dcd-4857-aa53-c5dd027b773d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2126524554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2126524554 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.643096563 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3111118312 ps |
| CPU time | 11.51 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:37:00 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-326967d0-4243-472f-bd4f-7ae258fc7a39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=643096563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.643096563 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.519422321 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 10592769302 ps |
| CPU time | 9 seconds |
| Started | May 21 02:36:34 PM PDT 24 |
| Finished | May 21 02:36:59 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-f4049f2c-e37c-40fb-8b82-4b90215a843c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=519422321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.519422321 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.584032248 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 14982222 ps |
| CPU time | 1.43 seconds |
| Started | May 21 02:36:33 PM PDT 24 |
| Finished | May 21 02:36:50 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-99d5c684-7cfd-4894-b1ba-0145dd8a03af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584032248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.584032248 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.619709960 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 422946585 ps |
| CPU time | 45.77 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:37:42 PM PDT 24 |
| Peak memory | 203208 kb |
| Host | smart-0e3a0c87-5ea6-407d-aed0-8026c753bcb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=619709960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.619709960 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2508233845 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4550635463 ps |
| CPU time | 60.65 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:37:57 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-270d5f7b-d2b0-4b93-952c-29e08305e7cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2508233845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2508233845 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1515764041 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 482423055 ps |
| CPU time | 87.95 seconds |
| Started | May 21 02:36:38 PM PDT 24 |
| Finished | May 21 02:38:22 PM PDT 24 |
| Peak memory | 205632 kb |
| Host | smart-47ac6d71-1803-4b65-8186-2a1883152f74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515764041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1515764041 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2680246661 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 468012950 ps |
| CPU time | 61.9 seconds |
| Started | May 21 02:36:40 PM PDT 24 |
| Finished | May 21 02:37:57 PM PDT 24 |
| Peak memory | 204144 kb |
| Host | smart-c8a27db6-92a6-4979-877f-9e6b5c63a401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2680246661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2680246661 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1198724269 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 147574507 ps |
| CPU time | 2.11 seconds |
| Started | May 21 02:36:40 PM PDT 24 |
| Finished | May 21 02:36:58 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-3dd85546-74de-4c95-b1c9-e91b17f214af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1198724269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1198724269 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2911944892 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 854868867 ps |
| CPU time | 9.4 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:39 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-cc22cc75-84cc-4d8f-8128-9078400315ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2911944892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2911944892 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2990838907 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 73103303381 ps |
| CPU time | 179.33 seconds |
| Started | May 21 02:33:17 PM PDT 24 |
| Finished | May 21 02:36:35 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-dbaaba04-b888-45b5-b175-2a70f237d254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2990838907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2990838907 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2399928689 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 537428420 ps |
| CPU time | 7.61 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:39 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-781e952b-866e-4a3c-aa23-b43fa574c9e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2399928689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2399928689 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3417140354 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 690226837 ps |
| CPU time | 5.92 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-1e3d6e67-a2a1-426f-8b86-847b84363eb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417140354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3417140354 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1865404386 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 586029609 ps |
| CPU time | 7.64 seconds |
| Started | May 21 02:33:14 PM PDT 24 |
| Finished | May 21 02:33:41 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-ea81503b-182c-4048-b976-c0fafbfcd8c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1865404386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1865404386 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1578815585 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 47703537080 ps |
| CPU time | 132.24 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:35:43 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-f0a8d5ae-ead9-4bf7-bf7a-0fb3e5805ded |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578815585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1578815585 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4262480028 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2671695127 ps |
| CPU time | 9.91 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:40 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-25ab0335-1c7a-44d3-92db-68a672f6a1cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4262480028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4262480028 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3458107878 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 28719310 ps |
| CPU time | 3.38 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:34 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-8efc02bf-81b5-458a-8035-b77d1d50c1ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458107878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3458107878 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1094122269 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 14625478 ps |
| CPU time | 1.62 seconds |
| Started | May 21 02:33:17 PM PDT 24 |
| Finished | May 21 02:33:37 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-76814c22-010a-4a3c-9c27-5dab9201521a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1094122269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1094122269 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2116598630 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 11695821 ps |
| CPU time | 1.26 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:32 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-77c187e6-a6bf-4ff8-a24e-2a2017a28ec9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2116598630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2116598630 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4122709803 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1249905966 ps |
| CPU time | 6.85 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:37 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-08d77b85-b570-4977-ab30-1d528b1d68f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122709803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4122709803 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2087283845 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1673731679 ps |
| CPU time | 5.28 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:35 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-203fe0c7-360e-43d7-8aaa-78f6b541d887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2087283845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2087283845 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2552558392 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 10741980 ps |
| CPU time | 1.14 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:31 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-d4bddbc9-3cd2-4013-adac-5a6359eabcf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552558392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2552558392 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3075852108 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 126838135 ps |
| CPU time | 14.71 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:44 PM PDT 24 |
| Peak memory | 203228 kb |
| Host | smart-632c518f-7c80-49b4-b584-adb484926899 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075852108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3075852108 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2104925622 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 561473883 ps |
| CPU time | 13.64 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:43 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-323ef15a-076c-459d-a910-e401878102b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2104925622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2104925622 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1255675764 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2121756313 ps |
| CPU time | 103.08 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:35:13 PM PDT 24 |
| Peak memory | 205128 kb |
| Host | smart-da421145-629f-41c8-8811-2ec4774acc21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1255675764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1255675764 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4091888495 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 95980592 ps |
| CPU time | 14.65 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:46 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-fa1d9ff4-85ac-478e-9eb3-a31bb281d56b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091888495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.4091888495 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1498491065 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 194547088 ps |
| CPU time | 3.8 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-a5d4f57e-08a0-4f8b-8899-3bbfe12f5e6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1498491065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1498491065 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4138839264 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 130214795 ps |
| CPU time | 13.46 seconds |
| Started | May 21 02:36:42 PM PDT 24 |
| Finished | May 21 02:37:11 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-85af4286-0b80-4984-b60f-f39302437013 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4138839264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4138839264 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3584857242 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 51056054062 ps |
| CPU time | 272.26 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:41:28 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-5e902850-4432-464c-8233-fb3db94c0372 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3584857242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3584857242 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2043949255 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1015257511 ps |
| CPU time | 10.6 seconds |
| Started | May 21 02:36:51 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-445cbb46-4403-435a-ba9a-574333933041 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2043949255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2043949255 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3960748919 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 111737962 ps |
| CPU time | 7.61 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-b4861234-0e6b-4e37-9109-2ca3595ae6ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960748919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3960748919 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.3555926213 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 883388123 ps |
| CPU time | 17.16 seconds |
| Started | May 21 02:36:40 PM PDT 24 |
| Finished | May 21 02:37:13 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-997792bf-2281-41d5-85b3-2c36b22d6b5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3555926213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3555926213 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.4072193135 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 16554299549 ps |
| CPU time | 56.29 seconds |
| Started | May 21 02:36:40 PM PDT 24 |
| Finished | May 21 02:37:52 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-2beb3c43-5302-4458-b92b-47506c9a3e9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072193135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4072193135 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.729616933 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 11312474407 ps |
| CPU time | 62.05 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:37:58 PM PDT 24 |
| Peak memory | 202300 kb |
| Host | smart-12ecb7ab-a9e4-461a-9545-e6aad734e752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=729616933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.729616933 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2862099883 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 9780152 ps |
| CPU time | 1.27 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:36:57 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-e1d52f84-a3f3-4794-91c3-5bc293626942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862099883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2862099883 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3444625202 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 69924341 ps |
| CPU time | 4.46 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:37:01 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-cae65894-10d6-4328-a615-435ba85c1ef0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444625202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3444625202 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.3165867009 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 85026403 ps |
| CPU time | 1.57 seconds |
| Started | May 21 02:36:41 PM PDT 24 |
| Finished | May 21 02:36:58 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-b0f900cc-8f59-4074-b410-c023575c49ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3165867009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3165867009 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2385327292 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4708343738 ps |
| CPU time | 6.29 seconds |
| Started | May 21 02:36:42 PM PDT 24 |
| Finished | May 21 02:37:04 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-66eece1f-3bd4-4500-9fc9-58aae3f3f960 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385327292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2385327292 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1178341715 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3095335335 ps |
| CPU time | 7.68 seconds |
| Started | May 21 02:36:42 PM PDT 24 |
| Finished | May 21 02:37:04 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-71bf5f02-7357-4ed0-9c23-222640162c6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1178341715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1178341715 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2338674844 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 9197906 ps |
| CPU time | 1.28 seconds |
| Started | May 21 02:36:40 PM PDT 24 |
| Finished | May 21 02:36:57 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-838dfedd-7e58-4492-a0f6-7219037eb47a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338674844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2338674844 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1509255910 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5456807097 ps |
| CPU time | 68.19 seconds |
| Started | May 21 02:36:49 PM PDT 24 |
| Finished | May 21 02:38:12 PM PDT 24 |
| Peak memory | 203304 kb |
| Host | smart-a1c8e036-994d-4ca2-976f-92f4fd1f10f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1509255910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1509255910 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2796191308 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 776154221 ps |
| CPU time | 18.65 seconds |
| Started | May 21 02:36:50 PM PDT 24 |
| Finished | May 21 02:37:23 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-589328c3-5b7d-4ed6-9f38-e35fc3abd088 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2796191308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2796191308 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3445741276 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 114163586 ps |
| CPU time | 19.33 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:26 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-1fcc2694-6713-490e-9d4e-1e81f12096b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3445741276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3445741276 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1923580408 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 51054160 ps |
| CPU time | 5.24 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:37:13 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-a7398bbf-f535-4d64-baf1-f1f996e0582b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1923580408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1923580408 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2244818201 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 22527752 ps |
| CPU time | 4.11 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:11 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-ce140929-7ac6-4f72-882e-e55a56ae0dd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2244818201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2244818201 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.806795912 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 70762344773 ps |
| CPU time | 245.74 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:41:14 PM PDT 24 |
| Peak memory | 204348 kb |
| Host | smart-6ecc3e35-24c1-4ec8-a525-bbd13eecf83d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=806795912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo w_rsp.806795912 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3749677039 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2014134464 ps |
| CPU time | 9.08 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-ea3d2c13-db9c-492d-8e95-003ae391e861 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3749677039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3749677039 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.542860038 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 833240958 ps |
| CPU time | 8 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-39d522fe-92b3-497d-b9c7-d010d651463b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=542860038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.542860038 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2332625129 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 783865006 ps |
| CPU time | 11.86 seconds |
| Started | May 21 02:36:48 PM PDT 24 |
| Finished | May 21 02:37:14 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-45821a95-b072-41ce-8001-1be2b11d1416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2332625129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2332625129 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.636472433 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 57919216195 ps |
| CPU time | 117.28 seconds |
| Started | May 21 02:36:51 PM PDT 24 |
| Finished | May 21 02:39:03 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-39e8d126-b593-416b-83b4-2be37cd6adbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=636472433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.636472433 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3602964631 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 13013643102 ps |
| CPU time | 68.41 seconds |
| Started | May 21 02:36:49 PM PDT 24 |
| Finished | May 21 02:38:12 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-18ee7cd7-38b2-4070-ad1c-628e3f00e9a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3602964631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3602964631 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1879737955 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 49418522 ps |
| CPU time | 5.21 seconds |
| Started | May 21 02:36:49 PM PDT 24 |
| Finished | May 21 02:37:09 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-0f6d2b9b-e5d1-4bf6-926b-ceed7745ca0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879737955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1879737955 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2726482774 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 26916155 ps |
| CPU time | 2.18 seconds |
| Started | May 21 02:36:57 PM PDT 24 |
| Finished | May 21 02:37:14 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-d287f578-3ba3-43a2-8211-8df83d0c4860 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2726482774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2726482774 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.1129966881 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 8893290 ps |
| CPU time | 1.19 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:08 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-5188aec1-2cdf-494f-84f6-68ddba4e3820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1129966881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1129966881 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1798088467 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2214167648 ps |
| CPU time | 6.51 seconds |
| Started | May 21 02:36:49 PM PDT 24 |
| Finished | May 21 02:37:10 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-7e737385-a551-4fce-bd93-d855c5dfb4e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798088467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1798088467 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4015570217 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1645430857 ps |
| CPU time | 5.42 seconds |
| Started | May 21 02:36:50 PM PDT 24 |
| Finished | May 21 02:37:10 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-ec6fd014-0f66-4970-86c0-bd23ea692c5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4015570217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4015570217 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1634224402 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 24431289 ps |
| CPU time | 1.15 seconds |
| Started | May 21 02:36:49 PM PDT 24 |
| Finished | May 21 02:37:05 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-dfc82d3c-6fc4-4706-ba24-25bab5e0f852 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634224402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1634224402 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1542708938 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1543038395 ps |
| CPU time | 20.4 seconds |
| Started | May 21 02:36:51 PM PDT 24 |
| Finished | May 21 02:37:26 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-0b045533-1f2a-467e-9dfb-52d51b9e5902 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1542708938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1542708938 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2581030635 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 484089344 ps |
| CPU time | 72.23 seconds |
| Started | May 21 02:36:51 PM PDT 24 |
| Finished | May 21 02:38:18 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-d02470df-c502-4c92-bcad-712f14aeb6ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581030635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2581030635 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.527701037 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 750433822 ps |
| CPU time | 85.38 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:38:33 PM PDT 24 |
| Peak memory | 203736 kb |
| Host | smart-a0ae1863-86f1-40ee-a039-898e4d71757c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=527701037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.527701037 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3498210417 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 30689306 ps |
| CPU time | 3.2 seconds |
| Started | May 21 02:36:54 PM PDT 24 |
| Finished | May 21 02:37:12 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-2aaffcf1-6b34-4257-a60e-a303257eb8b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498210417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3498210417 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3312704663 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 334909135 ps |
| CPU time | 13.84 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:37:22 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-f6ef1c78-54d1-46db-b538-1afdee90c01f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3312704663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3312704663 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4249975756 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 36830590019 ps |
| CPU time | 121.97 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:39:09 PM PDT 24 |
| Peak memory | 203348 kb |
| Host | smart-57fe6be0-5d24-448c-b82e-f400fb409616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4249975756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.4249975756 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.4243937227 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 191462801 ps |
| CPU time | 3.12 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:37:11 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-7043b359-102c-4d8e-977c-304605b4ba08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243937227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.4243937227 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.177664335 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1156746770 ps |
| CPU time | 14.65 seconds |
| Started | May 21 02:36:56 PM PDT 24 |
| Finished | May 21 02:37:25 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-abd065da-64bf-4c99-a8a4-c1cfd6d4d692 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177664335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.177664335 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.147661861 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 337151714 ps |
| CPU time | 6.87 seconds |
| Started | May 21 02:36:54 PM PDT 24 |
| Finished | May 21 02:37:15 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-212f7d27-cc3e-4df3-84c1-140722ba3178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=147661861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.147661861 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3418974839 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 289862523405 ps |
| CPU time | 155.33 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:39:44 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-25d9582f-7f88-4fb6-9b4a-0059f48f1fd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418974839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3418974839 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1266714851 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27532240228 ps |
| CPU time | 56.04 seconds |
| Started | May 21 02:36:54 PM PDT 24 |
| Finished | May 21 02:38:05 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-a23924ee-6110-4a4a-8702-ce39ab1b7f0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1266714851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1266714851 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2927061126 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 130457459 ps |
| CPU time | 4.47 seconds |
| Started | May 21 02:36:54 PM PDT 24 |
| Finished | May 21 02:37:13 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-264d3096-2663-41d6-86b7-9a263fb8b503 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927061126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2927061126 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.1157121626 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1038515991 ps |
| CPU time | 12.68 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:19 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-4f435fbd-dab8-4d41-b9b2-b6de5b4707cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1157121626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1157121626 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2242771485 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 67843659 ps |
| CPU time | 1.64 seconds |
| Started | May 21 02:36:52 PM PDT 24 |
| Finished | May 21 02:37:08 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-78dab328-aa50-49ec-8566-2a9b42e3da68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2242771485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2242771485 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1571552206 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1177451283 ps |
| CPU time | 6.18 seconds |
| Started | May 21 02:36:54 PM PDT 24 |
| Finished | May 21 02:37:15 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-efa1030b-eb8a-48a9-afb0-4185418c768b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571552206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1571552206 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2924840090 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 2686242963 ps |
| CPU time | 9.87 seconds |
| Started | May 21 02:36:56 PM PDT 24 |
| Finished | May 21 02:37:20 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-c2bb67e6-b1dc-4694-bcc2-8e47ca0d1628 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2924840090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2924840090 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1586644457 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 10922166 ps |
| CPU time | 1.26 seconds |
| Started | May 21 02:36:57 PM PDT 24 |
| Finished | May 21 02:37:13 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-879489d4-c7a1-4084-b714-e86d5179db7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586644457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1586644457 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4288931466 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1776406091 ps |
| CPU time | 31.66 seconds |
| Started | May 21 02:36:57 PM PDT 24 |
| Finished | May 21 02:37:44 PM PDT 24 |
| Peak memory | 203016 kb |
| Host | smart-2839b857-d582-405c-afce-c6e46c3b2d4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4288931466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4288931466 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3075057109 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 857826989 ps |
| CPU time | 15.74 seconds |
| Started | May 21 02:36:51 PM PDT 24 |
| Finished | May 21 02:37:21 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-dcff7b43-2396-4c84-9969-ed38f585dbb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075057109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3075057109 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1040599212 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 850679113 ps |
| CPU time | 123.13 seconds |
| Started | May 21 02:36:54 PM PDT 24 |
| Finished | May 21 02:39:11 PM PDT 24 |
| Peak memory | 206724 kb |
| Host | smart-7072b191-0840-4970-8588-a1b3fd38dc27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1040599212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1040599212 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2376711000 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 301278814 ps |
| CPU time | 6.09 seconds |
| Started | May 21 02:36:53 PM PDT 24 |
| Finished | May 21 02:37:14 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-eadc629c-4e98-467a-84f1-c5e5129a6fae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2376711000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2376711000 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.3440604114 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 508587631 ps |
| CPU time | 9.93 seconds |
| Started | May 21 02:37:01 PM PDT 24 |
| Finished | May 21 02:37:26 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-97bcd361-f14b-4cc8-be8e-1a81bc2303fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440604114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3440604114 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1033380273 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 17399808830 ps |
| CPU time | 85.81 seconds |
| Started | May 21 02:37:00 PM PDT 24 |
| Finished | May 21 02:38:40 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-0bd5fdf7-b08f-4b9c-8c3f-9fe896a6d1c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1033380273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1033380273 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1103285169 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1768797804 ps |
| CPU time | 4.79 seconds |
| Started | May 21 02:37:00 PM PDT 24 |
| Finished | May 21 02:37:19 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-8f905d2b-553a-4e24-807e-051bea5dce74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1103285169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1103285169 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.4189861164 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 310035339 ps |
| CPU time | 3.75 seconds |
| Started | May 21 02:36:57 PM PDT 24 |
| Finished | May 21 02:37:15 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-6cd8e3c4-f50f-4b6a-bc8e-5d0623a29840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4189861164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4189861164 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.2938490715 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 63435484 ps |
| CPU time | 6.58 seconds |
| Started | May 21 02:37:00 PM PDT 24 |
| Finished | May 21 02:37:21 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-457b944b-3e99-4dff-9872-c98bd6556538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2938490715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2938490715 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.17863855 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 113686173021 ps |
| CPU time | 148.32 seconds |
| Started | May 21 02:36:56 PM PDT 24 |
| Finished | May 21 02:39:39 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-56524ac9-f876-4bea-acac-61e988094dfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.17863855 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1434316789 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 30503449201 ps |
| CPU time | 150.32 seconds |
| Started | May 21 02:36:59 PM PDT 24 |
| Finished | May 21 02:39:44 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-63a9a6cd-4089-4d89-8563-3d0f1c84c33d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1434316789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1434316789 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1454911066 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 298390794 ps |
| CPU time | 5.18 seconds |
| Started | May 21 02:37:00 PM PDT 24 |
| Finished | May 21 02:37:20 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-258f9825-0164-4e09-8678-94bfe6332ff6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454911066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1454911066 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.3953455822 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1281373589 ps |
| CPU time | 9.29 seconds |
| Started | May 21 02:36:58 PM PDT 24 |
| Finished | May 21 02:37:23 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-82366202-ba49-448c-9f4f-01299cd1c39d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3953455822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3953455822 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3653738578 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 11744268 ps |
| CPU time | 1.27 seconds |
| Started | May 21 02:37:02 PM PDT 24 |
| Finished | May 21 02:37:19 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-536f7006-b109-4532-ab83-55d539c14b20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653738578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3653738578 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4161760067 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2110872488 ps |
| CPU time | 9.53 seconds |
| Started | May 21 02:37:02 PM PDT 24 |
| Finished | May 21 02:37:27 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-6a066ca0-21fc-47a7-aafc-b1ca5074892d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161760067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4161760067 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.295332358 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1323590392 ps |
| CPU time | 5.64 seconds |
| Started | May 21 02:36:58 PM PDT 24 |
| Finished | May 21 02:37:19 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-476cf2fb-0484-4812-8bea-663718360af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=295332358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.295332358 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.836677287 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 10759446 ps |
| CPU time | 1.18 seconds |
| Started | May 21 02:36:59 PM PDT 24 |
| Finished | May 21 02:37:15 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-b80d1907-6550-44f3-8e03-cfeb63040e89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836677287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.836677287 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.58239453 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 11592766425 ps |
| CPU time | 74.19 seconds |
| Started | May 21 02:37:03 PM PDT 24 |
| Finished | May 21 02:38:33 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-92726b88-854d-4086-8cc9-106ce66fae00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=58239453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.58239453 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1757882152 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1373500218 ps |
| CPU time | 66.32 seconds |
| Started | May 21 02:37:03 PM PDT 24 |
| Finished | May 21 02:38:26 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-9fb66256-d41b-456a-a586-37de3e7bc668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1757882152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1757882152 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.534641958 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 34574301 ps |
| CPU time | 5.63 seconds |
| Started | May 21 02:36:56 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-5db6fb34-c2e1-4886-b258-7867597bd0e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=534641958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.534641958 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3320836774 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 6968380 ps |
| CPU time | 1.65 seconds |
| Started | May 21 02:36:58 PM PDT 24 |
| Finished | May 21 02:37:14 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-0d131a2c-6054-4cc0-aea6-d8e60c16316d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320836774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3320836774 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3425082632 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 25792306 ps |
| CPU time | 2.21 seconds |
| Started | May 21 02:36:59 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-6bf9752a-7161-4254-aed3-8b13c5a816ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3425082632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3425082632 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1596393254 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 109969488 ps |
| CPU time | 7.65 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:37:28 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-9df36bf1-f005-4faf-a766-6ac26c1e7e39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1596393254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1596393254 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.475951889 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1719922217 ps |
| CPU time | 10.83 seconds |
| Started | May 21 02:37:06 PM PDT 24 |
| Finished | May 21 02:37:35 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-5ca2d898-eac4-4766-a6dd-c5eeec9d2bf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=475951889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.475951889 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1984417016 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 339827100 ps |
| CPU time | 3.02 seconds |
| Started | May 21 02:37:03 PM PDT 24 |
| Finished | May 21 02:37:23 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-9aaa5453-8c20-40c4-9434-1f5d731d0aa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1984417016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1984417016 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.1849921475 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 753045040 ps |
| CPU time | 10.92 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:37:31 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-28ba793f-522e-4360-ac28-a41b89e41f08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849921475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1849921475 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1838651419 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 24775410536 ps |
| CPU time | 110.76 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:39:12 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-812560e8-5840-4b06-a60a-f49832ae538b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838651419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1838651419 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.849541624 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4602504625 ps |
| CPU time | 16.8 seconds |
| Started | May 21 02:37:03 PM PDT 24 |
| Finished | May 21 02:37:35 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-4e143d06-8864-47af-91ae-ab8c428a7f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=849541624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.849541624 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3560556527 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 127958888 ps |
| CPU time | 6.57 seconds |
| Started | May 21 02:37:05 PM PDT 24 |
| Finished | May 21 02:37:29 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-413c91a9-930f-4f6c-90ce-1f7f6ea68475 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560556527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3560556527 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.715621740 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 739966698 ps |
| CPU time | 10.09 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:37:30 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-d618e7f3-83cd-4598-870e-44aeb5e24aa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=715621740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.715621740 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.2582352175 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 47298099 ps |
| CPU time | 1.43 seconds |
| Started | May 21 02:37:00 PM PDT 24 |
| Finished | May 21 02:37:16 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-416d5692-aa85-4b29-8b87-bdf8a471e44f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2582352175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2582352175 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2508188071 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 17961069014 ps |
| CPU time | 12.92 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:37:33 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-e6368744-854e-4bb6-97c2-b2a8ee55abdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508188071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2508188071 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4135421957 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1098380297 ps |
| CPU time | 8.26 seconds |
| Started | May 21 02:37:03 PM PDT 24 |
| Finished | May 21 02:37:28 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-4d8eac33-bc5d-4c88-80c2-e7b859d7ac36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4135421957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4135421957 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.20261865 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 9442825 ps |
| CPU time | 1.28 seconds |
| Started | May 21 02:37:02 PM PDT 24 |
| Finished | May 21 02:37:19 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-b5484001-7371-47f9-a8b9-2a78505e35f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20261865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.20261865 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3361474741 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 155381987 ps |
| CPU time | 17.44 seconds |
| Started | May 21 02:37:06 PM PDT 24 |
| Finished | May 21 02:37:41 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-96a7684a-8d5c-48d9-8f26-9254e812d0d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3361474741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3361474741 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3538766444 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 511903500 ps |
| CPU time | 77.6 seconds |
| Started | May 21 02:37:03 PM PDT 24 |
| Finished | May 21 02:38:37 PM PDT 24 |
| Peak memory | 204828 kb |
| Host | smart-50a70b0a-fdb4-4946-b6d0-7a43ce5a8fb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538766444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3538766444 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.75781415 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 180366807 ps |
| CPU time | 17.18 seconds |
| Started | May 21 02:37:05 PM PDT 24 |
| Finished | May 21 02:37:38 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-73df7487-ebdc-41d0-b0c8-ccb5b37cf978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=75781415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rese t_error.75781415 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.734794837 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 53462923 ps |
| CPU time | 4.48 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:37:25 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-b2f0288d-c44e-4d99-8756-99c95517dd21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734794837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.734794837 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.4154756526 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 91651458560 ps |
| CPU time | 310.06 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:42:39 PM PDT 24 |
| Peak memory | 204076 kb |
| Host | smart-34138689-2411-42d1-851b-c26feccae10a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4154756526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.4154756526 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.702680874 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 381767481 ps |
| CPU time | 5.7 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:37:34 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-d7cc44e9-4fdf-4f31-b055-c6eefeaf2d73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702680874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.702680874 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.56256425 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 2484526958 ps |
| CPU time | 14 seconds |
| Started | May 21 02:37:09 PM PDT 24 |
| Finished | May 21 02:37:40 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-f0e3496d-da36-4126-847a-58c44c4dc753 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=56256425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.56256425 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.1055595857 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 379124442 ps |
| CPU time | 6.88 seconds |
| Started | May 21 02:37:05 PM PDT 24 |
| Finished | May 21 02:37:29 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-c796996e-57b9-406a-a39f-945b5718306f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055595857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1055595857 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.204364535 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 71796248327 ps |
| CPU time | 168.77 seconds |
| Started | May 21 02:37:12 PM PDT 24 |
| Finished | May 21 02:40:19 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-79ed7ba9-6a79-475a-92e2-d6f416a6a31c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=204364535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.204364535 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.789471725 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 45043696114 ps |
| CPU time | 67.22 seconds |
| Started | May 21 02:37:12 PM PDT 24 |
| Finished | May 21 02:38:38 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-d044ff37-deff-461e-bb4d-5ad0d68b19fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=789471725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.789471725 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.649575667 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 18467171 ps |
| CPU time | 1.54 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:37:31 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-4f864925-8931-438b-9ead-e02be540fac9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649575667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.649575667 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1943193516 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 112412097 ps |
| CPU time | 6.4 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:37:36 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-ce93c611-e601-4cb4-b2cd-f8b9a52da68c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1943193516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1943193516 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.3960690032 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 436753333 ps |
| CPU time | 1.63 seconds |
| Started | May 21 02:37:06 PM PDT 24 |
| Finished | May 21 02:37:26 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-540459bd-8a22-4789-9201-73605b9d7768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960690032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3960690032 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1122477759 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2617622767 ps |
| CPU time | 7.33 seconds |
| Started | May 21 02:37:06 PM PDT 24 |
| Finished | May 21 02:37:30 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-9988d581-5997-4062-a4a8-6ebc5167c0e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122477759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1122477759 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1672186732 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2833789219 ps |
| CPU time | 6.49 seconds |
| Started | May 21 02:37:04 PM PDT 24 |
| Finished | May 21 02:37:27 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-7cabbd3a-290a-4c55-92aa-20da3ec2b9a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1672186732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1672186732 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2370720023 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 16696035 ps |
| CPU time | 1.21 seconds |
| Started | May 21 02:37:05 PM PDT 24 |
| Finished | May 21 02:37:23 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-138f9695-764b-4b91-a128-91a5adfc6c07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370720023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2370720023 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.343941568 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9673406736 ps |
| CPU time | 53.34 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:38:22 PM PDT 24 |
| Peak memory | 203288 kb |
| Host | smart-ee668c7a-ec39-4ba9-b26a-f8d7368d18a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=343941568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.343941568 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3561844256 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 358950210 ps |
| CPU time | 35.11 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:38:03 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-468c0de2-2d3a-4937-bb47-d8b817d0678a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3561844256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3561844256 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4029549348 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2340796663 ps |
| CPU time | 159.26 seconds |
| Started | May 21 02:37:08 PM PDT 24 |
| Finished | May 21 02:40:05 PM PDT 24 |
| Peak memory | 207116 kb |
| Host | smart-3908b4df-29a6-4624-ae44-8cf6ff006bcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4029549348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.4029549348 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4064264925 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 278071926 ps |
| CPU time | 34.18 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:38:03 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-d42e314a-3577-4f22-8891-4906c0dd876a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064264925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.4064264925 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.4231481301 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 477967775 ps |
| CPU time | 7.76 seconds |
| Started | May 21 02:37:12 PM PDT 24 |
| Finished | May 21 02:37:38 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-4665bb7f-2e52-4f9e-b26c-00ada3976d8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4231481301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4231481301 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3510411462 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 728363882 ps |
| CPU time | 14.76 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:37:52 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-526944d2-5008-4dda-97eb-067da653a8d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3510411462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3510411462 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3931411996 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 5966309409 ps |
| CPU time | 23.95 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:38:00 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-3bb75829-210e-45af-9aca-50f122bf78fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3931411996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.3931411996 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2988099838 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 448943980 ps |
| CPU time | 3.95 seconds |
| Started | May 21 02:37:15 PM PDT 24 |
| Finished | May 21 02:37:38 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-e8cd97b0-f1ee-4a01-b529-3681e98c327b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2988099838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2988099838 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.2134569291 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 95272722 ps |
| CPU time | 5.66 seconds |
| Started | May 21 02:37:18 PM PDT 24 |
| Finished | May 21 02:37:43 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-c38bd999-fb7b-4b5a-87fe-e47c6d5c4a79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2134569291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2134569291 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.1142189619 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 81473906 ps |
| CPU time | 1.71 seconds |
| Started | May 21 02:37:14 PM PDT 24 |
| Finished | May 21 02:37:34 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-96516cd6-ca26-4856-85d6-790534a1033c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142189619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1142189619 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1088976961 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 21917627604 ps |
| CPU time | 82.02 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:38:58 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-c5056f5c-5906-4d38-9b04-4eeffc792e3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088976961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1088976961 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3143830904 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 27453124214 ps |
| CPU time | 110.15 seconds |
| Started | May 21 02:37:17 PM PDT 24 |
| Finished | May 21 02:39:27 PM PDT 24 |
| Peak memory | 202292 kb |
| Host | smart-baec2991-fe56-4aeb-a7cb-ac189c366662 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3143830904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3143830904 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3041317561 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 237440228 ps |
| CPU time | 3.53 seconds |
| Started | May 21 02:37:14 PM PDT 24 |
| Finished | May 21 02:37:37 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-45ee1259-31cc-4ef2-9830-17a830c07ad2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041317561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3041317561 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1888255137 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 824808152 ps |
| CPU time | 11.69 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:37:49 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-cfa16edb-6838-4905-9102-1c5637b3e08e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1888255137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1888255137 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3735366843 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 10189364 ps |
| CPU time | 1.17 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:37:31 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-3f1cb88b-f2e4-4680-a05b-baacdbd634cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3735366843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3735366843 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4043740835 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 17308645938 ps |
| CPU time | 10.47 seconds |
| Started | May 21 02:37:09 PM PDT 24 |
| Finished | May 21 02:37:38 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-27106292-463e-4d21-91b5-cd9b6f09c126 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043740835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4043740835 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1432226215 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 676988444 ps |
| CPU time | 5.71 seconds |
| Started | May 21 02:37:17 PM PDT 24 |
| Finished | May 21 02:37:43 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-bee55324-3499-4be4-9948-b814e62746c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1432226215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1432226215 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2483266846 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 8190475 ps |
| CPU time | 1.13 seconds |
| Started | May 21 02:37:10 PM PDT 24 |
| Finished | May 21 02:37:30 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-82797b51-0874-41a5-a3e6-6256fd842e08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483266846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2483266846 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.908752791 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 6479958086 ps |
| CPU time | 56.37 seconds |
| Started | May 21 02:37:15 PM PDT 24 |
| Finished | May 21 02:38:31 PM PDT 24 |
| Peak memory | 203988 kb |
| Host | smart-277641d4-49fd-4100-b379-0e4c042f9f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=908752791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.908752791 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.413241533 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 483640315 ps |
| CPU time | 36.76 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:38:12 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-e4b8bd7a-d933-4ba3-baf0-6e68e5687c49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413241533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.413241533 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.625302674 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11165823184 ps |
| CPU time | 142.82 seconds |
| Started | May 21 02:37:15 PM PDT 24 |
| Finished | May 21 02:39:58 PM PDT 24 |
| Peak memory | 205468 kb |
| Host | smart-8ec7d4ff-5bbd-4ea7-87a9-ce3158826c4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=625302674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand _reset.625302674 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.61618795 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 673084537 ps |
| CPU time | 98.48 seconds |
| Started | May 21 02:37:17 PM PDT 24 |
| Finished | May 21 02:39:16 PM PDT 24 |
| Peak memory | 207404 kb |
| Host | smart-031948d5-fcfa-4e0a-b66c-287744bc5b1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61618795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rese t_error.61618795 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.3844335874 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 271962409 ps |
| CPU time | 7.94 seconds |
| Started | May 21 02:37:17 PM PDT 24 |
| Finished | May 21 02:37:45 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-1f2f4000-1416-4ee4-a0f3-bb78fde54a01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3844335874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3844335874 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3823849690 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 138605775 ps |
| CPU time | 7.46 seconds |
| Started | May 21 02:37:23 PM PDT 24 |
| Finished | May 21 02:37:50 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-ab4ac115-9664-4de3-93bc-289238dfb12a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3823849690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3823849690 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1291054611 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 214187052695 ps |
| CPU time | 322.68 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:43:05 PM PDT 24 |
| Peak memory | 204488 kb |
| Host | smart-db4c2cb8-cc13-43c2-a4ac-7b0f93b21f0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1291054611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1291054611 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2423999423 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 499535031 ps |
| CPU time | 10.49 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:37:53 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-d7a53296-18aa-4749-9b5d-1502cd526b9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2423999423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2423999423 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2750777636 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 82500569 ps |
| CPU time | 6.21 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:37:48 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-435d95c3-8e2d-4134-85df-d0dc16bc926c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2750777636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2750777636 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2534170135 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 86627116 ps |
| CPU time | 7.22 seconds |
| Started | May 21 02:37:17 PM PDT 24 |
| Finished | May 21 02:37:44 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-d0716a78-733e-41ee-bb6a-4f5bc3dabc92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534170135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2534170135 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1183045276 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 96189029133 ps |
| CPU time | 169.07 seconds |
| Started | May 21 02:37:24 PM PDT 24 |
| Finished | May 21 02:40:32 PM PDT 24 |
| Peak memory | 202296 kb |
| Host | smart-26e99c82-cce9-44e5-a4f7-bf73c149a269 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183045276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1183045276 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3726579016 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 58719010 ps |
| CPU time | 7.34 seconds |
| Started | May 21 02:37:17 PM PDT 24 |
| Finished | May 21 02:37:45 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-35710482-320d-4197-b4bd-2d7a1a41ff83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726579016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3726579016 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3762718371 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 53325823 ps |
| CPU time | 3.3 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:37:45 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-93c4c7c3-0682-45a8-9a90-15971f032619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3762718371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3762718371 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.885249786 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 9150776 ps |
| CPU time | 1.07 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:37:37 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-afc063ef-b215-4ef0-9d4b-f22afb8c667e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=885249786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.885249786 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1538230692 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5391732365 ps |
| CPU time | 10.41 seconds |
| Started | May 21 02:37:14 PM PDT 24 |
| Finished | May 21 02:37:44 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-a65143cf-8220-496f-824d-87c3bc443562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538230692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1538230692 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2995373647 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1593225383 ps |
| CPU time | 9.02 seconds |
| Started | May 21 02:37:16 PM PDT 24 |
| Finished | May 21 02:37:46 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-39a3649e-7b5c-44ad-995e-a8681360b8a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2995373647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2995373647 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1338719255 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 11092911 ps |
| CPU time | 1.07 seconds |
| Started | May 21 02:37:15 PM PDT 24 |
| Finished | May 21 02:37:36 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-ae62356a-037b-4eba-bd56-c52963ee93ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338719255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1338719255 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2277123671 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 4700582500 ps |
| CPU time | 26.92 seconds |
| Started | May 21 02:37:23 PM PDT 24 |
| Finished | May 21 02:38:09 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-35150e34-8be7-41c0-8af4-f292e0a75b66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2277123671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2277123671 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1479060651 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2182302435 ps |
| CPU time | 25.23 seconds |
| Started | May 21 02:37:24 PM PDT 24 |
| Finished | May 21 02:38:08 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-cebadbbd-0aa6-4226-a8f1-8d814992c4a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1479060651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1479060651 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.4287652781 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1957406141 ps |
| CPU time | 85.41 seconds |
| Started | May 21 02:37:23 PM PDT 24 |
| Finished | May 21 02:39:08 PM PDT 24 |
| Peak memory | 204724 kb |
| Host | smart-817c33a0-0caa-4468-a8af-ac6d9b6e808c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4287652781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.4287652781 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2499754715 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1457982364 ps |
| CPU time | 46.9 seconds |
| Started | May 21 02:37:24 PM PDT 24 |
| Finished | May 21 02:38:30 PM PDT 24 |
| Peak memory | 203468 kb |
| Host | smart-33ead2c1-76e5-4288-a423-114286534d13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2499754715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2499754715 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2873192078 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1405243314 ps |
| CPU time | 7.95 seconds |
| Started | May 21 02:37:23 PM PDT 24 |
| Finished | May 21 02:37:50 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-4256f0b9-e423-4b04-b33d-5e77641beaee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2873192078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2873192078 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3815460082 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1496990903 ps |
| CPU time | 19.26 seconds |
| Started | May 21 02:37:28 PM PDT 24 |
| Finished | May 21 02:38:07 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-fb35d14d-032d-4a0b-bb59-42f2e32b04de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3815460082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3815460082 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1425414785 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 21350469598 ps |
| CPU time | 92.46 seconds |
| Started | May 21 02:37:26 PM PDT 24 |
| Finished | May 21 02:39:19 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-21aa24ab-fa9a-433e-a701-5adec5502d18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1425414785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1425414785 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2547790260 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 670415049 ps |
| CPU time | 12.65 seconds |
| Started | May 21 02:37:28 PM PDT 24 |
| Finished | May 21 02:38:00 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-aff4e222-b60f-4b62-973b-9fd72eefb3cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2547790260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2547790260 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1554132553 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 45668697 ps |
| CPU time | 3.99 seconds |
| Started | May 21 02:37:27 PM PDT 24 |
| Finished | May 21 02:37:51 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-c8fe312c-7831-4e56-8dfd-cdef17c8fc3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1554132553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1554132553 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1098227406 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 53306773 ps |
| CPU time | 1.4 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:37:44 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-7ef0b8e2-7765-43ad-8432-21823478a59c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1098227406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1098227406 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2628871853 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 25782192853 ps |
| CPU time | 61.69 seconds |
| Started | May 21 02:37:24 PM PDT 24 |
| Finished | May 21 02:38:45 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-cf435b15-0f33-427d-a05f-7309aa31d735 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628871853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2628871853 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2330954039 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6578202116 ps |
| CPU time | 30.33 seconds |
| Started | May 21 02:37:29 PM PDT 24 |
| Finished | May 21 02:38:18 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-bbb53b48-913c-4b24-bac5-f614ef9f960b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2330954039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2330954039 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2949788637 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 10840608 ps |
| CPU time | 1.14 seconds |
| Started | May 21 02:37:23 PM PDT 24 |
| Finished | May 21 02:37:43 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-0c0b11e1-5f91-4376-85b1-a3376a232dbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949788637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2949788637 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3789005032 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 738185342 ps |
| CPU time | 7.8 seconds |
| Started | May 21 02:37:28 PM PDT 24 |
| Finished | May 21 02:37:55 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-6f121dd5-4926-4554-85f1-a41fd49c44f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3789005032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3789005032 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.874240221 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 351690094 ps |
| CPU time | 1.54 seconds |
| Started | May 21 02:37:21 PM PDT 24 |
| Finished | May 21 02:37:42 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-f12e0bc1-7297-4c60-b837-1fca3755d883 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874240221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.874240221 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3128780411 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1608627924 ps |
| CPU time | 5.73 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:37:47 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-32f56be4-7e75-4faa-887b-f6487ccc1673 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128780411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3128780411 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1946799529 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4510797741 ps |
| CPU time | 7.44 seconds |
| Started | May 21 02:37:21 PM PDT 24 |
| Finished | May 21 02:37:49 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-0782aec8-be2a-442a-b39c-baafcd997556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1946799529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1946799529 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.165096327 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 13823754 ps |
| CPU time | 1.15 seconds |
| Started | May 21 02:37:22 PM PDT 24 |
| Finished | May 21 02:37:44 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-7dcbcd3c-50bf-4a5d-a39c-2e623bdb174c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165096327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.165096327 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2208871835 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 13235762 ps |
| CPU time | 1.08 seconds |
| Started | May 21 02:37:28 PM PDT 24 |
| Finished | May 21 02:37:48 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-fafeb9ca-5fe4-4896-8e64-d23e31f5ce98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2208871835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2208871835 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.792026716 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1591154312 ps |
| CPU time | 45.99 seconds |
| Started | May 21 02:37:35 PM PDT 24 |
| Finished | May 21 02:38:40 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-bf311565-6d0c-4cb8-a510-e8ac7718b513 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=792026716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.792026716 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3521259032 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 283782265 ps |
| CPU time | 63.67 seconds |
| Started | May 21 02:37:33 PM PDT 24 |
| Finished | May 21 02:38:56 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-731492e6-73c5-4b8f-8c07-408f7480600e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3521259032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3521259032 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3533638282 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 82025979 ps |
| CPU time | 13.02 seconds |
| Started | May 21 02:37:33 PM PDT 24 |
| Finished | May 21 02:38:05 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-72f662b8-61e6-404b-90a7-c1ce565f2382 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3533638282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3533638282 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2289145370 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 431079632 ps |
| CPU time | 10.76 seconds |
| Started | May 21 02:37:25 PM PDT 24 |
| Finished | May 21 02:37:56 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-307c3aa5-555a-42db-998d-1b91d7052716 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2289145370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2289145370 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2571226576 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 27082001 ps |
| CPU time | 3.88 seconds |
| Started | May 21 02:37:35 PM PDT 24 |
| Finished | May 21 02:37:57 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-68bf799f-1054-4ed7-bf65-b7eacfa11109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2571226576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2571226576 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3452938109 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 38640399731 ps |
| CPU time | 174.28 seconds |
| Started | May 21 02:37:34 PM PDT 24 |
| Finished | May 21 02:40:47 PM PDT 24 |
| Peak memory | 203560 kb |
| Host | smart-66e062f5-6437-4935-8d81-b620c1facd2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3452938109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3452938109 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3084066161 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 633329991 ps |
| CPU time | 9.63 seconds |
| Started | May 21 02:37:34 PM PDT 24 |
| Finished | May 21 02:38:02 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-f2afd6ff-05d3-4cd0-874d-b65d0cb9edf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3084066161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3084066161 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.1558413747 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 66188594 ps |
| CPU time | 1.43 seconds |
| Started | May 21 02:37:33 PM PDT 24 |
| Finished | May 21 02:37:53 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-13dad073-304b-4d71-831b-55f046beddbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1558413747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1558413747 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.2935412192 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 70363835 ps |
| CPU time | 5.2 seconds |
| Started | May 21 02:37:35 PM PDT 24 |
| Finished | May 21 02:37:59 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-f9610d7b-762b-4afc-81a0-286941255736 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2935412192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2935412192 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3191694428 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 104205146712 ps |
| CPU time | 149.16 seconds |
| Started | May 21 02:37:38 PM PDT 24 |
| Finished | May 21 02:40:26 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-0f33cf38-f632-41a7-a6fd-18436d3d5046 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191694428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3191694428 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1176699898 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 22430760507 ps |
| CPU time | 111.94 seconds |
| Started | May 21 02:37:38 PM PDT 24 |
| Finished | May 21 02:39:49 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-4303b6ae-0964-4ff2-93cd-51ab6f3f710e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1176699898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1176699898 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.388972881 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 83809692 ps |
| CPU time | 8.53 seconds |
| Started | May 21 02:37:33 PM PDT 24 |
| Finished | May 21 02:38:00 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-1820b758-3350-427e-9399-60dba7fb6e28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388972881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.388972881 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.4032781551 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 30869786 ps |
| CPU time | 2.32 seconds |
| Started | May 21 02:37:35 PM PDT 24 |
| Finished | May 21 02:37:56 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-ecef30eb-e59d-432e-bf0a-68184bd85ff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4032781551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4032781551 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1577973687 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 386183253 ps |
| CPU time | 1.62 seconds |
| Started | May 21 02:37:34 PM PDT 24 |
| Finished | May 21 02:37:55 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-aab82c8c-c546-42fb-909b-b3e672d38d05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577973687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1577973687 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.903629345 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1397487604 ps |
| CPU time | 7.33 seconds |
| Started | May 21 02:37:38 PM PDT 24 |
| Finished | May 21 02:38:04 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-46ffa330-e409-4e0e-aa64-42bef1d7d0f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=903629345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.903629345 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1555764907 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1148633868 ps |
| CPU time | 7.13 seconds |
| Started | May 21 02:37:35 PM PDT 24 |
| Finished | May 21 02:38:01 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-2ddabe69-128d-4bcd-8c35-cfa92d25e459 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1555764907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1555764907 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4048473289 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 8619668 ps |
| CPU time | 1.15 seconds |
| Started | May 21 02:37:36 PM PDT 24 |
| Finished | May 21 02:37:55 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-fb55b290-15b7-4fff-8534-55673fabad21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048473289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.4048473289 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2869990444 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4103489586 ps |
| CPU time | 47.23 seconds |
| Started | May 21 02:37:36 PM PDT 24 |
| Finished | May 21 02:38:41 PM PDT 24 |
| Peak memory | 203348 kb |
| Host | smart-09fa5475-bfd3-4fa4-a4de-f02d4b6ea097 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2869990444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2869990444 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.697764620 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 466264086 ps |
| CPU time | 32.15 seconds |
| Started | May 21 02:37:33 PM PDT 24 |
| Finished | May 21 02:38:24 PM PDT 24 |
| Peak memory | 203212 kb |
| Host | smart-4bb75239-f814-43a2-91de-4d9970da77d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=697764620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.697764620 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3791546019 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1244350674 ps |
| CPU time | 159.82 seconds |
| Started | May 21 02:37:32 PM PDT 24 |
| Finished | May 21 02:40:31 PM PDT 24 |
| Peak memory | 205848 kb |
| Host | smart-a86993c8-a7ef-440b-953e-6f0307645773 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3791546019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3791546019 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4280387596 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 541420465 ps |
| CPU time | 44.9 seconds |
| Started | May 21 02:37:33 PM PDT 24 |
| Finished | May 21 02:38:36 PM PDT 24 |
| Peak memory | 203268 kb |
| Host | smart-f658d3f1-0510-4359-99a1-1f311bdd2e06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4280387596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.4280387596 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1892478129 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 59627534 ps |
| CPU time | 5.99 seconds |
| Started | May 21 02:37:35 PM PDT 24 |
| Finished | May 21 02:37:59 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-cdc04e43-42c8-49ea-9169-ff0d7ed2e57c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1892478129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1892478129 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2497790123 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 106604333 ps |
| CPU time | 10.12 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:40 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-493f7848-62ba-4070-a6f3-e7e5f0ab1156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2497790123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2497790123 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2134820933 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 12903435204 ps |
| CPU time | 53.56 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:34:23 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-cd16e0aa-ae21-4ed5-a226-3dcc0bfd7488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2134820933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.2134820933 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1101071073 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 65488645 ps |
| CPU time | 2.94 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:32 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-d7791d39-c141-4a69-a6c6-8e2327d2538c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1101071073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1101071073 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2729992021 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 448399105 ps |
| CPU time | 5.01 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:35 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-d276eb33-e5bc-48a1-be06-9523879204b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2729992021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2729992021 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.101483857 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1517699530 ps |
| CPU time | 14.88 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:45 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-e49c20c5-276c-4560-b835-0c1f36ae854a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101483857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.101483857 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2152681604 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 16104418877 ps |
| CPU time | 57.15 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:34:27 PM PDT 24 |
| Peak memory | 202308 kb |
| Host | smart-d1d96b20-ee05-4677-abc7-be22eb5975b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152681604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2152681604 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1433357386 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 9031779535 ps |
| CPU time | 63.83 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:34:35 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-c6e33a05-a861-4c76-b64b-2fa96309f71f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1433357386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1433357386 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3266549201 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 69863024 ps |
| CPU time | 8.83 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:41 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-177c0fc8-5841-4805-9de1-372b08f00d7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266549201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3266549201 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.171102936 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 773152622 ps |
| CPU time | 8.93 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:39 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-c5b313b5-6b0d-40e8-bae8-0cc7dd0b5e3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171102936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.171102936 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.492459430 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 276433591 ps |
| CPU time | 1.45 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:33 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-d7cc8d95-9be8-468d-9da3-c021ec168288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=492459430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.492459430 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.801340170 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 13246540963 ps |
| CPU time | 8.76 seconds |
| Started | May 21 02:33:11 PM PDT 24 |
| Finished | May 21 02:33:38 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-89050524-466d-49b0-9993-ad9be01b8a17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=801340170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.801340170 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3373696777 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5426036249 ps |
| CPU time | 6.17 seconds |
| Started | May 21 02:33:17 PM PDT 24 |
| Finished | May 21 02:33:42 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-e7854bc0-c2d6-4f31-804d-211c863e21e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3373696777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3373696777 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3231800117 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 8546177 ps |
| CPU time | 1.22 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:33 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-ca1747e1-cd29-475a-8bdc-619e0afa2f19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231800117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3231800117 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3863960257 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 6263540809 ps |
| CPU time | 25.9 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:57 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-baecba12-8365-4ac6-98e5-cf3308f0b0de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3863960257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3863960257 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3334501071 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 182725783 ps |
| CPU time | 12.78 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:43 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-690b097b-b0ea-4d78-8265-9fd2d22816ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3334501071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3334501071 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2325530625 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 930489847 ps |
| CPU time | 134.88 seconds |
| Started | May 21 02:33:10 PM PDT 24 |
| Finished | May 21 02:35:43 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-fe947863-616c-4670-98a3-9938b8db1587 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325530625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2325530625 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2821092875 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1020584994 ps |
| CPU time | 81.79 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:34:53 PM PDT 24 |
| Peak memory | 208188 kb |
| Host | smart-9749f09a-f202-4ea0-bd5d-d5258101ef92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2821092875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.2821092875 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2870773086 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 59519875 ps |
| CPU time | 4.49 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-ddbfa28d-3972-49ca-aa9c-71bfe548662a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2870773086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2870773086 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.518370979 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1435376497 ps |
| CPU time | 13.79 seconds |
| Started | May 21 02:33:17 PM PDT 24 |
| Finished | May 21 02:33:49 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-701543d9-9b16-4d99-b77c-4014bdce17ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518370979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.518370979 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.150958106 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 192355200491 ps |
| CPU time | 187.84 seconds |
| Started | May 21 02:33:18 PM PDT 24 |
| Finished | May 21 02:36:44 PM PDT 24 |
| Peak memory | 203572 kb |
| Host | smart-3a334d2b-f46c-4fdd-ba32-a45fc615e5c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=150958106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.150958106 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2801359929 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 119799715 ps |
| CPU time | 6.36 seconds |
| Started | May 21 02:33:24 PM PDT 24 |
| Finished | May 21 02:33:47 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-7ccc423f-f1ea-4708-b707-d102b15bb374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2801359929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2801359929 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.3133675605 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 308381353 ps |
| CPU time | 6.55 seconds |
| Started | May 21 02:33:23 PM PDT 24 |
| Finished | May 21 02:33:46 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-51f0274e-56e2-4481-8927-043fd4b4cbb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3133675605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3133675605 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.588971922 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 33768011 ps |
| CPU time | 3.86 seconds |
| Started | May 21 02:33:14 PM PDT 24 |
| Finished | May 21 02:33:37 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-2e6f4431-a6e8-4b32-a4f2-6257321e74b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588971922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.588971922 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3297663050 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26667377734 ps |
| CPU time | 91.68 seconds |
| Started | May 21 02:33:22 PM PDT 24 |
| Finished | May 21 02:35:10 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-fdba02a9-58b1-4f5a-a755-b8ba3a66a7fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297663050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3297663050 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.724240143 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 11107470773 ps |
| CPU time | 63.74 seconds |
| Started | May 21 02:33:23 PM PDT 24 |
| Finished | May 21 02:34:43 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-db782276-2803-4e0b-a3a7-c5b0257fb0f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=724240143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.724240143 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3053370811 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 38418933 ps |
| CPU time | 3.72 seconds |
| Started | May 21 02:33:19 PM PDT 24 |
| Finished | May 21 02:33:40 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-3450390e-d32f-4e6c-96d4-374832757c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053370811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3053370811 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.555712113 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 15876138 ps |
| CPU time | 1.56 seconds |
| Started | May 21 02:33:15 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-371bf949-55d6-4311-af46-398b49b6b790 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=555712113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.555712113 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.1321731084 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 137243838 ps |
| CPU time | 1.56 seconds |
| Started | May 21 02:33:13 PM PDT 24 |
| Finished | May 21 02:33:33 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-77536301-f4f6-4f95-aea7-80c4802d90a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1321731084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1321731084 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.554164947 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4542238863 ps |
| CPU time | 8.58 seconds |
| Started | May 21 02:33:14 PM PDT 24 |
| Finished | May 21 02:33:42 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-62552f6b-acfa-44c2-8958-01d6ae623289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=554164947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.554164947 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.437987427 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1694599195 ps |
| CPU time | 9.09 seconds |
| Started | May 21 02:33:12 PM PDT 24 |
| Finished | May 21 02:33:40 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-195206c6-aa42-46cf-8905-1e5a9e73007e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=437987427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.437987427 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1558757798 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 10854885 ps |
| CPU time | 1.4 seconds |
| Started | May 21 02:33:10 PM PDT 24 |
| Finished | May 21 02:33:30 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-ca9a90e7-34d4-466b-834a-bba157dde778 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558757798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1558757798 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2610759400 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 128993340 ps |
| CPU time | 11.1 seconds |
| Started | May 21 02:33:16 PM PDT 24 |
| Finished | May 21 02:33:46 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-3b2a3a7e-6d0a-4ebd-952d-cb2a860df265 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610759400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2610759400 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1360168810 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 7620117441 ps |
| CPU time | 81.69 seconds |
| Started | May 21 02:33:15 PM PDT 24 |
| Finished | May 21 02:34:56 PM PDT 24 |
| Peak memory | 203524 kb |
| Host | smart-4b6578d0-1979-4b82-a4ea-1744013b112e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1360168810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1360168810 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.24642474 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 22401429 ps |
| CPU time | 2.33 seconds |
| Started | May 21 02:33:15 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-4d12dc7a-a756-4138-97f3-c2aa990f8b22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24642474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.24642474 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2025872803 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 388663567 ps |
| CPU time | 9.21 seconds |
| Started | May 21 02:33:16 PM PDT 24 |
| Finished | May 21 02:33:44 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-8bcf0ecc-c797-4db8-bea4-28933125b5af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2025872803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2025872803 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1375228895 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 15768852642 ps |
| CPU time | 100.25 seconds |
| Started | May 21 02:33:16 PM PDT 24 |
| Finished | May 21 02:35:15 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-95cfd5d2-c3e3-49be-8841-668a1f051787 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1375228895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.1375228895 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1963694559 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 240468020 ps |
| CPU time | 5.51 seconds |
| Started | May 21 02:33:21 PM PDT 24 |
| Finished | May 21 02:33:43 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-1f8d6c96-7007-4586-9732-c79849db004a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1963694559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1963694559 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.1084937194 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 327254534 ps |
| CPU time | 6.87 seconds |
| Started | May 21 02:33:18 PM PDT 24 |
| Finished | May 21 02:33:43 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-d737bb71-45f6-4d81-b802-a780cae17959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1084937194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1084937194 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.729965686 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 21434869 ps |
| CPU time | 2.35 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:33:44 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-c0e0835c-c9e0-418b-8b7d-765732fe38cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=729965686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.729965686 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.628616810 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 7158638326 ps |
| CPU time | 12.21 seconds |
| Started | May 21 02:33:16 PM PDT 24 |
| Finished | May 21 02:33:47 PM PDT 24 |
| Peak memory | 202268 kb |
| Host | smart-d8503a84-1c01-4c66-b349-adf8eeb0cab0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=628616810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.628616810 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2215476126 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 24911504930 ps |
| CPU time | 179.27 seconds |
| Started | May 21 02:33:28 PM PDT 24 |
| Finished | May 21 02:36:44 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-66e7d8b8-f6d2-455e-b234-3e2e43f89fcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2215476126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2215476126 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1179249607 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 27619973 ps |
| CPU time | 2.14 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:33:44 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-98ad3761-86ab-44ef-aa66-017b5be45535 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179249607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1179249607 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.3137490152 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 34742739 ps |
| CPU time | 2.66 seconds |
| Started | May 21 02:33:15 PM PDT 24 |
| Finished | May 21 02:33:37 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-61bf03cf-027a-4c0a-86f9-61bc5c628c48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3137490152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3137490152 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.828790765 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 69236876 ps |
| CPU time | 1.42 seconds |
| Started | May 21 02:33:15 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-babe197c-223a-4ec9-b7cc-5bdc2bc71fa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=828790765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.828790765 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2107792004 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1893609549 ps |
| CPU time | 7.83 seconds |
| Started | May 21 02:33:16 PM PDT 24 |
| Finished | May 21 02:33:43 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-2aa06018-27d5-4edc-9557-b8611d60809c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107792004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2107792004 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3775319764 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4010214617 ps |
| CPU time | 9.1 seconds |
| Started | May 21 02:33:15 PM PDT 24 |
| Finished | May 21 02:33:43 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-7a885761-7d10-459b-af35-c303107df636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3775319764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3775319764 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3422508861 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 18217318 ps |
| CPU time | 1.04 seconds |
| Started | May 21 02:33:18 PM PDT 24 |
| Finished | May 21 02:33:37 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-c34a6306-2aa5-4274-813f-d4f6afaad74b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422508861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3422508861 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3568755704 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1089434752 ps |
| CPU time | 18.61 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:34:01 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-34d9e90b-832d-4e16-b0bb-1a3cea440f5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3568755704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3568755704 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3316737451 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 425627962 ps |
| CPU time | 25.05 seconds |
| Started | May 21 02:33:24 PM PDT 24 |
| Finished | May 21 02:34:05 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-0862ae56-8e56-43fa-b40c-6d789173a8cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316737451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3316737451 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1830681385 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1512242768 ps |
| CPU time | 66.78 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:34:49 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-9eef5753-5449-4424-98a2-e01a36fcccf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1830681385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1830681385 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1093332942 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 529211315 ps |
| CPU time | 36.81 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:34:19 PM PDT 24 |
| Peak memory | 203724 kb |
| Host | smart-f7d8f9c6-85a2-49a9-b718-2bfab2d0d87a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1093332942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1093332942 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.87257644 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 268348659 ps |
| CPU time | 2.9 seconds |
| Started | May 21 02:33:14 PM PDT 24 |
| Finished | May 21 02:33:36 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-a8519a99-4d35-43e4-a56b-3b82527edc86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87257644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.87257644 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1385818945 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1507834440 ps |
| CPU time | 17.14 seconds |
| Started | May 21 02:33:27 PM PDT 24 |
| Finished | May 21 02:34:00 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-74052f06-e384-47d4-8f72-0fc8ff531efc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1385818945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1385818945 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1932207726 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 404646592 ps |
| CPU time | 6.11 seconds |
| Started | May 21 02:33:29 PM PDT 24 |
| Finished | May 21 02:33:51 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-7b5956f6-c4ff-4f60-9bd7-a081d0b1fd39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1932207726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1932207726 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.1815378538 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 107125406 ps |
| CPU time | 4.5 seconds |
| Started | May 21 02:33:28 PM PDT 24 |
| Finished | May 21 02:33:48 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-5dd7d6a4-bbfd-4888-baaf-dcea0357137c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1815378538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1815378538 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.966189256 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 56046296 ps |
| CPU time | 5.51 seconds |
| Started | May 21 02:33:23 PM PDT 24 |
| Finished | May 21 02:33:45 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-6f5c5a62-751d-47bc-abaa-9d7939015163 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=966189256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.966189256 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2852262582 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2688075272 ps |
| CPU time | 12.22 seconds |
| Started | May 21 02:33:25 PM PDT 24 |
| Finished | May 21 02:33:53 PM PDT 24 |
| Peak memory | 202304 kb |
| Host | smart-ceb7f09f-f874-48b3-81dc-ec1c4e6c467e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852262582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2852262582 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.643950499 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 20960133372 ps |
| CPU time | 103.02 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:35:25 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-55d7b48a-d2ef-452a-a4a9-e50c90da08cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=643950499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.643950499 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.23709922 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 57202026 ps |
| CPU time | 7.38 seconds |
| Started | May 21 02:33:24 PM PDT 24 |
| Finished | May 21 02:33:47 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-1b96ad63-f1ce-4895-8315-031321dae7dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23709922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.23709922 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1393418554 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 14359908 ps |
| CPU time | 1.28 seconds |
| Started | May 21 02:33:24 PM PDT 24 |
| Finished | May 21 02:33:41 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-a2995fbc-4d00-4bbb-af30-680628f41214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1393418554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1393418554 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1878651791 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 57747179 ps |
| CPU time | 1.38 seconds |
| Started | May 21 02:33:24 PM PDT 24 |
| Finished | May 21 02:33:41 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-7c2fc390-b97a-46d3-8676-2117171b67de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878651791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1878651791 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.632016685 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2078524147 ps |
| CPU time | 8.01 seconds |
| Started | May 21 02:33:25 PM PDT 24 |
| Finished | May 21 02:33:49 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-f2f36d02-6249-4bbf-82ac-cd5f1b1d7c59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=632016685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.632016685 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.898383795 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4565210392 ps |
| CPU time | 6.37 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:33:48 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-d9bde0db-a1d0-4321-9e4f-652a7d8e6181 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=898383795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.898383795 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3383899081 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 8326614 ps |
| CPU time | 1.07 seconds |
| Started | May 21 02:33:26 PM PDT 24 |
| Finished | May 21 02:33:44 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-f53d8278-9c8b-4158-903d-ef16cc5a7f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383899081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3383899081 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1789137299 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1302408424 ps |
| CPU time | 31.24 seconds |
| Started | May 21 02:33:29 PM PDT 24 |
| Finished | May 21 02:34:16 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-5d81e595-5e2a-4eda-902e-a51b9a364a96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1789137299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1789137299 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4128012123 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 8618660189 ps |
| CPU time | 86.94 seconds |
| Started | May 21 02:33:29 PM PDT 24 |
| Finished | May 21 02:35:11 PM PDT 24 |
| Peak memory | 203280 kb |
| Host | smart-e0b82e8b-b835-4512-a1f8-dc1a1ffccadf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4128012123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4128012123 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3511171195 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 28107766 ps |
| CPU time | 12.28 seconds |
| Started | May 21 02:33:27 PM PDT 24 |
| Finished | May 21 02:33:55 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-fd9f7373-725a-4800-afd7-a190402954e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3511171195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3511171195 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2694459949 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 792961202 ps |
| CPU time | 104.01 seconds |
| Started | May 21 02:33:28 PM PDT 24 |
| Finished | May 21 02:35:28 PM PDT 24 |
| Peak memory | 206808 kb |
| Host | smart-64c2cb88-f690-4d77-b2d6-517439477ddb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694459949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2694459949 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2870425335 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 28245617 ps |
| CPU time | 2.75 seconds |
| Started | May 21 02:33:28 PM PDT 24 |
| Finished | May 21 02:33:47 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-347c77a2-846c-477a-b9cc-d6b9d1c96d20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2870425335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2870425335 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.4267998630 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 112354006 ps |
| CPU time | 8.71 seconds |
| Started | May 21 02:33:34 PM PDT 24 |
| Finished | May 21 02:33:58 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-531972fa-b4be-4f96-bdc0-8af37d7f789f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4267998630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.4267998630 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.4086697916 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 38055710268 ps |
| CPU time | 55.87 seconds |
| Started | May 21 02:33:37 PM PDT 24 |
| Finished | May 21 02:34:49 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-5defcafc-2a2d-40ea-ba65-b157c4394254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4086697916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.4086697916 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.157780454 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 60294206 ps |
| CPU time | 6.06 seconds |
| Started | May 21 02:33:38 PM PDT 24 |
| Finished | May 21 02:34:01 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-3cae8adc-3384-46e2-ae3e-2ec282d6e55a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=157780454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.157780454 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.2492072509 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 143070584 ps |
| CPU time | 1.67 seconds |
| Started | May 21 02:33:37 PM PDT 24 |
| Finished | May 21 02:33:54 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-751f5a60-4942-4e94-9980-e0d190676140 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492072509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2492072509 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.4000601519 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2437152373 ps |
| CPU time | 10.81 seconds |
| Started | May 21 02:33:34 PM PDT 24 |
| Finished | May 21 02:34:00 PM PDT 24 |
| Peak memory | 202280 kb |
| Host | smart-b115af61-926f-4610-8b30-38161d1e801a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000601519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.4000601519 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1988402737 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 15957216410 ps |
| CPU time | 45.89 seconds |
| Started | May 21 02:33:35 PM PDT 24 |
| Finished | May 21 02:34:37 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-dcadf18c-8cd7-4c05-935d-4b880235834e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988402737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1988402737 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3851995061 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 36310181696 ps |
| CPU time | 90.07 seconds |
| Started | May 21 02:33:35 PM PDT 24 |
| Finished | May 21 02:35:21 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-37ad220c-2227-47c6-82c2-6b45f7b1e7f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3851995061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3851995061 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.487562280 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 26309877 ps |
| CPU time | 3.8 seconds |
| Started | May 21 02:33:31 PM PDT 24 |
| Finished | May 21 02:33:50 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-7d2ef30b-2b94-4cea-a2b7-ebeb370b9620 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487562280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.487562280 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1676304093 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 850383473 ps |
| CPU time | 7.3 seconds |
| Started | May 21 02:33:37 PM PDT 24 |
| Finished | May 21 02:34:01 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-24c14192-91c6-4aae-8c1a-53c18763c8ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1676304093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1676304093 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.2092310934 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 173302404 ps |
| CPU time | 1.25 seconds |
| Started | May 21 02:33:31 PM PDT 24 |
| Finished | May 21 02:33:47 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-9439e22f-4704-456f-af2e-577f3c68ad4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2092310934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2092310934 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4094082929 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 4069888150 ps |
| CPU time | 8.44 seconds |
| Started | May 21 02:33:30 PM PDT 24 |
| Finished | May 21 02:33:54 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-f4e6c9fb-d395-4734-a0f1-de1ff02c338e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094082929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4094082929 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3418514433 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 7461277481 ps |
| CPU time | 7.64 seconds |
| Started | May 21 02:33:28 PM PDT 24 |
| Finished | May 21 02:33:51 PM PDT 24 |
| Peak memory | 202288 kb |
| Host | smart-a195ad84-4511-4aa9-a58b-a11bd3893c57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3418514433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3418514433 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3321824755 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 10815242 ps |
| CPU time | 1.18 seconds |
| Started | May 21 02:33:29 PM PDT 24 |
| Finished | May 21 02:33:45 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-4b9abfa7-2066-4865-989d-87e8c08f7328 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321824755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3321824755 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.4233184312 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 6789205586 ps |
| CPU time | 60.53 seconds |
| Started | May 21 02:33:36 PM PDT 24 |
| Finished | May 21 02:34:52 PM PDT 24 |
| Peak memory | 203280 kb |
| Host | smart-bb03b021-6825-4cd6-b0c2-627fa7c27884 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4233184312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4233184312 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3370223482 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 84665244 ps |
| CPU time | 6.21 seconds |
| Started | May 21 02:33:35 PM PDT 24 |
| Finished | May 21 02:33:57 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-7d609634-4a4d-4cc4-95c6-3f91ca4c3d24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3370223482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3370223482 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.27007749 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 409344417 ps |
| CPU time | 53.16 seconds |
| Started | May 21 02:33:35 PM PDT 24 |
| Finished | May 21 02:34:43 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-42630731-c152-45b8-a359-163292d6bce7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27007749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_r eset.27007749 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2951696792 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 276718654 ps |
| CPU time | 33.73 seconds |
| Started | May 21 02:33:39 PM PDT 24 |
| Finished | May 21 02:34:30 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-9d77b241-f80e-4e0d-93ad-c6eb625a86b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951696792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2951696792 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2989938197 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 590812319 ps |
| CPU time | 11.02 seconds |
| Started | May 21 02:33:36 PM PDT 24 |
| Finished | May 21 02:34:02 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-c8a7296a-b621-4c4e-bd08-bec4f8ebbea8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2989938197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2989938197 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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