| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.27 | 100.00 | 95.61 | 100.00 | 100.00 | 100.00 | 100.00 |
| T763 | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1018059052 | May 23 01:12:56 PM PDT 24 | May 23 01:13:07 PM PDT 24 | 65701836 ps | ||
| T11 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.113276423 | May 23 01:12:40 PM PDT 24 | May 23 01:14:22 PM PDT 24 | 6464515937 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1115235149 | May 23 01:14:05 PM PDT 24 | May 23 01:14:16 PM PDT 24 | 31490909 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1270149368 | May 23 01:14:31 PM PDT 24 | May 23 01:14:36 PM PDT 24 | 116703228 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3527562089 | May 23 01:14:07 PM PDT 24 | May 23 01:14:23 PM PDT 24 | 3894104210 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/20.xbar_same_source.116115131 | May 23 01:13:02 PM PDT 24 | May 23 01:13:06 PM PDT 24 | 15092387 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/46.xbar_same_source.4256738251 | May 23 01:14:18 PM PDT 24 | May 23 01:14:32 PM PDT 24 | 2169220603 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.856342888 | May 23 01:13:59 PM PDT 24 | May 23 01:15:01 PM PDT 24 | 4078361881 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2370673468 | May 23 01:13:00 PM PDT 24 | May 23 01:13:14 PM PDT 24 | 3399075185 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1351862047 | May 23 01:13:39 PM PDT 24 | May 23 01:13:57 PM PDT 24 | 144308342 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/5.xbar_error_random.3849768195 | May 23 01:12:26 PM PDT 24 | May 23 01:12:43 PM PDT 24 | 2130613316 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.746727452 | May 23 01:13:20 PM PDT 24 | May 23 01:13:25 PM PDT 24 | 11138892 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2016819924 | May 23 01:12:31 PM PDT 24 | May 23 01:12:44 PM PDT 24 | 682579202 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1966648109 | May 23 01:13:40 PM PDT 24 | May 23 01:13:44 PM PDT 24 | 8833615 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3944724454 | May 23 01:12:56 PM PDT 24 | May 23 01:13:55 PM PDT 24 | 27861903088 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3430135573 | May 23 01:12:51 PM PDT 24 | May 23 01:12:55 PM PDT 24 | 64520011 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.1680840598 | May 23 01:12:29 PM PDT 24 | May 23 01:12:56 PM PDT 24 | 290756330 ps | ||
| T219 | /workspace/coverage/xbar_build_mode/28.xbar_random.2202814215 | May 23 01:13:28 PM PDT 24 | May 23 01:13:46 PM PDT 24 | 2621451001 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2775055953 | May 23 01:14:18 PM PDT 24 | May 23 01:16:50 PM PDT 24 | 10940153230 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.195581336 | May 23 01:13:03 PM PDT 24 | May 23 01:13:14 PM PDT 24 | 68037794 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/19.xbar_random.3988012529 | May 23 01:12:56 PM PDT 24 | May 23 01:13:06 PM PDT 24 | 96726645 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.977757170 | May 23 01:14:21 PM PDT 24 | May 23 01:14:24 PM PDT 24 | 5884391 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.869075602 | May 23 01:12:14 PM PDT 24 | May 23 01:12:58 PM PDT 24 | 19944038068 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.572798324 | May 23 01:14:22 PM PDT 24 | May 23 01:14:30 PM PDT 24 | 168395431 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/20.xbar_random.3169849745 | May 23 01:12:56 PM PDT 24 | May 23 01:13:04 PM PDT 24 | 289205359 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/27.xbar_error_random.512642336 | May 23 01:13:26 PM PDT 24 | May 23 01:13:37 PM PDT 24 | 61380911 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1751389964 | May 23 01:12:24 PM PDT 24 | May 23 01:12:57 PM PDT 24 | 6962846156 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/13.xbar_random.863758521 | May 23 01:12:33 PM PDT 24 | May 23 01:12:37 PM PDT 24 | 176123239 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2253196352 | May 23 01:12:10 PM PDT 24 | May 23 01:12:13 PM PDT 24 | 73926363 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3736873079 | May 23 01:13:20 PM PDT 24 | May 23 01:14:58 PM PDT 24 | 25324400957 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3556831409 | May 23 01:12:14 PM PDT 24 | May 23 01:14:21 PM PDT 24 | 5209520682 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3578802845 | May 23 01:13:56 PM PDT 24 | May 23 01:14:10 PM PDT 24 | 1591762506 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/5.xbar_same_source.386451302 | May 23 01:12:26 PM PDT 24 | May 23 01:12:31 PM PDT 24 | 401650065 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.469584094 | May 23 01:13:55 PM PDT 24 | May 23 01:14:12 PM PDT 24 | 178747317 ps | ||
| T147 | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1045568393 | May 23 01:13:28 PM PDT 24 | May 23 01:16:04 PM PDT 24 | 62264037567 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2336354421 | May 23 01:13:56 PM PDT 24 | May 23 01:14:04 PM PDT 24 | 61614299 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.4045466346 | May 23 01:12:38 PM PDT 24 | May 23 01:12:41 PM PDT 24 | 91202150 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/32.xbar_same_source.4032533199 | May 23 01:13:36 PM PDT 24 | May 23 01:13:43 PM PDT 24 | 49345320 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2073040987 | May 23 01:14:32 PM PDT 24 | May 23 01:15:50 PM PDT 24 | 25629942292 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1104152597 | May 23 01:12:22 PM PDT 24 | May 23 01:12:42 PM PDT 24 | 1000984973 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.152467910 | May 23 01:13:15 PM PDT 24 | May 23 01:13:27 PM PDT 24 | 735109159 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/38.xbar_random.3180817944 | May 23 01:13:57 PM PDT 24 | May 23 01:14:04 PM PDT 24 | 47312104 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1414135399 | May 23 01:13:05 PM PDT 24 | May 23 01:13:13 PM PDT 24 | 49382264 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1068548077 | May 23 01:12:49 PM PDT 24 | May 23 01:12:55 PM PDT 24 | 44051159 ps | ||
| T221 | /workspace/coverage/xbar_build_mode/45.xbar_random.815839795 | May 23 01:14:17 PM PDT 24 | May 23 01:14:33 PM PDT 24 | 3551029976 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.755755225 | May 23 01:14:08 PM PDT 24 | May 23 01:14:17 PM PDT 24 | 66044427 ps | ||
| T184 | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1061941753 | May 23 01:13:46 PM PDT 24 | May 23 01:14:00 PM PDT 24 | 3957108583 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3127386608 | May 23 01:12:58 PM PDT 24 | May 23 01:13:03 PM PDT 24 | 29971771 ps | ||
| T186 | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.793873092 | May 23 01:12:58 PM PDT 24 | May 23 01:14:19 PM PDT 24 | 31932213655 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1011519114 | May 23 01:13:14 PM PDT 24 | May 23 01:13:24 PM PDT 24 | 2740225131 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1117008989 | May 23 01:12:59 PM PDT 24 | May 23 01:13:02 PM PDT 24 | 10857424 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1025233519 | May 23 01:13:55 PM PDT 24 | May 23 01:14:02 PM PDT 24 | 474850026 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2591638003 | May 23 01:14:29 PM PDT 24 | May 23 01:14:39 PM PDT 24 | 826729837 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3072035420 | May 23 01:12:42 PM PDT 24 | May 23 01:12:45 PM PDT 24 | 8939907 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3946845651 | May 23 01:14:18 PM PDT 24 | May 23 01:15:01 PM PDT 24 | 3595134745 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1254346111 | May 23 01:12:55 PM PDT 24 | May 23 01:12:59 PM PDT 24 | 33957429 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1404593276 | May 23 01:14:21 PM PDT 24 | May 23 01:14:29 PM PDT 24 | 256810893 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3907594287 | May 23 01:14:38 PM PDT 24 | May 23 01:14:58 PM PDT 24 | 3955464801 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.383101281 | May 23 01:14:29 PM PDT 24 | May 23 01:14:40 PM PDT 24 | 52260641 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.531359738 | May 23 01:13:13 PM PDT 24 | May 23 01:15:36 PM PDT 24 | 976936447 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3037590790 | May 23 01:14:36 PM PDT 24 | May 23 01:15:13 PM PDT 24 | 296680280 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2436668400 | May 23 01:13:33 PM PDT 24 | May 23 01:14:36 PM PDT 24 | 9825865337 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3342266660 | May 23 01:12:18 PM PDT 24 | May 23 01:12:28 PM PDT 24 | 667480853 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1403351735 | May 23 01:12:38 PM PDT 24 | May 23 01:15:03 PM PDT 24 | 44162877634 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.47131167 | May 23 01:13:14 PM PDT 24 | May 23 01:13:23 PM PDT 24 | 1319208093 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.518466227 | May 23 01:13:27 PM PDT 24 | May 23 01:13:37 PM PDT 24 | 2881632750 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.332057475 | May 23 01:12:23 PM PDT 24 | May 23 01:13:06 PM PDT 24 | 781852952 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.974015114 | May 23 01:14:30 PM PDT 24 | May 23 01:14:34 PM PDT 24 | 15985975 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2755383528 | May 23 01:14:28 PM PDT 24 | May 23 01:15:47 PM PDT 24 | 456218465 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.815331469 | May 23 01:13:16 PM PDT 24 | May 23 01:15:32 PM PDT 24 | 7906326095 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1505370608 | May 23 01:13:38 PM PDT 24 | May 23 01:14:14 PM PDT 24 | 2614692576 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3780547242 | May 23 01:13:09 PM PDT 24 | May 23 01:13:14 PM PDT 24 | 899503973 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.391042517 | May 23 01:12:40 PM PDT 24 | May 23 01:12:44 PM PDT 24 | 13667967 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/32.xbar_random.1775544513 | May 23 01:13:38 PM PDT 24 | May 23 01:13:41 PM PDT 24 | 10464256 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3894108688 | May 23 01:13:57 PM PDT 24 | May 23 01:14:44 PM PDT 24 | 4142787714 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/18.xbar_random.278713938 | May 23 01:12:56 PM PDT 24 | May 23 01:13:09 PM PDT 24 | 633461253 ps | ||
| T7 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2910394026 | May 23 01:12:30 PM PDT 24 | May 23 01:13:06 PM PDT 24 | 397127823 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1272398149 | May 23 01:12:08 PM PDT 24 | May 23 01:12:22 PM PDT 24 | 2793297077 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1130801624 | May 23 01:13:54 PM PDT 24 | May 23 01:14:02 PM PDT 24 | 680478596 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/36.xbar_same_source.4055379754 | May 23 01:13:54 PM PDT 24 | May 23 01:13:59 PM PDT 24 | 1289863028 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2192396298 | May 23 01:14:32 PM PDT 24 | May 23 01:15:25 PM PDT 24 | 5442786789 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1399097998 | May 23 01:13:06 PM PDT 24 | May 23 01:15:53 PM PDT 24 | 9559766349 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3036011323 | May 23 01:12:18 PM PDT 24 | May 23 01:12:20 PM PDT 24 | 9140244 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.573083930 | May 23 01:12:08 PM PDT 24 | May 23 01:12:14 PM PDT 24 | 145258784 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/2.xbar_random.2455283974 | May 23 01:12:15 PM PDT 24 | May 23 01:12:24 PM PDT 24 | 76380728 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/21.xbar_smoke.80699219 | May 23 01:13:06 PM PDT 24 | May 23 01:13:09 PM PDT 24 | 9896832 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3493635372 | May 23 01:12:09 PM PDT 24 | May 23 01:12:44 PM PDT 24 | 810228739 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.649042253 | May 23 01:12:30 PM PDT 24 | May 23 01:18:32 PM PDT 24 | 65476742151 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3809868704 | May 23 01:13:15 PM PDT 24 | May 23 01:13:27 PM PDT 24 | 56208914 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1862294415 | May 23 01:12:31 PM PDT 24 | May 23 01:12:35 PM PDT 24 | 16182581 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1517381373 | May 23 01:12:56 PM PDT 24 | May 23 01:13:02 PM PDT 24 | 78213131 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2955703140 | May 23 01:13:09 PM PDT 24 | May 23 01:16:52 PM PDT 24 | 2443400592 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2542315052 | May 23 01:12:09 PM PDT 24 | May 23 01:12:19 PM PDT 24 | 1168873916 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3929311497 | May 23 01:13:56 PM PDT 24 | May 23 01:15:55 PM PDT 24 | 19954335894 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.61883948 | May 23 01:13:06 PM PDT 24 | May 23 01:14:01 PM PDT 24 | 15373151182 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1696911592 | May 23 01:12:51 PM PDT 24 | May 23 01:12:54 PM PDT 24 | 13391739 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1885344107 | May 23 01:13:59 PM PDT 24 | May 23 01:14:03 PM PDT 24 | 10040566 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.227607310 | May 23 01:12:32 PM PDT 24 | May 23 01:12:40 PM PDT 24 | 266120632 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2616112691 | May 23 01:12:32 PM PDT 24 | May 23 01:13:22 PM PDT 24 | 8775897926 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.4164841007 | May 23 01:13:28 PM PDT 24 | May 23 01:13:34 PM PDT 24 | 115950292 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1156243843 | May 23 01:12:16 PM PDT 24 | May 23 01:12:26 PM PDT 24 | 615783954 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.571906582 | May 23 01:13:26 PM PDT 24 | May 23 01:13:37 PM PDT 24 | 554464042 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.852756119 | May 23 01:13:56 PM PDT 24 | May 23 01:16:01 PM PDT 24 | 36462941408 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2344277505 | May 23 01:13:08 PM PDT 24 | May 23 01:13:14 PM PDT 24 | 739345823 ps | ||
| T244 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3503767916 | May 23 01:12:29 PM PDT 24 | May 23 01:16:18 PM PDT 24 | 83504266295 ps | ||
| T160 | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4233899210 | May 23 01:13:39 PM PDT 24 | May 23 01:17:38 PM PDT 24 | 90418012424 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.4210600583 | May 23 01:12:42 PM PDT 24 | May 23 01:13:00 PM PDT 24 | 801670944 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4202382995 | May 23 01:12:08 PM PDT 24 | May 23 01:13:17 PM PDT 24 | 6803959997 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2357605015 | May 23 01:12:30 PM PDT 24 | May 23 01:12:36 PM PDT 24 | 51346030 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.41177539 | May 23 01:13:21 PM PDT 24 | May 23 01:13:52 PM PDT 24 | 338700158 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1145576152 | May 23 01:13:29 PM PDT 24 | May 23 01:13:40 PM PDT 24 | 1243803762 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.133902647 | May 23 01:14:04 PM PDT 24 | May 23 01:15:59 PM PDT 24 | 30306469134 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1223825237 | May 23 01:14:17 PM PDT 24 | May 23 01:14:20 PM PDT 24 | 42939544 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3161911074 | May 23 01:13:26 PM PDT 24 | May 23 01:13:33 PM PDT 24 | 17985773 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1342470111 | May 23 01:13:42 PM PDT 24 | May 23 01:13:49 PM PDT 24 | 45994188 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3844884078 | May 23 01:14:05 PM PDT 24 | May 23 01:14:10 PM PDT 24 | 20516416 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3069816505 | May 23 01:12:25 PM PDT 24 | May 23 01:12:28 PM PDT 24 | 9269187 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3696582408 | May 23 01:14:00 PM PDT 24 | May 23 01:14:12 PM PDT 24 | 1673170066 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3878076604 | May 23 01:13:28 PM PDT 24 | May 23 01:14:36 PM PDT 24 | 16817373796 ps | ||
| T107 | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.2256597221 | May 23 01:13:40 PM PDT 24 | May 23 01:13:54 PM PDT 24 | 2088035288 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3311047079 | May 23 01:12:48 PM PDT 24 | May 23 01:14:48 PM PDT 24 | 5182997891 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2046938971 | May 23 01:13:58 PM PDT 24 | May 23 01:14:01 PM PDT 24 | 9066498 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2378142143 | May 23 01:13:16 PM PDT 24 | May 23 01:13:25 PM PDT 24 | 990753907 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/8.xbar_random.4244370886 | May 23 01:12:32 PM PDT 24 | May 23 01:12:40 PM PDT 24 | 345802895 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.340739284 | May 23 01:13:26 PM PDT 24 | May 23 01:14:24 PM PDT 24 | 465281382 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1926715166 | May 23 01:13:29 PM PDT 24 | May 23 01:13:48 PM PDT 24 | 1639651731 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1104493554 | May 23 01:13:11 PM PDT 24 | May 23 01:13:19 PM PDT 24 | 298204792 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2855128172 | May 23 01:12:42 PM PDT 24 | May 23 01:12:44 PM PDT 24 | 9746504 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3159370768 | May 23 01:13:27 PM PDT 24 | May 23 01:15:54 PM PDT 24 | 29854613133 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4244980985 | May 23 01:12:59 PM PDT 24 | May 23 01:13:13 PM PDT 24 | 2852235996 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.261191502 | May 23 01:14:30 PM PDT 24 | May 23 01:14:52 PM PDT 24 | 993940580 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3813543459 | May 23 01:14:05 PM PDT 24 | May 23 01:14:09 PM PDT 24 | 43757644 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.153925500 | May 23 01:12:36 PM PDT 24 | May 23 01:13:01 PM PDT 24 | 3364065574 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3104911635 | May 23 01:13:03 PM PDT 24 | May 23 01:13:08 PM PDT 24 | 17964879 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3161395663 | May 23 01:13:54 PM PDT 24 | May 23 01:14:14 PM PDT 24 | 198502596 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/48.xbar_random.2709575635 | May 23 01:14:31 PM PDT 24 | May 23 01:14:41 PM PDT 24 | 789678899 ps | ||
| T108 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1825306021 | May 23 01:14:07 PM PDT 24 | May 23 01:20:16 PM PDT 24 | 438452861107 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1900756989 | May 23 01:12:24 PM PDT 24 | May 23 01:14:01 PM PDT 24 | 20384130415 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/42.xbar_random.208476514 | May 23 01:14:11 PM PDT 24 | May 23 01:14:18 PM PDT 24 | 152966334 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.995327936 | May 23 01:12:35 PM PDT 24 | May 23 01:12:44 PM PDT 24 | 50962321 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/29.xbar_error_random.1264448177 | May 23 01:13:25 PM PDT 24 | May 23 01:13:41 PM PDT 24 | 1288857973 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2291707066 | May 23 01:13:42 PM PDT 24 | May 23 01:13:52 PM PDT 24 | 88357283 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1482402393 | May 23 01:14:42 PM PDT 24 | May 23 01:14:49 PM PDT 24 | 209468134 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3141116033 | May 23 01:13:06 PM PDT 24 | May 23 01:13:28 PM PDT 24 | 540533556 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.930633953 | May 23 01:13:34 PM PDT 24 | May 23 01:16:44 PM PDT 24 | 1781616146 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/34.xbar_same_source.3295855398 | May 23 01:13:40 PM PDT 24 | May 23 01:13:49 PM PDT 24 | 97006119 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2909142872 | May 23 01:14:17 PM PDT 24 | May 23 01:15:13 PM PDT 24 | 15583797710 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2284718738 | May 23 01:13:14 PM PDT 24 | May 23 01:18:17 PM PDT 24 | 69525143452 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/42.xbar_smoke.98332126 | May 23 01:14:08 PM PDT 24 | May 23 01:14:12 PM PDT 24 | 45720389 ps | ||
| T181 | /workspace/coverage/xbar_build_mode/23.xbar_random.3846657277 | May 23 01:13:03 PM PDT 24 | May 23 01:13:15 PM PDT 24 | 3025792803 ps |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1287745843 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 16493785734 ps |
| CPU time | 66.85 seconds |
| Started | May 23 01:12:57 PM PDT 24 |
| Finished | May 23 01:14:07 PM PDT 24 |
| Peak memory | 203316 kb |
| Host | smart-2ab564bb-42da-4a2f-a87c-0b11be13cb48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1287745843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1287745843 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3727404966 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 47898949863 ps |
| CPU time | 291.39 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:17:33 PM PDT 24 |
| Peak memory | 203244 kb |
| Host | smart-458fcaf0-a69c-4010-9d64-98b48db0c2d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3727404966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3727404966 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.4169817458 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 40685330331 ps |
| CPU time | 220.21 seconds |
| Started | May 23 01:12:45 PM PDT 24 |
| Finished | May 23 01:16:27 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-898268c9-d0ef-4d86-9f6e-6bb875482ad9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4169817458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.4169817458 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2482479284 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 94349726741 ps |
| CPU time | 251.8 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:18:44 PM PDT 24 |
| Peak memory | 203292 kb |
| Host | smart-3fc91f89-7014-46f7-b190-85bb3c2cbaa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2482479284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2482479284 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1408944252 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 52106179721 ps |
| CPU time | 296.53 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:17:39 PM PDT 24 |
| Peak memory | 203164 kb |
| Host | smart-6adbd0f6-f81e-4dee-9ed3-feff54baad33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1408944252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1408944252 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4273953875 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 159346013 ps |
| CPU time | 29.71 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:52 PM PDT 24 |
| Peak memory | 203896 kb |
| Host | smart-03327bd9-1fdd-41b5-ab1a-84a090506248 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4273953875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.4273953875 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3173166366 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13281078018 ps |
| CPU time | 65.37 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:14:23 PM PDT 24 |
| Peak memory | 204260 kb |
| Host | smart-8d6f3a6b-4e71-4355-94a3-62624b926325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3173166366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3173166366 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2573647374 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 68079489311 ps |
| CPU time | 332.11 seconds |
| Started | May 23 01:14:12 PM PDT 24 |
| Finished | May 23 01:19:46 PM PDT 24 |
| Peak memory | 203184 kb |
| Host | smart-a594f043-f430-4f1a-b581-b01eb0b2f2c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2573647374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2573647374 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2226500276 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 211997160178 ps |
| CPU time | 204.89 seconds |
| Started | May 23 01:12:43 PM PDT 24 |
| Finished | May 23 01:16:09 PM PDT 24 |
| Peak memory | 203452 kb |
| Host | smart-1ccdade5-34f6-4d25-953e-1cfe069651ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2226500276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2226500276 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3612637328 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 37450492740 ps |
| CPU time | 267.53 seconds |
| Started | May 23 01:13:53 PM PDT 24 |
| Finished | May 23 01:18:21 PM PDT 24 |
| Peak memory | 203160 kb |
| Host | smart-6b4a45ad-bdf4-4856-b249-7f05320cb5e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3612637328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3612637328 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2227993450 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 31192857689 ps |
| CPU time | 119.58 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:14:58 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-47fe4f9e-3328-4f77-bea2-66c7727528d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227993450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2227993450 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.828362901 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1456438208 ps |
| CPU time | 133.59 seconds |
| Started | May 23 01:12:19 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 207584 kb |
| Host | smart-c1cc7809-aab6-4031-baf6-73de6576f3d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=828362901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.828362901 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1168403927 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7179507421 ps |
| CPU time | 163.4 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:15:16 PM PDT 24 |
| Peak memory | 206244 kb |
| Host | smart-ae064d7b-6bbe-4174-a658-09ee053d711d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168403927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1168403927 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.891132599 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 42339881794 ps |
| CPU time | 263.39 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:17:53 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-3989b52c-73a4-489a-aa51-3963121e8adc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=891132599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.891132599 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1308302048 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 996780635 ps |
| CPU time | 18.54 seconds |
| Started | May 23 01:13:19 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-6ece480c-0a01-48c2-aa3a-a3fcad7020d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1308302048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1308302048 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.845198818 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 520807456 ps |
| CPU time | 71.71 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:13:45 PM PDT 24 |
| Peak memory | 204956 kb |
| Host | smart-2359443c-7299-4f72-9269-a0056e5cbc19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=845198818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.845198818 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.984637154 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2280450957 ps |
| CPU time | 11.06 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:49 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-c666cf78-2f25-4bf9-b0c2-0d3d96bba359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=984637154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.984637154 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.113276423 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6464515937 ps |
| CPU time | 100.67 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:14:22 PM PDT 24 |
| Peak memory | 204276 kb |
| Host | smart-b6fadd16-4b03-4191-af30-af76f6924f1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=113276423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.113276423 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.262644776 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 996864703 ps |
| CPU time | 102.1 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:16:04 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-5e2d483a-cb1b-44e5-9667-fd27f7bfcd3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=262644776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.262644776 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1487661484 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 7384447827 ps |
| CPU time | 21.13 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:32 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-e1e674ff-4961-472a-8909-c30862e8b041 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487661484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1487661484 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2969980017 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2211224182 ps |
| CPU time | 51.54 seconds |
| Started | May 23 01:12:46 PM PDT 24 |
| Finished | May 23 01:13:40 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-2c23d08b-c1ac-44e3-93e1-0bebe2c4de28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2969980017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.2969980017 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1825306021 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 438452861107 ps |
| CPU time | 365.97 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:20:16 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-f495ebb8-2f73-424c-8c67-dd10d1459965 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1825306021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1825306021 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3741114452 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 21997628349 ps |
| CPU time | 184.53 seconds |
| Started | May 23 01:12:49 PM PDT 24 |
| Finished | May 23 01:15:55 PM PDT 24 |
| Peak memory | 205148 kb |
| Host | smart-2bec6f51-37a5-410d-aca1-f124a83b59ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3741114452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3741114452 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3210391774 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 408108164 ps |
| CPU time | 62.21 seconds |
| Started | May 23 01:12:52 PM PDT 24 |
| Finished | May 23 01:13:57 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-044bd0be-81fb-4fc9-a641-aa8b92d60023 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3210391774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3210391774 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.712293656 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5592608843 ps |
| CPU time | 41.96 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:15:02 PM PDT 24 |
| Peak memory | 203244 kb |
| Host | smart-aa0c01c2-647c-4a05-88eb-882218557a9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=712293656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.712293656 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.4213404543 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5589654046 ps |
| CPU time | 70 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:13:21 PM PDT 24 |
| Peak memory | 206656 kb |
| Host | smart-2ccda8d4-418d-4d40-b0f9-023e01b8f045 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213404543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.4213404543 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.4292077986 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26060347944 ps |
| CPU time | 126.99 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:15:05 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-d8a59c53-9542-448d-b09e-9a6d65ff0634 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292077986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4292077986 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4099655918 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3429500090 ps |
| CPU time | 82.98 seconds |
| Started | May 23 01:13:07 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 204960 kb |
| Host | smart-51a9c20a-5fbb-4d65-8915-14a5bc8f4785 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4099655918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.4099655918 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1489340571 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 21867922899 ps |
| CPU time | 111.05 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:14:06 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-1604b503-bfd2-466e-b6eb-453a32125653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1489340571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.1489340571 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2218948615 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 315434826 ps |
| CPU time | 6.74 seconds |
| Started | May 23 01:12:07 PM PDT 24 |
| Finished | May 23 01:12:14 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-85eb188e-2564-4c38-8362-60f6ddd7b9fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2218948615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2218948615 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.1990549001 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 219052406 ps |
| CPU time | 4.85 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:14 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-f557c81a-863e-4848-99e1-8a7f9bcdfe6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990549001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1990549001 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.2114683264 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 24934424 ps |
| CPU time | 1.46 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-11dae088-93c7-4705-8cb4-88829943cf9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2114683264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2114683264 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3731971961 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 53680045186 ps |
| CPU time | 106.54 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:14:02 PM PDT 24 |
| Peak memory | 201884 kb |
| Host | smart-128c34d1-5524-4e4c-8f6b-4f600bdf46e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731971961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3731971961 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.279985550 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5546892464 ps |
| CPU time | 25.72 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:37 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-f34d3852-a0d7-4489-b9af-d3758f88e3ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=279985550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.279985550 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3941301231 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 92038083 ps |
| CPU time | 1.94 seconds |
| Started | May 23 01:12:11 PM PDT 24 |
| Finished | May 23 01:12:14 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-a2c794f1-1b10-46ff-b5bb-9348d43010b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941301231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3941301231 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.573083930 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 145258784 ps |
| CPU time | 4.58 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:14 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-177e79e1-8270-49b1-9cc1-993297394aea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=573083930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.573083930 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.810497254 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 10948445 ps |
| CPU time | 1.36 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:11 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-f987f11a-4222-4109-98df-0dfbeb6c0194 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=810497254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.810497254 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.4109538287 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2634652968 ps |
| CPU time | 8.84 seconds |
| Started | May 23 01:12:16 PM PDT 24 |
| Finished | May 23 01:12:26 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-dd9ec5d8-a660-4331-a04f-38a7ab82ee23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109538287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4109538287 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.819740030 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3575118720 ps |
| CPU time | 11.39 seconds |
| Started | May 23 01:12:12 PM PDT 24 |
| Finished | May 23 01:12:24 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-a584b0f0-5d68-427d-b976-2ac0501cb7ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=819740030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.819740030 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3036011323 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 9140244 ps |
| CPU time | 1.34 seconds |
| Started | May 23 01:12:18 PM PDT 24 |
| Finished | May 23 01:12:20 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-cb544ac9-9e96-4b97-b3b2-a1fb901296f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036011323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3036011323 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.1609693692 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 922139111 ps |
| CPU time | 48.22 seconds |
| Started | May 23 01:12:09 PM PDT 24 |
| Finished | May 23 01:12:58 PM PDT 24 |
| Peak memory | 203288 kb |
| Host | smart-dba7ca41-c9bd-4670-a0e1-838bbcb1c49d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1609693692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1609693692 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3493635372 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 810228739 ps |
| CPU time | 33.96 seconds |
| Started | May 23 01:12:09 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-1a24cabb-7dd8-4bbb-bbf4-991e6d615a16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3493635372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3493635372 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1182134971 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2615162120 ps |
| CPU time | 85.16 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 206940 kb |
| Host | smart-99812200-d898-47b1-9665-eb3e32e1cc13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1182134971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1182134971 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3804319362 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3127705548 ps |
| CPU time | 122.01 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 206412 kb |
| Host | smart-2e7324a7-affb-41ed-835e-b308bc3e68e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3804319362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3804319362 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2784053603 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 120243917 ps |
| CPU time | 1.19 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:12:16 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-2dfe3820-abe8-4bef-9274-ecc2a9a85f8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784053603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2784053603 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3675255173 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 41441160 ps |
| CPU time | 8.17 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:17 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-98975d0c-942a-42f6-9dfa-b2a995a2d776 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3675255173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3675255173 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.556312629 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 15018863877 ps |
| CPU time | 60.72 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:13:10 PM PDT 24 |
| Peak memory | 203156 kb |
| Host | smart-0dca5d09-e09d-4531-9ba6-d16af355d859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=556312629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.556312629 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1153914247 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1154249627 ps |
| CPU time | 10.99 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:12:26 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-0c48a7ab-a625-44d9-9e26-79e307ca1f42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1153914247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1153914247 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.1000092609 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 543905271 ps |
| CPU time | 4.42 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:15 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-cf7fca5f-cc05-47b5-8fb8-e90d82c88141 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1000092609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1000092609 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.409224243 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 300408396 ps |
| CPU time | 1.99 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-8bcf466e-e5b9-4f1c-84a6-c0307aab0cfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409224243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.409224243 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.78680436 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 60087696384 ps |
| CPU time | 218.46 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:15:53 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-a62993c2-03f7-443c-ba95-1bdd7d599b65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=78680436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.78680436 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3623533804 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 31752866007 ps |
| CPU time | 117.13 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:14:06 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-779cae26-3a6c-4e86-b47c-7f96a112259e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3623533804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3623533804 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1238104619 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 15603981 ps |
| CPU time | 2.07 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-1e8d4328-c5bb-4b91-abf2-a576d6c123b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238104619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1238104619 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.3208622135 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 141784403 ps |
| CPU time | 2.09 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:11 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-69eaf553-f353-42cd-8283-0f0a44e39d59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3208622135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3208622135 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.2492159569 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 122395879 ps |
| CPU time | 1.35 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:11 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-37749deb-1f91-475a-ba55-4ab4525d709d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492159569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2492159569 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3653614730 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2621574683 ps |
| CPU time | 8.07 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:12:24 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-fb2133f3-0e15-410e-a965-5ac99130819f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653614730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3653614730 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1272398149 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2793297077 ps |
| CPU time | 12.07 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:22 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-f20bde53-f409-4dd4-a890-6752f675e55f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1272398149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1272398149 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1103545963 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 14985425 ps |
| CPU time | 1.23 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:10 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-c1c22860-5a38-4d2d-ab79-e7b6907ba0fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103545963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1103545963 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.477001180 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 70700020 ps |
| CPU time | 8.53 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:12:23 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-59eb414d-86f2-4237-a4e0-e47d7e75a05d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=477001180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.477001180 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2486974325 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 62723367 ps |
| CPU time | 5.54 seconds |
| Started | May 23 01:12:07 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-f2557799-0d19-480c-bd40-70fbf5702665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2486974325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2486974325 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.819036722 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2258292910 ps |
| CPU time | 110.81 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:14:06 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-e1556f00-9821-4b00-8b7c-e32953a81e94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=819036722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.819036722 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2542315052 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1168873916 ps |
| CPU time | 9.03 seconds |
| Started | May 23 01:12:09 PM PDT 24 |
| Finished | May 23 01:12:19 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-b1b7030e-3207-4262-9e66-9c1adb076b35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2542315052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2542315052 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1159022892 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 671273059 ps |
| CPU time | 13.67 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:55 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-0c716511-ecf9-4235-9cc8-c7df46d0438b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1159022892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1159022892 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2475776397 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 109175584 ps |
| CPU time | 6.28 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-12847b07-9723-4939-a7a5-6452d60e3012 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2475776397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2475776397 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.1581463682 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 242545549 ps |
| CPU time | 2.85 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-cfa956fc-52c9-41f6-bf1c-d191009e5016 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1581463682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1581463682 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.1188434778 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 64892462 ps |
| CPU time | 5 seconds |
| Started | May 23 01:12:48 PM PDT 24 |
| Finished | May 23 01:12:54 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-5bc27877-4756-4298-b853-f78a2af6641a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1188434778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1188434778 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3057665630 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 67549630658 ps |
| CPU time | 134.9 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:14:57 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-65e8a0ed-4285-41c6-be42-30a3484091de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057665630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3057665630 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2828596517 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4071969772 ps |
| CPU time | 29.48 seconds |
| Started | May 23 01:12:51 PM PDT 24 |
| Finished | May 23 01:13:22 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-b8fb7196-7867-4f5f-8092-06965c4537ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2828596517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2828596517 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.995327936 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 50962321 ps |
| CPU time | 7.1 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-47bcf42c-3f5b-4946-8092-67ca5a9d1d15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995327936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.995327936 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.2139501355 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 833838670 ps |
| CPU time | 9 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:49 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-bc943e1b-b0b3-4caf-bfe3-de309d090a34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2139501355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2139501355 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.4045466346 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 91202150 ps |
| CPU time | 1.42 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:41 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-6e395d04-d361-4303-9a5d-bb0b72d8eca2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4045466346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4045466346 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1703106308 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3645334584 ps |
| CPU time | 5.62 seconds |
| Started | May 23 01:12:41 PM PDT 24 |
| Finished | May 23 01:12:48 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-f19743ce-f12e-4398-b3f6-5d20430b77c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703106308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1703106308 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.347582400 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1768908198 ps |
| CPU time | 8.57 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:50 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-3457e501-4c00-4a71-b8ad-3f9609d7afa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=347582400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.347582400 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2855128172 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 9746504 ps |
| CPU time | 1.07 seconds |
| Started | May 23 01:12:42 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-1b7669ed-b723-40f3-9622-5be4caf08077 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855128172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2855128172 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1145294815 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2465673333 ps |
| CPU time | 20.54 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:13:01 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-f89ab5fb-67f9-469e-8153-a08f31d8a344 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1145294815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1145294815 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.598326007 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2343982449 ps |
| CPU time | 19.47 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:15 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-5d32e7ed-0506-4cea-a55f-86651c4a5cdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=598326007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.598326007 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3135210218 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1038376701 ps |
| CPU time | 130.04 seconds |
| Started | May 23 01:12:47 PM PDT 24 |
| Finished | May 23 01:14:58 PM PDT 24 |
| Peak memory | 206872 kb |
| Host | smart-4f2aa51c-c68b-4706-9785-2048ec06fae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3135210218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3135210218 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3311047079 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 5182997891 ps |
| CPU time | 117.89 seconds |
| Started | May 23 01:12:48 PM PDT 24 |
| Finished | May 23 01:14:48 PM PDT 24 |
| Peak memory | 205260 kb |
| Host | smart-0d906485-48e1-47b1-bfa1-51c872e2142c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3311047079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3311047079 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2000572158 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 17885660 ps |
| CPU time | 1.79 seconds |
| Started | May 23 01:12:45 PM PDT 24 |
| Finished | May 23 01:12:48 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-67ff973a-0af2-4311-b529-7edcfe341db8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2000572158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2000572158 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3315332456 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 11099145 ps |
| CPU time | 1.32 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:39 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-da413ee0-dad8-49e5-b202-526e89e0a031 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3315332456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3315332456 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1389274091 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 63933323 ps |
| CPU time | 6.26 seconds |
| Started | May 23 01:12:46 PM PDT 24 |
| Finished | May 23 01:12:54 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-372713d6-cb9d-4022-9dc6-ad6fdb3f2aa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1389274091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1389274091 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1588291226 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 94257533 ps |
| CPU time | 7.46 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:49 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-b926df7e-b5de-4d36-b944-4be1f78ad90b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1588291226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1588291226 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.3356877291 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 55343081 ps |
| CPU time | 2.81 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:37 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-06843945-c5e6-4396-ab10-08f8d9a0ddca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3356877291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3356877291 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1202636961 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 30081197852 ps |
| CPU time | 61.11 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202108 kb |
| Host | smart-e0cd9333-91ea-47c8-9382-a6d500ad2b50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202636961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1202636961 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3155161629 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 182348834926 ps |
| CPU time | 161.23 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:15:21 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-18b1c250-05db-4be0-a120-b526112719d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3155161629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3155161629 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1073789061 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 64668849 ps |
| CPU time | 8.73 seconds |
| Started | May 23 01:12:43 PM PDT 24 |
| Finished | May 23 01:12:54 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-8f93bf70-d1a7-4ec6-99e9-f2765667cf26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073789061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1073789061 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3085120476 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1697374007 ps |
| CPU time | 11.12 seconds |
| Started | May 23 01:12:48 PM PDT 24 |
| Finished | May 23 01:13:00 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-b56455a1-4601-4521-865e-653ea86a53b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085120476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3085120476 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3060100454 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 131155048 ps |
| CPU time | 1.58 seconds |
| Started | May 23 01:12:44 PM PDT 24 |
| Finished | May 23 01:12:47 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-463f9395-0697-411d-9b30-bf95aab32896 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3060100454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3060100454 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2109828237 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2306253728 ps |
| CPU time | 6.58 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:45 PM PDT 24 |
| Peak memory | 202108 kb |
| Host | smart-e54fa177-6a0e-463c-95e5-ef721ed2bdf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109828237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2109828237 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.4031503349 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1692949036 ps |
| CPU time | 7.47 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-5837cc46-55c2-4ad1-baec-d82ad030f1ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4031503349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.4031503349 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.116459055 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 10027845 ps |
| CPU time | 1.33 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:36 PM PDT 24 |
| Peak memory | 202108 kb |
| Host | smart-fc00934b-a833-495a-a2a0-6de95f16e3b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116459055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.116459055 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3698100052 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1536011020 ps |
| CPU time | 61.12 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:13:38 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-65431870-00bc-4c3b-979b-616a9c6f83f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3698100052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3698100052 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1649305010 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 364278348 ps |
| CPU time | 7.75 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-e6527cc1-7364-4cb2-ba5e-6b98faef3a2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1649305010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1649305010 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2802377156 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5240972403 ps |
| CPU time | 107.33 seconds |
| Started | May 23 01:12:42 PM PDT 24 |
| Finished | May 23 01:14:31 PM PDT 24 |
| Peak memory | 204068 kb |
| Host | smart-b8c92b3c-14ed-4e05-a791-4fce2520db90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2802377156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2802377156 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.391042517 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 13667967 ps |
| CPU time | 1.67 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-8a195af4-2125-4330-8a0f-e31a58702ba5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=391042517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.391042517 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3887776559 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1208932910 ps |
| CPU time | 15.7 seconds |
| Started | May 23 01:12:34 PM PDT 24 |
| Finished | May 23 01:12:51 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-fc4f8a37-d681-4ded-9f2d-4d7476c191ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3887776559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3887776559 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1791302115 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 271392953 ps |
| CPU time | 5.42 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202116 kb |
| Host | smart-14868037-d405-417c-b7fd-d37dda29a7ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1791302115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1791302115 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.3389409325 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3630683006 ps |
| CPU time | 14.67 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:12:47 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-cd4c7af7-7dcb-4dbe-92cc-cbaea11f7b9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3389409325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3389409325 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.1149764552 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 736271067 ps |
| CPU time | 8.72 seconds |
| Started | May 23 01:12:48 PM PDT 24 |
| Finished | May 23 01:12:58 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-aa7ac9b1-2d23-430c-a3ec-2a84db179246 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149764552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1149764552 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3501134511 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 18939621858 ps |
| CPU time | 86.88 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-6c3f2393-1259-4969-8e1e-81a476d26f32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501134511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3501134511 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3518689218 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 11972867449 ps |
| CPU time | 82.01 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 202116 kb |
| Host | smart-bb062265-a71a-49f0-ab2c-31cae78a5e92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3518689218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3518689218 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1626907632 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 26978479 ps |
| CPU time | 2.66 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-580cb98a-ea9d-4145-97b4-1541ca6afd1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626907632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1626907632 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.2029463022 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2705469166 ps |
| CPU time | 11.02 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:53 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-3dda6f02-1bf7-45e9-88de-d20c55408fde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2029463022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2029463022 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2103344287 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 42642744 ps |
| CPU time | 1.31 seconds |
| Started | May 23 01:12:47 PM PDT 24 |
| Finished | May 23 01:12:50 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-dd5b2a02-df88-4f87-af92-865ded07a9ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103344287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2103344287 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2182290738 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4480674883 ps |
| CPU time | 7.36 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:49 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-1c144d82-28c9-402a-8fce-522146254b5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182290738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2182290738 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3143846536 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 3174903643 ps |
| CPU time | 13.63 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:12:50 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-4067fd91-e807-4953-a6ed-2e90d38995af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3143846536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3143846536 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3072035420 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 8939907 ps |
| CPU time | 1.27 seconds |
| Started | May 23 01:12:42 PM PDT 24 |
| Finished | May 23 01:12:45 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-9578827d-d76c-4a51-9ed2-747dea05c7ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072035420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3072035420 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2364135503 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 792975343 ps |
| CPU time | 23.33 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:13:00 PM PDT 24 |
| Peak memory | 203184 kb |
| Host | smart-ab2c4947-06de-427f-a028-c38a8ce7759f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2364135503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2364135503 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.4210600583 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 801670944 ps |
| CPU time | 16.45 seconds |
| Started | May 23 01:12:42 PM PDT 24 |
| Finished | May 23 01:13:00 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-072699a5-7592-4331-9b90-62e914fadb80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4210600583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4210600583 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2718657187 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 211228991 ps |
| CPU time | 23.29 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 203276 kb |
| Host | smart-bea006fc-9742-4e48-9db0-b0de25426061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2718657187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2718657187 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1740038113 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 54448645 ps |
| CPU time | 1.64 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-7a15d65c-00ef-479d-b845-3a8f37cdf317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1740038113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1740038113 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1891712131 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 53760310 ps |
| CPU time | 9.29 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-5432a86e-7106-4d8c-8aa9-aa90387dc40e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1891712131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1891712131 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2930064415 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 173408285880 ps |
| CPU time | 285.4 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:17:24 PM PDT 24 |
| Peak memory | 203168 kb |
| Host | smart-33a6bb54-f407-4d8c-9a89-7aff3361a9c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2930064415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2930064415 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3372044710 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 836141732 ps |
| CPU time | 8.34 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:48 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-6e3633e3-3107-4bb9-ab70-5cad96c0df89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372044710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3372044710 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.740244849 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 790867302 ps |
| CPU time | 10.92 seconds |
| Started | May 23 01:12:46 PM PDT 24 |
| Finished | May 23 01:12:59 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-a12fb1de-0b3e-41bf-bf70-8c6d90b5c0e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=740244849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.740244849 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.863758521 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 176123239 ps |
| CPU time | 2.35 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:37 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-8ffc5e79-d90e-4ced-9045-ecc5de80d8a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863758521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.863758521 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.313392665 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 12839640296 ps |
| CPU time | 50.2 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:13:27 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-1d5509a6-6e18-49c8-8fde-6e26a09fc7ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=313392665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.313392665 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2940703399 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1176675831 ps |
| CPU time | 7.41 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:47 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-85067332-06ca-429b-bcb8-daa4b2553c58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2940703399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2940703399 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3819031080 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 87686668 ps |
| CPU time | 8.98 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:51 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-1b16fd5e-3d0a-4afb-aa25-7662d41ccf82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819031080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3819031080 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.536795675 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 287715616 ps |
| CPU time | 3.41 seconds |
| Started | May 23 01:12:46 PM PDT 24 |
| Finished | May 23 01:12:51 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-4f74a92f-0fd3-4f0b-98ef-137f04b0c998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=536795675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.536795675 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1696911592 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 13391739 ps |
| CPU time | 1.45 seconds |
| Started | May 23 01:12:51 PM PDT 24 |
| Finished | May 23 01:12:54 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-a341402a-34da-4b38-a37f-c517c3b65e2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1696911592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1696911592 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2196381636 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1917004989 ps |
| CPU time | 8.08 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-92edf051-51c1-4894-9f0b-83475302f3be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196381636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2196381636 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3366293421 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 936511843 ps |
| CPU time | 7.11 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-c054e18c-df34-43c0-9a02-15b03b8ccd9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3366293421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3366293421 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1419573125 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 10078392 ps |
| CPU time | 1.21 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:12:35 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-a6fa78d6-0059-45bd-aa64-086061a57dc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419573125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1419573125 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3087028676 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2893121843 ps |
| CPU time | 47.98 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:13:24 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-7308f976-8060-4a4d-9654-f8ccad5bf6a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3087028676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3087028676 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2427459277 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2771164232 ps |
| CPU time | 27.24 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-fc297523-5926-4ae4-a7e1-02f2a6987484 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2427459277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2427459277 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.173547052 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3823241672 ps |
| CPU time | 115.42 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:14:31 PM PDT 24 |
| Peak memory | 205128 kb |
| Host | smart-ebd0bd1e-be5a-404d-bdaf-36b95f368d85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173547052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.173547052 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.425746563 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 177681240 ps |
| CPU time | 24.99 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 203256 kb |
| Host | smart-73e38dae-e6d5-49be-ba0e-b6f2dfe4996e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=425746563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.425746563 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1254346111 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 33957429 ps |
| CPU time | 2.95 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:12:59 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-b5f55f30-80b2-4a23-8914-b16fbc92ec05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1254346111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1254346111 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2739847318 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 85940365 ps |
| CPU time | 6.07 seconds |
| Started | May 23 01:12:50 PM PDT 24 |
| Finished | May 23 01:12:58 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-5df48bdd-370b-47cf-9f5e-c789ad452944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2739847318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2739847318 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.3771115710 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 691013916 ps |
| CPU time | 7.39 seconds |
| Started | May 23 01:12:45 PM PDT 24 |
| Finished | May 23 01:12:55 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-6478a3ee-b5b0-469a-884a-b82da2255017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3771115710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3771115710 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.2315383027 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1262065446 ps |
| CPU time | 6.09 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-ae7b9bf2-38ea-46f6-a9bd-dc910d6eece4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2315383027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2315383027 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.320562202 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 29760646610 ps |
| CPU time | 141.62 seconds |
| Started | May 23 01:12:44 PM PDT 24 |
| Finished | May 23 01:15:07 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-7fa69f7f-ef6d-4f70-9c8d-251a9cea6cd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=320562202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.320562202 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3775542110 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 14447749512 ps |
| CPU time | 81.35 seconds |
| Started | May 23 01:12:52 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-ea11974b-1ddb-461c-8c48-a17778bfedd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3775542110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3775542110 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3889576326 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 48646747 ps |
| CPU time | 5.32 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:45 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-859a5c8b-199f-4532-aca6-84d5203f58eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889576326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3889576326 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.2424584503 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 61464687 ps |
| CPU time | 4.22 seconds |
| Started | May 23 01:12:48 PM PDT 24 |
| Finished | May 23 01:12:54 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-9a7cada5-442b-4123-a2e1-09b77ec897ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2424584503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2424584503 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3430135573 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 64520011 ps |
| CPU time | 1.54 seconds |
| Started | May 23 01:12:51 PM PDT 24 |
| Finished | May 23 01:12:55 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-19e38d89-b6bb-4e8b-b8bd-45bbf4b391d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430135573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3430135573 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3564129618 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1667115548 ps |
| CPU time | 7.86 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:47 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-4af01a25-6822-45b0-8177-13d8b81b5f72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564129618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3564129618 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.198561387 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5096449213 ps |
| CPU time | 12.47 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:10 PM PDT 24 |
| Peak memory | 202004 kb |
| Host | smart-b197e963-aef5-4d32-b575-ebdc8a46f9b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=198561387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.198561387 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.807106092 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 10406267 ps |
| CPU time | 1.1 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:12:39 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-2d25e709-4106-49d8-ab34-569b85a824db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807106092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.807106092 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3780601384 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 241610929 ps |
| CPU time | 22.06 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:13:02 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-a9b59951-1cbb-4e80-8a0d-3f1c58c7f143 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3780601384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3780601384 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.967154180 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 89986739 ps |
| CPU time | 6.61 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:45 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-4af44eba-9185-46c5-a93a-13fa9953b33a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=967154180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.967154180 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2612058004 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 294392465 ps |
| CPU time | 50.32 seconds |
| Started | May 23 01:12:50 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-fb79cf03-d288-4119-bef6-b10141adcf02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2612058004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.2612058004 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2247692714 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 403922382 ps |
| CPU time | 39.89 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:13:21 PM PDT 24 |
| Peak memory | 204504 kb |
| Host | smart-68b58a4b-5eea-4f9f-960e-b3b57fdb26cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2247692714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2247692714 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.474095591 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 678384890 ps |
| CPU time | 3.2 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:12:40 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-6736f0ec-5b2c-43e2-b113-972078b4ac38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=474095591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.474095591 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.694511274 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4351599301 ps |
| CPU time | 15.64 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:12 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-d128698d-3e99-4280-8eab-3f7e65e44b3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=694511274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.694511274 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2976121083 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6982574636 ps |
| CPU time | 30.01 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:32 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-85c46f38-0788-4d8a-a4e9-0eaebf84e1e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2976121083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2976121083 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1068548077 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 44051159 ps |
| CPU time | 4.13 seconds |
| Started | May 23 01:12:49 PM PDT 24 |
| Finished | May 23 01:12:55 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-77cfcb35-7e4d-4e9a-95f0-c91733d4b69a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1068548077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1068548077 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.1845942248 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 738112236 ps |
| CPU time | 11.21 seconds |
| Started | May 23 01:12:50 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-dff886c2-9b43-4c17-ab3e-847d2b3fc6a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1845942248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1845942248 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.171518949 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3327603931 ps |
| CPU time | 16.71 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:15 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-fff427fd-9dbf-44fc-b55d-ea9d1405d3ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171518949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.171518949 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.4032328247 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12501021538 ps |
| CPU time | 39.33 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:13:39 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-e8a6048b-a531-4ee4-88c5-508c9d24f010 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4032328247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4032328247 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.807426692 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 77272971 ps |
| CPU time | 8.08 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:07 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-a941b034-4292-411a-9dfa-a58819ff3e26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807426692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.807426692 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3127386608 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 29971771 ps |
| CPU time | 2.83 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-ecd274a9-24ff-42b1-a63e-99ba01fb1898 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127386608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3127386608 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.2666607823 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 14357294 ps |
| CPU time | 1.15 seconds |
| Started | May 23 01:12:52 PM PDT 24 |
| Finished | May 23 01:12:55 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-feb15f6d-14b8-4440-b816-ccee535a7907 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2666607823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2666607823 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1488978642 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3273720386 ps |
| CPU time | 9.22 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-f27ee76c-f9bf-43de-bbcd-83fb76d5752c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488978642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1488978642 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.742507843 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1778146219 ps |
| CPU time | 7.15 seconds |
| Started | May 23 01:13:05 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-55c4a4ad-1f51-46a0-aa2e-ee0c7a989b25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=742507843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.742507843 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1525361183 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 12470424 ps |
| CPU time | 1.14 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:42 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-b6ed5135-5adc-4825-949b-adc33613b892 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525361183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1525361183 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2731714765 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 76490267 ps |
| CPU time | 7.8 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-34cd25ac-c52b-4d2a-9763-defb7cc2f0ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2731714765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2731714765 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1242740723 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 9597450902 ps |
| CPU time | 96.33 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202324 kb |
| Host | smart-f85b4690-b136-4a0e-a9ed-f37e4d14b8c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242740723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1242740723 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2536218043 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1274153207 ps |
| CPU time | 116.96 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:14:54 PM PDT 24 |
| Peak memory | 206332 kb |
| Host | smart-9ac85e6c-c993-4b5b-9a71-50e7786c4f44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2536218043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.2536218043 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2653286220 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1929798049 ps |
| CPU time | 8.01 seconds |
| Started | May 23 01:12:57 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-5c4e1127-b02e-4bb3-9fcc-74f0f00c4115 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2653286220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2653286220 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3588701229 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 52937819 ps |
| CPU time | 4.83 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:07 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-23048de1-e66c-41fd-8e8a-31f7be657a81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3588701229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3588701229 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1810352513 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 91119779042 ps |
| CPU time | 331.74 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:18:32 PM PDT 24 |
| Peak memory | 203180 kb |
| Host | smart-63ed26ba-b30b-4a1c-b915-8b2724b2f728 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1810352513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.1810352513 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3763068602 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1039496333 ps |
| CPU time | 11.77 seconds |
| Started | May 23 01:13:05 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-5d6c893e-6157-46ca-810a-fe0d31cda0b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3763068602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3763068602 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.2351508880 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 308436873 ps |
| CPU time | 4.41 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:12:59 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-c06fd1e5-42be-497f-bc13-b4e0ac7ee143 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2351508880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2351508880 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.4215695627 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 257972495 ps |
| CPU time | 10 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-8dcc9449-6882-46dc-80e4-fecb38d5be9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215695627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4215695627 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3077257137 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 56956656473 ps |
| CPU time | 151.87 seconds |
| Started | May 23 01:12:51 PM PDT 24 |
| Finished | May 23 01:15:25 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-5bf298ac-81dd-48b7-aa38-52d3a2a7ba35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077257137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3077257137 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2695854733 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 30312841723 ps |
| CPU time | 147.82 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:15:29 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-e7227f75-95ee-45e8-b0be-ae4cf10c6b48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2695854733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2695854733 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3104911635 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 17964879 ps |
| CPU time | 2.33 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-dd2174ab-1754-4f67-b0d8-61446b663aa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104911635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3104911635 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1758562295 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 101664752 ps |
| CPU time | 1.8 seconds |
| Started | May 23 01:12:52 PM PDT 24 |
| Finished | May 23 01:12:56 PM PDT 24 |
| Peak memory | 201960 kb |
| Host | smart-4e4c5989-4cef-4d18-bec4-a80956d34bb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758562295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1758562295 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2034857359 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 160665309 ps |
| CPU time | 1.62 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-cb7c7c13-8af0-411a-9ee1-d3dfa6e30cff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2034857359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2034857359 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.234187620 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3677909051 ps |
| CPU time | 7.16 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-d4c053a7-b2d2-427e-9fab-04121c02d74f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=234187620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.234187620 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2232918890 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 816435589 ps |
| CPU time | 5.32 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-b6cc5966-2f6d-47b0-8a7b-94fab038ee9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2232918890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2232918890 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2920839345 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 13528776 ps |
| CPU time | 1.44 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:04 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-bf49e807-1f3d-4a24-af27-91d9923e39e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920839345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2920839345 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2184171665 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3207971610 ps |
| CPU time | 22 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-07d9489f-aa02-4114-83c2-243da9990bc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2184171665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2184171665 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1642523732 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 378076774 ps |
| CPU time | 27.81 seconds |
| Started | May 23 01:13:04 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-c23b8bd2-42da-4129-814e-c0ee1acbb8be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642523732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1642523732 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1212200580 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 11750082458 ps |
| CPU time | 111.76 seconds |
| Started | May 23 01:12:57 PM PDT 24 |
| Finished | May 23 01:14:51 PM PDT 24 |
| Peak memory | 204896 kb |
| Host | smart-b7b52fd5-d332-4e26-bb10-e56f45a2c32e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1212200580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1212200580 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.255756350 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1008431063 ps |
| CPU time | 6.01 seconds |
| Started | May 23 01:12:50 PM PDT 24 |
| Finished | May 23 01:12:58 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-077345e8-4d74-4d3c-ae5f-8efd70340049 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=255756350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.255756350 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2751621236 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 889816734 ps |
| CPU time | 12.99 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-29b4a679-12bd-4ef8-8de4-749a123b6931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751621236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2751621236 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1238222237 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 29488466121 ps |
| CPU time | 137.85 seconds |
| Started | May 23 01:12:49 PM PDT 24 |
| Finished | May 23 01:15:08 PM PDT 24 |
| Peak memory | 203248 kb |
| Host | smart-b7497670-d9e1-4cae-9b84-2cf668cbf266 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1238222237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1238222237 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.738593160 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 449025939 ps |
| CPU time | 7.69 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-aaaa7ab7-4152-4e73-836d-ecf6a495ef00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=738593160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.738593160 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2125304408 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 84174218 ps |
| CPU time | 4.69 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:02 PM PDT 24 |
| Peak memory | 201708 kb |
| Host | smart-bf4dae19-a9bc-4681-bdfe-cb10fc5fb8cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2125304408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2125304408 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.2594731633 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 536613864 ps |
| CPU time | 3.38 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-c2009283-5a9b-4aec-bb2c-36e84768cf24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2594731633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2594731633 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1024274139 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 50376635265 ps |
| CPU time | 149.14 seconds |
| Started | May 23 01:12:57 PM PDT 24 |
| Finished | May 23 01:15:29 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-31277c54-5ac6-4cda-ba2a-a26e80c150a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024274139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1024274139 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3944724454 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 27861903088 ps |
| CPU time | 57.78 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:55 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-56db5c4d-f316-4200-88a7-b91d47db24c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3944724454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3944724454 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1535675373 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 33426348 ps |
| CPU time | 3.9 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 202028 kb |
| Host | smart-cdc432f9-fe89-4f94-8030-7e923f0a365f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535675373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1535675373 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.3382052300 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1110355977 ps |
| CPU time | 13.87 seconds |
| Started | May 23 01:12:50 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-94513123-901c-43a8-bece-f83e5fabdd43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3382052300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3382052300 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.647428458 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 148130363 ps |
| CPU time | 1.53 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:12:56 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-8e7337c3-f311-40dc-b4b2-7b7d9ed5e853 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647428458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.647428458 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2370673468 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3399075185 ps |
| CPU time | 10.93 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-82c24f76-3681-4b18-8e03-657a7904d27f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370673468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2370673468 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.989693120 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2111343662 ps |
| CPU time | 13.41 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:12 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-d02e4e82-504f-4426-b911-f7059c21c2c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=989693120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.989693120 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1789776953 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9606922 ps |
| CPU time | 1.23 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-5f0593d7-19e4-470e-ac42-2851611db734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789776953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1789776953 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1405206682 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 796524253 ps |
| CPU time | 26.75 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:22 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-d9d8900f-0d26-4e25-b449-e96435028255 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1405206682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1405206682 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1102495134 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1357412557 ps |
| CPU time | 100.16 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 204664 kb |
| Host | smart-9420584b-0c2b-4185-9ef7-91e1188ef4eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102495134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1102495134 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.669323847 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 696204717 ps |
| CPU time | 80.99 seconds |
| Started | May 23 01:12:51 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 203672 kb |
| Host | smart-c24a5f05-3ab2-4d0b-9d5d-b9a7d99a3980 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=669323847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.669323847 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1018059052 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 65701836 ps |
| CPU time | 8.23 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:07 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-8a6f68f1-4a9b-4b19-ab84-45e744727057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1018059052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1018059052 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.364705389 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2321461565 ps |
| CPU time | 8.62 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-9054877a-eaa7-467f-85a3-410f6d69b178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364705389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.364705389 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3493217424 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 113235472903 ps |
| CPU time | 190 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:16:12 PM PDT 24 |
| Peak memory | 203320 kb |
| Host | smart-5fa61130-6b63-4fd2-8354-870d507c484d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3493217424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3493217424 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1069439524 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 55785920 ps |
| CPU time | 2.67 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:12:58 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-6467e0d3-163e-4737-831f-9cd42b7e20a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1069439524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1069439524 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1428289319 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 203001426 ps |
| CPU time | 4.78 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-5a851fc3-b150-427b-9782-ac8e7faf8939 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1428289319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1428289319 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.278713938 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 633461253 ps |
| CPU time | 11.05 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:09 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-243d8e69-dcdb-4657-899a-6ee9e790c851 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=278713938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.278713938 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.793873092 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 31932213655 ps |
| CPU time | 78.93 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:14:19 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-24b7f280-f036-40c3-84cf-e56b68f9d4f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=793873092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.793873092 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3142688074 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 5969837672 ps |
| CPU time | 40.31 seconds |
| Started | May 23 01:12:54 PM PDT 24 |
| Finished | May 23 01:13:36 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-2ab1cb6e-62a8-44c3-b28d-6be0f1b7bd1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3142688074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3142688074 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.195581336 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 68037794 ps |
| CPU time | 9.18 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-31cdab72-10d9-4387-9f03-4f082693a970 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195581336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.195581336 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1097384582 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 216021102 ps |
| CPU time | 4.94 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:03 PM PDT 24 |
| Peak memory | 201688 kb |
| Host | smart-9aca23a9-4d40-4a69-b7af-a9a03deea5c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097384582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1097384582 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.873097968 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 8237561 ps |
| CPU time | 1.23 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:13:02 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-a63cc454-8ff9-4ca9-aa4c-2e2910ff9fd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=873097968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.873097968 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4244980985 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2852235996 ps |
| CPU time | 12 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:13 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-f4562582-218a-497a-8f14-af127727d560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244980985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4244980985 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2820510741 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1051575904 ps |
| CPU time | 6.58 seconds |
| Started | May 23 01:12:57 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-d24b5409-3715-4b5b-b1ce-b74eb7a91aa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2820510741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2820510741 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3847489936 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 23021604 ps |
| CPU time | 1.15 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:12:59 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-335c11a8-f6c1-428a-acea-314c44fc5209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847489936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3847489936 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2342369663 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5038741782 ps |
| CPU time | 32.99 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:30 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-05275530-be9b-40b7-974d-9169a40e89c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2342369663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2342369663 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.833490486 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 898145527 ps |
| CPU time | 42.98 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:40 PM PDT 24 |
| Peak memory | 201964 kb |
| Host | smart-ebbb7cf7-3bb4-41e3-abb8-46cbb00747db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833490486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.833490486 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3919533662 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 831574109 ps |
| CPU time | 107.58 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:14:43 PM PDT 24 |
| Peak memory | 206352 kb |
| Host | smart-f5768b0d-99e3-460e-8540-dcc5a402c0c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3919533662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3919533662 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2590891465 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 9915390798 ps |
| CPU time | 81.61 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:14:20 PM PDT 24 |
| Peak memory | 203720 kb |
| Host | smart-7c0b612e-6d0c-41e1-8a73-365e48ca3347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590891465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2590891465 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2266672796 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 376088654 ps |
| CPU time | 2.67 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-5abc742a-8f63-40e5-95d3-7e76520869fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2266672796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2266672796 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1824768279 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 978838622 ps |
| CPU time | 21 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:18 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-f5f46f31-04fe-498f-a7a9-4cf37b06e46d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1824768279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1824768279 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2940396195 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4636092898 ps |
| CPU time | 34.56 seconds |
| Started | May 23 01:12:52 PM PDT 24 |
| Finished | May 23 01:13:28 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-ce14e1eb-3918-43b7-a8e4-a13ddc14b335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2940396195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2940396195 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.851145168 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 9689612 ps |
| CPU time | 1.45 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:12:59 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-962c8688-c0ca-419e-b9d0-29121c038bc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851145168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.851145168 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.308241061 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 545712797 ps |
| CPU time | 5 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-949607fb-3ac5-4a8c-b839-b6115178a47c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308241061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.308241061 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.3988012529 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 96726645 ps |
| CPU time | 7.05 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-3f20ca0c-10f2-4261-bdb1-732c93f5a678 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3988012529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3988012529 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.484994003 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 7604562414 ps |
| CPU time | 39.31 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-e3df3e39-c066-4978-8022-cd00e5e05b9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=484994003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.484994003 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1336965833 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 92422757 ps |
| CPU time | 4.92 seconds |
| Started | May 23 01:12:53 PM PDT 24 |
| Finished | May 23 01:13:00 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-7ce24313-6013-47df-9375-3ab87fe9a679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336965833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1336965833 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.2319836874 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 119595479 ps |
| CPU time | 5.46 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:04 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-cfd86d3f-a67f-4a92-a9d6-5583e8a10b0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2319836874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2319836874 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.2904094600 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 9791422 ps |
| CPU time | 1.31 seconds |
| Started | May 23 01:12:49 PM PDT 24 |
| Finished | May 23 01:12:52 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-ab6704d9-95ae-420d-b172-170c0b27c89d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2904094600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2904094600 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3390090627 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2648950901 ps |
| CPU time | 6.68 seconds |
| Started | May 23 01:12:52 PM PDT 24 |
| Finished | May 23 01:13:01 PM PDT 24 |
| Peak memory | 201988 kb |
| Host | smart-687d80b3-9750-414c-998b-722ebc85c781 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390090627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3390090627 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.4101400638 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2097296946 ps |
| CPU time | 7.89 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-9f3fed12-9ac3-4b34-916b-dd7e3c212d91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4101400638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.4101400638 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2959952006 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 11667146 ps |
| CPU time | 1.29 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:04 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-66c75b0d-c507-4970-bdc8-4db83a8cf963 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959952006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2959952006 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1842032107 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 6266814033 ps |
| CPU time | 62.06 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:14:05 PM PDT 24 |
| Peak memory | 203180 kb |
| Host | smart-d909b6c4-8056-4275-8edd-19dd6a31645f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1842032107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1842032107 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4169424278 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 342271594 ps |
| CPU time | 22.53 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:26 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-136e64f7-afe2-40a7-9b00-81d668fb535c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4169424278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4169424278 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2476724133 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7305420657 ps |
| CPU time | 143.62 seconds |
| Started | May 23 01:12:55 PM PDT 24 |
| Finished | May 23 01:15:21 PM PDT 24 |
| Peak memory | 206064 kb |
| Host | smart-1cbe41b1-6e61-4b05-99b4-75cfd9325c09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2476724133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2476724133 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.547419234 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 45755689 ps |
| CPU time | 2.42 seconds |
| Started | May 23 01:13:00 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-7279f0c3-cb21-4af9-aa4b-52b413f58d6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=547419234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.547419234 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2125338678 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 113900433 ps |
| CPU time | 1.5 seconds |
| Started | May 23 01:12:58 PM PDT 24 |
| Finished | May 23 01:13:02 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-58bff783-6e42-46ae-814d-4c4c5921ad1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2125338678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2125338678 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1156243843 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 615783954 ps |
| CPU time | 9.2 seconds |
| Started | May 23 01:12:16 PM PDT 24 |
| Finished | May 23 01:12:26 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-57bd7235-7c17-451d-bb3e-ef69564c1e60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1156243843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1156243843 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2075673058 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2607127262 ps |
| CPU time | 20.2 seconds |
| Started | May 23 01:12:20 PM PDT 24 |
| Finished | May 23 01:12:41 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-00b63008-8bdb-484e-aa35-4e38cb7776b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2075673058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2075673058 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.972458335 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 552371694 ps |
| CPU time | 8.16 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:19 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-cd606d84-38c6-4a1c-96b9-51244f436f38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=972458335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.972458335 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.3160354625 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 93886694 ps |
| CPU time | 2.05 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:12:17 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-6e4777d2-f8df-4c01-9235-b0fa664311ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3160354625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3160354625 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.2455283974 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 76380728 ps |
| CPU time | 7.82 seconds |
| Started | May 23 01:12:15 PM PDT 24 |
| Finished | May 23 01:12:24 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-e11c8ee9-6a31-48f2-b7cf-5b9a9b22a614 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455283974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2455283974 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2093706289 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 50733318108 ps |
| CPU time | 133.07 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-8757607d-a2df-4c80-8478-b620f564c5c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093706289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2093706289 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.4217156385 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 51999370894 ps |
| CPU time | 187.69 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:15:22 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-b10bd3fb-38a5-45ff-ba4c-a6821e3f1daa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4217156385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4217156385 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.511651009 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 126261295 ps |
| CPU time | 3.01 seconds |
| Started | May 23 01:12:09 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-09a2b3f3-0c22-4d5c-9b7c-4c015a3c7a92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511651009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.511651009 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.498713588 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 69742132 ps |
| CPU time | 6.12 seconds |
| Started | May 23 01:12:18 PM PDT 24 |
| Finished | May 23 01:12:25 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-ad75386c-19db-4d0c-84a4-c65477a5bd18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=498713588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.498713588 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.173063543 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 9030219 ps |
| CPU time | 1.09 seconds |
| Started | May 23 01:12:13 PM PDT 24 |
| Finished | May 23 01:12:16 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-dd4783e5-3f44-4614-88ad-8af683288245 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173063543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.173063543 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.67144809 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 9672544313 ps |
| CPU time | 9.29 seconds |
| Started | May 23 01:12:07 PM PDT 24 |
| Finished | May 23 01:12:18 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-660adf90-d943-4431-af98-0307f4719d5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=67144809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.67144809 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3782176629 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1926810678 ps |
| CPU time | 7.33 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:18 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-5047826a-3aa2-4c32-9ade-cf952307448f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3782176629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3782176629 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2552231064 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 11810503 ps |
| CPU time | 1.13 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:12:24 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-06cd0c13-1b8c-4de7-a745-34d6d1e7ec26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552231064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2552231064 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2472143439 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 11854345638 ps |
| CPU time | 81.92 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:13:33 PM PDT 24 |
| Peak memory | 204272 kb |
| Host | smart-b9798ca0-9136-4341-9e30-5dee124e8308 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2472143439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2472143439 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.4202382995 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 6803959997 ps |
| CPU time | 67.43 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:13:17 PM PDT 24 |
| Peak memory | 203136 kb |
| Host | smart-f0454726-c43a-49df-97c1-4d5c93a1d9ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4202382995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4202382995 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2735818536 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 279220028 ps |
| CPU time | 26.01 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:37 PM PDT 24 |
| Peak memory | 204164 kb |
| Host | smart-e17f9228-240c-4785-b39a-b8b2a120f003 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2735818536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.2735818536 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3556831409 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5209520682 ps |
| CPU time | 126.14 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 207156 kb |
| Host | smart-11431363-c89f-4654-87b4-bed74623d9c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3556831409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3556831409 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2662777132 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 57453171 ps |
| CPU time | 6.77 seconds |
| Started | May 23 01:12:08 PM PDT 24 |
| Finished | May 23 01:12:16 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-0883f303-8831-4561-bb11-9598ad098440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662777132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2662777132 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2442138358 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 136484696 ps |
| CPU time | 8.51 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:13:17 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-035ae6d7-9f03-43d5-a386-27ad817b207b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2442138358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2442138358 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1341158137 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 17164311199 ps |
| CPU time | 90.16 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-c9f3137a-da99-4c47-9a75-170a50de04ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1341158137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.1341158137 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.152467910 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 735109159 ps |
| CPU time | 8.19 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:13:27 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-18f53380-1e9f-4467-92c0-e05e32df5ce9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=152467910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.152467910 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3032676581 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 956942086 ps |
| CPU time | 15.48 seconds |
| Started | May 23 01:13:11 PM PDT 24 |
| Finished | May 23 01:13:28 PM PDT 24 |
| Peak memory | 201744 kb |
| Host | smart-b5035540-c2aa-4e1f-93d3-0b2c9027bef0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3032676581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3032676581 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3169849745 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 289205359 ps |
| CPU time | 5.6 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:04 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-f20c7702-e783-4e4e-8d30-258ca9083b39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3169849745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3169849745 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2031509592 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 22716088961 ps |
| CPU time | 57.32 seconds |
| Started | May 23 01:13:04 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-8adb1350-2e95-4e8a-8f87-d05d74064262 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031509592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2031509592 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3539524930 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 46506388646 ps |
| CPU time | 203.8 seconds |
| Started | May 23 01:13:07 PM PDT 24 |
| Finished | May 23 01:16:33 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-429c56ef-56fb-4da8-9659-bbb09ccc9c6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3539524930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3539524930 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1517381373 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 78213131 ps |
| CPU time | 3.52 seconds |
| Started | May 23 01:12:56 PM PDT 24 |
| Finished | May 23 01:13:02 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-e8547e8f-d82c-44c5-9c7f-4cab73b33289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517381373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1517381373 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.116115131 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 15092387 ps |
| CPU time | 1.32 seconds |
| Started | May 23 01:13:02 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-497711a2-0be4-4316-bf40-f57d4626f298 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=116115131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.116115131 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.987930875 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 76468388 ps |
| CPU time | 1.86 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-9957d37e-91d4-4123-8cbe-dc3a1a808360 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987930875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.987930875 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.412884512 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 13536746981 ps |
| CPU time | 9.42 seconds |
| Started | May 23 01:12:54 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-9b27bd2e-aa5f-4711-98b7-5ce5f48e3885 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=412884512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.412884512 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2394161803 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3036101840 ps |
| CPU time | 8.9 seconds |
| Started | May 23 01:12:57 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-da6aef8b-90dc-47a2-9783-f1ef90171574 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2394161803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2394161803 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1117008989 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 10857424 ps |
| CPU time | 1.15 seconds |
| Started | May 23 01:12:59 PM PDT 24 |
| Finished | May 23 01:13:02 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-7b13f51d-62e4-401b-8a95-f35d9ecadade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117008989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1117008989 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2429411526 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 160237676 ps |
| CPU time | 20.44 seconds |
| Started | May 23 01:13:04 PM PDT 24 |
| Finished | May 23 01:13:27 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-6f307606-65e5-4a46-8257-2883e52b7f52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429411526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2429411526 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3483381417 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 8372693802 ps |
| CPU time | 45.42 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:50 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-b30ea3c2-9945-416d-9f92-829c2f30ef86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3483381417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3483381417 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1399097998 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 9559766349 ps |
| CPU time | 164.46 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:15:53 PM PDT 24 |
| Peak memory | 206980 kb |
| Host | smart-07690c54-3e8d-4713-9f74-6dff638210fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399097998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1399097998 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2203637733 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 520955240 ps |
| CPU time | 58.58 seconds |
| Started | May 23 01:13:02 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 204176 kb |
| Host | smart-a0499579-8bca-4cc5-ab28-19d7c8c8b0a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203637733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2203637733 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1414135399 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 49382264 ps |
| CPU time | 4.83 seconds |
| Started | May 23 01:13:05 PM PDT 24 |
| Finished | May 23 01:13:13 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-9d75b5f2-a493-40c8-8e5f-79363bbbe88a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1414135399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1414135399 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1032176126 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 5595985514 ps |
| CPU time | 17.11 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-8aa12e83-ab31-446e-82a6-bd150345d017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1032176126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1032176126 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3168221389 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 34384579973 ps |
| CPU time | 161.16 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:15:59 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-9521b2b7-1f9e-4a50-b48c-a60bcbbacdb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3168221389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3168221389 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.478788785 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 67555356 ps |
| CPU time | 1.42 seconds |
| Started | May 23 01:13:07 PM PDT 24 |
| Finished | May 23 01:13:10 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-fa3e6456-ae50-4c2d-b138-79c7ba42249d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=478788785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.478788785 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1373569194 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 268122038 ps |
| CPU time | 4.54 seconds |
| Started | May 23 01:13:09 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-133c243b-bd51-4a22-a2d2-9823faf9c207 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1373569194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1373569194 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.3366068746 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 77441059 ps |
| CPU time | 5.83 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:22 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-74e453e8-ebe9-4f8a-b14f-81d8c31c517b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3366068746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3366068746 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4116671749 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 9667739564 ps |
| CPU time | 34.05 seconds |
| Started | May 23 01:13:02 PM PDT 24 |
| Finished | May 23 01:13:38 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-4178a546-b60a-44c2-b116-5d204649aabb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116671749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4116671749 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2737925621 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 12872408969 ps |
| CPU time | 75.46 seconds |
| Started | May 23 01:13:08 PM PDT 24 |
| Finished | May 23 01:14:25 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-fdbff296-0200-421d-9ef3-43811695d388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2737925621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2737925621 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3909206338 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 87332392 ps |
| CPU time | 1.73 seconds |
| Started | May 23 01:13:09 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-bc4ecdad-3449-41b2-b01e-5e5c02cddab1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909206338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3909206338 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2671164866 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 156459670 ps |
| CPU time | 1.99 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-f3c3024a-beef-4653-be75-a07705d573f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2671164866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2671164866 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.80699219 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 9896832 ps |
| CPU time | 1.13 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:13:09 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-e8a2bd64-0118-479c-8c83-1a9d29326f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=80699219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.80699219 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2606840882 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3607068059 ps |
| CPU time | 8.97 seconds |
| Started | May 23 01:13:07 PM PDT 24 |
| Finished | May 23 01:13:18 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-0aee9a97-de2c-4836-b347-444f25fbe208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606840882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2606840882 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2344277505 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 739345823 ps |
| CPU time | 5.13 seconds |
| Started | May 23 01:13:08 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-1078b5e5-ec92-4be7-a440-91532715c53d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2344277505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2344277505 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.4179241822 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 10237073 ps |
| CPU time | 1.12 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:13:19 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-dcb19c1e-7913-41b5-be4e-f95936ddd240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179241822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.4179241822 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1312646478 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 320130076 ps |
| CPU time | 19.41 seconds |
| Started | May 23 01:13:05 PM PDT 24 |
| Finished | May 23 01:13:26 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-37d12a8b-8226-4402-8141-41e81e183a13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1312646478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1312646478 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3154643388 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 270182405 ps |
| CPU time | 30 seconds |
| Started | May 23 01:13:08 PM PDT 24 |
| Finished | May 23 01:13:39 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-7472e02d-81a4-4eeb-ab4a-a9126bacfa12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154643388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3154643388 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.55022592 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 12208002774 ps |
| CPU time | 186.58 seconds |
| Started | May 23 01:13:13 PM PDT 24 |
| Finished | May 23 01:16:22 PM PDT 24 |
| Peak memory | 207656 kb |
| Host | smart-0dcd3966-1d2c-42d6-8db8-7814a3d00491 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=55022592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rese t_error.55022592 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.841053120 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 326781110 ps |
| CPU time | 4.2 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:21 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-22cf6bba-62ea-4247-a4d2-41558768694c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841053120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.841053120 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1288038394 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 631681567 ps |
| CPU time | 10.55 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-e7a4c8de-e67b-4b2e-ae60-9dcec4685de5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1288038394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1288038394 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3087593310 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 65319005228 ps |
| CPU time | 225.35 seconds |
| Started | May 23 01:13:09 PM PDT 24 |
| Finished | May 23 01:16:56 PM PDT 24 |
| Peak memory | 203172 kb |
| Host | smart-40779163-bd3b-4776-abb2-474331bfa5da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3087593310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.3087593310 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1734061007 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 619908105 ps |
| CPU time | 7.31 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:24 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-6be0581c-3929-4d65-88b5-a86e9d4921b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1734061007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1734061007 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.1558290035 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 604439053 ps |
| CPU time | 11.87 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:17 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-b313cba7-3e75-4523-b3a8-3f6c72084a5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1558290035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1558290035 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.3629207016 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 22782114 ps |
| CPU time | 1.15 seconds |
| Started | May 23 01:13:08 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-59787036-b2d7-49d1-9cd3-161cee4f554e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3629207016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3629207016 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1872958136 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 57575117000 ps |
| CPU time | 61.55 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:14:05 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-2334c1a4-10f5-44da-b4fd-d50af5552bf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872958136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1872958136 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1455085353 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 46890775351 ps |
| CPU time | 96.73 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:14:53 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-c0c8cf17-a2dd-4110-ad90-e89fca214ac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1455085353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1455085353 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.865945347 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 140608928 ps |
| CPU time | 2.47 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-c3afdca2-2f7e-46d2-816c-3d18e53825d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865945347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.865945347 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2319556189 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 25769969 ps |
| CPU time | 1.25 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-a2646393-6b60-421f-b4f2-aca4be1d769d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2319556189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2319556189 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.1017926505 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 29441519 ps |
| CPU time | 1.09 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-6518a97b-1b6f-4b97-b5bb-58ff20e35dee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017926505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1017926505 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.861259074 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 11353341969 ps |
| CPU time | 9.24 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:13 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-1148a01c-8878-4045-ab35-eecc64276489 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=861259074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.861259074 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.384616949 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3078241529 ps |
| CPU time | 13.41 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:13:22 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-2d1d03f2-2432-466b-a96a-5e3edb5a204f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=384616949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.384616949 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2177938966 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13123149 ps |
| CPU time | 1.32 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:13:09 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-55b44a52-8df4-41da-b9ce-1f3e358c0cc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177938966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2177938966 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.4125552653 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 55473185 ps |
| CPU time | 5.48 seconds |
| Started | May 23 01:13:05 PM PDT 24 |
| Finished | May 23 01:13:13 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-d0761452-591a-4c07-a83e-4f55775f040b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4125552653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4125552653 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.805768352 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 328758578 ps |
| CPU time | 55.53 seconds |
| Started | May 23 01:13:12 PM PDT 24 |
| Finished | May 23 01:14:09 PM PDT 24 |
| Peak memory | 204504 kb |
| Host | smart-9087f088-5721-421c-ae78-86bd07fde5ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=805768352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.805768352 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3648190511 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 319054440 ps |
| CPU time | 32.45 seconds |
| Started | May 23 01:13:11 PM PDT 24 |
| Finished | May 23 01:13:45 PM PDT 24 |
| Peak memory | 203188 kb |
| Host | smart-b869e4a2-8dee-4159-b533-ad711e66271a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3648190511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3648190511 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3780547242 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 899503973 ps |
| CPU time | 3.93 seconds |
| Started | May 23 01:13:09 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-c90ee098-cc82-478d-82cf-d6ed03bc75fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3780547242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3780547242 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1842786304 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3318707127 ps |
| CPU time | 28.92 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:33 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-3d4b2920-3bd4-4d10-8448-103a7593f687 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1842786304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1842786304 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3586993905 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 100162670847 ps |
| CPU time | 346.13 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:18:50 PM PDT 24 |
| Peak memory | 203752 kb |
| Host | smart-cf13d3f5-26a5-4804-af70-6dc578e68b84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3586993905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3586993905 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1104493554 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 298204792 ps |
| CPU time | 6.98 seconds |
| Started | May 23 01:13:11 PM PDT 24 |
| Finished | May 23 01:13:19 PM PDT 24 |
| Peak memory | 201716 kb |
| Host | smart-ac5e41c8-1fac-4f2e-8175-6a10a7d06770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1104493554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1104493554 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.127364505 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 294937999 ps |
| CPU time | 4.69 seconds |
| Started | May 23 01:13:04 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-3c4e3c60-2be2-47ee-a9e5-71eb5e44cb44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=127364505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.127364505 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3846657277 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3025792803 ps |
| CPU time | 9.74 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:15 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-316d1f71-14e7-4b03-b94d-f1a077afd56a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3846657277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3846657277 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.275460117 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 22625809620 ps |
| CPU time | 70.18 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-ed053f3c-396f-47b2-84e8-ebd342ca8dc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=275460117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.275460117 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.61883948 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 15373151182 ps |
| CPU time | 52.46 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-f6a3f23c-5fbc-497b-9869-8831726b0510 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=61883948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.61883948 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2954979518 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 121022487 ps |
| CPU time | 7.45 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-81851db0-bff2-4b9b-9922-0fecc35ed29b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954979518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2954979518 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2652210150 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 127449163 ps |
| CPU time | 5.72 seconds |
| Started | May 23 01:13:09 PM PDT 24 |
| Finished | May 23 01:13:16 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-90cf2263-85b6-454e-9b25-32bf4602324c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2652210150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2652210150 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.1625438290 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 15026633 ps |
| CPU time | 1.19 seconds |
| Started | May 23 01:13:05 PM PDT 24 |
| Finished | May 23 01:13:08 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-404c94e4-6065-439e-acee-287980625a58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1625438290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1625438290 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.590803020 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 7149717177 ps |
| CPU time | 7.81 seconds |
| Started | May 23 01:13:01 PM PDT 24 |
| Finished | May 23 01:13:11 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-76fd0cfa-0b74-4dd0-aa51-db006caab93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=590803020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.590803020 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2019660396 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 692761737 ps |
| CPU time | 6.15 seconds |
| Started | May 23 01:13:02 PM PDT 24 |
| Finished | May 23 01:13:10 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-caa9abf7-a013-45c4-b974-87e7eb2ea0b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2019660396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2019660396 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1566752326 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 11883653 ps |
| CPU time | 1.1 seconds |
| Started | May 23 01:13:03 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-38828c1e-c9ee-40a2-980c-b3517be75a5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566752326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1566752326 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3141116033 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 540533556 ps |
| CPU time | 19.94 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:13:28 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-494f5965-cd12-4ecf-96c5-b1849caaa6bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3141116033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3141116033 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1826768381 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2014824197 ps |
| CPU time | 34.35 seconds |
| Started | May 23 01:13:12 PM PDT 24 |
| Finished | May 23 01:13:48 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-cc88c1b7-a010-4cea-b71e-c77f9b82fb5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1826768381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1826768381 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2955703140 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2443400592 ps |
| CPU time | 220.51 seconds |
| Started | May 23 01:13:09 PM PDT 24 |
| Finished | May 23 01:16:52 PM PDT 24 |
| Peak memory | 208884 kb |
| Host | smart-8cb752ca-a1b5-44bf-ac1a-fbbda852a226 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2955703140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.2955703140 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.249236877 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 31831565 ps |
| CPU time | 5.23 seconds |
| Started | May 23 01:13:06 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-beefe21b-c907-4f31-97fe-9d1c660ef230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=249236877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.249236877 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3915015748 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1106004367 ps |
| CPU time | 9.05 seconds |
| Started | May 23 01:13:02 PM PDT 24 |
| Finished | May 23 01:13:13 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-b45fa711-e78d-4a9a-8462-7e7c5513d935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3915015748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3915015748 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2915187918 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 65383916943 ps |
| CPU time | 142.86 seconds |
| Started | May 23 01:13:16 PM PDT 24 |
| Finished | May 23 01:15:42 PM PDT 24 |
| Peak memory | 203148 kb |
| Host | smart-703e7187-6da0-4f8c-8f65-8341035b0320 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2915187918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.2915187918 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.47131167 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1319208093 ps |
| CPU time | 6.64 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-af2ffe3b-f8f7-4e78-8b9a-32d93b555abb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=47131167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.47131167 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2166908005 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 531254997 ps |
| CPU time | 6.33 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:31 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-1ee3081e-9841-4f89-8e05-e33814a42e93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2166908005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2166908005 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1863802778 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 322929494 ps |
| CPU time | 8.17 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:33 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-7c18dcf8-5e9a-4af9-b5e2-1be908ce806e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1863802778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1863802778 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3736873079 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 25324400957 ps |
| CPU time | 94.11 seconds |
| Started | May 23 01:13:20 PM PDT 24 |
| Finished | May 23 01:14:58 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-c0a842ee-eba5-4395-96a0-8ce360d10429 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736873079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3736873079 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2971871462 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 14458233265 ps |
| CPU time | 86.71 seconds |
| Started | May 23 01:13:20 PM PDT 24 |
| Finished | May 23 01:14:51 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-c6fda89b-69c5-4de0-b31f-345640cf0ad0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2971871462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2971871462 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3215758341 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 18678310 ps |
| CPU time | 2.62 seconds |
| Started | May 23 01:13:22 PM PDT 24 |
| Finished | May 23 01:13:28 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-0c371f45-b001-4423-a20b-d1da243ea376 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215758341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3215758341 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.732370582 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 826822012 ps |
| CPU time | 3.65 seconds |
| Started | May 23 01:13:16 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-28328d1c-0bdd-41e6-b381-37dfd3b3692f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=732370582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.732370582 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.3648451055 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 84445076 ps |
| CPU time | 1.58 seconds |
| Started | May 23 01:13:12 PM PDT 24 |
| Finished | May 23 01:13:14 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-3de506fe-4ee9-4b33-b524-25025d7944fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3648451055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3648451055 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.260807762 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2922053012 ps |
| CPU time | 7.34 seconds |
| Started | May 23 01:13:19 PM PDT 24 |
| Finished | May 23 01:13:30 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-58a66464-5461-4c34-be52-9ad01f7f8327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=260807762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.260807762 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.4051909593 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 901385476 ps |
| CPU time | 7.89 seconds |
| Started | May 23 01:13:13 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-784c11f8-945f-4cf2-b4c8-0b73b2caa8cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4051909593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.4051909593 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1322335770 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 14678824 ps |
| CPU time | 1.21 seconds |
| Started | May 23 01:13:17 PM PDT 24 |
| Finished | May 23 01:13:22 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-75b7c565-ae73-4401-a028-47bd89d4c690 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322335770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1322335770 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2809710451 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3187044341 ps |
| CPU time | 43.33 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 203172 kb |
| Host | smart-808ac7bd-0f64-4d76-b656-c9f56d1c6415 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809710451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2809710451 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.625333853 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 740352475 ps |
| CPU time | 17.77 seconds |
| Started | May 23 01:13:12 PM PDT 24 |
| Finished | May 23 01:13:31 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-fc208383-56e7-48e5-9246-a418c72247b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=625333853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.625333853 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.815331469 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 7906326095 ps |
| CPU time | 132.83 seconds |
| Started | May 23 01:13:16 PM PDT 24 |
| Finished | May 23 01:15:32 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-828b48df-6709-4885-8397-0f52eb7da2ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=815331469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.815331469 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.531359738 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 976936447 ps |
| CPU time | 140.34 seconds |
| Started | May 23 01:13:13 PM PDT 24 |
| Finished | May 23 01:15:36 PM PDT 24 |
| Peak memory | 206760 kb |
| Host | smart-9c6f719f-1922-4b6f-9ed5-598a64cf71b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=531359738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.531359738 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2063806392 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 33273010 ps |
| CPU time | 2.14 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:31 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-d09123c5-153a-4f58-9ca7-ee3bc572b346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2063806392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2063806392 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3638293666 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 377407681 ps |
| CPU time | 9.77 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:26 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-0916923b-c6bb-4724-881e-abf672b4faaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3638293666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3638293666 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1493449044 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 69420313143 ps |
| CPU time | 329.73 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:18:48 PM PDT 24 |
| Peak memory | 203236 kb |
| Host | smart-56684fff-67f4-4d2b-9292-580be17f1577 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1493449044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.1493449044 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3141124908 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 32511392 ps |
| CPU time | 2.14 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:31 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-557399aa-2d2b-4b07-b60c-14b30c99e7fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3141124908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3141124908 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.1083365397 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 28212916 ps |
| CPU time | 1.9 seconds |
| Started | May 23 01:13:13 PM PDT 24 |
| Finished | May 23 01:13:17 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-667a7d68-9e00-4eb8-9290-254027bf607b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1083365397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1083365397 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.969002933 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1642284688 ps |
| CPU time | 13.48 seconds |
| Started | May 23 01:13:22 PM PDT 24 |
| Finished | May 23 01:13:39 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-c0130d67-2c87-4cc2-aebf-d7f009d0780e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=969002933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.969002933 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1647039483 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1768329775 ps |
| CPU time | 7.16 seconds |
| Started | May 23 01:13:13 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-b281a47b-77aa-416a-8b80-86e5bc30bb27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647039483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1647039483 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.405006493 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 180196625400 ps |
| CPU time | 154.1 seconds |
| Started | May 23 01:13:13 PM PDT 24 |
| Finished | May 23 01:15:48 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-924f3997-3d76-4eff-816a-a9f7ed3ee9a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=405006493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.405006493 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2508780609 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 117005381 ps |
| CPU time | 8.19 seconds |
| Started | May 23 01:13:23 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-dc0d1d96-0f6d-43f9-8e41-04a26808a9b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508780609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2508780609 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.1318864984 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 19081073 ps |
| CPU time | 1.98 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-fcf03cfc-ccd4-4399-a104-fc295aa7de5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1318864984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1318864984 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.2612998126 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 12435482 ps |
| CPU time | 1.07 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:26 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-4b6fa5ec-dde2-4048-a130-5eed264c4c20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2612998126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2612998126 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1011519114 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2740225131 ps |
| CPU time | 7.09 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:24 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-c5053e52-eaaa-4f25-8b77-1fdca0ad9b83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011519114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1011519114 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2197639349 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 641976845 ps |
| CPU time | 4.86 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:21 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-9f0252f3-7e9d-426b-baf6-ae9cd104d6db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2197639349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2197639349 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1431608732 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 8416932 ps |
| CPU time | 1.17 seconds |
| Started | May 23 01:13:17 PM PDT 24 |
| Finished | May 23 01:13:21 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-fa0982ce-1933-4c93-a7ec-2bd6ff9587c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431608732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1431608732 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.41177539 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 338700158 ps |
| CPU time | 26.89 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:52 PM PDT 24 |
| Peak memory | 203324 kb |
| Host | smart-6f834fa2-2b1a-4b45-acd9-f4664dcaba31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41177539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.41177539 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.793215995 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1255320284 ps |
| CPU time | 10.72 seconds |
| Started | May 23 01:13:20 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-48fd5856-7bf6-4b9f-b2d7-3ed94269e5d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=793215995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.793215995 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1236967763 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 839124564 ps |
| CPU time | 151.31 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:15:56 PM PDT 24 |
| Peak memory | 205368 kb |
| Host | smart-c3bc199c-3011-4cbf-b254-830a5dcf7b30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1236967763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1236967763 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1507145393 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 167872673 ps |
| CPU time | 17.85 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 203460 kb |
| Host | smart-f298304d-da49-4de3-9d82-d8e949315ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1507145393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1507145393 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3056973324 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 596417773 ps |
| CPU time | 6.95 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:23 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-9f75f460-e89b-4ff6-a333-51377b873fbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056973324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3056973324 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2615506151 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 132178169 ps |
| CPU time | 3.57 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-02e939b8-c00c-49f2-b4a9-4cf14dfe6686 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2615506151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2615506151 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2284718738 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 69525143452 ps |
| CPU time | 300.74 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:18:17 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-b1dec624-9302-42eb-a3b0-f82786e2ea6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2284718738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.2284718738 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2348579726 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 138812960 ps |
| CPU time | 3.44 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:28 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-ca10479d-5c10-4f27-9d7e-314b3f2aaf9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348579726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2348579726 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.1584939163 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 73886578 ps |
| CPU time | 3.62 seconds |
| Started | May 23 01:13:16 PM PDT 24 |
| Finished | May 23 01:13:24 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-b6c7ff2b-a6bb-4108-9310-04b051b0970e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1584939163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1584939163 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.802378369 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 135129875 ps |
| CPU time | 6.97 seconds |
| Started | May 23 01:13:17 PM PDT 24 |
| Finished | May 23 01:13:27 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-af6ffde8-7cec-40af-8dab-ad075fa7ba47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=802378369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.802378369 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.163170089 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 84890474684 ps |
| CPU time | 85.71 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:14:43 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-d2a2ec17-1d5d-43eb-b47d-4a9158115aa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=163170089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.163170089 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2378142143 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 990753907 ps |
| CPU time | 5.46 seconds |
| Started | May 23 01:13:16 PM PDT 24 |
| Finished | May 23 01:13:25 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-7b0f7d62-f990-48c3-a055-da8c0e46f4c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2378142143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2378142143 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3809868704 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 56208914 ps |
| CPU time | 9.38 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:13:27 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-bbe66c24-c47a-41f0-b8fe-42a6ae110efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809868704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3809868704 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.1178895522 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 154334567 ps |
| CPU time | 1.86 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-bcdfe0c4-d17c-4086-af37-f05cfab49efa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1178895522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1178895522 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2168525967 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 31861399 ps |
| CPU time | 1.25 seconds |
| Started | May 23 01:13:22 PM PDT 24 |
| Finished | May 23 01:13:26 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-498decfd-23ac-4726-bc36-d973bb61083d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2168525967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2168525967 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.369911759 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1981904168 ps |
| CPU time | 7.36 seconds |
| Started | May 23 01:13:19 PM PDT 24 |
| Finished | May 23 01:13:31 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-70961897-58be-424c-afe0-2c0130b8b604 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=369911759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.369911759 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.864857315 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1779761448 ps |
| CPU time | 5.14 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:30 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-42c001ec-313a-4b8f-b9e4-32419676f1a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=864857315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.864857315 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.746727452 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 11138892 ps |
| CPU time | 1.18 seconds |
| Started | May 23 01:13:20 PM PDT 24 |
| Finished | May 23 01:13:25 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-6af0f1ac-4049-4e1d-97b2-dbb9d9f58615 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746727452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.746727452 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.1475092673 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 7139478300 ps |
| CPU time | 82.16 seconds |
| Started | May 23 01:13:14 PM PDT 24 |
| Finished | May 23 01:14:39 PM PDT 24 |
| Peak memory | 203888 kb |
| Host | smart-044831f0-fa7f-43cc-ba68-9f46fac2ca5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1475092673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1475092673 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.821860788 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2410779583 ps |
| CPU time | 41.01 seconds |
| Started | May 23 01:13:17 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-94a1fb68-4879-4dc2-badc-7523ff4f687b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=821860788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.821860788 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3497476496 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 375018384 ps |
| CPU time | 28.3 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:58 PM PDT 24 |
| Peak memory | 204140 kb |
| Host | smart-b5b74ff3-79f6-4708-83de-16babc5ca856 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3497476496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.3497476496 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.4099128074 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 473910441 ps |
| CPU time | 52.49 seconds |
| Started | May 23 01:13:19 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 203912 kb |
| Host | smart-ee932522-0bb6-4738-a859-effdfe8bfcf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4099128074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.4099128074 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.408085292 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 84864387 ps |
| CPU time | 1.91 seconds |
| Started | May 23 01:13:15 PM PDT 24 |
| Finished | May 23 01:13:21 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-f9eaa1a9-9257-4153-ac28-ca41269f4afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=408085292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.408085292 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2648923379 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 714852692 ps |
| CPU time | 14.74 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-c423bb1f-405d-4d84-9544-5f2f46b7854b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2648923379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2648923379 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.571906582 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 554464042 ps |
| CPU time | 6.13 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:37 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-4db9906d-a968-4f7e-967c-3c51445ffdbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571906582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.571906582 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.512642336 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 61380911 ps |
| CPU time | 6.42 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:37 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-432ecf01-30cd-4951-81f3-afcb75e1c183 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=512642336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.512642336 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.762869531 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 72663427 ps |
| CPU time | 2.6 seconds |
| Started | May 23 01:13:30 PM PDT 24 |
| Finished | May 23 01:13:37 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-e71cef49-d031-47de-afa3-6e018a4bafdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762869531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.762869531 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1045568393 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 62264037567 ps |
| CPU time | 151.17 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:16:04 PM PDT 24 |
| Peak memory | 201852 kb |
| Host | smart-d5af6133-ab64-4532-b038-5fea5ab3dec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045568393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1045568393 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2991020297 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 21171043600 ps |
| CPU time | 76.36 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:14:46 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-44de6547-f066-4fca-8d89-23ed423c3e2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2991020297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2991020297 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3161911074 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 17985773 ps |
| CPU time | 2.29 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:33 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-9aa0c6e4-6411-4215-861b-55b43d6e986f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161911074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3161911074 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.289898784 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 46571847 ps |
| CPU time | 4.42 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:36 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-1a674bd3-bf0f-4dcc-81ed-775b212e1b10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=289898784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.289898784 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.2170195051 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 8625211 ps |
| CPU time | 1.18 seconds |
| Started | May 23 01:13:21 PM PDT 24 |
| Finished | May 23 01:13:26 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-50d37532-dd20-4dac-baf3-cba2ac19f85e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2170195051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2170195051 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1207953 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2710743450 ps |
| CPU time | 11.37 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:44 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-a6a7ae4c-67cb-465f-95d4-36c41aa7ce5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1207953 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1145576152 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1243803762 ps |
| CPU time | 6.74 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:13:40 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-55dbc545-fd7a-478e-95be-6556ff9fea0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1145576152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1145576152 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.647113376 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 13929202 ps |
| CPU time | 1.2 seconds |
| Started | May 23 01:13:16 PM PDT 24 |
| Finished | May 23 01:13:20 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-1c1e88a5-34f2-47c6-aff5-2e0e9bc3ae66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647113376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.647113376 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3017747797 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 25769769011 ps |
| CPU time | 130.01 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:15:41 PM PDT 24 |
| Peak memory | 203244 kb |
| Host | smart-c8477cf5-9f42-4a88-8047-10cc62e95e26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3017747797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3017747797 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.340739284 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 465281382 ps |
| CPU time | 53.75 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-b90b0551-e44f-4319-8771-1423e9059b71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=340739284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.340739284 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.917253273 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 11195009503 ps |
| CPU time | 223.57 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:17:18 PM PDT 24 |
| Peak memory | 206852 kb |
| Host | smart-07340886-4a47-47cc-b7ac-3d8d8e816a74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=917253273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.917253273 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2738090533 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1493385224 ps |
| CPU time | 105.52 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:15:20 PM PDT 24 |
| Peak memory | 205056 kb |
| Host | smart-f5c1d10d-4e8f-4fa0-895e-1b10beec529e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738090533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.2738090533 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3204544165 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1398039037 ps |
| CPU time | 11.45 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-bf945100-1e26-4b82-83d0-a64bd209aa2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3204544165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3204544165 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2545814936 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 78416249 ps |
| CPU time | 10.86 seconds |
| Started | May 23 01:13:24 PM PDT 24 |
| Finished | May 23 01:13:38 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-49b120ed-0896-4307-bbd6-4de799db9acc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2545814936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2545814936 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3159370768 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 29854613133 ps |
| CPU time | 142.36 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:15:54 PM PDT 24 |
| Peak memory | 203252 kb |
| Host | smart-417e8505-7c20-410c-a242-289547134173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3159370768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3159370768 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.670783129 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 158908729 ps |
| CPU time | 3.47 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-99386b70-89c7-4ab8-b84c-f75ae6653ea4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670783129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.670783129 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.1238744682 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 109194916 ps |
| CPU time | 1.67 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-85395aca-3e97-4153-ac9f-0b3308aacede |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238744682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1238744682 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.2202814215 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2621451001 ps |
| CPU time | 14.26 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-3ecde5e5-619b-4161-878b-bec0dce8f83f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2202814215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2202814215 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2025070707 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 9344275536 ps |
| CPU time | 43.43 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-20ba6532-17af-426f-8eba-166497d7f8e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025070707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2025070707 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1239135572 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 23784368033 ps |
| CPU time | 71.08 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:14:42 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-6b26531e-afc5-4972-ad43-7e53208b540c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1239135572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1239135572 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1804309727 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 225771314 ps |
| CPU time | 5.61 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-45539992-7a7e-4aa0-aa30-19f712c7d8a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804309727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1804309727 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1926715166 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1639651731 ps |
| CPU time | 14.06 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:13:48 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-f05e18af-966d-44d0-b419-bb58191afbb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926715166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1926715166 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.2369725632 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 72427181 ps |
| CPU time | 1.58 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:31 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-4a949baa-ace8-4102-b4b0-6064e6d73fa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369725632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2369725632 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3387832820 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1702331955 ps |
| CPU time | 7.38 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-223d98f4-6900-4880-84a9-40e9cb3b31e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387832820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3387832820 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.906416628 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1396541096 ps |
| CPU time | 5.07 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-e4545734-42f7-4de8-8c13-900c1090e639 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=906416628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.906416628 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3236018303 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11145041 ps |
| CPU time | 1.07 seconds |
| Started | May 23 01:13:30 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-efde2214-7d75-46de-982a-cf278ae1951b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236018303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3236018303 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1924029632 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 12184960099 ps |
| CPU time | 25.63 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:54 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-55157f90-8385-4241-851c-711ef05acd9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924029632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1924029632 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2255742593 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8128497782 ps |
| CPU time | 25.02 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:54 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-3ed4ba58-37ae-4435-8bd7-e789bb1d5175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2255742593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2255742593 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.417117694 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 157957037 ps |
| CPU time | 9.08 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 202276 kb |
| Host | smart-9ab124a0-b858-4cca-b3b7-d138187ca220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=417117694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.417117694 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2586270741 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 252390834 ps |
| CPU time | 40.33 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 203428 kb |
| Host | smart-9c0dea87-960b-430a-9a98-3fe89290f045 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2586270741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.2586270741 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.4164841007 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 115950292 ps |
| CPU time | 2.37 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-ce48babd-3dde-4b10-adf7-b19ff5baf7f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4164841007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4164841007 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1557899062 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 24444496 ps |
| CPU time | 4.19 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:13:39 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-331e51ac-4778-4d49-ae3d-d749a3bf036d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1557899062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1557899062 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2103941162 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 38233650309 ps |
| CPU time | 234.22 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:17:25 PM PDT 24 |
| Peak memory | 203160 kb |
| Host | smart-065f6b52-b6f4-41ec-8660-2f885b3f1a09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2103941162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2103941162 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.398949783 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 146556163 ps |
| CPU time | 2.15 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-fd3699b6-8f51-4490-8d38-5c4e34edbc06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=398949783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.398949783 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.1264448177 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1288857973 ps |
| CPU time | 12.68 seconds |
| Started | May 23 01:13:25 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-7c452ed0-4538-49ff-ba42-0d711f1c02cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1264448177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1264448177 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.3348023429 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 11872734 ps |
| CPU time | 1.18 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:32 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-3eb80042-6c8a-4f46-a34f-e2358fb2d539 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3348023429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3348023429 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.506647678 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3864775264 ps |
| CPU time | 18.86 seconds |
| Started | May 23 01:13:24 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-46fff063-0e47-4d02-9612-7a37cc97b409 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=506647678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.506647678 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2765929165 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 50719413386 ps |
| CPU time | 164.23 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:16:14 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-562001a9-693d-4b13-9e9f-b707e67f1536 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2765929165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2765929165 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2711033509 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 72404200 ps |
| CPU time | 9.58 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:40 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-1a728bb6-3550-4804-9636-53fe77a01bad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711033509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2711033509 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.2591729986 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 34158241 ps |
| CPU time | 3.72 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-c56eac4d-d24a-41b5-90af-8cff46549b37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2591729986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2591729986 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.1047085176 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 90157416 ps |
| CPU time | 1.44 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:32 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-095701e7-5494-455c-9b12-9a74260dbc1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1047085176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1047085176 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3554496079 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6266372198 ps |
| CPU time | 10.92 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:42 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-ca8d12f3-2c30-4cd9-9e36-eb862e8bdf91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554496079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3554496079 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3103948356 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1347332868 ps |
| CPU time | 10.46 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:13:45 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-f15ab9a6-0dd0-47f0-8719-ad6ecd85d150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3103948356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3103948356 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1581765941 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 10032626 ps |
| CPU time | 1.28 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:32 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-6ced682c-3cb8-493a-a88a-312e0cba1c3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581765941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1581765941 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2003029051 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 445869941 ps |
| CPU time | 13.92 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-9973f3f9-1ad3-437a-8344-5e2f508ab770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2003029051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2003029051 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.4091756766 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6956430293 ps |
| CPU time | 13.27 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-0369d788-9d3e-4807-a4cf-221dd6266c26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091756766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4091756766 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2033348117 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 116635326 ps |
| CPU time | 19.99 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:51 PM PDT 24 |
| Peak memory | 203068 kb |
| Host | smart-b78e0844-0876-4d48-8de8-304e1c71aa70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2033348117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2033348117 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.4174300975 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 897255755 ps |
| CPU time | 132.01 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:15:45 PM PDT 24 |
| Peak memory | 206020 kb |
| Host | smart-e6b7d07c-8e00-43c8-ab9d-44af733bd19c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4174300975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.4174300975 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2299491172 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 343105296 ps |
| CPU time | 6.69 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:36 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-317f53b8-bf8b-4e16-9e6c-065c77c41482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2299491172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2299491172 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.237124368 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 11542261 ps |
| CPU time | 1.79 seconds |
| Started | May 23 01:12:11 PM PDT 24 |
| Finished | May 23 01:12:14 PM PDT 24 |
| Peak memory | 202024 kb |
| Host | smart-ef4250c7-cb78-4a6f-9f57-226aa6759ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237124368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.237124368 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3769500581 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 38784968927 ps |
| CPU time | 223.21 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:15:58 PM PDT 24 |
| Peak memory | 202920 kb |
| Host | smart-79fa0fac-7d1d-4561-baac-5260da60f350 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3769500581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.3769500581 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1040899047 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 192045313 ps |
| CPU time | 1.4 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:12:25 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-d5bf2491-de5f-4009-8323-1b91747121c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1040899047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1040899047 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2253196352 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 73926363 ps |
| CPU time | 1.81 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-3efc74cd-e36f-4982-b2c1-fd1e130406eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2253196352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2253196352 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.4203337765 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 52699748 ps |
| CPU time | 5.49 seconds |
| Started | May 23 01:12:12 PM PDT 24 |
| Finished | May 23 01:12:18 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-3fbcd4cf-6dfd-45e4-8751-bd84dd8d9abd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4203337765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.4203337765 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2235780025 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 38640059665 ps |
| CPU time | 129.83 seconds |
| Started | May 23 01:12:11 PM PDT 24 |
| Finished | May 23 01:14:22 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-4882f9be-e634-4838-84b4-564fb0665aef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235780025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2235780025 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.869075602 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 19944038068 ps |
| CPU time | 42.22 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:12:58 PM PDT 24 |
| Peak memory | 202272 kb |
| Host | smart-e92a9abc-e3e2-4dbc-8d21-0447970f3672 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=869075602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.869075602 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.511489358 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 61160339 ps |
| CPU time | 5.65 seconds |
| Started | May 23 01:12:10 PM PDT 24 |
| Finished | May 23 01:12:17 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-a2f4903e-60fc-48fa-9797-0a7d072b9ee4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511489358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.511489358 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3342266660 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 667480853 ps |
| CPU time | 9.16 seconds |
| Started | May 23 01:12:18 PM PDT 24 |
| Finished | May 23 01:12:28 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-bb907eb6-55b1-4213-a939-fa6f97991f30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3342266660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3342266660 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.3519088837 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 335877616 ps |
| CPU time | 1.52 seconds |
| Started | May 23 01:12:11 PM PDT 24 |
| Finished | May 23 01:12:13 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-22857b9e-0711-46ab-b08c-aa35d0092bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3519088837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3519088837 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3020627912 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2324888968 ps |
| CPU time | 10.6 seconds |
| Started | May 23 01:12:18 PM PDT 24 |
| Finished | May 23 01:12:29 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-9502faf1-234b-4b45-9c75-a01f7abbf8e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020627912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3020627912 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3732790995 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1925693753 ps |
| CPU time | 10.1 seconds |
| Started | May 23 01:12:14 PM PDT 24 |
| Finished | May 23 01:12:25 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-9ab7cf7a-acfc-4721-b744-b25a8bb875d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3732790995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3732790995 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1448465987 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8080207 ps |
| CPU time | 1.04 seconds |
| Started | May 23 01:12:12 PM PDT 24 |
| Finished | May 23 01:12:14 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-782fb3e3-3680-4f51-8255-ece617b230b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448465987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1448465987 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1463276213 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2734741985 ps |
| CPU time | 30.12 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:12:54 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-7daa50e3-ebd9-461a-a131-fd1bf5a01ecd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1463276213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1463276213 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.332057475 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 781852952 ps |
| CPU time | 42.05 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-e2b46b4e-2722-452d-be0e-9707ae3e9f43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332057475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.332057475 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3644073861 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 41699247 ps |
| CPU time | 7.64 seconds |
| Started | May 23 01:12:28 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-113c9eaf-77b0-4e3e-b43d-1f09a6211f1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3644073861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3644073861 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2590795942 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 149235867 ps |
| CPU time | 20.36 seconds |
| Started | May 23 01:12:18 PM PDT 24 |
| Finished | May 23 01:12:39 PM PDT 24 |
| Peak memory | 203196 kb |
| Host | smart-941d9bfd-8e82-4b52-9b05-b7d4033a12e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590795942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.2590795942 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.94986300 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 35379007 ps |
| CPU time | 3.84 seconds |
| Started | May 23 01:12:20 PM PDT 24 |
| Finished | May 23 01:12:25 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-985fce52-7dc7-4791-b67e-c3fbc662b2ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=94986300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.94986300 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2934994469 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 19637608 ps |
| CPU time | 3.72 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-d0f0f925-0405-4a49-9815-84e96ef463c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2934994469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2934994469 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2139487212 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 24936809272 ps |
| CPU time | 186.38 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:16:38 PM PDT 24 |
| Peak memory | 203252 kb |
| Host | smart-c0256270-5408-47c1-b9ed-d2ed149256b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2139487212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2139487212 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2394071859 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 32719859 ps |
| CPU time | 3.21 seconds |
| Started | May 23 01:13:33 PM PDT 24 |
| Finished | May 23 01:13:39 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-e7d6539a-a3f2-4e5f-bbeb-95eab0747d36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394071859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2394071859 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.348935666 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 139050301 ps |
| CPU time | 2.71 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:33 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-a401d2c8-cd38-4909-b285-14ccdb111266 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=348935666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.348935666 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2146183605 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 100255615 ps |
| CPU time | 2.92 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-79a6a79f-fc46-47cf-9de4-a64bddbdb075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2146183605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2146183605 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.4197143457 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 56050256613 ps |
| CPU time | 157.1 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:16:10 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-ce5223bd-540c-4695-aaec-f02328231d0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197143457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.4197143457 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3878076604 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 16817373796 ps |
| CPU time | 63.3 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:14:36 PM PDT 24 |
| Peak memory | 201952 kb |
| Host | smart-709faa9a-f987-484f-ae73-7b90f57c9c83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3878076604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3878076604 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1830651495 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 51847751 ps |
| CPU time | 6.33 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:38 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-3bc00b1b-f87f-4b1e-8ff3-31a114ce0eff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830651495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1830651495 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1972139131 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 140910909 ps |
| CPU time | 3.22 seconds |
| Started | May 23 01:13:28 PM PDT 24 |
| Finished | May 23 01:13:35 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-5ecdf878-955a-4b54-a77d-7771683b57ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1972139131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1972139131 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.408221543 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 13021550 ps |
| CPU time | 1.07 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:13:36 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-9730e883-064b-4ce5-9466-4e3b6a4fb060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=408221543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.408221543 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4240433119 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 10145224016 ps |
| CPU time | 9.59 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-7f82df1b-8b89-405f-9560-a423e291bd14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240433119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4240433119 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2668066922 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 8131912527 ps |
| CPU time | 11.56 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-c8d62b33-518b-4d31-9e0b-769582ed6e4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2668066922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2668066922 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.780303742 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 11743862 ps |
| CPU time | 0.98 seconds |
| Started | May 23 01:13:26 PM PDT 24 |
| Finished | May 23 01:13:32 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-8233ff82-a754-4bd7-931a-0a2c1b262c52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780303742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.780303742 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.101492138 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3035882207 ps |
| CPU time | 62.99 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:14:37 PM PDT 24 |
| Peak memory | 202796 kb |
| Host | smart-1c082b28-8da9-47eb-8b3d-8469bb0d752f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101492138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.101492138 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2789221784 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 92671620 ps |
| CPU time | 6.29 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:13:40 PM PDT 24 |
| Peak memory | 201688 kb |
| Host | smart-d192d6be-9775-42e8-8210-8c33b977fce1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2789221784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2789221784 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.930633953 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1781616146 ps |
| CPU time | 188.13 seconds |
| Started | May 23 01:13:34 PM PDT 24 |
| Finished | May 23 01:16:44 PM PDT 24 |
| Peak memory | 208392 kb |
| Host | smart-a4d94503-fcda-43be-9801-df92ad0279cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930633953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand _reset.930633953 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.21107982 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 91886732 ps |
| CPU time | 16.48 seconds |
| Started | May 23 01:13:29 PM PDT 24 |
| Finished | May 23 01:13:50 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-0f036370-f8f8-4f5b-8760-21015b1c342b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=21107982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rese t_error.21107982 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3625674679 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 235129882 ps |
| CPU time | 1.92 seconds |
| Started | May 23 01:13:30 PM PDT 24 |
| Finished | May 23 01:13:36 PM PDT 24 |
| Peak memory | 202104 kb |
| Host | smart-2eea4834-9dfa-4b62-a014-6ba32870e5dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625674679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3625674679 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2020124133 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3988011180 ps |
| CPU time | 22.75 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:13:57 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-024d4eac-a2fc-458f-8723-11e442da911e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020124133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2020124133 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3643444816 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3057200048 ps |
| CPU time | 17.17 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:14:00 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-1312f86a-a80f-4447-8999-9c7fed4a7a33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3643444816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.3643444816 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2894381001 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 67352932 ps |
| CPU time | 7.32 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:48 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-10a18471-e311-4ecd-b70a-a1b992621a9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2894381001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2894381001 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.14799890 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 70178732 ps |
| CPU time | 6.04 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:51 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-3a2009a1-a0d1-4f9f-85f6-44dfd7047b74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=14799890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.14799890 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.3681032874 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 30940087 ps |
| CPU time | 2.84 seconds |
| Started | May 23 01:13:33 PM PDT 24 |
| Finished | May 23 01:13:38 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-727daf0d-9387-462b-9257-61bf20640207 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3681032874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3681032874 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1880673227 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 37933082918 ps |
| CPU time | 79.19 seconds |
| Started | May 23 01:13:32 PM PDT 24 |
| Finished | May 23 01:14:54 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-ef2de451-0dd1-4d0b-be6a-3f88854f080a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880673227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1880673227 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2436668400 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 9825865337 ps |
| CPU time | 60.4 seconds |
| Started | May 23 01:13:33 PM PDT 24 |
| Finished | May 23 01:14:36 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-06b5fef0-15a2-42ad-9f2f-14f81b18e9da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2436668400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2436668400 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3665680816 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 95486290 ps |
| CPU time | 7.81 seconds |
| Started | May 23 01:13:34 PM PDT 24 |
| Finished | May 23 01:13:44 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-0757ced1-3fe1-42b6-9c8f-e85fa4088ad0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665680816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3665680816 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.2837608752 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 80421404 ps |
| CPU time | 5.94 seconds |
| Started | May 23 01:13:36 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-b94f7141-f434-4577-ba5c-c65f04741f13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2837608752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2837608752 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2740351184 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 44055282 ps |
| CPU time | 1.46 seconds |
| Started | May 23 01:13:32 PM PDT 24 |
| Finished | May 23 01:13:37 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-6c05256f-8dd7-47b5-96c8-b69f972f56bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2740351184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2740351184 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2704844613 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1396887486 ps |
| CPU time | 6.34 seconds |
| Started | May 23 01:13:31 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-a7898f24-fd9b-45f6-bfb0-0b487f9d3a21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704844613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2704844613 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.518466227 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2881632750 ps |
| CPU time | 5.6 seconds |
| Started | May 23 01:13:27 PM PDT 24 |
| Finished | May 23 01:13:37 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-ee832eb7-20ac-4cfb-a52a-898f0ef2aac0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=518466227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.518466227 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1595269687 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 13407489 ps |
| CPU time | 1.08 seconds |
| Started | May 23 01:13:32 PM PDT 24 |
| Finished | May 23 01:13:36 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-b93a046d-1503-42bf-aec9-cb267bf73458 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595269687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1595269687 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.124778876 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1145981210 ps |
| CPU time | 24.43 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-68f0d60c-2d08-43a8-b415-95726cca6ca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=124778876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.124778876 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.579662984 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 576103936 ps |
| CPU time | 20.32 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:14:00 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-9e14a4af-2e73-4d44-9873-f984038f70e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579662984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.579662984 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1505370608 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2614692576 ps |
| CPU time | 35.12 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:14:14 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-71bdb928-8ab8-42a0-9b65-fa18a24c0959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505370608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1505370608 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2291707066 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 88357283 ps |
| CPU time | 6.17 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:52 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-378ebc0e-a6d1-4d57-b77b-d0599c637fb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291707066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.2291707066 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2580209170 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 266999471 ps |
| CPU time | 6.41 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-f7f95caa-2e3b-44db-b63e-7419c9add2b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2580209170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2580209170 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3801498429 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5082006888 ps |
| CPU time | 15.81 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 202104 kb |
| Host | smart-1162b899-68e2-4a15-a5cf-657e45e984f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3801498429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3801498429 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1125434437 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 16979777842 ps |
| CPU time | 115.63 seconds |
| Started | May 23 01:13:43 PM PDT 24 |
| Finished | May 23 01:15:42 PM PDT 24 |
| Peak memory | 203132 kb |
| Host | smart-00c8ee11-d2f3-42e4-a5fa-69fa77582bb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1125434437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1125434437 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2981483090 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 508602929 ps |
| CPU time | 10 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:50 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-74839619-4190-4274-bbfb-029839870b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2981483090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2981483090 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.304276325 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 18531432 ps |
| CPU time | 1.99 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:42 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-f1d4ff9e-24af-4dac-88a8-0362b6f22b59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=304276325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.304276325 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.1775544513 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 10464256 ps |
| CPU time | 1.55 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-4586331c-91eb-4464-ae7e-7b910d69e65b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1775544513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1775544513 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3463078488 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 27725650925 ps |
| CPU time | 113 seconds |
| Started | May 23 01:13:37 PM PDT 24 |
| Finished | May 23 01:15:31 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-8239008f-4c1a-4e76-82d9-5c99e6799205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463078488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3463078488 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3212756242 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 22104976072 ps |
| CPU time | 95.25 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:15:19 PM PDT 24 |
| Peak memory | 202108 kb |
| Host | smart-659a1a6f-465d-45b7-92d6-429958a72935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3212756242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3212756242 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1342470111 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 45994188 ps |
| CPU time | 4.21 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:49 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-25fc7053-8dcb-4599-b90f-88fc489cb42e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342470111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1342470111 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.4032533199 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 49345320 ps |
| CPU time | 5.48 seconds |
| Started | May 23 01:13:36 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-ad9b7404-1ee2-4c57-83fe-3bf987dde1b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4032533199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4032533199 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.291563669 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 91073153 ps |
| CPU time | 1.7 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-09eb0202-8d1c-4838-be06-b6e9221a1ba0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291563669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.291563669 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1837773531 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1984030552 ps |
| CPU time | 6.57 seconds |
| Started | May 23 01:13:37 PM PDT 24 |
| Finished | May 23 01:13:45 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-a359a454-bdf1-4ee9-a66d-cc42cf4a1d23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837773531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1837773531 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3834122520 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1625078942 ps |
| CPU time | 8.55 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:13:48 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-2a343e66-8867-466d-a424-8bd0d48cd978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3834122520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3834122520 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1966648109 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 8833615 ps |
| CPU time | 1.4 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:13:44 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-959215cc-1995-4614-b7b7-de6f9d96c254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966648109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1966648109 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2528263399 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1241942592 ps |
| CPU time | 48.76 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:14:29 PM PDT 24 |
| Peak memory | 203204 kb |
| Host | smart-b58b7e5d-756f-4357-9cf8-b722f3bc9cbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2528263399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2528263399 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1490858477 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 7471282197 ps |
| CPU time | 15.17 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-e2922392-9b28-46c4-8045-aa4cd21fc1cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1490858477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1490858477 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3583614382 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 10409203480 ps |
| CPU time | 208.65 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:17:10 PM PDT 24 |
| Peak memory | 207800 kb |
| Host | smart-74991952-4af2-4b90-9ebb-491e9ea23025 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3583614382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3583614382 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2005302010 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 90544776 ps |
| CPU time | 8.17 seconds |
| Started | May 23 01:13:37 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-65c6f525-2d9e-40ac-a256-306215636172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005302010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.2005302010 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3499546894 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 351799603 ps |
| CPU time | 2.08 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-bf8c0997-ba14-4de5-ace6-68131b7a07be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499546894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3499546894 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.2256597221 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2088035288 ps |
| CPU time | 12.04 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:13:54 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-288ebede-0188-49cc-b559-baaedebb8b8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2256597221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2256597221 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4233899210 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 90418012424 ps |
| CPU time | 236.97 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:17:38 PM PDT 24 |
| Peak memory | 203260 kb |
| Host | smart-aae08c32-5c48-4ee2-a728-d74f3bbf3b1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4233899210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.4233899210 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.776751240 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 726700155 ps |
| CPU time | 9.55 seconds |
| Started | May 23 01:13:43 PM PDT 24 |
| Finished | May 23 01:13:56 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-c1e27c01-c2bd-4e50-aaac-c8b51c9260ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=776751240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.776751240 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2550479627 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 287068275 ps |
| CPU time | 7.66 seconds |
| Started | May 23 01:13:46 PM PDT 24 |
| Finished | May 23 01:13:56 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-5ad21bd2-8f30-4212-ab6b-f329e5b672ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2550479627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2550479627 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2565639315 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 30941632 ps |
| CPU time | 2.66 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:13:42 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-0ccfd8d8-2be0-4f6d-944c-6430ad488145 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2565639315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2565639315 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2176742375 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 95458703675 ps |
| CPU time | 94 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:15:18 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-4cd0f5dc-5cc6-4987-bd79-ca2e9c5869cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176742375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2176742375 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3092377577 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2458719175 ps |
| CPU time | 8.29 seconds |
| Started | May 23 01:13:45 PM PDT 24 |
| Finished | May 23 01:13:56 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-0a160c31-9abb-406b-822f-3fcb5c996f0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3092377577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3092377577 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2328610990 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 223683380 ps |
| CPU time | 4.59 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:45 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-fd9dc1ee-c638-456d-8229-0d9eb0923064 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328610990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2328610990 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.1940790050 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 55651841 ps |
| CPU time | 4.16 seconds |
| Started | May 23 01:13:46 PM PDT 24 |
| Finished | May 23 01:13:52 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-002d0f1b-59e3-47af-9169-f99f8c024110 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940790050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1940790050 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1613297738 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 176903721 ps |
| CPU time | 1.82 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-4870626b-e8ce-4514-8f08-1fa08f3522c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1613297738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1613297738 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1020269843 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 12174725635 ps |
| CPU time | 10.04 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:50 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-ee888657-885f-48aa-9e63-99002bc92481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020269843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1020269843 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.561091215 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2727112556 ps |
| CPU time | 13.12 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:13:53 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-21711dc4-f843-423f-85a6-b555e1d398ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=561091215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.561091215 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4024300767 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 10049794 ps |
| CPU time | 1.14 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:13:44 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-b051ecd3-2691-4984-93bd-1d909ffefca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024300767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4024300767 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1351862047 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 144308342 ps |
| CPU time | 15.56 seconds |
| Started | May 23 01:13:39 PM PDT 24 |
| Finished | May 23 01:13:57 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-3f86e1a7-14eb-406c-84e6-249e06e061ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351862047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1351862047 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3453575217 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 562171871 ps |
| CPU time | 43.99 seconds |
| Started | May 23 01:13:43 PM PDT 24 |
| Finished | May 23 01:14:30 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-23f0af91-f60a-407f-b769-2305cc64fe58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3453575217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3453575217 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3745122866 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1227663184 ps |
| CPU time | 144.74 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:16:07 PM PDT 24 |
| Peak memory | 205124 kb |
| Host | smart-e471e841-2cbf-4d50-bac4-12a19b9a6a8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745122866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3745122866 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1917344265 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3075556866 ps |
| CPU time | 79.61 seconds |
| Started | May 23 01:13:46 PM PDT 24 |
| Finished | May 23 01:15:08 PM PDT 24 |
| Peak memory | 206132 kb |
| Host | smart-c3856bbf-33f8-44d9-905f-c8e9eb135c9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1917344265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.1917344265 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1061941753 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3957108583 ps |
| CPU time | 11.55 seconds |
| Started | May 23 01:13:46 PM PDT 24 |
| Finished | May 23 01:14:00 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-cf3d2606-8ea1-4e4e-9e40-e640554873c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1061941753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1061941753 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3145828242 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 943571320 ps |
| CPU time | 6.14 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:13:51 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-91b05c3c-ef01-4bbe-b5fb-30e1946e154d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3145828242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3145828242 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1825139252 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 16771920989 ps |
| CPU time | 51.9 seconds |
| Started | May 23 01:13:43 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-f93a3faf-b787-4a84-a3ea-f4013727c8c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1825139252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1825139252 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3136133219 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 71618520 ps |
| CPU time | 1.95 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-e63bb2b5-2e9c-4a53-bc93-e98169c2b2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3136133219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3136133219 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1737443474 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1280361604 ps |
| CPU time | 6.14 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:13:48 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-492d5b40-0837-4733-bc10-0eb1c6982b60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1737443474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1737443474 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.81649113 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 10594246 ps |
| CPU time | 1.02 seconds |
| Started | May 23 01:13:43 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-05fa3d6b-618d-4f7b-b9fe-7f0a64f995fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81649113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.81649113 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.775034457 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 127706832875 ps |
| CPU time | 162.01 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:16:26 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-20b4a5ae-f4ff-4f1e-ac19-e59696d86983 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=775034457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.775034457 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2365943444 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 31923177940 ps |
| CPU time | 116.36 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:15:41 PM PDT 24 |
| Peak memory | 202312 kb |
| Host | smart-bab9b5ab-78b0-422b-9572-c0e9003ab994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2365943444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2365943444 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2209183316 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 46982283 ps |
| CPU time | 3.88 seconds |
| Started | May 23 01:13:43 PM PDT 24 |
| Finished | May 23 01:13:50 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-d6b2da3e-9f22-4954-a8c5-f1bc38e681b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209183316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2209183316 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.3295855398 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 97006119 ps |
| CPU time | 6.19 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:13:49 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-3272c8ff-cd2c-49d9-bdfa-476123ce8944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3295855398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3295855398 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1996776056 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 8657732 ps |
| CPU time | 1.37 seconds |
| Started | May 23 01:13:38 PM PDT 24 |
| Finished | May 23 01:13:41 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-848b7a69-8beb-4424-bdc7-45b61ad8dd48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996776056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1996776056 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.635636520 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3748374807 ps |
| CPU time | 9.84 seconds |
| Started | May 23 01:13:40 PM PDT 24 |
| Finished | May 23 01:13:51 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-f79e48c0-64fd-4b6e-a254-d19945c6f9d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=635636520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.635636520 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.585641487 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 982059910 ps |
| CPU time | 7.71 seconds |
| Started | May 23 01:13:42 PM PDT 24 |
| Finished | May 23 01:13:53 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-b07acbf7-1463-4ef8-82f8-7ffedd3bc8cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=585641487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.585641487 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.827008784 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 10437789 ps |
| CPU time | 1.24 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:13:45 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-759fe1b1-f1e9-441a-8a8e-902e9b0ec14b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827008784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.827008784 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3354608454 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5168293778 ps |
| CPU time | 34.64 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-6996af9b-fa7e-4e15-855b-83cc8aaefdf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354608454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3354608454 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3748263604 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 25447874390 ps |
| CPU time | 54.35 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:53 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-3b4e8cd5-2e80-40b0-b21e-b8980c719ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3748263604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3748263604 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.610831811 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 131929970 ps |
| CPU time | 12.18 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:08 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-343b29fd-7dd8-496e-91ba-c9d46e8bf962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=610831811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand _reset.610831811 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.668563528 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 520278314 ps |
| CPU time | 77.48 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:15:14 PM PDT 24 |
| Peak memory | 204368 kb |
| Host | smart-09331f66-d1c0-4640-bd91-55e1b01843ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=668563528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.668563528 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.4204298640 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3300186259 ps |
| CPU time | 12.55 seconds |
| Started | May 23 01:13:41 PM PDT 24 |
| Finished | May 23 01:13:56 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-06818b04-32c5-4685-89ec-4c7cb5b71410 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4204298640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4204298640 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.4057677334 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13709333 ps |
| CPU time | 2.2 seconds |
| Started | May 23 01:13:53 PM PDT 24 |
| Finished | May 23 01:13:56 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-917cfc77-2ed1-429f-a3fe-2adc184226bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4057677334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4057677334 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2028693897 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 103955080138 ps |
| CPU time | 329.08 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:19:26 PM PDT 24 |
| Peak memory | 204988 kb |
| Host | smart-5d73a372-09fe-43c3-8899-4785f236e1c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2028693897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2028693897 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.213747662 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 270381442 ps |
| CPU time | 3.27 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:13:58 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-90ed17d3-10dd-4281-af83-3e4f72e29ead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=213747662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.213747662 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1130801624 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 680478596 ps |
| CPU time | 6.66 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:02 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-db87126b-3a34-45d0-82be-8694c7a25a6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1130801624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1130801624 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.1770388203 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 505136051 ps |
| CPU time | 5.44 seconds |
| Started | May 23 01:13:59 PM PDT 24 |
| Finished | May 23 01:14:07 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-99aad907-f961-4324-881e-a10f81355a2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1770388203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1770388203 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.364941331 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 57764045051 ps |
| CPU time | 102.85 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:15:43 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-88c52d76-b370-40c9-9c4d-710e53c0c12a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=364941331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.364941331 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.852756119 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 36462941408 ps |
| CPU time | 122.77 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:16:01 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-3bff83ad-7db6-4f39-81c9-fd2cc73b1e98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=852756119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.852756119 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1653112819 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 105724120 ps |
| CPU time | 5.43 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-bf2f8536-b874-44d5-aac2-7976f53b7362 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653112819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1653112819 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.2043181188 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1228403898 ps |
| CPU time | 11.64 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:09 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-9cf19961-23d1-4775-9c71-24e758aab91f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2043181188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2043181188 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.117632292 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 88974906 ps |
| CPU time | 1.54 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-18c565de-7748-461c-af5b-83a0b8c66407 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117632292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.117632292 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3052413269 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5662573439 ps |
| CPU time | 8.57 seconds |
| Started | May 23 01:14:00 PM PDT 24 |
| Finished | May 23 01:14:11 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-dd2fe180-bd23-48ff-b5fb-fdacf4938955 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052413269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3052413269 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.734333698 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3032058999 ps |
| CPU time | 8.31 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:06 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-c4bc2516-fbca-4d33-a6b8-8ad2805411ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=734333698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.734333698 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2770344799 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 14132035 ps |
| CPU time | 1.22 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-7d4138ed-1c6b-4b4d-aad7-c1edad7e933b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770344799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2770344799 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.469584094 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 178747317 ps |
| CPU time | 14.61 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-0b475d33-506f-4c2a-a745-0088d0f0eb6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=469584094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.469584094 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1220569053 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2741479408 ps |
| CPU time | 48.75 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:48 PM PDT 24 |
| Peak memory | 203152 kb |
| Host | smart-009b9026-3918-4574-b167-bc8c0e1c4e4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220569053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1220569053 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.120963534 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3663754617 ps |
| CPU time | 27.3 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:26 PM PDT 24 |
| Peak memory | 203176 kb |
| Host | smart-51fb908a-30f4-40e2-b34e-c29040748530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=120963534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.120963534 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2811346872 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 878468249 ps |
| CPU time | 128.09 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:16:05 PM PDT 24 |
| Peak memory | 207292 kb |
| Host | smart-2a828ffe-3a61-485a-bcd4-c78b8bc0f733 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811346872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2811346872 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1658979603 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 23671172 ps |
| CPU time | 2.57 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-2028225f-33be-4c69-a88f-2a4d9b03c2a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658979603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1658979603 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1322006551 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 45601229 ps |
| CPU time | 6.57 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-1e2b00d9-d075-4ad3-90ed-a6fee2ffa064 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322006551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1322006551 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1265132089 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 5593393717 ps |
| CPU time | 35.96 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202200 kb |
| Host | smart-5a3bca59-3d94-4fcb-aefa-ba1890749582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1265132089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1265132089 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1007006954 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 27399991 ps |
| CPU time | 1.86 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:13:57 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-b8d491a9-44c0-4344-a4b0-4144f4e71907 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1007006954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1007006954 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1025233519 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 474850026 ps |
| CPU time | 5.07 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:02 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-61ee730c-084c-4e3e-9725-615fc415fca0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1025233519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1025233519 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3688895591 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 303571625 ps |
| CPU time | 6.87 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:08 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-ef768f25-aea9-4ae2-a8ce-3d1c1b7e5281 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3688895591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3688895591 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2892965458 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 28916959627 ps |
| CPU time | 70.01 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:15:09 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-fead8b02-e400-4c73-8b40-186a76f381ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892965458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2892965458 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3929311497 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 19954335894 ps |
| CPU time | 116.3 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:15:55 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-60fcb403-c027-4ab6-bc11-fabbf1a5d967 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3929311497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3929311497 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2046938971 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 9066498 ps |
| CPU time | 1.35 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-440442a6-e770-4de0-a6b6-7e8aed226197 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046938971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2046938971 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.4055379754 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1289863028 ps |
| CPU time | 3.16 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-e67ef054-0516-4fb8-8505-0028cd51df2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055379754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4055379754 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.699041151 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 33140265 ps |
| CPU time | 1.39 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-2c68dce2-ca42-4f13-9200-ce1e4026b2c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=699041151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.699041151 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.947379028 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2080278689 ps |
| CPU time | 10.28 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:08 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-8f71d861-1999-4587-b61a-214948bee84c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=947379028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.947379028 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.64056450 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 696244559 ps |
| CPU time | 5.17 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-0f0a9122-c748-4cdc-9ea3-d26c70ea92b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=64056450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.64056450 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3245582847 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 12774682 ps |
| CPU time | 1.15 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:00 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-fd0d1ea5-d220-4e9e-9a8b-1154f707e18a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245582847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3245582847 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.848148146 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3718548961 ps |
| CPU time | 36.96 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-cde915eb-593a-4260-8f67-449b77bfefae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=848148146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.848148146 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1555528080 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1499673790 ps |
| CPU time | 20.24 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-880acd23-8350-44f9-931f-589901d075a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555528080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1555528080 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.828834114 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6696938778 ps |
| CPU time | 87.24 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:15:28 PM PDT 24 |
| Peak memory | 205744 kb |
| Host | smart-ed592524-6891-4675-b528-d7d4053f4baa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=828834114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand _reset.828834114 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3161395663 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 198502596 ps |
| CPU time | 18.65 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:14 PM PDT 24 |
| Peak memory | 203108 kb |
| Host | smart-dd1272bd-b576-4d91-ae20-facc2fb11210 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3161395663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3161395663 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.698022484 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 35270040 ps |
| CPU time | 1.39 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-16c9f403-b67b-4715-b8c0-e915819b86fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=698022484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.698022484 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3193423592 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 88814326 ps |
| CPU time | 5.22 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-2df852cb-af36-4790-98ac-114bcb28df28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3193423592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3193423592 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2088720727 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 26261786 ps |
| CPU time | 1.63 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:13:58 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-a077b9e9-8311-4c14-a6f7-73a64f988be1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2088720727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2088720727 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.2910997370 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 857190987 ps |
| CPU time | 15.9 seconds |
| Started | May 23 01:13:59 PM PDT 24 |
| Finished | May 23 01:14:18 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-333b85a4-dbd1-4a22-ab0f-89d5a9c71c48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2910997370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2910997370 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2318235835 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 130580642 ps |
| CPU time | 1.88 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-578b5de9-6600-4e6f-ba5a-e30d7bd76d6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2318235835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2318235835 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2826767530 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 99830421549 ps |
| CPU time | 145.59 seconds |
| Started | May 23 01:13:53 PM PDT 24 |
| Finished | May 23 01:16:20 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-a4d2471b-85c7-4de7-b72c-c8fd1b7a2a85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826767530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2826767530 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3601511172 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5244003087 ps |
| CPU time | 24.23 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-715579ee-7943-40bd-a32d-b441fbe57e63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3601511172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3601511172 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.872303018 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 148534315 ps |
| CPU time | 5.6 seconds |
| Started | May 23 01:13:59 PM PDT 24 |
| Finished | May 23 01:14:07 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-9fee4145-e712-4674-bd35-67ed2bf4f446 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872303018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.872303018 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.897804497 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 705097711 ps |
| CPU time | 10.64 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:08 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-4e904d0a-1da5-4376-ae29-afc8844eddd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=897804497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.897804497 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.3986761019 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 83467037 ps |
| CPU time | 1.73 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-efe13509-1eae-4db4-b5cd-43b0c48ef3e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3986761019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3986761019 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2211270823 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1297877654 ps |
| CPU time | 7.01 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-1615f615-f48b-47d0-9f12-110244a4d0c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211270823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2211270823 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3578802845 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1591762506 ps |
| CPU time | 11.08 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:10 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-6780b2da-e13f-4886-b354-dfa424c0e985 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3578802845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3578802845 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.522876014 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 8827927 ps |
| CPU time | 1.27 seconds |
| Started | May 23 01:14:01 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-a02fb19e-a614-4352-9e4e-1cf5de3c8681 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522876014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.522876014 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3288468489 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 13277557644 ps |
| CPU time | 27.95 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-a355022d-923d-4e58-bb5d-c2ff8bf8f1be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288468489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3288468489 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1160139488 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 466163427 ps |
| CPU time | 10.45 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:06 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-2a638bc4-fd0d-4bc2-999d-7cf3da528d68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1160139488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1160139488 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.4227451240 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 492062984 ps |
| CPU time | 56.65 seconds |
| Started | May 23 01:13:54 PM PDT 24 |
| Finished | May 23 01:14:52 PM PDT 24 |
| Peak memory | 204120 kb |
| Host | smart-66fd8cab-a2f9-421f-b924-6cefc923d9d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4227451240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.4227451240 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3894108688 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4142787714 ps |
| CPU time | 45.04 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:44 PM PDT 24 |
| Peak memory | 203276 kb |
| Host | smart-cc998835-2a2c-4736-b8c2-235c04083da7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3894108688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3894108688 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2336354421 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 61614299 ps |
| CPU time | 6.29 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-df9a2297-de2f-49d6-bd6b-9a83dac43e7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336354421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2336354421 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2156156496 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 247521166 ps |
| CPU time | 9.45 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:08 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-4e36793c-7746-4220-9493-2e2b392e9d7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2156156496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2156156496 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4129803842 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 30356647728 ps |
| CPU time | 180.85 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:17:00 PM PDT 24 |
| Peak memory | 203236 kb |
| Host | smart-8d82bde1-9d38-46f3-a814-fee6ac921b36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4129803842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.4129803842 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.977977509 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 856819646 ps |
| CPU time | 10.33 seconds |
| Started | May 23 01:14:00 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-37792c6e-755d-42ee-a190-2ec85ea716d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=977977509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.977977509 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.827676140 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 941218323 ps |
| CPU time | 8.11 seconds |
| Started | May 23 01:14:00 PM PDT 24 |
| Finished | May 23 01:14:10 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-e6ff6988-4e53-494e-91e7-ef98f9312876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827676140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.827676140 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.3180817944 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 47312104 ps |
| CPU time | 4.58 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:04 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-5eebd0a5-f8ae-4443-a4b4-12602e124c19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180817944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3180817944 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2241089412 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 44728927044 ps |
| CPU time | 138.04 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:16:17 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-155df364-d36c-4f4d-be61-d1949c3008e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241089412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2241089412 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2013565559 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3894059847 ps |
| CPU time | 14.86 seconds |
| Started | May 23 01:13:55 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-b016e733-6a5b-4180-b24f-7578df19f082 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2013565559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2013565559 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3081398140 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 145075989 ps |
| CPU time | 3.15 seconds |
| Started | May 23 01:14:00 PM PDT 24 |
| Finished | May 23 01:14:05 PM PDT 24 |
| Peak memory | 202236 kb |
| Host | smart-7f0df89f-8458-43f5-84cc-76ef4dedec46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081398140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3081398140 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1675136040 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 13423579 ps |
| CPU time | 1.14 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:00 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-adb5ac28-8a8b-43d9-b8ea-fd3f19c43907 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1675136040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1675136040 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1487442357 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 273281396 ps |
| CPU time | 1.25 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-55b41b3b-6a51-43ad-91b9-ff01d902375c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487442357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1487442357 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3696582408 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 1673170066 ps |
| CPU time | 8.85 seconds |
| Started | May 23 01:14:00 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-edf88e55-0b03-4370-a41f-48de644af801 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696582408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3696582408 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1052901128 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1137490933 ps |
| CPU time | 8.66 seconds |
| Started | May 23 01:14:00 PM PDT 24 |
| Finished | May 23 01:14:11 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-7ad21327-fdd4-4cc5-af9d-933e279aef04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1052901128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1052901128 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1885344107 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 10040566 ps |
| CPU time | 1.16 seconds |
| Started | May 23 01:13:59 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-729480a1-f761-4160-9598-21f0dd9f4c33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885344107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1885344107 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.465661666 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3866763986 ps |
| CPU time | 55.97 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:57 PM PDT 24 |
| Peak memory | 202396 kb |
| Host | smart-5e09c4de-b9cd-4e41-9f97-1e40ded0f8e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465661666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.465661666 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1958702540 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 978283300 ps |
| CPU time | 14.56 seconds |
| Started | May 23 01:13:58 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-4c3597fa-b938-483d-a969-14d729b1938c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1958702540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1958702540 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1243312418 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5541727597 ps |
| CPU time | 115.51 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:15:54 PM PDT 24 |
| Peak memory | 206396 kb |
| Host | smart-f8a70125-d5f1-4df4-b1fa-9900af36a5b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1243312418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1243312418 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.856342888 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4078361881 ps |
| CPU time | 58.97 seconds |
| Started | May 23 01:13:59 PM PDT 24 |
| Finished | May 23 01:15:01 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-af887dff-529c-49bb-9747-d30a566e7f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=856342888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res et_error.856342888 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.4183389910 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 98388602 ps |
| CPU time | 1.86 seconds |
| Started | May 23 01:13:57 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-0f9c13bf-7868-45fe-99d4-204a76cdd241 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4183389910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4183389910 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.991229076 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2233050199 ps |
| CPU time | 9.82 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-786f8077-7ece-40c8-b1bc-383ad186a6ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=991229076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.991229076 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.755755225 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 66044427 ps |
| CPU time | 6.07 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-93449b0e-6463-4fc3-ada2-739cba0a994d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=755755225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.755755225 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3844884078 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 20516416 ps |
| CPU time | 1.97 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:10 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-012c2d5d-cec9-4965-a917-7cd6ad776cf1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3844884078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3844884078 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.2307761921 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 74231279 ps |
| CPU time | 6.89 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:15 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-81daefd4-ba23-41f7-8b8c-f62422c90775 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307761921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2307761921 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.133902647 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 30306469134 ps |
| CPU time | 113.05 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:15:59 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-174d485d-6516-428b-a6c6-789370272255 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=133902647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.133902647 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1593397047 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 18283166632 ps |
| CPU time | 108.55 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:15:56 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-7a5dded8-9e5d-45b4-84a6-beff94396a8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1593397047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1593397047 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3107525602 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 25012506 ps |
| CPU time | 1.73 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:10 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-7caafcf7-a8bc-4922-9c85-a0943f55ff1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107525602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3107525602 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.345221749 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 15553126 ps |
| CPU time | 1.7 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:08 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-f719720c-1b77-44df-93f8-1dd8c2b95fd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=345221749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.345221749 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.1071627741 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 12123383 ps |
| CPU time | 1.34 seconds |
| Started | May 23 01:13:56 PM PDT 24 |
| Finished | May 23 01:14:00 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-8a678171-5560-4a68-b9c2-51044b295550 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1071627741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1071627741 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3757887519 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3437001271 ps |
| CPU time | 7.58 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-f39b2a5d-0e1d-4ad4-acf9-d40ccfb66bf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757887519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3757887519 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2625295623 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1442606239 ps |
| CPU time | 10.96 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-4408d275-128e-4d58-af47-8f159e4b5f62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2625295623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2625295623 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3004830175 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 17556566 ps |
| CPU time | 1.32 seconds |
| Started | May 23 01:13:59 PM PDT 24 |
| Finished | May 23 01:14:03 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-33fdccda-4fb4-4df5-8824-f77ff3c5a755 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004830175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3004830175 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2918436383 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 677061051 ps |
| CPU time | 54.13 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:15:04 PM PDT 24 |
| Peak memory | 204328 kb |
| Host | smart-1a3a98a0-69dd-4104-b69c-abcf48eceb89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2918436383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2918436383 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1513801 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 364965236 ps |
| CPU time | 27.69 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-656fdc8d-03a7-4c88-923e-62e21b51b215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1513801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1513801 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1115235149 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 31490909 ps |
| CPU time | 6.93 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-02d15f95-9313-4503-8d6a-f1722a576bca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1115235149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1115235149 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3507432014 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6875768402 ps |
| CPU time | 159.95 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:16:51 PM PDT 24 |
| Peak memory | 208004 kb |
| Host | smart-d7b182f4-e3f8-4081-97e4-43bf49fdc838 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507432014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3507432014 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2711288595 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 87542103 ps |
| CPU time | 7.23 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-f4654f22-0dfc-463f-9a14-2411bda2871c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2711288595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2711288595 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.224806726 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 83585446 ps |
| CPU time | 8.44 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-5a59216e-b9da-4dd6-9c60-0ad5ff82dadf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=224806726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.224806726 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2844049920 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 9858466705 ps |
| CPU time | 34.75 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-63f36783-104b-4bc2-a869-9db92293641e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2844049920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2844049920 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1520729940 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 228892124 ps |
| CPU time | 3.45 seconds |
| Started | May 23 01:12:25 PM PDT 24 |
| Finished | May 23 01:12:31 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-380a50dc-5618-4963-b7ea-93cd4254cb32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1520729940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1520729940 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3093731586 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 631114056 ps |
| CPU time | 7.54 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:12:30 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-bf3903fa-b7d8-4c84-a804-1485f0f18ccf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093731586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3093731586 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.479612894 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1390510260 ps |
| CPU time | 11.07 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-56f4fa2b-4348-4a33-96da-6dfb060e62de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=479612894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.479612894 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1900756989 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 20384130415 ps |
| CPU time | 96.28 seconds |
| Started | May 23 01:12:24 PM PDT 24 |
| Finished | May 23 01:14:01 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-5b8e0896-43cf-4f24-b07d-b38a0193194e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900756989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1900756989 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1751389964 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 6962846156 ps |
| CPU time | 31.58 seconds |
| Started | May 23 01:12:24 PM PDT 24 |
| Finished | May 23 01:12:57 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-5f998e1d-9a5f-42c0-a885-019e9e5120f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1751389964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1751389964 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3093752967 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 99280219 ps |
| CPU time | 6.79 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:39 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-cbec7e9b-dcad-4ef6-92ae-79c3faf6021c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093752967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3093752967 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.174720543 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 57636658 ps |
| CPU time | 3.37 seconds |
| Started | May 23 01:12:19 PM PDT 24 |
| Finished | May 23 01:12:23 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-4c07396f-f887-4ff5-9456-e24d82e132ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=174720543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.174720543 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.4283733736 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 10765083 ps |
| CPU time | 1.25 seconds |
| Started | May 23 01:12:25 PM PDT 24 |
| Finished | May 23 01:12:28 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-f48963d2-ad27-4f86-bfd2-468e3955d675 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283733736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4283733736 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3798499496 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2442289244 ps |
| CPU time | 10.26 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-c11fd633-93f8-42ff-a3c1-9e234d043cbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798499496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3798499496 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2404529558 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 6378005644 ps |
| CPU time | 10.44 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:12:32 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-a10588ca-53ca-4822-bd40-3d46ecf31038 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2404529558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2404529558 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2202260375 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 13660356 ps |
| CPU time | 1.15 seconds |
| Started | May 23 01:12:19 PM PDT 24 |
| Finished | May 23 01:12:21 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-430c3fc5-ef3a-4fc6-80d6-9df2eb2a45dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202260375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2202260375 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1856787434 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 105462902 ps |
| CPU time | 5.27 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-28d0061b-8142-4e0f-b8b8-833926213078 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1856787434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1856787434 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2160892248 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 886189709 ps |
| CPU time | 13.51 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:12:50 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-177edeb1-e8b3-4784-bc59-8dd3759d3c9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2160892248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2160892248 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1461417851 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 303039478 ps |
| CPU time | 18.77 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 203104 kb |
| Host | smart-8fc81daa-c210-4953-a5ee-a0dc91c715db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461417851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1461417851 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2016819924 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 682579202 ps |
| CPU time | 10.82 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-40abb888-31c1-4424-9823-965ea2806efc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2016819924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2016819924 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.184491405 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 271957982 ps |
| CPU time | 4.59 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:14:15 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-8df7584a-1242-4e0d-8644-1cd442a3e8b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184491405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.184491405 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2197611500 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5593646296 ps |
| CPU time | 38.17 seconds |
| Started | May 23 01:14:09 PM PDT 24 |
| Finished | May 23 01:14:50 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-b514d270-5ee1-47e9-9c1d-13372f53a57e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2197611500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.2197611500 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1249912302 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 64032924 ps |
| CPU time | 4.77 seconds |
| Started | May 23 01:14:03 PM PDT 24 |
| Finished | May 23 01:14:09 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-95f2c10c-0cc7-462a-9a9c-a2f2c3434d90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1249912302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1249912302 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3003903582 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 635778276 ps |
| CPU time | 3.86 seconds |
| Started | May 23 01:14:06 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-21d8dd64-4d63-45aa-9cec-3eb4c6aa2493 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003903582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3003903582 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.3381915917 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 695818416 ps |
| CPU time | 9.04 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-0249d030-bdf3-45ac-b057-c0473c2e0a3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381915917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3381915917 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1658638978 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 93079240390 ps |
| CPU time | 147.05 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:16:33 PM PDT 24 |
| Peak memory | 202264 kb |
| Host | smart-919127ab-7beb-4728-b72b-41b1ebd62d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658638978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1658638978 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.147664683 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 17709046161 ps |
| CPU time | 42.73 seconds |
| Started | May 23 01:14:01 PM PDT 24 |
| Finished | May 23 01:14:46 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-0e3fc570-8fe6-4111-9ec8-e63d938313dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=147664683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.147664683 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.874049831 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 23809172 ps |
| CPU time | 2.63 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-33ea848f-93c2-4b8c-b8e6-85f280d23a91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874049831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.874049831 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2136546504 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 51440357 ps |
| CPU time | 2.8 seconds |
| Started | May 23 01:14:06 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-f4166351-ee70-4936-9702-2d7940ae0492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2136546504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2136546504 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.318891156 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 30295742 ps |
| CPU time | 1.39 seconds |
| Started | May 23 01:14:03 PM PDT 24 |
| Finished | May 23 01:14:06 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-78d29713-3a83-41ba-ab91-03b74fcb92c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=318891156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.318891156 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.481131020 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 12555081917 ps |
| CPU time | 9.01 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-8ceeafd1-9557-433c-bc00-986f185b86a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=481131020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.481131020 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.479945885 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 741753977 ps |
| CPU time | 6.46 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:14:17 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-c210ae65-df1a-4547-adc9-0e40acb9f758 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=479945885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.479945885 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3813543459 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 43757644 ps |
| CPU time | 1.17 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:09 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-a455956c-3e7c-4a74-8de8-3233d1187781 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813543459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3813543459 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.196971464 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 460087941 ps |
| CPU time | 37.45 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-be99868c-e160-43cb-84ef-3cf996cd8331 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=196971464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.196971464 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1396278587 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 163795806 ps |
| CPU time | 11.54 seconds |
| Started | May 23 01:14:10 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-6f4ae4d2-8c31-47a9-a708-c501839380fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1396278587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1396278587 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.813767954 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1189775822 ps |
| CPU time | 104.23 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:15:54 PM PDT 24 |
| Peak memory | 204400 kb |
| Host | smart-c37fa42d-8b30-4925-b040-af04bb0e2f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=813767954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.813767954 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2130761076 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5656771808 ps |
| CPU time | 120.43 seconds |
| Started | May 23 01:14:15 PM PDT 24 |
| Finished | May 23 01:16:17 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-d5508bfd-453a-45c6-916c-e388c241197c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2130761076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.2130761076 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1681738532 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 3518532026 ps |
| CPU time | 8.28 seconds |
| Started | May 23 01:14:09 PM PDT 24 |
| Finished | May 23 01:14:20 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-2ce5019d-2ab6-4b41-954a-71464a39df85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1681738532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1681738532 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1529256876 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 51785160 ps |
| CPU time | 1.71 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:07 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-7b52df78-14e9-45d7-b961-a86cf4129536 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1529256876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1529256876 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2695024144 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 42142171584 ps |
| CPU time | 261.53 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:18:41 PM PDT 24 |
| Peak memory | 203516 kb |
| Host | smart-d6b999bc-c923-4b98-8a09-104a9c734b0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2695024144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.2695024144 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3729335052 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 335886946 ps |
| CPU time | 5.51 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-502798d3-1e39-43c3-899a-abca1e280919 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3729335052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3729335052 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.184063168 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 892493670 ps |
| CPU time | 11.51 seconds |
| Started | May 23 01:14:10 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-956c7f9c-a356-4515-94d8-4ec8374b47a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184063168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.184063168 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.3493761354 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 84607386 ps |
| CPU time | 5.56 seconds |
| Started | May 23 01:14:09 PM PDT 24 |
| Finished | May 23 01:14:18 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-c2cd9d85-247e-4090-a2a1-37221d28bf20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3493761354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3493761354 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1678346971 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 109779800667 ps |
| CPU time | 99.38 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:15:50 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-870be357-a1ab-40a6-91d3-cfbdc1ec9f79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678346971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1678346971 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.4121165962 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 26059820087 ps |
| CPU time | 121.05 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:16:08 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-8e44caca-61d5-4710-92ba-00ed90f5d4bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4121165962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4121165962 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1474096380 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 70927243 ps |
| CPU time | 7.4 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:14:18 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-a4912ab1-f408-4d29-8bcb-5a76b0ecccb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474096380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1474096380 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.1638167613 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 17139105 ps |
| CPU time | 1.08 seconds |
| Started | May 23 01:14:11 PM PDT 24 |
| Finished | May 23 01:14:14 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-1d6dea67-b907-4b26-b467-4b02b5da6baa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1638167613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1638167613 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.1207725130 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 137861395 ps |
| CPU time | 1.63 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-67c799cf-1a7c-4c1d-8590-d8e6d97de58d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1207725130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1207725130 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.622009835 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 7061105952 ps |
| CPU time | 6.69 seconds |
| Started | May 23 01:14:06 PM PDT 24 |
| Finished | May 23 01:14:16 PM PDT 24 |
| Peak memory | 202212 kb |
| Host | smart-69bac4a5-c110-4121-8d48-a36f016b53f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=622009835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.622009835 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3527562089 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3894104210 ps |
| CPU time | 13.36 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:14:23 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-315acd5e-7a53-4a40-ad68-3853a4014bc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3527562089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3527562089 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3105135836 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 10633878 ps |
| CPU time | 1.2 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-a8c22641-b5a2-4ad3-9351-1b43d0690972 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105135836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3105135836 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3281533966 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2049560071 ps |
| CPU time | 51.29 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:15:02 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-254811ac-3e8b-4e5c-9146-ad8ad7132e82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281533966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3281533966 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3456668766 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 10705150609 ps |
| CPU time | 96.46 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:15:48 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-67efc164-190e-4521-9024-2c29c44eb40a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3456668766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3456668766 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2201122906 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 561114328 ps |
| CPU time | 55.4 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:15:15 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-6befe56f-e675-43ba-9169-8b7ab20a1c31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2201122906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2201122906 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2879911612 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 41626190 ps |
| CPU time | 7.87 seconds |
| Started | May 23 01:14:15 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-8212e5f2-e045-4d01-a5d1-37525256e5e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879911612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2879911612 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3444320623 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2258641351 ps |
| CPU time | 11.02 seconds |
| Started | May 23 01:14:15 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202120 kb |
| Host | smart-dac9d266-cb85-487c-aa22-bfff9b26205d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444320623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3444320623 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1407337743 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 113551761 ps |
| CPU time | 6.63 seconds |
| Started | May 23 01:14:14 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-64c5f33a-d991-42ce-8abf-19bc795d5cb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1407337743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1407337743 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.681815753 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 491483603 ps |
| CPU time | 6.42 seconds |
| Started | May 23 01:14:12 PM PDT 24 |
| Finished | May 23 01:14:20 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-614227cf-a458-4815-b18e-a5f31f578dc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681815753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.681815753 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.3260890726 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 53596240 ps |
| CPU time | 5.21 seconds |
| Started | May 23 01:14:14 PM PDT 24 |
| Finished | May 23 01:14:20 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-02750749-abc9-44d2-ba12-abf27bcfc0f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3260890726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3260890726 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.208476514 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 152966334 ps |
| CPU time | 4.36 seconds |
| Started | May 23 01:14:11 PM PDT 24 |
| Finished | May 23 01:14:18 PM PDT 24 |
| Peak memory | 201760 kb |
| Host | smart-02da3058-4b21-4bc0-a8f4-73720bafe694 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=208476514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.208476514 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2407966575 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 28132662523 ps |
| CPU time | 98.99 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:15:58 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-72c48c69-a8e3-40b3-bc57-fecb474fbd8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407966575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2407966575 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3966967967 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 19668975896 ps |
| CPU time | 126.48 seconds |
| Started | May 23 01:14:11 PM PDT 24 |
| Finished | May 23 01:16:20 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-9327e262-429f-461f-a41d-310c77ad55a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3966967967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3966967967 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3549929809 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 24699589 ps |
| CPU time | 1.27 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:07 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-3330a16a-ded9-45ee-9498-2d6284f85ae1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549929809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3549929809 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.680666315 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 384953514 ps |
| CPU time | 5.55 seconds |
| Started | May 23 01:14:03 PM PDT 24 |
| Finished | May 23 01:14:10 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-c7bc376e-0595-4b1c-b751-82c2ed115142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=680666315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.680666315 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.98332126 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 45720389 ps |
| CPU time | 1.37 seconds |
| Started | May 23 01:14:08 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-9b8d443e-46d2-4c1e-a880-a3bb00205504 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=98332126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.98332126 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2513900677 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2258418115 ps |
| CPU time | 8.64 seconds |
| Started | May 23 01:14:10 PM PDT 24 |
| Finished | May 23 01:14:22 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-9369ae25-def1-4b42-8e6c-173fcda5b1aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513900677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2513900677 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.637958497 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1589972731 ps |
| CPU time | 10.99 seconds |
| Started | May 23 01:14:05 PM PDT 24 |
| Finished | May 23 01:14:19 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-a791168e-9b5f-42a8-b6cc-8e0276b1099a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=637958497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.637958497 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1308663536 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 25221366 ps |
| CPU time | 1.27 seconds |
| Started | May 23 01:14:07 PM PDT 24 |
| Finished | May 23 01:14:11 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-42b5177c-8a2c-4739-af15-be00e4aa9995 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308663536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1308663536 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1672391862 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2699291059 ps |
| CPU time | 29.61 seconds |
| Started | May 23 01:14:11 PM PDT 24 |
| Finished | May 23 01:14:43 PM PDT 24 |
| Peak memory | 201000 kb |
| Host | smart-a5a73257-2a0f-4647-a8e0-111592bd49ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1672391862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1672391862 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3712649567 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3489146326 ps |
| CPU time | 54.3 seconds |
| Started | May 23 01:14:16 PM PDT 24 |
| Finished | May 23 01:15:11 PM PDT 24 |
| Peak memory | 203312 kb |
| Host | smart-d23dd0ae-6ad1-4c13-a3b4-b7bc8465e9ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3712649567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3712649567 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1345725222 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 9310163232 ps |
| CPU time | 205.68 seconds |
| Started | May 23 01:14:11 PM PDT 24 |
| Finished | May 23 01:17:39 PM PDT 24 |
| Peak memory | 205072 kb |
| Host | smart-72f65084-5f9a-4e0b-a57a-ac5d9d56f0fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1345725222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1345725222 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3597896855 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2991592364 ps |
| CPU time | 59.49 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:15:20 PM PDT 24 |
| Peak memory | 204188 kb |
| Host | smart-d14c1698-359f-46d3-8236-1c7e8f593a00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3597896855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3597896855 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.323801660 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2197820984 ps |
| CPU time | 6.15 seconds |
| Started | May 23 01:14:04 PM PDT 24 |
| Finished | May 23 01:14:12 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-ddcc57df-bd35-4f98-aa79-255acf1bfd38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323801660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.323801660 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2720326310 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 88203118 ps |
| CPU time | 9.51 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:30 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-839a1a06-d613-4dbb-88bd-1fb772990887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2720326310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2720326310 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1648560123 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 31166799854 ps |
| CPU time | 134.11 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:16:37 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-3fec655e-1f43-47f9-9c2a-f465ebc810e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1648560123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1648560123 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1443880912 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 302124185 ps |
| CPU time | 5.44 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:14:30 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-c2fc5357-da31-47a8-88a9-8ca66a47f62e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443880912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1443880912 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3903056948 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1008247428 ps |
| CPU time | 2.8 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:23 PM PDT 24 |
| Peak memory | 202052 kb |
| Host | smart-3db957b9-4d7d-4a6c-8a85-8cae59625288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3903056948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3903056948 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.3762105667 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 771588858 ps |
| CPU time | 15.32 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:37 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-012ed2ab-2cb7-40ce-9ba7-3eb11297f276 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3762105667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3762105667 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3611637935 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 107259761043 ps |
| CPU time | 106.85 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:16:11 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-0f12c3e4-fa06-4978-9233-c9a45c316b01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611637935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3611637935 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1568019421 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 100219732847 ps |
| CPU time | 119.37 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:16:21 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-cf07628f-724f-4ec5-bcc5-8df1c5f32261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1568019421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1568019421 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.872235149 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 397554367 ps |
| CPU time | 8.9 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:28 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-bde4afc2-ca53-434b-954c-538237e8792a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872235149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.872235149 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.617966897 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3131764206 ps |
| CPU time | 11.3 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-3674d2b3-0ef6-4f84-aead-761556951977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=617966897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.617966897 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3570686945 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 86982282 ps |
| CPU time | 1.64 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-28c9f3f6-7faa-4b78-a936-244c9c32dd2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3570686945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3570686945 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1863619317 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2343195442 ps |
| CPU time | 9.61 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:31 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-c6a2ea38-c7cc-4835-9a42-aecbb4f218eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863619317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1863619317 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.198244981 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3751408039 ps |
| CPU time | 10.61 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-30094504-aa0e-4e62-b387-3172e1999922 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=198244981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.198244981 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3555563383 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 9071471 ps |
| CPU time | 1.26 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-9af8e6af-a68b-49e6-804a-d5d3d54578bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555563383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3555563383 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2498248967 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1227087353 ps |
| CPU time | 26.49 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:48 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-914ec8f2-7615-46ce-a4e2-907c41335631 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2498248967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2498248967 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.162572520 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 394836752 ps |
| CPU time | 52.4 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:15:11 PM PDT 24 |
| Peak memory | 203928 kb |
| Host | smart-84f406b7-525e-4ef7-b556-6b27f4dd0e8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=162572520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res et_error.162572520 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.577292517 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 656716944 ps |
| CPU time | 10.52 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-84c70e53-17b8-466e-a655-80ee8c29ebae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=577292517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.577292517 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1146426405 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1509539060 ps |
| CPU time | 19.41 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-924617bf-6785-4408-9709-a8bc147fbf2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1146426405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1146426405 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.498491996 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 69613800731 ps |
| CPU time | 134.82 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:16:37 PM PDT 24 |
| Peak memory | 203152 kb |
| Host | smart-1c92590c-1124-41bf-8352-fee90589d73e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=498491996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.498491996 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3320900702 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1418351075 ps |
| CPU time | 11.39 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-eeb1d952-380b-4057-a9f9-d0a1bfc68e32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320900702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3320900702 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.711782399 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1505856711 ps |
| CPU time | 9.33 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:31 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-8fb1963f-d54c-4f4c-b870-520a43b4cccb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711782399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.711782399 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.65774222 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 54316035 ps |
| CPU time | 5.42 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202116 kb |
| Host | smart-a35cd800-34e1-45c3-a94b-177c26e7efc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=65774222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.65774222 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2909142872 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 15583797710 ps |
| CPU time | 54.71 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:15:13 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-7eb93079-690e-4c1a-9016-38dd7f7e9ed2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909142872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2909142872 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2860633622 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 97119039847 ps |
| CPU time | 126.06 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:16:28 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-70498aa5-9465-4ea9-99a3-7411d6e879ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2860633622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2860633622 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1404593276 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 256810893 ps |
| CPU time | 5.95 seconds |
| Started | May 23 01:14:21 PM PDT 24 |
| Finished | May 23 01:14:29 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-4d29c438-ed4a-4b62-a86b-f5f810d208cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404593276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1404593276 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1781576354 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 51637234 ps |
| CPU time | 2.76 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202044 kb |
| Host | smart-cae3094f-6e97-47f9-82b6-9f2a93dd1b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1781576354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1781576354 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1223825237 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 42939544 ps |
| CPU time | 1.39 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:20 PM PDT 24 |
| Peak memory | 202060 kb |
| Host | smart-441d06b4-5af0-4117-b900-892df3e3b01e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223825237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1223825237 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3011930345 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2443775647 ps |
| CPU time | 11.61 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202228 kb |
| Host | smart-001fde45-928d-4603-a810-f8a4d4d52d9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011930345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3011930345 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3567043367 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 5999517011 ps |
| CPU time | 8.72 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:28 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-5a50a7ef-7e97-4f53-a32a-3f90746488fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3567043367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3567043367 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3614070167 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 9647470 ps |
| CPU time | 1.4 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-a89c61ea-9772-4ceb-9c87-d9225eab99a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614070167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3614070167 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.4125106488 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 525891577 ps |
| CPU time | 17.49 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-a0855e3b-a447-40ec-bb53-b9cb5a999051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4125106488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4125106488 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3946845651 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3595134745 ps |
| CPU time | 40.86 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:15:01 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-026599ee-ec58-40a4-b69f-f3e64fda4996 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3946845651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3946845651 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.283180822 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 129690417 ps |
| CPU time | 21.04 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:41 PM PDT 24 |
| Peak memory | 203196 kb |
| Host | smart-f50aa0f6-35d6-427d-bf67-3c4f5745e0dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=283180822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.283180822 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3044000984 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 50692602 ps |
| CPU time | 1.36 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-88aa6c77-26e5-4728-bfbe-00aa06b279cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3044000984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3044000984 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1802055949 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 921931747 ps |
| CPU time | 3.84 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:26 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-32b86db3-714c-46f3-84f1-572f5af3b481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1802055949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1802055949 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1030212055 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 71671557798 ps |
| CPU time | 150.5 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:16:50 PM PDT 24 |
| Peak memory | 203184 kb |
| Host | smart-e459d17f-3b4b-4dcb-87df-aac9cd5c91df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1030212055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1030212055 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4095968454 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 51066708 ps |
| CPU time | 2.47 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-4e6078be-b748-4f03-872c-e1e7020f22a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4095968454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4095968454 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.1202700189 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 759420273 ps |
| CPU time | 9.26 seconds |
| Started | May 23 01:14:21 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-7af34e07-3c3a-4d90-b36c-2cdb8b385fe7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1202700189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1202700189 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.815839795 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3551029976 ps |
| CPU time | 15.33 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-19a5f766-13f6-4c9d-bac5-bb6f60ba74a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=815839795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.815839795 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.575058092 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 36531279111 ps |
| CPU time | 142.88 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:16:46 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-70a514f7-d5e6-4139-998f-08aea7e9ced2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=575058092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.575058092 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3737858186 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 33016667938 ps |
| CPU time | 42.5 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:15:04 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-d381311d-46c2-48bd-a814-90a741fff42e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3737858186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3737858186 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1324810739 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 11706029 ps |
| CPU time | 1.66 seconds |
| Started | May 23 01:14:17 PM PDT 24 |
| Finished | May 23 01:14:21 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-104eb9d0-130d-4ffb-a038-64183a95dca6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324810739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1324810739 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1603658495 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 21071377 ps |
| CPU time | 2.61 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-7e05a86a-4acd-455a-99ee-390aa2f46b15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1603658495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1603658495 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.1051799532 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 12553463 ps |
| CPU time | 1.05 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:14:26 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-ba8a3b8d-af26-4b58-abf1-06c540e09246 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1051799532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1051799532 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.107405764 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3487072388 ps |
| CPU time | 9.52 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:29 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-ddb04024-9bea-4945-b637-25eca5626e5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=107405764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.107405764 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2670666673 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1974776944 ps |
| CPU time | 6.49 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-8c7b883c-892d-43ff-a210-f46faf8ce576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2670666673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2670666673 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2233571271 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 13678157 ps |
| CPU time | 1.11 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:22 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-58568aaa-881d-415a-9acf-67815543dbbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233571271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2233571271 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.977757170 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5884391 ps |
| CPU time | 0.83 seconds |
| Started | May 23 01:14:21 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 193888 kb |
| Host | smart-d94d1bfe-081c-4db7-b472-f5a4eacd8fa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=977757170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.977757170 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.570738792 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 373312820 ps |
| CPU time | 2.56 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-9f49762c-2711-4f7d-898b-b58eade0f758 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=570738792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.570738792 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2775055953 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 10940153230 ps |
| CPU time | 150.3 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:16:50 PM PDT 24 |
| Peak memory | 206452 kb |
| Host | smart-365f6d1e-b67b-43c1-830f-cee4774ac4e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2775055953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2775055953 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3379178516 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 422714058 ps |
| CPU time | 31.94 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:52 PM PDT 24 |
| Peak memory | 204204 kb |
| Host | smart-a7e299c4-1620-4994-92a1-0fd53035699b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379178516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3379178516 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1747611092 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 29481333 ps |
| CPU time | 1.96 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:22 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-0f3878d1-82df-4c61-b7c0-0ea6e2b3c2db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1747611092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1747611092 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1138531600 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 171634531 ps |
| CPU time | 4.23 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202040 kb |
| Host | smart-3040d51c-fd1d-4d99-9269-4acce2832d47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1138531600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1138531600 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1226579463 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2520451781 ps |
| CPU time | 18.88 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:40 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-486aef79-84bb-4232-8e41-825eba82171a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1226579463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1226579463 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.572798324 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 168395431 ps |
| CPU time | 5.86 seconds |
| Started | May 23 01:14:22 PM PDT 24 |
| Finished | May 23 01:14:30 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-f13d3093-8d7f-4f7f-9d57-17097aa4ffde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572798324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.572798324 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.909000461 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 78787462 ps |
| CPU time | 3.83 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-62b8fb57-61d4-4fd2-bda8-76fed9366198 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=909000461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.909000461 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.2504495225 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1675104510 ps |
| CPU time | 12.34 seconds |
| Started | May 23 01:14:19 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-d2e6b004-ff7d-4d00-b50d-14856aa81e65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2504495225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2504495225 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.488877687 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 23665844515 ps |
| CPU time | 49.87 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:15:13 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-62b38186-ea69-426e-965c-c46a703e31ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=488877687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.488877687 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.434069083 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 43845419517 ps |
| CPU time | 64.3 seconds |
| Started | May 23 01:14:21 PM PDT 24 |
| Finished | May 23 01:15:27 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-7510b81b-c93b-437a-92c7-92ff552c3dcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=434069083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.434069083 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2737265527 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 130956469 ps |
| CPU time | 4.24 seconds |
| Started | May 23 01:14:21 PM PDT 24 |
| Finished | May 23 01:14:27 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-6f28f837-2d1c-451e-a6e7-5c18d3cc87ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737265527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2737265527 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.4256738251 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2169220603 ps |
| CPU time | 12.16 seconds |
| Started | May 23 01:14:18 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-fae56a50-08f8-48f3-967b-fc15b72b4d7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4256738251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4256738251 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.1831069772 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 55744313 ps |
| CPU time | 1.34 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:24 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-4959799a-8ceb-4b39-a178-598635b499f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1831069772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1831069772 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2468388065 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2206780622 ps |
| CPU time | 9.32 seconds |
| Started | May 23 01:14:20 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-fa39d3c7-d3a3-487f-9dad-49a0699381ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468388065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2468388065 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.566408881 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1162299463 ps |
| CPU time | 6.54 seconds |
| Started | May 23 01:14:21 PM PDT 24 |
| Finished | May 23 01:14:30 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-e12da466-6ddd-4b08-a4ab-b8b97f53ac29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=566408881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.566408881 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2604224769 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 12210504 ps |
| CPU time | 1.07 seconds |
| Started | May 23 01:14:23 PM PDT 24 |
| Finished | May 23 01:14:25 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-108bfdcd-9587-4ccf-b585-092d4733d9db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604224769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2604224769 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1518745206 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 568309195 ps |
| CPU time | 53.65 seconds |
| Started | May 23 01:14:26 PM PDT 24 |
| Finished | May 23 01:15:21 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-78665395-aa82-48ce-b10d-132b312c3200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518745206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1518745206 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1328409396 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 7278769301 ps |
| CPU time | 40.62 seconds |
| Started | May 23 01:14:37 PM PDT 24 |
| Finished | May 23 01:15:18 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-a5f2ba63-89b4-4859-8e3f-01ca49620dc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1328409396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1328409396 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1708462826 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 325293287 ps |
| CPU time | 27.1 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:57 PM PDT 24 |
| Peak memory | 203120 kb |
| Host | smart-203c7099-a84f-4bfb-ad87-76dd9095601a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708462826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1708462826 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.941058220 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2445013124 ps |
| CPU time | 46.7 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:15:19 PM PDT 24 |
| Peak memory | 204408 kb |
| Host | smart-c3fc8db6-f7bd-4a83-8ee3-4ab00264ae85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=941058220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.941058220 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2067697673 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 82359689 ps |
| CPU time | 6.3 seconds |
| Started | May 23 01:14:26 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-7b8ab827-ef96-45d5-8f53-addfe5c250fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2067697673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2067697673 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2949598254 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 836218034 ps |
| CPU time | 5.28 seconds |
| Started | May 23 01:14:26 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-a4109c6b-7847-42c0-a435-5d29068a496e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2949598254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2949598254 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3377671994 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 82214841 ps |
| CPU time | 2.2 seconds |
| Started | May 23 01:14:34 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-c36122c5-f3eb-4885-bc81-c479e8a3bfa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3377671994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3377671994 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2302532392 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 483111349 ps |
| CPU time | 6.1 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-51359b28-9a16-4c01-a19d-6ed64a7666db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2302532392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2302532392 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.3225010775 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 831304872 ps |
| CPU time | 11.93 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 202036 kb |
| Host | smart-029824d6-a354-4aba-be25-34095010cdd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3225010775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3225010775 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2073040987 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 25629942292 ps |
| CPU time | 75.52 seconds |
| Started | May 23 01:14:32 PM PDT 24 |
| Finished | May 23 01:15:50 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-96e7f29f-1298-460c-b02d-0ce79b4a26de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073040987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2073040987 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3701381406 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 14713869922 ps |
| CPU time | 100.74 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:16:13 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-45dcd7c8-4db1-499c-b2e2-62dc0212d377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3701381406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3701381406 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1482402393 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 209468134 ps |
| CPU time | 4.45 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:14:49 PM PDT 24 |
| Peak memory | 201976 kb |
| Host | smart-955ff901-ad59-4c3d-8c34-4e53a015d635 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482402393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1482402393 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3157755563 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3579954426 ps |
| CPU time | 13.27 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:44 PM PDT 24 |
| Peak memory | 202124 kb |
| Host | smart-23731742-c294-4535-a5e7-663aed141d4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157755563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3157755563 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.2842928539 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 8197222 ps |
| CPU time | 1.1 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-1861179b-ca3d-4b79-8acd-abb60faf2728 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2842928539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2842928539 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1204294841 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1722069073 ps |
| CPU time | 7.18 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202116 kb |
| Host | smart-541388fb-65b0-467c-8204-236fe7c0762e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204294841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1204294841 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2591638003 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 826729837 ps |
| CPU time | 7.38 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:39 PM PDT 24 |
| Peak memory | 202096 kb |
| Host | smart-06f0bf53-ac9e-4a00-83fe-1b4508b8b50a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2591638003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2591638003 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3115416631 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 9728025 ps |
| CPU time | 1.16 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-18d2f449-95db-43e8-9403-0aa212c39cc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115416631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3115416631 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1819364270 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 18837293210 ps |
| CPU time | 42.33 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:15:16 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-47869ded-f839-4140-aa7f-737f63991bb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1819364270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1819364270 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4078406117 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4055884346 ps |
| CPU time | 30.95 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:15:02 PM PDT 24 |
| Peak memory | 202204 kb |
| Host | smart-e8171c9c-5ef5-406d-85be-3df7f1e9c051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078406117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4078406117 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.383101281 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 52260641 ps |
| CPU time | 8.06 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:40 PM PDT 24 |
| Peak memory | 202196 kb |
| Host | smart-7854e099-279b-4027-818b-310d75f8b095 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=383101281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand _reset.383101281 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1190721813 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 669181818 ps |
| CPU time | 41.7 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:15:16 PM PDT 24 |
| Peak memory | 204108 kb |
| Host | smart-b7b3f5d4-5a85-4a31-846c-3087fef51372 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1190721813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1190721813 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.4220132841 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 9433921 ps |
| CPU time | 1.25 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-0610683c-d0fc-40db-873a-1c45a30a46d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4220132841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4220132841 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3635232084 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 47304617 ps |
| CPU time | 8.15 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-e5b3f715-b889-4a0d-97b1-c2d61471122f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635232084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3635232084 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.516688078 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 16011959878 ps |
| CPU time | 75.59 seconds |
| Started | May 23 01:14:27 PM PDT 24 |
| Finished | May 23 01:15:44 PM PDT 24 |
| Peak memory | 202192 kb |
| Host | smart-db867f49-a30c-4cf6-bc6b-14928bbdfdb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=516688078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.516688078 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.651639266 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 538541489 ps |
| CPU time | 5.79 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:36 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-baeff07e-48e1-4d57-af17-b921af2502f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=651639266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.651639266 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1820077259 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2866884010 ps |
| CPU time | 8.91 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:39 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-da2efd53-ca94-48b3-a377-e39bd1aa3b18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1820077259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1820077259 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.2709575635 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 789678899 ps |
| CPU time | 6.5 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:41 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-017e45b0-d413-4d14-a12b-d56049b42fa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2709575635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2709575635 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3907594287 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3955464801 ps |
| CPU time | 18.93 seconds |
| Started | May 23 01:14:38 PM PDT 24 |
| Finished | May 23 01:14:58 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-79610529-c072-4891-b050-04a9919f7bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907594287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3907594287 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2310222118 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 17601368298 ps |
| CPU time | 71.5 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:15:56 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-db0b1775-b427-4927-9b2b-6bb1a6cbf317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2310222118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2310222118 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.919794808 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 25348912 ps |
| CPU time | 1.6 seconds |
| Started | May 23 01:14:27 PM PDT 24 |
| Finished | May 23 01:14:30 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-06f4ec73-534e-4b70-998c-f5622a390695 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919794808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.919794808 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.4176045356 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 191296872 ps |
| CPU time | 3.02 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-4ce618ee-b3d5-4fa4-8465-18054b6c7f79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176045356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4176045356 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.974015114 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 15985975 ps |
| CPU time | 1 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-48e2f1ec-856b-4a47-b5f9-be631ef4b976 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=974015114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.974015114 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2289485989 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2795505775 ps |
| CPU time | 10.96 seconds |
| Started | May 23 01:14:32 PM PDT 24 |
| Finished | May 23 01:14:46 PM PDT 24 |
| Peak memory | 202240 kb |
| Host | smart-474a641a-ceb7-44ca-a261-69437dc6b1a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289485989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2289485989 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4138391143 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1003918836 ps |
| CPU time | 6.49 seconds |
| Started | May 23 01:14:33 PM PDT 24 |
| Finished | May 23 01:14:42 PM PDT 24 |
| Peak memory | 202188 kb |
| Host | smart-235b95b5-8198-456f-9bde-bee04bab7027 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4138391143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4138391143 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.255850981 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 10168295 ps |
| CPU time | 1.23 seconds |
| Started | May 23 01:14:26 PM PDT 24 |
| Finished | May 23 01:14:28 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-bf0a952a-f71c-4a05-b08b-134ad3457b57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255850981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.255850981 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.261191502 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 993940580 ps |
| CPU time | 20.01 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:52 PM PDT 24 |
| Peak memory | 203100 kb |
| Host | smart-72a4ba93-c09a-488c-a488-3dc2e3d23af9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=261191502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.261191502 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1505375513 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 7670459340 ps |
| CPU time | 52.19 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:15:22 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-36005070-8dc2-405b-ac47-3a631bc36dd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505375513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1505375513 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3316290475 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1543626515 ps |
| CPU time | 146.66 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:16:58 PM PDT 24 |
| Peak memory | 204656 kb |
| Host | smart-b18c9241-23f9-429a-9680-150c32d677f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316290475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3316290475 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2755383528 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 456218465 ps |
| CPU time | 77.78 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:15:47 PM PDT 24 |
| Peak memory | 204752 kb |
| Host | smart-b1aaf5da-31d0-4b82-90b8-0223225d2bda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2755383528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.2755383528 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1793327152 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 92844977 ps |
| CPU time | 6.92 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:39 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-0d6fc73d-587a-4c5f-9a4d-063e2dd80724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1793327152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1793327152 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.114170843 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 53628837 ps |
| CPU time | 12.59 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:45 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-971927f3-b703-4cd7-85e1-7e7224ece174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=114170843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.114170843 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2666972257 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 21172866450 ps |
| CPU time | 98.53 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:16:09 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-30047e21-404f-4574-a142-1a627c84a2a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2666972257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2666972257 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1270149368 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 116703228 ps |
| CPU time | 1.97 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:36 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-741fb13a-8dec-46c3-9d5c-760ebb9f8bca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1270149368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1270149368 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.2435948075 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 236534913 ps |
| CPU time | 8.55 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:42 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-f83347c3-8ea0-4a56-82cc-b77798ce66f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2435948075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2435948075 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.2085388513 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 7534965 ps |
| CPU time | 1.17 seconds |
| Started | May 23 01:14:36 PM PDT 24 |
| Finished | May 23 01:14:38 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-a2b8fa73-4746-4a06-a16d-d9e14e5ec12c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2085388513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2085388513 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2461540287 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 10171568653 ps |
| CPU time | 32.28 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:15:06 PM PDT 24 |
| Peak memory | 202256 kb |
| Host | smart-86f418c9-e42e-4e5b-80d6-df37ece31ac9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461540287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2461540287 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1853300465 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 18434400589 ps |
| CPU time | 46.06 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:15:18 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-e9f22314-f8f7-40bb-9fea-b1ef5a1d22be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1853300465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1853300465 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.619924874 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 20118072 ps |
| CPU time | 2.75 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 202032 kb |
| Host | smart-e0ca0b4e-37f0-40f5-993a-aeb2a56f68a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619924874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.619924874 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.3964025343 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 57183300 ps |
| CPU time | 1.73 seconds |
| Started | May 23 01:14:30 PM PDT 24 |
| Finished | May 23 01:14:35 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-80b08a45-abd1-4a07-9894-8509c42e632c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3964025343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3964025343 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.4216667950 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 106463447 ps |
| CPU time | 1.94 seconds |
| Started | May 23 01:14:32 PM PDT 24 |
| Finished | May 23 01:14:37 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-b8e0d139-6936-4d7b-93d0-d2c8e4eda720 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4216667950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4216667950 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.27083156 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 13314551749 ps |
| CPU time | 10.64 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:42 PM PDT 24 |
| Peak memory | 202220 kb |
| Host | smart-60eb982d-e58f-46a8-9cc4-19001fc73fd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.27083156 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.4056679735 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 619398741 ps |
| CPU time | 4.94 seconds |
| Started | May 23 01:14:28 PM PDT 24 |
| Finished | May 23 01:14:34 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-60bc9b1a-684b-40bf-9321-3f3ebd02e5d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4056679735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.4056679735 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1982181933 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8146892 ps |
| CPU time | 1.24 seconds |
| Started | May 23 01:14:29 PM PDT 24 |
| Finished | May 23 01:14:33 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-18f3cd8f-ff6e-464f-acc0-a0819138532f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982181933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1982181933 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3037590790 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 296680280 ps |
| CPU time | 35.78 seconds |
| Started | May 23 01:14:36 PM PDT 24 |
| Finished | May 23 01:15:13 PM PDT 24 |
| Peak memory | 202088 kb |
| Host | smart-231319cc-9f2c-4ab3-9082-38835514c93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3037590790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3037590790 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2192396298 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 5442786789 ps |
| CPU time | 50.05 seconds |
| Started | May 23 01:14:32 PM PDT 24 |
| Finished | May 23 01:15:25 PM PDT 24 |
| Peak memory | 202216 kb |
| Host | smart-e43eefe8-1cd6-4d54-96f3-0fb86998cff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192396298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2192396298 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4276653913 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 6255440432 ps |
| CPU time | 104.79 seconds |
| Started | May 23 01:14:38 PM PDT 24 |
| Finished | May 23 01:16:24 PM PDT 24 |
| Peak memory | 205020 kb |
| Host | smart-557a3ff5-ef05-4b8f-b9f5-c43808eff49e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4276653913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.4276653913 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.590607223 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 783175709 ps |
| CPU time | 46.2 seconds |
| Started | May 23 01:14:33 PM PDT 24 |
| Finished | May 23 01:15:21 PM PDT 24 |
| Peak memory | 204232 kb |
| Host | smart-13f7553b-97cb-425a-b77f-0c9b2110dae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=590607223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res et_error.590607223 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.986079617 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 260062446 ps |
| CPU time | 2.98 seconds |
| Started | May 23 01:14:31 PM PDT 24 |
| Finished | May 23 01:14:37 PM PDT 24 |
| Peak memory | 202056 kb |
| Host | smart-3b8eeda2-5f7c-4c0b-9659-3e8191ab2155 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=986079617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.986079617 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1077637167 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 51698620 ps |
| CPU time | 1.77 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-19c0a8ea-546e-4660-9714-fc643e013d52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077637167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1077637167 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3503767916 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 83504266295 ps |
| CPU time | 226.03 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:16:18 PM PDT 24 |
| Peak memory | 203264 kb |
| Host | smart-34f0ecb6-df82-434e-99f4-289bc700cc8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3503767916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3503767916 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.179998578 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 232230094 ps |
| CPU time | 5.2 seconds |
| Started | May 23 01:12:20 PM PDT 24 |
| Finished | May 23 01:12:26 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-f14320d1-d6c0-4f32-8d48-0ff893b7c404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=179998578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.179998578 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.3849768195 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2130613316 ps |
| CPU time | 15.35 seconds |
| Started | May 23 01:12:26 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-ec9a9a35-00e2-45d6-834a-5285288e4fca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3849768195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3849768195 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.3309526561 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1116434485 ps |
| CPU time | 8.27 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:12:30 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-9137a1c4-5187-49ab-a769-b36a96755f4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3309526561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3309526561 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1671803574 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 24898653052 ps |
| CPU time | 66.43 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:13:43 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-71b037dc-50a8-4682-8ca6-b2f70fce0f0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671803574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1671803574 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1354654211 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 8584684774 ps |
| CPU time | 56.02 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:13:18 PM PDT 24 |
| Peak memory | 202260 kb |
| Host | smart-a582d6d5-4f7b-4701-9224-3df8fb28d0ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1354654211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1354654211 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3992549020 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 119888599 ps |
| CPU time | 6.26 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-2727afe8-ae79-41d1-9642-6475f9975498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992549020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3992549020 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.386451302 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 401650065 ps |
| CPU time | 2.8 seconds |
| Started | May 23 01:12:26 PM PDT 24 |
| Finished | May 23 01:12:31 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-cc9e45c0-af1f-451d-9053-bd869f324676 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=386451302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.386451302 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2271271344 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 78753568 ps |
| CPU time | 1.72 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202140 kb |
| Host | smart-8402bab4-fd5b-47b2-9af8-19cbd3d72a7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2271271344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2271271344 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1431289685 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3942226646 ps |
| CPU time | 10.74 seconds |
| Started | May 23 01:12:27 PM PDT 24 |
| Finished | May 23 01:12:40 PM PDT 24 |
| Peak memory | 202100 kb |
| Host | smart-7e51e310-918c-4cc7-9f42-9a17f4cae6d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431289685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1431289685 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2258808719 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1836712207 ps |
| CPU time | 7.87 seconds |
| Started | May 23 01:12:20 PM PDT 24 |
| Finished | May 23 01:12:29 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-0384e78e-8e2b-43ee-bbe5-affaf6c6bfca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2258808719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2258808719 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3069816505 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 9269187 ps |
| CPU time | 1.18 seconds |
| Started | May 23 01:12:25 PM PDT 24 |
| Finished | May 23 01:12:28 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-f02fab1b-9001-4ebe-851e-6f263abf88d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069816505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3069816505 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2853816363 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 7886812517 ps |
| CPU time | 95.38 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:14:13 PM PDT 24 |
| Peak memory | 203256 kb |
| Host | smart-75a46154-ed19-4800-bc71-70178a265805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853816363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2853816363 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1181088793 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 21017454816 ps |
| CPU time | 66.24 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:13:28 PM PDT 24 |
| Peak memory | 202128 kb |
| Host | smart-c22c3755-a67c-4584-96c5-60e671f29c67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1181088793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1181088793 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3437210297 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 851452096 ps |
| CPU time | 75.31 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:13:40 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-ae8b585c-1957-4c48-b78d-dd91fcd419e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437210297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3437210297 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.500083910 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 272402121 ps |
| CPU time | 5.58 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:12:45 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-2c2d1545-a4a9-4bb3-b9e5-acbb9ab8e1b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=500083910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.500083910 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2639230809 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 472544520 ps |
| CPU time | 9.47 seconds |
| Started | May 23 01:12:28 PM PDT 24 |
| Finished | May 23 01:12:39 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-a94ea42f-f21c-468d-8b3c-1920872526be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639230809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2639230809 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1403351735 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 44162877634 ps |
| CPU time | 142.79 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:15:03 PM PDT 24 |
| Peak memory | 203272 kb |
| Host | smart-fbea2dff-435e-4e76-9d14-51d38ac00d0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1403351735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1403351735 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3599630041 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 37256665 ps |
| CPU time | 3.69 seconds |
| Started | May 23 01:12:39 PM PDT 24 |
| Finished | May 23 01:12:44 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-f954fa9d-bb78-43cf-b6b0-6f6ca99e72b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3599630041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3599630041 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.1394711373 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 82705222 ps |
| CPU time | 4.5 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:12:29 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-0418d448-45ec-4194-8f00-9d69b33592b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1394711373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1394711373 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.4271765598 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1678651176 ps |
| CPU time | 11.76 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:12:35 PM PDT 24 |
| Peak memory | 202108 kb |
| Host | smart-859db2e6-841f-4c58-b9e3-e56761d207dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271765598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.4271765598 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.145649276 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 23122070829 ps |
| CPU time | 101.35 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:14:05 PM PDT 24 |
| Peak memory | 202224 kb |
| Host | smart-e013db9b-37b1-4a12-856c-a7831b62766e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=145649276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.145649276 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2616112691 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 8775897926 ps |
| CPU time | 48.61 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:13:22 PM PDT 24 |
| Peak memory | 202244 kb |
| Host | smart-d7122226-c46e-406f-8bb4-e4f057071add |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2616112691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2616112691 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.326874250 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 89975582 ps |
| CPU time | 4.57 seconds |
| Started | May 23 01:12:26 PM PDT 24 |
| Finished | May 23 01:12:32 PM PDT 24 |
| Peak memory | 202152 kb |
| Host | smart-b8667933-1122-4568-a789-1b398bc9b03b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326874250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.326874250 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.1912453000 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 550668494 ps |
| CPU time | 6.99 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:42 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-b391fa6a-9877-4298-836d-a95de45d574a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1912453000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1912453000 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.726702981 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 86665254 ps |
| CPU time | 1.55 seconds |
| Started | May 23 01:12:26 PM PDT 24 |
| Finished | May 23 01:12:30 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-fd6743f4-6a3b-42f6-adc6-19565aa1bd43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726702981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.726702981 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2819832978 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1295144065 ps |
| CPU time | 7.04 seconds |
| Started | May 23 01:12:38 PM PDT 24 |
| Finished | May 23 01:12:47 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-57d840df-1a4a-47eb-bb5d-75f16189320f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819832978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2819832978 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.4082272566 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1751613297 ps |
| CPU time | 9.61 seconds |
| Started | May 23 01:12:24 PM PDT 24 |
| Finished | May 23 01:12:35 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-65bc5c33-6ece-4cef-b0f4-1e65b8b1590e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4082272566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.4082272566 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2698942213 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 26081747 ps |
| CPU time | 1.16 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-c0413ace-1660-4f32-a0e2-a92ff8fd2128 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698942213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2698942213 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2282356485 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 84094812 ps |
| CPU time | 15.77 seconds |
| Started | May 23 01:12:28 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202172 kb |
| Host | smart-b22c1a3a-2df7-4a6a-8ac7-c3373ac7a2e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282356485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2282356485 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1640402715 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 77118544 ps |
| CPU time | 8.81 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-a5a7cabd-9d52-4432-8e3a-2e9741d956ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1640402715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1640402715 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.532782391 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 17899094476 ps |
| CPU time | 205.98 seconds |
| Started | May 23 01:12:34 PM PDT 24 |
| Finished | May 23 01:16:02 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-7665ab0a-274c-48e5-8a60-80798c1b6695 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=532782391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.532782391 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2910394026 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 397127823 ps |
| CPU time | 34.45 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:13:06 PM PDT 24 |
| Peak memory | 203552 kb |
| Host | smart-6b72bd7a-ccd7-443b-bbdd-c8b7ee898189 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2910394026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2910394026 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.4192508423 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 686203374 ps |
| CPU time | 10.14 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:42 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-5843a6bf-2d5c-4660-bce6-f61c0e1e410e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4192508423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.4192508423 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.4063760301 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 315900160 ps |
| CPU time | 1.81 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:12:26 PM PDT 24 |
| Peak memory | 202064 kb |
| Host | smart-b200b909-fdb6-411b-8f7c-e6c2f77a7d62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063760301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.4063760301 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.659792948 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 17643965112 ps |
| CPU time | 117.9 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:14:32 PM PDT 24 |
| Peak memory | 202144 kb |
| Host | smart-86cc542f-2b0e-466c-8603-424793f29e18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=659792948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow _rsp.659792948 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3101414356 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 166392566 ps |
| CPU time | 2.74 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:34 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-4b2aac3d-15eb-4090-b9d9-2e09c27e2cb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3101414356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3101414356 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.445127546 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 341216130 ps |
| CPU time | 5.47 seconds |
| Started | May 23 01:12:27 PM PDT 24 |
| Finished | May 23 01:12:35 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-d7302f48-526c-4dfa-99cc-277a6c60c598 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=445127546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.445127546 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.3806927835 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 179538961 ps |
| CPU time | 8.09 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-2da2a55f-5996-4333-8f26-7fa4d6a899c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3806927835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3806927835 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3891135032 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 30279837125 ps |
| CPU time | 61.45 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:13:34 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-3f8f4463-9abe-4747-8ac5-70b6cd936a5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891135032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3891135032 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4269978734 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 30657572429 ps |
| CPU time | 168.57 seconds |
| Started | May 23 01:12:25 PM PDT 24 |
| Finished | May 23 01:15:15 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-9cb52a76-00f2-4711-b65c-71ae52994547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4269978734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4269978734 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3216468745 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 29883401 ps |
| CPU time | 3.03 seconds |
| Started | May 23 01:12:23 PM PDT 24 |
| Finished | May 23 01:12:28 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-61e206bb-f854-449a-9843-758e15a562f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216468745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3216468745 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2556788765 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 93712757 ps |
| CPU time | 3 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-4a24b515-2e16-42cb-8788-9926ff9d3573 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2556788765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2556788765 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.3049084171 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 50268894 ps |
| CPU time | 1.38 seconds |
| Started | May 23 01:12:27 PM PDT 24 |
| Finished | May 23 01:12:31 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-4b184dd1-4490-4b3c-b86b-a5cd82e107f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3049084171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3049084171 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3364059572 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 14731735913 ps |
| CPU time | 10.83 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:12:41 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-2a027199-2384-4509-aa16-4d0b49346cc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364059572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3364059572 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.281743703 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1784125672 ps |
| CPU time | 7.08 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:12:41 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-0c5f1bd0-7889-4382-8b3a-4d98e42df231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=281743703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.281743703 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3874816338 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 10193132 ps |
| CPU time | 1.17 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-c770e9ab-280a-4864-8820-8a7921060fbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874816338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3874816338 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.1680840598 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 290756330 ps |
| CPU time | 25.46 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:12:56 PM PDT 24 |
| Peak memory | 203088 kb |
| Host | smart-d5a6dd7d-3c5c-4565-af0c-150d54bea247 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680840598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1680840598 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1104152597 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1000984973 ps |
| CPU time | 18.89 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:12:42 PM PDT 24 |
| Peak memory | 202156 kb |
| Host | smart-ee7c2391-9560-47c6-8858-3d4074642528 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1104152597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1104152597 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2914661788 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 4018469358 ps |
| CPU time | 63.02 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:13:39 PM PDT 24 |
| Peak memory | 203796 kb |
| Host | smart-e6df1aa5-47b8-430a-be80-0596e31c5b0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2914661788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2914661788 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2946296422 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 8823114 ps |
| CPU time | 1.01 seconds |
| Started | May 23 01:12:28 PM PDT 24 |
| Finished | May 23 01:12:31 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-d2a3599f-5b0d-4701-ba92-277a6be3e8b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2946296422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2946296422 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.653909235 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 95926388 ps |
| CPU time | 11.04 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:43 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-cf3b52f4-c9ab-4bd3-937a-1da68ded027c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=653909235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.653909235 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.649042253 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 65476742151 ps |
| CPU time | 359.59 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:18:32 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-12948640-717d-4fdd-b844-e6e3979b0397 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=649042253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.649042253 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2214752929 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 21358648 ps |
| CPU time | 2.7 seconds |
| Started | May 23 01:12:34 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-719d008f-b78a-4aa0-bc1f-265944c65c9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2214752929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2214752929 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2357605015 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 51346030 ps |
| CPU time | 4.28 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:12:36 PM PDT 24 |
| Peak memory | 202092 kb |
| Host | smart-9dc815b8-9186-43e3-8a2c-71d9f4efed37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2357605015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2357605015 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.4244370886 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 345802895 ps |
| CPU time | 6.03 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:12:40 PM PDT 24 |
| Peak memory | 202076 kb |
| Host | smart-48024820-a40a-4a55-b42a-5c1139d23a90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4244370886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.4244370886 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2168126327 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11711071322 ps |
| CPU time | 29.29 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:13:01 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-da2ab4ad-709e-4a6b-8883-c587d0a64026 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168126327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2168126327 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3948257151 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1580229826 ps |
| CPU time | 7.97 seconds |
| Started | May 23 01:12:28 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-63411418-8ff2-4a14-b012-492e11913153 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3948257151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3948257151 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1089080927 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 58261989 ps |
| CPU time | 4.03 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:12:37 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-474556aa-9bd2-4f69-aff5-e041af11e09f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089080927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1089080927 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.3013904175 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 33675513 ps |
| CPU time | 2.26 seconds |
| Started | May 23 01:12:21 PM PDT 24 |
| Finished | May 23 01:12:25 PM PDT 24 |
| Peak memory | 202048 kb |
| Host | smart-bc022a4e-5776-4af4-83a7-aa62d7438cb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013904175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3013904175 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.992132310 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 145516814 ps |
| CPU time | 1.69 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:12:33 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-1eabe45c-cb3f-429d-8f0a-fce702a314c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992132310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.992132310 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.68720323 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2471172738 ps |
| CPU time | 10.67 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:46 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-737fcd62-654a-46a8-bccd-8d69bd66ef86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=68720323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.68720323 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.690385561 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 614783119 ps |
| CPU time | 4.99 seconds |
| Started | May 23 01:12:24 PM PDT 24 |
| Finished | May 23 01:12:30 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-4753a578-9a6e-498a-859b-a81efd101c94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=690385561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.690385561 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2176114807 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 10557876 ps |
| CPU time | 1.19 seconds |
| Started | May 23 01:12:27 PM PDT 24 |
| Finished | May 23 01:12:30 PM PDT 24 |
| Peak memory | 202132 kb |
| Host | smart-2cdeceab-0789-4f4d-bb0c-b76972e0d1a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176114807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2176114807 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.663471567 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3725042957 ps |
| CPU time | 75.78 seconds |
| Started | May 23 01:12:30 PM PDT 24 |
| Finished | May 23 01:13:47 PM PDT 24 |
| Peak memory | 203496 kb |
| Host | smart-8a6545ab-9872-407d-99fc-9cd5c237c4dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=663471567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.663471567 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.153925500 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3364065574 ps |
| CPU time | 23.5 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:13:01 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-0bdee48c-fb55-4aab-922a-bdd9076bd166 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=153925500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.153925500 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.834474910 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 860231532 ps |
| CPU time | 10.61 seconds |
| Started | May 23 01:12:25 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202080 kb |
| Host | smart-3003cd71-751f-4733-90fa-a0bba701ab62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=834474910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_ reset.834474910 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2211480727 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 130902406 ps |
| CPU time | 8.1 seconds |
| Started | May 23 01:12:29 PM PDT 24 |
| Finished | May 23 01:12:40 PM PDT 24 |
| Peak memory | 202112 kb |
| Host | smart-7d808930-de44-48a0-aee1-eed6b261746b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211480727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2211480727 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2427595669 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 838786005 ps |
| CPU time | 7.48 seconds |
| Started | May 23 01:12:25 PM PDT 24 |
| Finished | May 23 01:12:34 PM PDT 24 |
| Peak memory | 202180 kb |
| Host | smart-cdbb0143-bc75-47e1-801b-a4448e9abb20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2427595669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2427595669 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1498089752 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1462342183 ps |
| CPU time | 12.85 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:55 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-5f213ae5-bdd6-4023-a953-2b486970a323 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1498089752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1498089752 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.70391345 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 12459708837 ps |
| CPU time | 72.82 seconds |
| Started | May 23 01:12:42 PM PDT 24 |
| Finished | May 23 01:13:57 PM PDT 24 |
| Peak memory | 202252 kb |
| Host | smart-99f08c5a-eb7e-4565-8613-1e35ced2101c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=70391345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.70391345 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2960868230 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1133154114 ps |
| CPU time | 12.9 seconds |
| Started | May 23 01:12:42 PM PDT 24 |
| Finished | May 23 01:12:56 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-ad3d0fc4-e707-45b5-aac4-73b54a20d6c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2960868230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2960868230 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1862294415 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 16182581 ps |
| CPU time | 2.22 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:12:35 PM PDT 24 |
| Peak memory | 202168 kb |
| Host | smart-d80e87d8-42b4-4103-9ff6-f1033574f098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1862294415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1862294415 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.2397610186 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 54222525 ps |
| CPU time | 5.68 seconds |
| Started | May 23 01:12:31 PM PDT 24 |
| Finished | May 23 01:12:38 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-f9780f8b-fb3f-402c-8f50-08432ebb37eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2397610186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2397610186 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.988684313 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 19656435991 ps |
| CPU time | 32.17 seconds |
| Started | May 23 01:12:36 PM PDT 24 |
| Finished | May 23 01:13:10 PM PDT 24 |
| Peak memory | 202160 kb |
| Host | smart-2d26fd56-1bc0-40c5-99b9-88148bd9594c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=988684313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.988684313 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2701641373 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 11603261498 ps |
| CPU time | 59.96 seconds |
| Started | May 23 01:12:44 PM PDT 24 |
| Finished | May 23 01:13:46 PM PDT 24 |
| Peak memory | 202248 kb |
| Host | smart-b666c27a-945a-4a51-855c-0d2f0ce6c399 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2701641373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2701641373 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.227607310 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 266120632 ps |
| CPU time | 6.43 seconds |
| Started | May 23 01:12:32 PM PDT 24 |
| Finished | May 23 01:12:40 PM PDT 24 |
| Peak memory | 202068 kb |
| Host | smart-972956c6-ba19-4597-8cb8-bf0c6f800ae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227607310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.227607310 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1504398638 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1391270552 ps |
| CPU time | 9.99 seconds |
| Started | May 23 01:12:40 PM PDT 24 |
| Finished | May 23 01:12:52 PM PDT 24 |
| Peak memory | 202084 kb |
| Host | smart-9158f802-dfdd-4eca-bf62-6cc44ed04702 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1504398638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1504398638 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.2340189412 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 43791162 ps |
| CPU time | 1.23 seconds |
| Started | May 23 01:12:22 PM PDT 24 |
| Finished | May 23 01:12:24 PM PDT 24 |
| Peak memory | 202072 kb |
| Host | smart-aa592f62-9643-4bb0-bf71-2f6049161d0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2340189412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2340189412 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3013062964 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 7857733406 ps |
| CPU time | 10.86 seconds |
| Started | May 23 01:12:26 PM PDT 24 |
| Finished | May 23 01:12:39 PM PDT 24 |
| Peak memory | 202136 kb |
| Host | smart-8bbdca09-6c89-47bc-a68e-d26ad09d8804 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013062964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3013062964 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3557807130 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3270329008 ps |
| CPU time | 6.93 seconds |
| Started | May 23 01:12:19 PM PDT 24 |
| Finished | May 23 01:12:27 PM PDT 24 |
| Peak memory | 202148 kb |
| Host | smart-8c541fa7-dcbb-40ba-a969-02eeb083edfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3557807130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3557807130 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1636580386 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 9493367 ps |
| CPU time | 1.24 seconds |
| Started | May 23 01:12:26 PM PDT 24 |
| Finished | May 23 01:12:29 PM PDT 24 |
| Peak memory | 202184 kb |
| Host | smart-c2b2c0cd-435e-46e6-bffa-2ed101c36d5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636580386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1636580386 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3432051172 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 110849778 ps |
| CPU time | 13.55 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:12:50 PM PDT 24 |
| Peak memory | 202164 kb |
| Host | smart-f020b514-f983-49a8-a855-2e6109dbc9ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3432051172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3432051172 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3744374797 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 686534829 ps |
| CPU time | 28.65 seconds |
| Started | May 23 01:12:35 PM PDT 24 |
| Finished | May 23 01:13:05 PM PDT 24 |
| Peak memory | 203180 kb |
| Host | smart-e2d6fdb8-c11c-4ae4-a2cd-796f8cdd4796 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3744374797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3744374797 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1874804476 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2602707508 ps |
| CPU time | 80.23 seconds |
| Started | May 23 01:12:37 PM PDT 24 |
| Finished | May 23 01:13:59 PM PDT 24 |
| Peak memory | 205652 kb |
| Host | smart-d23f925c-72c5-46a7-a156-5ed2d91011fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1874804476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1874804476 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2805777003 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 6266841129 ps |
| CPU time | 157.73 seconds |
| Started | May 23 01:12:44 PM PDT 24 |
| Finished | May 23 01:15:23 PM PDT 24 |
| Peak memory | 206964 kb |
| Host | smart-a993d69a-c57d-4a60-9df6-1443482e9a49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2805777003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2805777003 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1919558330 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 642042278 ps |
| CPU time | 10.29 seconds |
| Started | May 23 01:12:33 PM PDT 24 |
| Finished | May 23 01:12:45 PM PDT 24 |
| Peak memory | 202176 kb |
| Host | smart-989bf7c0-5564-4f5f-aad3-631db3199490 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1919558330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1919558330 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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