Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	100.00	95.42	100.00		100.00	100.00	100.00

Total test records in report: 900

T761	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2347962886	May 30 12:46:59 PM PDT 24	May 30 12:47:12 PM PDT 24	801416501 ps
T762	/workspace/coverage/xbar_build_mode/38.xbar_smoke.1285297438	May 30 12:46:44 PM PDT 24	May 30 12:46:46 PM PDT 24	98515167 ps
T763	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2036225550	May 30 12:46:22 PM PDT 24	May 30 12:48:26 PM PDT 24	41946034094 ps
T115	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2172160031	May 30 12:45:48 PM PDT 24	May 30 12:46:04 PM PDT 24	1464901411 ps
T764	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1977625710	May 30 12:46:55 PM PDT 24	May 30 12:50:02 PM PDT 24	133534241242 ps
T160	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3638369829	May 30 12:47:02 PM PDT 24	May 30 12:48:46 PM PDT 24	21054804211 ps
T51	/workspace/coverage/xbar_build_mode/36.xbar_random.187393305	May 30 12:46:39 PM PDT 24	May 30 12:46:50 PM PDT 24	460834695 ps
T765	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2073702620	May 30 12:45:54 PM PDT 24	May 30 12:46:00 PM PDT 24	304979900 ps
T766	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.8337839	May 30 12:45:33 PM PDT 24	May 30 12:45:38 PM PDT 24	36856447 ps
T767	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3437987970	May 30 12:45:34 PM PDT 24	May 30 12:46:58 PM PDT 24	13634160928 ps
T198	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1871825889	May 30 12:47:38 PM PDT 24	May 30 12:53:04 PM PDT 24	119218814878 ps
T768	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3586991808	May 30 12:44:29 PM PDT 24	May 30 12:45:25 PM PDT 24	3406440830 ps
T769	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.378571074	May 30 12:45:27 PM PDT 24	May 30 12:45:35 PM PDT 24	1404321023 ps
T770	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3072116984	May 30 12:45:53 PM PDT 24	May 30 12:49:12 PM PDT 24	7257103122 ps
T771	/workspace/coverage/xbar_build_mode/43.xbar_error_random.733030322	May 30 12:47:11 PM PDT 24	May 30 12:47:17 PM PDT 24	59047022 ps
T772	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1801358687	May 30 12:46:51 PM PDT 24	May 30 12:46:56 PM PDT 24	381317903 ps
T773	/workspace/coverage/xbar_build_mode/38.xbar_same_source.3076586536	May 30 12:46:45 PM PDT 24	May 30 12:46:52 PM PDT 24	1236799562 ps
T774	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4052131474	May 30 12:44:54 PM PDT 24	May 30 12:45:06 PM PDT 24	6088156266 ps
T775	/workspace/coverage/xbar_build_mode/16.xbar_error_random.3798126301	May 30 12:45:39 PM PDT 24	May 30 12:45:41 PM PDT 24	46226617 ps
T776	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.775200915	May 30 12:47:15 PM PDT 24	May 30 12:49:49 PM PDT 24	19758368508 ps
T777	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2993646927	May 30 12:45:49 PM PDT 24	May 30 12:47:20 PM PDT 24	3233193734 ps
T778	/workspace/coverage/xbar_build_mode/44.xbar_error_random.1180860306	May 30 12:47:11 PM PDT 24	May 30 12:47:17 PM PDT 24	87302767 ps
T779	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3668873862	May 30 12:46:39 PM PDT 24	May 30 12:46:42 PM PDT 24	21957142 ps
T780	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1797144122	May 30 12:46:39 PM PDT 24	May 30 12:47:18 PM PDT 24	6154302555 ps
T781	/workspace/coverage/xbar_build_mode/48.xbar_random.190656098	May 30 12:47:35 PM PDT 24	May 30 12:47:40 PM PDT 24	29079789 ps
T782	/workspace/coverage/xbar_build_mode/39.xbar_random.2539610730	May 30 12:46:47 PM PDT 24	May 30 12:46:53 PM PDT 24	60586191 ps
T783	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.634709591	May 30 12:44:43 PM PDT 24	May 30 12:44:55 PM PDT 24	3148287680 ps
T784	/workspace/coverage/xbar_build_mode/17.xbar_same_source.1202872207	May 30 12:45:32 PM PDT 24	May 30 12:45:43 PM PDT 24	1463461345 ps
T785	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3512614471	May 30 12:45:43 PM PDT 24	May 30 12:46:56 PM PDT 24	41594503034 ps
T786	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1813918561	May 30 12:46:03 PM PDT 24	May 30 12:46:11 PM PDT 24	2140562148 ps
T787	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2860025246	May 30 12:44:43 PM PDT 24	May 30 12:44:54 PM PDT 24	660230499 ps
T788	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1469333877	May 30 12:47:37 PM PDT 24	May 30 12:47:48 PM PDT 24	1260616623 ps
T789	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3884048975	May 30 12:44:44 PM PDT 24	May 30 12:45:21 PM PDT 24	506198968 ps
T790	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1438536412	May 30 12:44:45 PM PDT 24	May 30 12:46:48 PM PDT 24	1609373432 ps
T791	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.546320296	May 30 12:46:39 PM PDT 24	May 30 12:47:03 PM PDT 24	1176133033 ps
T792	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2799517375	May 30 12:44:42 PM PDT 24	May 30 12:44:48 PM PDT 24	50129130 ps
T793	/workspace/coverage/xbar_build_mode/14.xbar_smoke.2461982668	May 30 12:45:27 PM PDT 24	May 30 12:45:30 PM PDT 24	203715340 ps
T794	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1690785807	May 30 12:44:40 PM PDT 24	May 30 12:44:47 PM PDT 24	2052416755 ps
T795	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.609714920	May 30 12:45:35 PM PDT 24	May 30 12:45:39 PM PDT 24	103846400 ps
T796	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1956570336	May 30 12:46:24 PM PDT 24	May 30 12:46:34 PM PDT 24	623459970 ps
T797	/workspace/coverage/xbar_build_mode/5.xbar_same_source.2701689460	May 30 12:44:51 PM PDT 24	May 30 12:45:03 PM PDT 24	850940419 ps
T798	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.658484989	May 30 12:44:51 PM PDT 24	May 30 12:44:57 PM PDT 24	203267980 ps
T799	/workspace/coverage/xbar_build_mode/25.xbar_random.1909601771	May 30 12:45:53 PM PDT 24	May 30 12:46:00 PM PDT 24	161824855 ps
T800	/workspace/coverage/xbar_build_mode/18.xbar_smoke.702325692	May 30 12:45:36 PM PDT 24	May 30 12:45:38 PM PDT 24	23688566 ps
T801	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3628683013	May 30 12:46:58 PM PDT 24	May 30 12:47:35 PM PDT 24	5593114893 ps
T802	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2024946783	May 30 12:45:32 PM PDT 24	May 30 12:45:38 PM PDT 24	309993743 ps
T803	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.660183452	May 30 12:45:48 PM PDT 24	May 30 12:45:58 PM PDT 24	13460325767 ps
T804	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.460837840	May 30 12:46:32 PM PDT 24	May 30 12:46:44 PM PDT 24	1237492302 ps
T805	/workspace/coverage/xbar_build_mode/10.xbar_smoke.3550366793	May 30 12:45:25 PM PDT 24	May 30 12:45:27 PM PDT 24	13325160 ps
T806	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2213439298	May 30 12:44:40 PM PDT 24	May 30 12:44:45 PM PDT 24	420131075 ps
T807	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.309609816	May 30 12:46:51 PM PDT 24	May 30 12:47:02 PM PDT 24	66119263 ps
T808	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.1047608328	May 30 12:45:42 PM PDT 24	May 30 12:46:49 PM PDT 24	7028352705 ps
T809	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3248580480	May 30 12:45:30 PM PDT 24	May 30 12:48:00 PM PDT 24	128961328598 ps
T810	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.768648436	May 30 12:45:27 PM PDT 24	May 30 12:46:51 PM PDT 24	24092116117 ps
T811	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.402274568	May 30 12:45:54 PM PDT 24	May 30 12:46:08 PM PDT 24	2318188995 ps
T812	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.967113643	May 30 12:46:04 PM PDT 24	May 30 12:46:15 PM PDT 24	6181095497 ps
T813	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1431341684	May 30 12:44:43 PM PDT 24	May 30 12:44:52 PM PDT 24	88719545 ps
T814	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.3087972362	May 30 12:45:30 PM PDT 24	May 30 12:45:45 PM PDT 24	443458133 ps
T815	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1736452357	May 30 12:47:36 PM PDT 24	May 30 12:47:37 PM PDT 24	7032641 ps
T816	/workspace/coverage/xbar_build_mode/37.xbar_random.4071071366	May 30 12:46:47 PM PDT 24	May 30 12:46:55 PM PDT 24	322364162 ps
T817	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2825758752	May 30 12:46:55 PM PDT 24	May 30 12:47:23 PM PDT 24	181794670 ps
T818	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3166984794	May 30 12:46:21 PM PDT 24	May 30 12:46:31 PM PDT 24	3613749937 ps
T819	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1818889822	May 30 12:45:51 PM PDT 24	May 30 12:46:02 PM PDT 24	7445186355 ps
T820	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1450604639	May 30 12:46:48 PM PDT 24	May 30 12:46:57 PM PDT 24	2409890632 ps
T161	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.2707737719	May 30 12:47:39 PM PDT 24	May 30 12:48:06 PM PDT 24	2912106654 ps
T821	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2977994141	May 30 12:45:27 PM PDT 24	May 30 12:48:09 PM PDT 24	55345766423 ps
T822	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2430684522	May 30 12:46:56 PM PDT 24	May 30 12:47:02 PM PDT 24	120191849 ps
T119	/workspace/coverage/xbar_build_mode/46.xbar_random.1622032223	May 30 12:47:11 PM PDT 24	May 30 12:47:26 PM PDT 24	4088586478 ps
T170	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.3618327382	May 30 12:45:23 PM PDT 24	May 30 12:46:43 PM PDT 24	4809239682 ps
T215	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.821230743	May 30 12:46:21 PM PDT 24	May 30 12:51:29 PM PDT 24	70587316201 ps
T823	/workspace/coverage/xbar_build_mode/12.xbar_same_source.1760076899	May 30 12:45:29 PM PDT 24	May 30 12:45:35 PM PDT 24	266554405 ps
T824	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3077019591	May 30 12:45:42 PM PDT 24	May 30 12:49:56 PM PDT 24	108570298440 ps
T825	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2300598676	May 30 12:46:49 PM PDT 24	May 30 12:47:57 PM PDT 24	2108311748 ps
T826	/workspace/coverage/xbar_build_mode/47.xbar_random.3008730636	May 30 12:47:36 PM PDT 24	May 30 12:47:44 PM PDT 24	2155055255 ps
T827	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1472350250	May 30 12:46:37 PM PDT 24	May 30 12:47:20 PM PDT 24	637712450 ps
T828	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.792808283	May 30 12:44:53 PM PDT 24	May 30 12:45:03 PM PDT 24	571764430 ps
T829	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3662511695	May 30 12:44:51 PM PDT 24	May 30 12:45:17 PM PDT 24	2857508686 ps
T830	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3079170046	May 30 12:47:09 PM PDT 24	May 30 12:47:12 PM PDT 24	8472059 ps
T831	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1982843169	May 30 12:47:35 PM PDT 24	May 30 12:47:53 PM PDT 24	1170648158 ps
T832	/workspace/coverage/xbar_build_mode/3.xbar_error_random.1514377453	May 30 12:44:42 PM PDT 24	May 30 12:44:50 PM PDT 24	66871958 ps
T833	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3853553834	May 30 12:46:35 PM PDT 24	May 30 12:47:33 PM PDT 24	15431728239 ps
T834	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1233830119	May 30 12:45:46 PM PDT 24	May 30 12:47:41 PM PDT 24	4378434300 ps
T835	/workspace/coverage/xbar_build_mode/12.xbar_random.2303498534	May 30 12:45:26 PM PDT 24	May 30 12:45:31 PM PDT 24	246097745 ps
T836	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1587753364	May 30 12:47:09 PM PDT 24	May 30 12:47:27 PM PDT 24	4359867812 ps
T837	/workspace/coverage/xbar_build_mode/6.xbar_random.1724387732	May 30 12:44:52 PM PDT 24	May 30 12:45:01 PM PDT 24	79387556 ps
T838	/workspace/coverage/xbar_build_mode/30.xbar_random.3332107992	May 30 12:46:21 PM PDT 24	May 30 12:46:25 PM PDT 24	100023812 ps
T839	/workspace/coverage/xbar_build_mode/29.xbar_same_source.1059794876	May 30 12:46:21 PM PDT 24	May 30 12:46:35 PM PDT 24	862027908 ps
T840	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2638122815	May 30 12:44:40 PM PDT 24	May 30 12:46:06 PM PDT 24	21332614611 ps
T841	/workspace/coverage/xbar_build_mode/41.xbar_error_random.1271527222	May 30 12:47:02 PM PDT 24	May 30 12:47:17 PM PDT 24	1162466076 ps
T842	/workspace/coverage/xbar_build_mode/0.xbar_error_random.2615477416	May 30 12:44:28 PM PDT 24	May 30 12:44:33 PM PDT 24	199741826 ps
T843	/workspace/coverage/xbar_build_mode/43.xbar_same_source.3314382975	May 30 12:47:11 PM PDT 24	May 30 12:47:13 PM PDT 24	19917248 ps
T844	/workspace/coverage/xbar_build_mode/4.xbar_error_random.2783898152	May 30 12:44:45 PM PDT 24	May 30 12:44:53 PM PDT 24	589067909 ps
T845	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1339974465	May 30 12:45:20 PM PDT 24	May 30 12:46:46 PM PDT 24	10434068443 ps
T846	/workspace/coverage/xbar_build_mode/33.xbar_same_source.466194295	May 30 12:46:33 PM PDT 24	May 30 12:46:38 PM PDT 24	245984193 ps
T847	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2525798106	May 30 12:46:49 PM PDT 24	May 30 12:47:07 PM PDT 24	11018401116 ps
T848	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2548428170	May 30 12:46:55 PM PDT 24	May 30 12:47:34 PM PDT 24	3035493806 ps
T849	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.483596058	May 30 12:46:48 PM PDT 24	May 30 12:48:00 PM PDT 24	307752888 ps
T850	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2814639197	May 30 12:44:50 PM PDT 24	May 30 12:44:52 PM PDT 24	11876341 ps
T851	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1437725565	May 30 12:46:50 PM PDT 24	May 30 12:49:07 PM PDT 24	23888790150 ps
T852	/workspace/coverage/xbar_build_mode/26.xbar_smoke.378517364	May 30 12:46:04 PM PDT 24	May 30 12:46:07 PM PDT 24	125959040 ps
T853	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2869650808	May 30 12:45:32 PM PDT 24	May 30 12:46:46 PM PDT 24	10192846840 ps
T854	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.977344669	May 30 12:44:41 PM PDT 24	May 30 12:46:52 PM PDT 24	49363172233 ps
T855	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.218443392	May 30 12:45:22 PM PDT 24	May 30 12:45:24 PM PDT 24	14243023 ps
T856	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1906002353	May 30 12:46:45 PM PDT 24	May 30 12:46:47 PM PDT 24	9836910 ps
T857	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1467083801	May 30 12:46:37 PM PDT 24	May 30 12:47:51 PM PDT 24	3411180379 ps
T178	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2539652266	May 30 12:44:51 PM PDT 24	May 30 12:44:55 PM PDT 24	132819220 ps
T120	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.978734035	May 30 12:44:31 PM PDT 24	May 30 12:47:30 PM PDT 24	37213060169 ps
T858	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.529950408	May 30 12:44:52 PM PDT 24	May 30 12:45:01 PM PDT 24	441643552 ps
T859	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.308376535	May 30 12:46:31 PM PDT 24	May 30 12:48:53 PM PDT 24	9615415329 ps
T860	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.983884121	May 30 12:47:09 PM PDT 24	May 30 12:48:27 PM PDT 24	2476647997 ps
T861	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2778430150	May 30 12:46:36 PM PDT 24	May 30 12:46:46 PM PDT 24	6153276723 ps
T862	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1733786349	May 30 12:46:37 PM PDT 24	May 30 12:47:03 PM PDT 24	1014793623 ps
T863	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.58579411	May 30 12:47:34 PM PDT 24	May 30 12:47:41 PM PDT 24	1229958583 ps
T864	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2236194862	May 30 12:46:38 PM PDT 24	May 30 12:46:47 PM PDT 24	666077204 ps
T865	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3894819257	May 30 12:45:30 PM PDT 24	May 30 12:47:44 PM PDT 24	58836532882 ps
T866	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.905544172	May 30 12:46:04 PM PDT 24	May 30 12:48:48 PM PDT 24	33284022426 ps
T867	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3240614204	May 30 12:46:21 PM PDT 24	May 30 12:46:24 PM PDT 24	37440796 ps
T868	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.364057481	May 30 12:45:53 PM PDT 24	May 30 12:46:05 PM PDT 24	1786508763 ps
T869	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2722729788	May 30 12:44:26 PM PDT 24	May 30 12:44:30 PM PDT 24	25140470 ps
T870	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2175718082	May 30 12:46:23 PM PDT 24	May 30 12:46:59 PM PDT 24	465016171 ps
T871	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3518358259	May 30 12:46:22 PM PDT 24	May 30 12:48:55 PM PDT 24	21503992843 ps
T872	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3571685378	May 30 12:46:44 PM PDT 24	May 30 12:46:47 PM PDT 24	312122332 ps
T873	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.174660769	May 30 12:45:46 PM PDT 24	May 30 12:47:27 PM PDT 24	83616994601 ps
T874	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.791430709	May 30 12:46:20 PM PDT 24	May 30 12:49:02 PM PDT 24	80313739947 ps
T875	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1342883628	May 30 12:44:44 PM PDT 24	May 30 12:47:21 PM PDT 24	34925901404 ps
T876	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3866270418	May 30 12:46:20 PM PDT 24	May 30 12:46:29 PM PDT 24	536542013 ps
T877	/workspace/coverage/xbar_build_mode/46.xbar_smoke.2253273752	May 30 12:47:13 PM PDT 24	May 30 12:47:15 PM PDT 24	199274264 ps
T878	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.23314016	May 30 12:45:55 PM PDT 24	May 30 12:45:58 PM PDT 24	65829412 ps
T879	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2560410951	May 30 12:46:03 PM PDT 24	May 30 12:46:50 PM PDT 24	316403045 ps
T880	/workspace/coverage/xbar_build_mode/23.xbar_same_source.3168810629	May 30 12:46:02 PM PDT 24	May 30 12:46:07 PM PDT 24	56253532 ps
T881	/workspace/coverage/xbar_build_mode/31.xbar_random.1812306691	May 30 12:46:24 PM PDT 24	May 30 12:46:32 PM PDT 24	133956614 ps
T882	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.843571632	May 30 12:45:53 PM PDT 24	May 30 12:45:57 PM PDT 24	28733693 ps
T883	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.441950869	May 30 12:44:41 PM PDT 24	May 30 12:44:46 PM PDT 24	36967335 ps
T884	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4277653000	May 30 12:46:21 PM PDT 24	May 30 12:46:52 PM PDT 24	2558832265 ps
T885	/workspace/coverage/xbar_build_mode/24.xbar_error_random.2329611955	May 30 12:46:02 PM PDT 24	May 30 12:46:10 PM PDT 24	820846161 ps
T886	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1461701023	May 30 12:47:01 PM PDT 24	May 30 12:47:07 PM PDT 24	54040754 ps
T887	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2426584555	May 30 12:46:36 PM PDT 24	May 30 12:46:39 PM PDT 24	88560761 ps
T888	/workspace/coverage/xbar_build_mode/13.xbar_same_source.1025975772	May 30 12:45:31 PM PDT 24	May 30 12:45:37 PM PDT 24	416949165 ps
T889	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1149458234	May 30 12:46:50 PM PDT 24	May 30 12:47:14 PM PDT 24	3298021391 ps
T890	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1885225427	May 30 12:46:21 PM PDT 24	May 30 12:46:28 PM PDT 24	1177290545 ps
T891	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3380331126	May 30 12:46:46 PM PDT 24	May 30 12:46:51 PM PDT 24	37469171 ps
T892	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.301789445	May 30 12:44:53 PM PDT 24	May 30 12:45:22 PM PDT 24	2410803236 ps
T893	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.812481213	May 30 12:44:53 PM PDT 24	May 30 12:45:04 PM PDT 24	61081067 ps
T894	/workspace/coverage/xbar_build_mode/26.xbar_error_random.2507476860	May 30 12:46:19 PM PDT 24	May 30 12:46:25 PM PDT 24	710299592 ps
T895	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1046946286	May 30 12:45:34 PM PDT 24	May 30 12:49:30 PM PDT 24	9778113447 ps
T896	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3927136252	May 30 12:45:35 PM PDT 24	May 30 12:45:39 PM PDT 24	14900426 ps
T897	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2326373999	May 30 12:45:32 PM PDT 24	May 30 12:45:37 PM PDT 24	22193866 ps
T898	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.1509759166	May 30 12:46:21 PM PDT 24	May 30 12:47:02 PM PDT 24	435054975 ps
T899	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2151759753	May 30 12:45:21 PM PDT 24	May 30 12:45:27 PM PDT 24	1089926038 ps
T900	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.954068149	May 30 12:45:26 PM PDT 24	May 30 12:45:44 PM PDT 24	1115542365 ps

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2506798641
Short name	T4
Test name
Test status
Simulation time	15955024338 ps
CPU time	82.61 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:48:35 PM PDT 24
Peak memory	203228 kb
Host	smart-3e2c9f30-918c-4de6-824f-5c832b96aeac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2506798641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2506798641
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1133270599
Short name	T201
Test name
Test status
Simulation time	207030029417 ps
CPU time	330.11 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:51:54 PM PDT 24
Peak memory	203092 kb
Host	smart-0293dc93-3c11-4d5e-971c-9130b234389a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1133270599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.1133270599
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3197405982
Short name	T173
Test name
Test status
Simulation time	152233142601 ps
CPU time	268.23 seconds
Started	May 30 12:46:00 PM PDT 24
Finished	May 30 12:50:29 PM PDT 24
Peak memory	203072 kb
Host	smart-fee82d96-f259-4acf-9770-09b85f468294
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3197405982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.3197405982
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.639539246
Short name	T95
Test name
Test status
Simulation time	50645763637 ps
CPU time	327.34 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:51:09 PM PDT 24
Peak memory	204816 kb
Host	smart-80162771-c641-4ded-b938-5bdfeb4f58e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=639539246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.639539246
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4102094547
Short name	T687
Test name
Test status
Simulation time	187371744618 ps
CPU time	315.73 seconds
Started	May 30 12:45:25 PM PDT 24
Finished	May 30 12:50:42 PM PDT 24
Peak memory	205160 kb
Host	smart-a7ae0768-9a07-41cb-916b-9641343f5b4f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4102094547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.4102094547
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.753131521
Short name	T35
Test name
Test status
Simulation time	71567829917 ps
CPU time	96.76 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:48:01 PM PDT 24
Peak memory	201972 kb
Host	smart-e0e2d195-ab42-496b-81eb-41f0c123b458
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=753131521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.753131521
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.3316272514
Short name	T24
Test name
Test status
Simulation time	79657236 ps
CPU time	5.37 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:32 PM PDT 24
Peak memory	202008 kb
Host	smart-eb67f160-d58d-40ad-a5d0-9c4e72df1c70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316272514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3316272514
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3978263760
Short name	T28
Test name
Test status
Simulation time	203252932898 ps
CPU time	388.26 seconds
Started	May 30 12:47:39 PM PDT 24
Finished	May 30 12:54:08 PM PDT 24
Peak memory	205168 kb
Host	smart-a54a5fa3-29ba-45ee-aea7-95456a7be7a9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3978263760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.3978263760
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.821230743
Short name	T215
Test name
Test status
Simulation time	70587316201 ps
CPU time	305.92 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:51:29 PM PDT 24
Peak memory	203728 kb
Host	smart-cb11fed3-75b3-4f55-a144-bccc837f634c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=821230743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.821230743
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.4177210741
Short name	T62
Test name
Test status
Simulation time	8990805805 ps
CPU time	127.03 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:47:34 PM PDT 24
Peak memory	204944 kb
Host	smart-395b2e5c-b74a-42e7-a990-c39e0677b905
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4177210741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.4177210741
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2041406010
Short name	T110
Test name
Test status
Simulation time	52421125844 ps
CPU time	391.43 seconds
Started	May 30 12:45:25 PM PDT 24
Finished	May 30 12:51:58 PM PDT 24
Peak memory	203104 kb
Host	smart-adee52b4-20a3-4582-be3c-6dd7a3b6d4ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2041406010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2041406010
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1092920764
Short name	T12
Test name
Test status
Simulation time	4057896431 ps
CPU time	190.71 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:48:44 PM PDT 24
Peak memory	208840 kb
Host	smart-cb69b8ee-da2d-4360-8899-bee92feb5349
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092920764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1092920764
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1725135188
Short name	T9
Test name
Test status
Simulation time	288740344 ps
CPU time	82.87 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	204724 kb
Host	smart-a74a3b79-4c82-4972-aaa0-af74675b5153
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1725135188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.1725135188
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2533403728
Short name	T69
Test name
Test status
Simulation time	108029932802 ps
CPU time	125.11 seconds
Started	May 30 12:47:41 PM PDT 24
Finished	May 30 12:49:47 PM PDT 24
Peak memory	202044 kb
Host	smart-ab867e3c-2219-4576-9e5f-30a39f957b72
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533403728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2533403728
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3409246353
Short name	T81
Test name
Test status
Simulation time	137013081847 ps
CPU time	241.72 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:51:05 PM PDT 24
Peak memory	203504 kb
Host	smart-8f011364-286f-4350-ba83-6ddcc7b8d781
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3409246353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3409246353
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2543639164
Short name	T56
Test name
Test status
Simulation time	453997573 ps
CPU time	75.33 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:47:50 PM PDT 24
Peak memory	204216 kb
Host	smart-494aa76f-892d-44e9-a331-f5de109963d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2543639164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2543639164
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1927298527
Short name	T96
Test name
Test status
Simulation time	32184173894 ps
CPU time	246.62 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:49:00 PM PDT 24
Peak memory	204024 kb
Host	smart-27419aa8-937a-463c-a65b-e68c737b4c6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1927298527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1927298527
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3518358259
Short name	T871
Test name
Test status
Simulation time	21503992843 ps
CPU time	152.33 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:48:55 PM PDT 24
Peak memory	202764 kb
Host	smart-c8d3fa93-c807-4b06-ab5a-2f30cea49366
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3518358259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3518358259
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.572010207
Short name	T584
Test name
Test status
Simulation time	963250361 ps
CPU time	133.58 seconds
Started	May 30 12:44:31 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	205488 kb
Host	smart-82cc0ae6-3d01-4617-b9cf-76c749db1bfe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572010207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_ reset.572010207
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3881408347
Short name	T230
Test name
Test status
Simulation time	6369648150 ps
CPU time	106.77 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:46:28 PM PDT 24
Peak memory	206404 kb
Host	smart-4c417e7d-a719-4183-8cc4-d7fd327382da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3881408347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3881408347
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.3913039924
Short name	T88
Test name
Test status
Simulation time	6043094361 ps
CPU time	93.36 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:47:18 PM PDT 24
Peak memory	203104 kb
Host	smart-a52293a4-dd8a-49ce-a442-224c48cb88e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3913039924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3913039924
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3762564179
Short name	T485
Test name
Test status
Simulation time	528987752 ps
CPU time	59.08 seconds
Started	May 30 12:44:29 PM PDT 24
Finished	May 30 12:45:29 PM PDT 24
Peak memory	204168 kb
Host	smart-d99a0c47-05a4-425c-892c-0b428235fa51
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3762564179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3762564179
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2472880169
Short name	T585
Test name
Test status
Simulation time	277794704 ps
CPU time	56.35 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:46:20 PM PDT 24
Peak memory	204192 kb
Host	smart-7af185c4-9e7f-461e-91a1-73056fae113f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2472880169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2472880169
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3836576911
Short name	T455
Test name
Test status
Simulation time	29514680 ps
CPU time	5.79 seconds
Started	May 30 12:44:30 PM PDT 24
Finished	May 30 12:44:36 PM PDT 24
Peak memory	201900 kb
Host	smart-81e04ef8-9157-48e9-8b6a-f677b8d75b67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3836576911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3836576911
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2453003919
Short name	T200
Test name
Test status
Simulation time	3604032519 ps
CPU time	21.78 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:49 PM PDT 24
Peak memory	202076 kb
Host	smart-f7a4241a-dc92-4d56-ad01-2eadcc9e8a0b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2453003919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2453003919
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3271211306
Short name	T703
Test name
Test status
Simulation time	68053359 ps
CPU time	1.65 seconds
Started	May 30 12:44:30 PM PDT 24
Finished	May 30 12:44:32 PM PDT 24
Peak memory	202004 kb
Host	smart-d5ea45f8-99d5-4d5c-8ba4-4aa2bbce60db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3271211306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3271211306
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.2615477416
Short name	T842
Test name
Test status
Simulation time	199741826 ps
CPU time	3.29 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:33 PM PDT 24
Peak memory	201892 kb
Host	smart-20cd4f53-2078-4b16-983a-474cbda33017
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2615477416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2615477416
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.3157886993
Short name	T273
Test name
Test status
Simulation time	135011463 ps
CPU time	6.74 seconds
Started	May 30 12:44:26 PM PDT 24
Finished	May 30 12:44:34 PM PDT 24
Peak memory	201984 kb
Host	smart-c4eb47b6-6f15-44ba-afc5-b4594f79dafd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157886993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3157886993
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3659669001
Short name	T48
Test name
Test status
Simulation time	55135962375 ps
CPU time	81.8 seconds
Started	May 30 12:44:25 PM PDT 24
Finished	May 30 12:45:47 PM PDT 24
Peak memory	202060 kb
Host	smart-12004736-e4e4-42bb-bd97-b65657a63c05
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659669001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3659669001
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.978734035
Short name	T120
Test name
Test status
Simulation time	37213060169 ps
CPU time	178.26 seconds
Started	May 30 12:44:31 PM PDT 24
Finished	May 30 12:47:30 PM PDT 24
Peak memory	201984 kb
Host	smart-6ff9803b-559f-446f-a483-af38ba5c1bd2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=978734035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.978734035
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3982999182
Short name	T341
Test name
Test status
Simulation time	116855354 ps
CPU time	6.79 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:35 PM PDT 24
Peak memory	201948 kb
Host	smart-20b2a731-a31f-4c11-a7ba-a74b84d69c3c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982999182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3982999182
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2081054793
Short name	T271
Test name
Test status
Simulation time	70984735 ps
CPU time	4.41 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:32 PM PDT 24
Peak memory	202004 kb
Host	smart-0d0994a6-12ae-4526-8234-e1a5d344d872
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2081054793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2081054793
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.915598974
Short name	T543
Test name
Test status
Simulation time	121903754 ps
CPU time	1.34 seconds
Started	May 30 12:44:32 PM PDT 24
Finished	May 30 12:44:34 PM PDT 24
Peak memory	201744 kb
Host	smart-22d431b3-f43f-4c69-a269-9df0354f507f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915598974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.915598974
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.691857849
Short name	T323
Test name
Test status
Simulation time	2435311485 ps
CPU time	10.72 seconds
Started	May 30 12:44:26 PM PDT 24
Finished	May 30 12:44:38 PM PDT 24
Peak memory	202072 kb
Host	smart-8e45966e-bafc-41e3-a3fc-6cb20c283535
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=691857849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.691857849
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2899069152
Short name	T392
Test name
Test status
Simulation time	2962441262 ps
CPU time	13.43 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:42 PM PDT 24
Peak memory	202008 kb
Host	smart-24e4838b-fe8a-47ac-992d-4bc318c6cabc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2899069152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2899069152
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3855869225
Short name	T686
Test name
Test status
Simulation time	27556645 ps
CPU time	1.14 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:30 PM PDT 24
Peak memory	201904 kb
Host	smart-fa1adf5c-e17e-45fa-9856-7e6904a86dd1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855869225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3855869225
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.1568449604
Short name	T684
Test name
Test status
Simulation time	1934170552 ps
CPU time	23.02 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201892 kb
Host	smart-16a0a515-052c-4015-a491-b6b5094b19d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1568449604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1568449604
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3586991808
Short name	T768
Test name
Test status
Simulation time	3406440830 ps
CPU time	55.24 seconds
Started	May 30 12:44:29 PM PDT 24
Finished	May 30 12:45:25 PM PDT 24
Peak memory	202128 kb
Host	smart-89cf1cae-b74e-43a6-9190-c780699b73aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3586991808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3586991808
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2558820801
Short name	T514
Test name
Test status
Simulation time	72177033 ps
CPU time	2.13 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:31 PM PDT 24
Peak memory	201980 kb
Host	smart-df277202-32c0-4470-aeb6-4f28125ad60a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2558820801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2558820801
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1623805164
Short name	T290
Test name
Test status
Simulation time	73359049 ps
CPU time	12.93 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:41 PM PDT 24
Peak memory	201992 kb
Host	smart-14dae8f4-2597-40b3-bce3-0cab66872f7a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1623805164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1623805164
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.856954466
Short name	T199
Test name
Test status
Simulation time	131941622338 ps
CPU time	246.21 seconds
Started	May 30 12:44:31 PM PDT 24
Finished	May 30 12:48:38 PM PDT 24
Peak memory	203344 kb
Host	smart-6e123b68-ad24-4d31-902b-47b6d8b4561a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=856954466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.856954466
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.910821457
Short name	T640
Test name
Test status
Simulation time	327648371 ps
CPU time	5.35 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:33 PM PDT 24
Peak memory	201928 kb
Host	smart-832d6dc8-357a-4aff-bea7-a81fd389e740
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=910821457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.910821457
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.548037566
Short name	T383
Test name
Test status
Simulation time	480597983 ps
CPU time	6.02 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:35 PM PDT 24
Peak memory	202040 kb
Host	smart-ffa31690-1931-4533-8d1b-5ccf5f226153
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=548037566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.548037566
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.4054519078
Short name	T87
Test name
Test status
Simulation time	876121837 ps
CPU time	11.54 seconds
Started	May 30 12:44:32 PM PDT 24
Finished	May 30 12:44:44 PM PDT 24
Peak memory	201732 kb
Host	smart-30a04ac9-8464-4c66-a978-7b81149ecbef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4054519078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.4054519078
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.282988885
Short name	T266
Test name
Test status
Simulation time	8326245305 ps
CPU time	16.01 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:46 PM PDT 24
Peak memory	201984 kb
Host	smart-5d6e51a8-5dfe-4b5c-bacb-483ff4b9cb2f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=282988885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.282988885
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3264080774
Short name	T627
Test name
Test status
Simulation time	20851345342 ps
CPU time	112.72 seconds
Started	May 30 12:44:31 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	202060 kb
Host	smart-961a3d81-5fb9-4fa5-b5bf-a5308dcaade5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3264080774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3264080774
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.970273268
Short name	T604
Test name
Test status
Simulation time	131099969 ps
CPU time	3.22 seconds
Started	May 30 12:44:30 PM PDT 24
Finished	May 30 12:44:34 PM PDT 24
Peak memory	201888 kb
Host	smart-f83a0042-01a0-4558-b2af-dae24f299ab4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970273268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.970273268
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.121323579
Short name	T665
Test name
Test status
Simulation time	70597734 ps
CPU time	1.47 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:31 PM PDT 24
Peak memory	201916 kb
Host	smart-4c1f00dc-f39e-4fd9-9f1c-84767f49da34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121323579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.121323579
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.4038835544
Short name	T441
Test name
Test status
Simulation time	7639108 ps
CPU time	1.02 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:44:29 PM PDT 24
Peak memory	202012 kb
Host	smart-90e4f5af-7ecf-49c0-9840-15b3d02f2956
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4038835544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4038835544
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3874336097
Short name	T235
Test name
Test status
Simulation time	20024031723 ps
CPU time	11.96 seconds
Started	May 30 12:44:25 PM PDT 24
Finished	May 30 12:44:38 PM PDT 24
Peak memory	202020 kb
Host	smart-0db1edf4-8980-4e70-8012-f972904cfc1a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874336097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3874336097
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2717292525
Short name	T97
Test name
Test status
Simulation time	1155618877 ps
CPU time	8.3 seconds
Started	May 30 12:44:30 PM PDT 24
Finished	May 30 12:44:39 PM PDT 24
Peak memory	201996 kb
Host	smart-5925f9ec-75c0-4a00-820d-40869c0abb73
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2717292525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2717292525
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.264002399
Short name	T623
Test name
Test status
Simulation time	10556148 ps
CPU time	1.12 seconds
Started	May 30 12:44:26 PM PDT 24
Finished	May 30 12:44:28 PM PDT 24
Peak memory	201980 kb
Host	smart-cba7a977-4755-4cd9-bdef-bccafb0ae827
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264002399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.264002399
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.3172629581
Short name	T735
Test name
Test status
Simulation time	1271175173 ps
CPU time	36.44 seconds
Started	May 30 12:44:27 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	203980 kb
Host	smart-1698d585-880b-4e8d-8813-94e78ea122c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3172629581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3172629581
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2743549747
Short name	T295
Test name
Test status
Simulation time	1405290461 ps
CPU time	18.23 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:45:01 PM PDT 24
Peak memory	201884 kb
Host	smart-4d60dfc4-56cb-47ea-b932-bee398d76bbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2743549747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2743549747
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2722729788
Short name	T869
Test name
Test status
Simulation time	25140470 ps
CPU time	2.86 seconds
Started	May 30 12:44:26 PM PDT 24
Finished	May 30 12:44:30 PM PDT 24
Peak memory	201972 kb
Host	smart-6cf19e28-dc92-444e-b449-b1c86d314e9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2722729788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2722729788
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1228916483
Short name	T449
Test name
Test status
Simulation time	10130630 ps
CPU time	1.02 seconds
Started	May 30 12:44:28 PM PDT 24
Finished	May 30 12:44:30 PM PDT 24
Peak memory	201960 kb
Host	smart-1bd81cba-b207-4aaa-98cf-20a262fa40e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228916483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1228916483
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3101171794
Short name	T668
Test name
Test status
Simulation time	39944770 ps
CPU time	3.6 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:45:26 PM PDT 24
Peak memory	201908 kb
Host	smart-06e2b469-81ce-479c-9830-09cebee11b31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3101171794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3101171794
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2626097436
Short name	T113
Test name
Test status
Simulation time	53108109370 ps
CPU time	323.79 seconds
Started	May 30 12:45:19 PM PDT 24
Finished	May 30 12:50:44 PM PDT 24
Peak memory	204048 kb
Host	smart-f1bee437-d579-4b93-ac4d-3059c0d38fc8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2626097436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2626097436
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2811644684
Short name	T305
Test name
Test status
Simulation time	540142459 ps
CPU time	5.2 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201980 kb
Host	smart-d920f40c-891b-4c42-bd41-6872f479ca1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811644684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2811644684
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.460647442
Short name	T677
Test name
Test status
Simulation time	58024574 ps
CPU time	6.23 seconds
Started	May 30 12:45:21 PM PDT 24
Finished	May 30 12:45:28 PM PDT 24
Peak memory	201944 kb
Host	smart-97e4d7e1-7247-4fd5-87d0-af98e1dc1085
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=460647442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.460647442
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.2291224617
Short name	T411
Test name
Test status
Simulation time	37012540 ps
CPU time	4.16 seconds
Started	May 30 12:45:24 PM PDT 24
Finished	May 30 12:45:29 PM PDT 24
Peak memory	201900 kb
Host	smart-74dcac07-0828-4af8-bcf7-cdfe45d21a00
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291224617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2291224617
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.528683230
Short name	T572
Test name
Test status
Simulation time	3650363887 ps
CPU time	11.09 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	202104 kb
Host	smart-527711c7-3c28-4de9-8345-084d66bce197
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=528683230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.528683230
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1413291562
Short name	T730
Test name
Test status
Simulation time	53609259473 ps
CPU time	74.78 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201980 kb
Host	smart-3cae8978-b094-429e-89ce-75e3ad342106
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1413291562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1413291562
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2367997813
Short name	T643
Test name
Test status
Simulation time	26651785 ps
CPU time	3.24 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:30 PM PDT 24
Peak memory	202008 kb
Host	smart-679636f2-62fc-4d9c-9423-9cfe998d0be8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367997813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2367997813
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.614163354
Short name	T452
Test name
Test status
Simulation time	130224407 ps
CPU time	5.1 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201992 kb
Host	smart-020dbe9f-c8bf-4de3-b6b6-7ff5a22aeb1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=614163354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.614163354
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.3550366793
Short name	T805
Test name
Test status
Simulation time	13325160 ps
CPU time	1.24 seconds
Started	May 30 12:45:25 PM PDT 24
Finished	May 30 12:45:27 PM PDT 24
Peak memory	201972 kb
Host	smart-f86999c4-fff0-469a-a0bb-db0ef6662cd1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550366793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3550366793
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.84161802
Short name	T675
Test name
Test status
Simulation time	2097929932 ps
CPU time	6.19 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	201928 kb
Host	smart-5e16d61e-a602-4505-9083-0265fe5a4ae8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=84161802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.84161802
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.851374651
Short name	T524
Test name
Test status
Simulation time	2891414901 ps
CPU time	7.66 seconds
Started	May 30 12:45:25 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	201988 kb
Host	smart-57c39ed0-11a6-409c-be70-27aa738ac70f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=851374651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.851374651
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.218443392
Short name	T855
Test name
Test status
Simulation time	14243023 ps
CPU time	1.11 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:45:24 PM PDT 24
Peak memory	201960 kb
Host	smart-47df27bb-2495-4ad7-8ba2-264232e7004b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218443392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.218443392
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.3618327382
Short name	T170
Test name
Test status
Simulation time	4809239682 ps
CPU time	78.67 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:46:43 PM PDT 24
Peak memory	205044 kb
Host	smart-35d163ed-1cf7-40a5-8c59-07acd3f5861c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3618327382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3618327382
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2987529853
Short name	T639
Test name
Test status
Simulation time	6895664956 ps
CPU time	60.75 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	202008 kb
Host	smart-8fbb4831-643b-4c21-891d-538f527ac75c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2987529853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2987529853
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1339974465
Short name	T845
Test name
Test status
Simulation time	10434068443 ps
CPU time	84.69 seconds
Started	May 30 12:45:20 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	205140 kb
Host	smart-b18d4d18-34a0-47af-97de-8234008e846b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1339974465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1339974465
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.606952490
Short name	T463
Test name
Test status
Simulation time	156921687 ps
CPU time	5.55 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201940 kb
Host	smart-237f1b49-9a82-431e-8171-034cca1b7bfc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=606952490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.606952490
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.954068149
Short name	T900
Test name
Test status
Simulation time	1115542365 ps
CPU time	15.91 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:44 PM PDT 24
Peak memory	202012 kb
Host	smart-f008c646-faad-4919-bec4-a535c2d98e85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=954068149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.954068149
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3574719963
Short name	T196
Test name
Test status
Simulation time	69241839555 ps
CPU time	332.46 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:50:56 PM PDT 24
Peak memory	204148 kb
Host	smart-af8c4c96-a5e9-4a7c-934d-980f467884cd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3574719963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3574719963
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4176689004
Short name	T632
Test name
Test status
Simulation time	1331150589 ps
CPU time	7.45 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:35 PM PDT 24
Peak memory	202016 kb
Host	smart-6aebaf01-6448-4781-920c-16ceffb8798d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176689004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4176689004
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.1198960148
Short name	T513
Test name
Test status
Simulation time	674696631 ps
CPU time	6.45 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	201996 kb
Host	smart-3b65b909-16cd-4066-b327-c01d99e6cd68
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1198960148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1198960148
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.20219899
Short name	T387
Test name
Test status
Simulation time	243442530 ps
CPU time	5.42 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:45:30 PM PDT 24
Peak memory	201920 kb
Host	smart-9a8a7742-b37a-485d-835e-0fe3028d9213
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20219899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.20219899
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2977994141
Short name	T821
Test name
Test status
Simulation time	55345766423 ps
CPU time	160.62 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:48:09 PM PDT 24
Peak memory	202076 kb
Host	smart-b8003008-f816-4685-b482-0513c9e138c5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977994141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2977994141
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3126947922
Short name	T650
Test name
Test status
Simulation time	41097367348 ps
CPU time	184.34 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:48:31 PM PDT 24
Peak memory	202052 kb
Host	smart-c99137a4-c39a-45ef-bfdd-20ed9c807070
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3126947922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3126947922
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2635393830
Short name	T429
Test name
Test status
Simulation time	58276622 ps
CPU time	2.3 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	201984 kb
Host	smart-85273a46-218b-439e-a267-58b4349c3fdf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635393830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2635393830
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.1151852052
Short name	T500
Test name
Test status
Simulation time	152361665 ps
CPU time	1.49 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201984 kb
Host	smart-9c11f45e-e010-4f68-9171-f883cfef1c4c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1151852052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1151852052
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2047787968
Short name	T589
Test name
Test status
Simulation time	1848749991 ps
CPU time	8.34 seconds
Started	May 30 12:45:24 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201916 kb
Host	smart-6d59a572-e092-4771-bc4b-4b9252638dc0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047787968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2047787968
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3348755112
Short name	T312
Test name
Test status
Simulation time	4605876752 ps
CPU time	7.1 seconds
Started	May 30 12:45:21 PM PDT 24
Finished	May 30 12:45:29 PM PDT 24
Peak memory	202068 kb
Host	smart-b0483924-07ae-43c9-a6ba-b227da8248a4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3348755112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3348755112
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.64385346
Short name	T655
Test name
Test status
Simulation time	10012978 ps
CPU time	1.25 seconds
Started	May 30 12:45:21 PM PDT 24
Finished	May 30 12:45:23 PM PDT 24
Peak memory	202036 kb
Host	smart-c0dd6f62-5f62-4258-98e2-14118309b37d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64385346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.64385346
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.1858343854
Short name	T202
Test name
Test status
Simulation time	4879772574 ps
CPU time	60.96 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:46:28 PM PDT 24
Peak memory	203084 kb
Host	smart-48556e73-3744-4216-a5b5-5199bae65f12
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1858343854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1858343854
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2896651171
Short name	T741
Test name
Test status
Simulation time	617029710 ps
CPU time	41.7 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:46:13 PM PDT 24
Peak memory	201980 kb
Host	smart-e4e6177f-28c7-49e4-a9a4-d4ef219073a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896651171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2896651171
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3372081911
Short name	T5
Test name
Test status
Simulation time	1295496192 ps
CPU time	116.86 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:47:25 PM PDT 24
Peak memory	206400 kb
Host	smart-2f0f612d-78bd-438b-b265-e1ff79128138
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372081911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3372081911
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2151759753
Short name	T899
Test name
Test status
Simulation time	1089926038 ps
CPU time	4.66 seconds
Started	May 30 12:45:21 PM PDT 24
Finished	May 30 12:45:27 PM PDT 24
Peak memory	201972 kb
Host	smart-b478ca5e-b679-46f6-ac71-6b8e271e0764
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2151759753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2151759753
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2510583281
Short name	T136
Test name
Test status
Simulation time	612413154 ps
CPU time	13.03 seconds
Started	May 30 12:45:28 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201932 kb
Host	smart-866a5d45-ad58-4cab-b6a0-47b8fcbd5abe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2510583281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2510583281
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2347493522
Short name	T381
Test name
Test status
Simulation time	37606955 ps
CPU time	3.28 seconds
Started	May 30 12:45:28 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201980 kb
Host	smart-410a550b-7ddc-4c70-b167-1a6e2ba322e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347493522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2347493522
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.1767059606
Short name	T94
Test name
Test status
Simulation time	1210851564 ps
CPU time	10.03 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201980 kb
Host	smart-6307cb58-5ff7-4021-aae7-c36dd7846afd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1767059606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1767059606
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.2303498534
Short name	T835
Test name
Test status
Simulation time	246097745 ps
CPU time	3.98 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	202004 kb
Host	smart-51878cb8-f464-48b8-bd6f-295360c50fcd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2303498534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2303498534
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3894819257
Short name	T865
Test name
Test status
Simulation time	58836532882 ps
CPU time	132.21 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	201956 kb
Host	smart-f43caeaa-6ee5-4ebc-b66a-2db6cb28bc5b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894819257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3894819257
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.76355115
Short name	T481
Test name
Test status
Simulation time	7398252268 ps
CPU time	51.35 seconds
Started	May 30 12:45:28 PM PDT 24
Finished	May 30 12:46:21 PM PDT 24
Peak memory	202052 kb
Host	smart-3bf33c47-5df7-4f2f-a2cc-39b4cdd71b10
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=76355115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.76355115
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2625275850
Short name	T389
Test name
Test status
Simulation time	21941498 ps
CPU time	2.9 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201916 kb
Host	smart-93ea5ac7-8af3-4ec7-97ca-5c3e124d71b3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625275850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2625275850
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.1760076899
Short name	T823
Test name
Test status
Simulation time	266554405 ps
CPU time	5.03 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:35 PM PDT 24
Peak memory	201928 kb
Host	smart-59f697a9-fdd8-451d-a4e2-9aa5296773fe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1760076899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1760076899
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.635195215
Short name	T304
Test name
Test status
Simulation time	41684142 ps
CPU time	1.26 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:29 PM PDT 24
Peak memory	202004 kb
Host	smart-e3d4207a-248c-4953-b38c-859b0940cf8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=635195215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.635195215
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2100344227
Short name	T73
Test name
Test status
Simulation time	3355955458 ps
CPU time	11.95 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	202072 kb
Host	smart-4168eab2-abd3-470c-ae63-c0cd28cc6785
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100344227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2100344227
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.378571074
Short name	T769
Test name
Test status
Simulation time	1404321023 ps
CPU time	6.26 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:35 PM PDT 24
Peak memory	201924 kb
Host	smart-b9f8097b-8482-4f86-9e7d-6b0fe377e2e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=378571074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.378571074
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.459526672
Short name	T352
Test name
Test status
Simulation time	19242121 ps
CPU time	1.16 seconds
Started	May 30 12:45:24 PM PDT 24
Finished	May 30 12:45:27 PM PDT 24
Peak memory	201908 kb
Host	smart-d4d57ad3-37cf-4406-9323-b1bb4ac7fce5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459526672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.459526672
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.1449685549
Short name	T457
Test name
Test status
Simulation time	73221043 ps
CPU time	6.25 seconds
Started	May 30 12:45:28 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201976 kb
Host	smart-f8d7e8e9-3791-4272-995c-9049bb0c68e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1449685549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1449685549
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3938090965
Short name	T334
Test name
Test status
Simulation time	970400399 ps
CPU time	25.15 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:54 PM PDT 24
Peak memory	201980 kb
Host	smart-97069921-2576-4cbc-ae86-7210265e8a16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938090965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3938090965
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1841140751
Short name	T722
Test name
Test status
Simulation time	7060847097 ps
CPU time	42.11 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:46:10 PM PDT 24
Peak memory	203700 kb
Host	smart-4bcc5588-5e17-448c-8d73-543e18724934
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841140751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.1841140751
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1017847745
Short name	T674
Test name
Test status
Simulation time	106159449 ps
CPU time	1.85 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:30 PM PDT 24
Peak memory	201988 kb
Host	smart-e259d68d-1321-41b2-9ee3-f9579c013ed2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017847745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1017847745
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2576465587
Short name	T669
Test name
Test status
Simulation time	11629092 ps
CPU time	1.41 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201948 kb
Host	smart-85412ce7-76b7-4ca5-b97f-5b3f5e8ab818
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2576465587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2576465587
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2558818712
Short name	T15
Test name
Test status
Simulation time	10431372321 ps
CPU time	39.33 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:46:12 PM PDT 24
Peak memory	202068 kb
Host	smart-79f5e4a5-8ece-458f-9119-22cf3b20c9c4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2558818712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2558818712
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.8337839
Short name	T766
Test name
Test status
Simulation time	36856447 ps
CPU time	3.64 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:38 PM PDT 24
Peak memory	201892 kb
Host	smart-19fe4fd2-ba7c-4df2-a3fd-a2605299d3b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=8337839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.8337839
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.3891884924
Short name	T274
Test name
Test status
Simulation time	864939086 ps
CPU time	13.41 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201980 kb
Host	smart-25b14946-9219-4d89-984c-881a80c0794b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3891884924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3891884924
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.1567983524
Short name	T528
Test name
Test status
Simulation time	15280545 ps
CPU time	1.17 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	201944 kb
Host	smart-eee382b8-7b64-44aa-bdf1-a8762b563537
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1567983524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1567983524
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.768648436
Short name	T810
Test name
Test status
Simulation time	24092116117 ps
CPU time	82.79 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201984 kb
Host	smart-8500e334-5ed6-49fb-9970-0b65214c9585
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=768648436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.768648436
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3248580480
Short name	T809
Test name
Test status
Simulation time	128961328598 ps
CPU time	148.02 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	201952 kb
Host	smart-93b028c2-7454-463a-93bb-71aec1202a99
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3248580480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3248580480
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3394694658
Short name	T151
Test name
Test status
Simulation time	53531709 ps
CPU time	2.29 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:30 PM PDT 24
Peak memory	201888 kb
Host	smart-3de68eda-71fb-4775-bfcf-4dceff46cdf8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394694658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3394694658
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.1025975772
Short name	T888
Test name
Test status
Simulation time	416949165 ps
CPU time	4.14 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201900 kb
Host	smart-030c3394-948d-4ffc-b674-407b83c01303
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1025975772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1025975772
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.1478265259
Short name	T616
Test name
Test status
Simulation time	62344503 ps
CPU time	1.46 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	202004 kb
Host	smart-c315a6ff-cb4a-4290-8532-1ddba3a4cab9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1478265259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1478265259
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3690069168
Short name	T454
Test name
Test status
Simulation time	1505651325 ps
CPU time	7.99 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	201944 kb
Host	smart-718c467a-1808-4506-9f3b-5a9f28ad8f3a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690069168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3690069168
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2959757366
Short name	T393
Test name
Test status
Simulation time	5574019458 ps
CPU time	7.17 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:45:35 PM PDT 24
Peak memory	201904 kb
Host	smart-a87d4ffe-8b4f-4351-81f0-ad5f865f9836
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2959757366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2959757366
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3597353859
Short name	T739
Test name
Test status
Simulation time	19205245 ps
CPU time	1.01 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201960 kb
Host	smart-abac6024-494f-421a-b7a7-ac06114b5e11
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597353859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3597353859
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.2077133353
Short name	T253
Test name
Test status
Simulation time	3440449566 ps
CPU time	16.35 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:49 PM PDT 24
Peak memory	202060 kb
Host	smart-d2c2dc2e-f809-4eba-b000-9ed64a2fd3d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2077133353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2077133353
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1885046498
Short name	T365
Test name
Test status
Simulation time	1890403358 ps
CPU time	22.49 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201976 kb
Host	smart-3d59a82d-9205-4fd4-a387-9b633e87f3bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1885046498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1885046498
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3845086967
Short name	T218
Test name
Test status
Simulation time	430997083 ps
CPU time	41.52 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	204136 kb
Host	smart-976a74bc-5c64-485c-8787-2ae76a415fe6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3845086967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3845086967
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1551455045
Short name	T732
Test name
Test status
Simulation time	9187190158 ps
CPU time	149.13 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	204228 kb
Host	smart-96e9db2a-45ff-4be0-b906-e3dd8b445b3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1551455045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1551455045
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2024946783
Short name	T802
Test name
Test status
Simulation time	309993743 ps
CPU time	3.51 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:45:38 PM PDT 24
Peak memory	201904 kb
Host	smart-78aa5043-251b-4b92-8786-3af737cf30f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2024946783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2024946783
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3410394609
Short name	T503
Test name
Test status
Simulation time	578063567 ps
CPU time	9.41 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:40 PM PDT 24
Peak memory	202004 kb
Host	smart-5d863f7e-dfed-4fae-ad38-4c04a66bd7db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3410394609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3410394609
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1815096488
Short name	T193
Test name
Test status
Simulation time	42777130278 ps
CPU time	134.67 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:47:46 PM PDT 24
Peak memory	203088 kb
Host	smart-4757469e-d7b4-409d-a897-9343161fd9f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1815096488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1815096488
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3957464065
Short name	T242
Test name
Test status
Simulation time	88337529 ps
CPU time	4.94 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:38 PM PDT 24
Peak memory	201884 kb
Host	smart-33c4b518-fcf0-4829-85f7-fc922251a992
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3957464065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3957464065
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.1289286704
Short name	T546
Test name
Test status
Simulation time	18866232 ps
CPU time	1.36 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201980 kb
Host	smart-eb57ea1e-934e-4195-9b6a-7be13cea596b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289286704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1289286704
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.2400313442
Short name	T713
Test name
Test status
Simulation time	19329894 ps
CPU time	3.16 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	201972 kb
Host	smart-a8b73e9c-f05d-4c20-b189-7ddd82698ce9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2400313442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2400313442
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2056136903
Short name	T508
Test name
Test status
Simulation time	196293718190 ps
CPU time	143.88 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:47:57 PM PDT 24
Peak memory	201972 kb
Host	smart-63d5ffe0-fbb2-409e-b567-34f0966c4145
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056136903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2056136903
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2869650808
Short name	T853
Test name
Test status
Simulation time	10192846840 ps
CPU time	71.5 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	202048 kb
Host	smart-33b5b24d-f323-424f-9385-a068d60a17cf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2869650808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2869650808
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2375436783
Short name	T662
Test name
Test status
Simulation time	89815502 ps
CPU time	9.42 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:45:45 PM PDT 24
Peak memory	201960 kb
Host	smart-2c00e9c6-9796-478e-b7c1-9ec27065e38e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375436783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2375436783
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.1161032727
Short name	T612
Test name
Test status
Simulation time	1013390122 ps
CPU time	11.19 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	201972 kb
Host	smart-2795e857-848a-4858-8f7b-79ce0c1cf815
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1161032727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1161032727
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.2461982668
Short name	T793
Test name
Test status
Simulation time	203715340 ps
CPU time	1.39 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:30 PM PDT 24
Peak memory	201916 kb
Host	smart-62a8bb55-49af-4fef-a0e5-a3affedff957
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2461982668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2461982668
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.453584228
Short name	T248
Test name
Test status
Simulation time	8746826132 ps
CPU time	12.45 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:44 PM PDT 24
Peak memory	202048 kb
Host	smart-651e6c24-00f6-4cd2-86ba-a046f5f31a4f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=453584228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.453584228
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.310024136
Short name	T424
Test name
Test status
Simulation time	3541765931 ps
CPU time	8.65 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	202052 kb
Host	smart-7f758dbb-b362-4043-8799-fe66512f3e83
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=310024136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.310024136
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4052677433
Short name	T418
Test name
Test status
Simulation time	9090519 ps
CPU time	1.11 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	202000 kb
Host	smart-477283d0-d230-414b-aef6-f11025be28d9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052677433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4052677433
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.3087972362
Short name	T814
Test name
Test status
Simulation time	443458133 ps
CPU time	12.79 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:45 PM PDT 24
Peak memory	201984 kb
Host	smart-a30d65db-442e-41cf-aaa0-1268ef326ee2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3087972362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3087972362
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3833184576
Short name	T717
Test name
Test status
Simulation time	1138736900 ps
CPU time	13.85 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	201896 kb
Host	smart-1c5e0358-4ad4-4e65-bd4e-3e8f3c35cb9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3833184576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3833184576
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2546643464
Short name	T220
Test name
Test status
Simulation time	391676189 ps
CPU time	86.31 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	205068 kb
Host	smart-07130520-0664-46e7-9955-dcd4958d41af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2546643464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.2546643464
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1046946286
Short name	T895
Test name
Test status
Simulation time	9778113447 ps
CPU time	233.37 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:49:30 PM PDT 24
Peak memory	210152 kb
Host	smart-8d3a903f-7a2d-48bb-abbf-e49ddb8bfcff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1046946286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.1046946286
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2821305540
Short name	T719
Test name
Test status
Simulation time	1148629767 ps
CPU time	12.77 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:47 PM PDT 24
Peak memory	202008 kb
Host	smart-7f1698da-f8c7-46c2-8d4c-88c5126eaf48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2821305540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2821305540
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1399418713
Short name	T347
Test name
Test status
Simulation time	126181899 ps
CPU time	10.35 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201892 kb
Host	smart-2a69511c-2e9d-4521-a5da-921ad0df2b0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399418713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1399418713
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.724864078
Short name	T195
Test name
Test status
Simulation time	27324268604 ps
CPU time	129.08 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:47:43 PM PDT 24
Peak memory	202076 kb
Host	smart-6f355ffb-11f9-4cf2-8fde-1c835876b7c8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=724864078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo w_rsp.724864078
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3174491318
Short name	T192
Test name
Test status
Simulation time	692926328 ps
CPU time	5.72 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	202008 kb
Host	smart-32b44176-d74a-4eb1-bde4-84bfd9886cea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3174491318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3174491318
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.3382601835
Short name	T599
Test name
Test status
Simulation time	20097465 ps
CPU time	1.73 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201960 kb
Host	smart-9476d212-fb0e-40c3-a94e-58ae38f2894a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3382601835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3382601835
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.206770633
Short name	T247
Test name
Test status
Simulation time	144728868 ps
CPU time	5.93 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	202012 kb
Host	smart-9500ea2c-eacc-484d-bec0-a9f46d58f1a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=206770633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.206770633
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2431918500
Short name	T44
Test name
Test status
Simulation time	69937563850 ps
CPU time	80.5 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	201976 kb
Host	smart-6c5d29fc-a27c-40cf-90fd-6c6b8ba4a5b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431918500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2431918500
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3990866567
Short name	T444
Test name
Test status
Simulation time	17555640682 ps
CPU time	37.51 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:46:11 PM PDT 24
Peak memory	202004 kb
Host	smart-68f25b99-a40f-44ad-ad8e-4d4aaa41ea51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3990866567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3990866567
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3894146495
Short name	T394
Test name
Test status
Simulation time	152527823 ps
CPU time	6.06 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:45:40 PM PDT 24
Peak memory	201960 kb
Host	smart-c4bb933e-615b-4f1c-81c4-ba6f7baec45e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894146495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3894146495
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.1979609398
Short name	T587
Test name
Test status
Simulation time	482508893 ps
CPU time	6.98 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201980 kb
Host	smart-13d381c6-37a9-400e-b8e8-a9cbe34a25cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1979609398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1979609398
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.3187653956
Short name	T333
Test name
Test status
Simulation time	11718632 ps
CPU time	1.21 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	201996 kb
Host	smart-cbd501b0-4bbf-467b-853d-04696af781ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3187653956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3187653956
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3340166841
Short name	T497
Test name
Test status
Simulation time	7486315159 ps
CPU time	9.04 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:40 PM PDT 24
Peak memory	202012 kb
Host	smart-92becf5b-cddd-4e4b-8811-1eb790bae314
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340166841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3340166841
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.474131714
Short name	T659
Test name
Test status
Simulation time	1709301700 ps
CPU time	11.63 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201996 kb
Host	smart-febd18e6-feea-4a07-b263-d506562543c7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=474131714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.474131714
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3109519019
Short name	T555
Test name
Test status
Simulation time	9238259 ps
CPU time	1 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201892 kb
Host	smart-6def76a0-587a-43f5-b916-b71fd2f61366
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109519019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3109519019
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.988395556
Short name	T348
Test name
Test status
Simulation time	5900952315 ps
CPU time	50.59 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	204784 kb
Host	smart-695b9ea5-5fba-4023-87d4-70d4ce9fca82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=988395556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.988395556
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.518196754
Short name	T536
Test name
Test status
Simulation time	161211749 ps
CPU time	9.03 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:42 PM PDT 24
Peak memory	201960 kb
Host	smart-7690c1c3-d7ca-430f-a583-d77caf1e303c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518196754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.518196754
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3457092021
Short name	T380
Test name
Test status
Simulation time	17915439 ps
CPU time	4.94 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201972 kb
Host	smart-bb7f2a46-3e7d-4bae-a125-a00daa019bf9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3457092021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3457092021
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3461451539
Short name	T466
Test name
Test status
Simulation time	292975481 ps
CPU time	24.74 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:46:00 PM PDT 24
Peak memory	203168 kb
Host	smart-6b0983cb-7389-43ed-a140-796859bc29dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3461451539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3461451539
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.4074500328
Short name	T600
Test name
Test status
Simulation time	488248542 ps
CPU time	5.16 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	201956 kb
Host	smart-236edb9d-abb5-43f0-a410-23fe3d8bd45a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4074500328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4074500328
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3304602911
Short name	T726
Test name
Test status
Simulation time	8603999 ps
CPU time	1.18 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201932 kb
Host	smart-18f73f92-c8b6-4de7-92f5-87fb30e4d3fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3304602911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3304602911
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.548226900
Short name	T109
Test name
Test status
Simulation time	38715300852 ps
CPU time	151.97 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:48:08 PM PDT 24
Peak memory	203016 kb
Host	smart-da851eba-5ed0-4ce0-b29f-d76adbeefeeb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=548226900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.548226900
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.641259779
Short name	T276
Test name
Test status
Simulation time	345462149 ps
CPU time	3.36 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201896 kb
Host	smart-ad9c3fa5-e112-44e2-afae-b5ed354d5f31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=641259779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.641259779
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.3798126301
Short name	T775
Test name
Test status
Simulation time	46226617 ps
CPU time	1.33 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201896 kb
Host	smart-53ac13ec-0453-480f-a6d7-d80dd6b86d8c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3798126301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3798126301
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.282354266
Short name	T560
Test name
Test status
Simulation time	197758117 ps
CPU time	1.58 seconds
Started	May 30 12:45:28 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	202008 kb
Host	smart-c9bf98d9-dfc7-43b6-881d-9b725fd92605
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=282354266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.282354266
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.480187866
Short name	T156
Test name
Test status
Simulation time	44780736515 ps
CPU time	40.22 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	202048 kb
Host	smart-f677e169-751e-4ec1-b9e7-d46d16e9bf79
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=480187866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.480187866
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3437987970
Short name	T767
Test name
Test status
Simulation time	13634160928 ps
CPU time	82.4 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:46:58 PM PDT 24
Peak memory	202080 kb
Host	smart-49731cf8-94bf-4566-9fc7-60b852d8c760
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3437987970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3437987970
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3488672406
Short name	T321
Test name
Test status
Simulation time	137368966 ps
CPU time	5.12 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201884 kb
Host	smart-587c055a-687f-43c0-bfc7-ce262ab53b46
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488672406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3488672406
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.1969947074
Short name	T163
Test name
Test status
Simulation time	430233275 ps
CPU time	1.53 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:42 PM PDT 24
Peak memory	201896 kb
Host	smart-4791be93-12d9-4f5b-92ea-0dd71d6af1e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1969947074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1969947074
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.2144312437
Short name	T628
Test name
Test status
Simulation time	74060040 ps
CPU time	1.7 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	201936 kb
Host	smart-0c4c745a-e4c5-4a15-9eee-f508e7517a91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2144312437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2144312437
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.309565372
Short name	T453
Test name
Test status
Simulation time	4432233115 ps
CPU time	6.71 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201972 kb
Host	smart-3baff72e-d084-4d0b-a86e-93d0d342ecc3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=309565372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.309565372
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1651375878
Short name	T688
Test name
Test status
Simulation time	751814995 ps
CPU time	5.5 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	201896 kb
Host	smart-a47f728e-2f8d-484f-9f33-69237e6e6a39
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1651375878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1651375878
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3938978690
Short name	T122
Test name
Test status
Simulation time	9235073 ps
CPU time	1.22 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201916 kb
Host	smart-bc0db681-dc33-4100-8753-632d0838890f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938978690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3938978690
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.1296312050
Short name	T346
Test name
Test status
Simulation time	783393140 ps
CPU time	18.66 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:56 PM PDT 24
Peak memory	201924 kb
Host	smart-b73098c1-0d03-468a-ad74-5d3f99f61647
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1296312050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1296312050
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3896788572
Short name	T491
Test name
Test status
Simulation time	911810114 ps
CPU time	16.02 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	201892 kb
Host	smart-97af7a11-7d82-47c9-97b6-c0498f7999ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3896788572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3896788572
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2676260435
Short name	T222
Test name
Test status
Simulation time	65458626 ps
CPU time	11.12 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201912 kb
Host	smart-52a7c633-7d15-4add-9ab9-536d5a19b021
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2676260435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.2676260435
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.238277346
Short name	T219
Test name
Test status
Simulation time	1103306201 ps
CPU time	145.82 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	206280 kb
Host	smart-2e3d4c2d-73c8-4afd-8679-5cda65c9eb26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=238277346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res et_error.238277346
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.301530272
Short name	T591
Test name
Test status
Simulation time	73735165 ps
CPU time	7.29 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	201884 kb
Host	smart-7b8883f2-a991-4812-88f3-b1cd118ea231
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=301530272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.301530272
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2326373999
Short name	T897
Test name
Test status
Simulation time	22193866 ps
CPU time	3.53 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201952 kb
Host	smart-3e0f99bf-c432-4399-ba14-7008d8644261
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2326373999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2326373999
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.389439563
Short name	T211
Test name
Test status
Simulation time	48769160892 ps
CPU time	279.21 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:50:10 PM PDT 24
Peak memory	203016 kb
Host	smart-52b33ed9-5db3-46fe-a2e5-8cbb7f6d1ce8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=389439563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slo w_rsp.389439563
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.609714920
Short name	T795
Test name
Test status
Simulation time	103846400 ps
CPU time	2.07 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	201920 kb
Host	smart-cdfd7365-a841-46ea-a4ff-57bf1bc76361
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=609714920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.609714920
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.357104046
Short name	T438
Test name
Test status
Simulation time	38886132 ps
CPU time	2.95 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:40 PM PDT 24
Peak memory	201900 kb
Host	smart-6e7109ad-1088-4522-b356-6189040aed4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=357104046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.357104046
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.515019087
Short name	T549
Test name
Test status
Simulation time	935091675 ps
CPU time	9.42 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	201920 kb
Host	smart-6087b90e-cb23-4a01-8967-b30af27ff1b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=515019087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.515019087
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2560948348
Short name	T527
Test name
Test status
Simulation time	30310097097 ps
CPU time	68.2 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	201932 kb
Host	smart-6ec7a8be-2eb0-46d3-bb4f-d65cc3b3373f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560948348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2560948348
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4159669867
Short name	T27
Test name
Test status
Simulation time	29269234374 ps
CPU time	185.82 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:48:39 PM PDT 24
Peak memory	202104 kb
Host	smart-72bef968-8153-4efe-92de-97f7ab192c16
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4159669867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4159669867
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.734659455
Short name	T342
Test name
Test status
Simulation time	94059212 ps
CPU time	4.75 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:45:42 PM PDT 24
Peak memory	201964 kb
Host	smart-fb745687-9c8b-44ec-9729-3e7501209fb6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734659455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.734659455
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.1202872207
Short name	T784
Test name
Test status
Simulation time	1463461345 ps
CPU time	8.4 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201956 kb
Host	smart-8d20f22b-d1b6-4c92-8aad-c80cfb7be313
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1202872207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1202872207
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.2607416586
Short name	T77
Test name
Test status
Simulation time	8958779 ps
CPU time	1.07 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:38 PM PDT 24
Peak memory	201912 kb
Host	smart-1969c138-704c-4b43-9fc9-4b44af5a4a69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2607416586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2607416586
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.601234232
Short name	T188
Test name
Test status
Simulation time	4610986628 ps
CPU time	7.28 seconds
Started	May 30 12:45:28 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	202052 kb
Host	smart-13866505-3d5c-4e12-8ce5-ab53a5ff59df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=601234232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.601234232
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1552946576
Short name	T125
Test name
Test status
Simulation time	1526857105 ps
CPU time	6.37 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:45:44 PM PDT 24
Peak memory	201852 kb
Host	smart-290334b8-ee3c-4de6-8d16-58def410ecea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1552946576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1552946576
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3808385236
Short name	T376
Test name
Test status
Simulation time	12988484 ps
CPU time	1.24 seconds
Started	May 30 12:45:34 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201916 kb
Host	smart-b1ade8c3-60b9-4093-b390-89254697ad8e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808385236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3808385236
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.154184592
Short name	T447
Test name
Test status
Simulation time	954980802 ps
CPU time	17.96 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	202988 kb
Host	smart-183dbe41-b4b3-49fd-b99a-9378fe95cb87
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=154184592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.154184592
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.4030328124
Short name	T357
Test name
Test status
Simulation time	470070085 ps
CPU time	41.12 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:46:19 PM PDT 24
Peak memory	201964 kb
Host	smart-7e6d9b81-7524-488f-a375-4c3fe9a82f99
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4030328124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.4030328124
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3997454130
Short name	T711
Test name
Test status
Simulation time	550223373 ps
CPU time	62.04 seconds
Started	May 30 12:45:38 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	203996 kb
Host	smart-829a7579-1c02-47eb-a981-85454ca1e38c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3997454130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3997454130
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1862028285
Short name	T629
Test name
Test status
Simulation time	3630790242 ps
CPU time	68.57 seconds
Started	May 30 12:45:32 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	204284 kb
Host	smart-cce0e14c-e152-4080-be36-61503018c01e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1862028285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1862028285
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3927136252
Short name	T896
Test name
Test status
Simulation time	14900426 ps
CPU time	1.7 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	201916 kb
Host	smart-3595caff-58a5-406a-8c96-bb9d4e1bb5bd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3927136252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3927136252
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3582292558
Short name	T26
Test name
Test status
Simulation time	347220263 ps
CPU time	6.01 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:38 PM PDT 24
Peak memory	201932 kb
Host	smart-87242a97-9297-4f4b-8e26-cc4741828300
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582292558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3582292558
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3424977202
Short name	T615
Test name
Test status
Simulation time	10693491781 ps
CPU time	54.69 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:46:30 PM PDT 24
Peak memory	202072 kb
Host	smart-c72ba393-b4e8-4b10-94ae-1ea8cdb7be6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3424977202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3424977202
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2460177628
Short name	T428
Test name
Test status
Simulation time	76477177 ps
CPU time	5.44 seconds
Started	May 30 12:45:40 PM PDT 24
Finished	May 30 12:45:47 PM PDT 24
Peak memory	201988 kb
Host	smart-16268813-4a09-41de-8c20-fabf48c59d64
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2460177628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2460177628
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.3793956812
Short name	T154
Test name
Test status
Simulation time	84853129 ps
CPU time	8.82 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	201968 kb
Host	smart-8933c756-7f0d-4863-9170-f2b01cefcd3a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3793956812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3793956812
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.3028670902
Short name	T43
Test name
Test status
Simulation time	630122078 ps
CPU time	13.41 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:51 PM PDT 24
Peak memory	201908 kb
Host	smart-e66a4275-2bed-4a35-aa66-7d7e958fadab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3028670902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3028670902
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2078366945
Short name	T251
Test name
Test status
Simulation time	47289580709 ps
CPU time	92.98 seconds
Started	May 30 12:45:38 PM PDT 24
Finished	May 30 12:47:12 PM PDT 24
Peak memory	202020 kb
Host	smart-ec2d5827-53e4-4366-9e0b-431d74b8b4cb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078366945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2078366945
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3453891122
Short name	T517
Test name
Test status
Simulation time	16321278184 ps
CPU time	48.86 seconds
Started	May 30 12:45:38 PM PDT 24
Finished	May 30 12:46:29 PM PDT 24
Peak memory	202016 kb
Host	smart-26528978-3eef-41cb-897b-dbda1c83ac88
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3453891122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3453891122
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.177946620
Short name	T598
Test name
Test status
Simulation time	42187043 ps
CPU time	5.2 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:40 PM PDT 24
Peak memory	201912 kb
Host	smart-4875237a-897e-4676-a884-1e0ec741a226
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177946620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.177946620
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.3326915111
Short name	T240
Test name
Test status
Simulation time	40313709 ps
CPU time	2.02 seconds
Started	May 30 12:45:33 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201928 kb
Host	smart-60be1081-16d1-48f7-8698-a13e434aeb07
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3326915111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3326915111
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.702325692
Short name	T800
Test name
Test status
Simulation time	23688566 ps
CPU time	1.11 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:45:38 PM PDT 24
Peak memory	201912 kb
Host	smart-1f36a283-4e96-4303-8018-0be61aa33890
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702325692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.702325692
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1502235078
Short name	T597
Test name
Test status
Simulation time	2028788216 ps
CPU time	6.48 seconds
Started	May 30 12:45:37 PM PDT 24
Finished	May 30 12:45:44 PM PDT 24
Peak memory	201920 kb
Host	smart-ae9cab69-8067-494b-968f-afd3c1e069f8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502235078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1502235078
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4089073416
Short name	T39
Test name
Test status
Simulation time	841422766 ps
CPU time	5.36 seconds
Started	May 30 12:45:38 PM PDT 24
Finished	May 30 12:45:45 PM PDT 24
Peak memory	201956 kb
Host	smart-81566625-abce-41cb-9046-d1e20ca053f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4089073416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4089073416
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1928057632
Short name	T134
Test name
Test status
Simulation time	8797412 ps
CPU time	1.18 seconds
Started	May 30 12:45:36 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	201904 kb
Host	smart-5685bd38-21d7-49d3-b6ed-765ae11cf5d2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928057632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1928057632
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.3712017053
Short name	T63
Test name
Test status
Simulation time	1936413861 ps
CPU time	30.51 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:46:24 PM PDT 24
Peak memory	203012 kb
Host	smart-459b47a3-a223-42cb-a3be-95f2cd32a7be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3712017053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3712017053
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3484206650
Short name	T547
Test name
Test status
Simulation time	1049867808 ps
CPU time	7.47 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	201896 kb
Host	smart-0c1dad2a-1599-4af9-9098-5d4b10c917df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484206650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3484206650
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.148537484
Short name	T734
Test name
Test status
Simulation time	4344709485 ps
CPU time	86.95 seconds
Started	May 30 12:45:47 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	204472 kb
Host	smart-da9997cb-8bed-4f97-ac37-e992ed181ebb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=148537484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand _reset.148537484
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.736348913
Short name	T223
Test name
Test status
Simulation time	745920707 ps
CPU time	50.85 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	204308 kb
Host	smart-2738d929-391d-4943-961b-b24edee0e4c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=736348913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.736348913
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1477177009
Short name	T350
Test name
Test status
Simulation time	1921510650 ps
CPU time	4.83 seconds
Started	May 30 12:45:37 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201916 kb
Host	smart-4da05f2a-2273-42a6-a92a-319ecc4025ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1477177009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1477177009
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2172160031
Short name	T115
Test name
Test status
Simulation time	1464901411 ps
CPU time	14.92 seconds
Started	May 30 12:45:48 PM PDT 24
Finished	May 30 12:46:04 PM PDT 24
Peak memory	202004 kb
Host	smart-8f1b0cdc-48b4-4647-948a-b743aa4ed680
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172160031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2172160031
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3905516149
Short name	T359
Test name
Test status
Simulation time	1857413725 ps
CPU time	10.35 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:45:54 PM PDT 24
Peak memory	201924 kb
Host	smart-9790add4-6b33-4b8d-8506-6ed3766ba500
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3905516149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3905516149
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.2710763364
Short name	T685
Test name
Test status
Simulation time	526894665 ps
CPU time	2.86 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:45 PM PDT 24
Peak memory	201968 kb
Host	smart-3e231a96-1b0f-4f6d-bc25-6382b9903d88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2710763364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2710763364
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.3181098314
Short name	T40
Test name
Test status
Simulation time	1331496950 ps
CPU time	8.92 seconds
Started	May 30 12:45:39 PM PDT 24
Finished	May 30 12:45:49 PM PDT 24
Peak memory	201956 kb
Host	smart-4cb5a514-9ca7-43ef-8cdd-33b470636eb8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3181098314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3181098314
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.660183452
Short name	T803
Test name
Test status
Simulation time	13460325767 ps
CPU time	8.54 seconds
Started	May 30 12:45:48 PM PDT 24
Finished	May 30 12:45:58 PM PDT 24
Peak memory	202024 kb
Host	smart-001b81bd-0f56-448f-abd9-e836fb978128
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=660183452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.660183452
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.4202984253
Short name	T328
Test name
Test status
Simulation time	16226706902 ps
CPU time	110.09 seconds
Started	May 30 12:45:45 PM PDT 24
Finished	May 30 12:47:37 PM PDT 24
Peak memory	202060 kb
Host	smart-9c259991-71d4-4ba4-885b-3ac23bb4d144
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4202984253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.4202984253
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1273699513
Short name	T128
Test name
Test status
Simulation time	29100454 ps
CPU time	2.49 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	201944 kb
Host	smart-fb1cccb4-4581-47ee-8924-87f00247ae16
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273699513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1273699513
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.1503520598
Short name	T552
Test name
Test status
Simulation time	77906072 ps
CPU time	5.19 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	202012 kb
Host	smart-8960fc7d-ce29-43fc-9fa7-5fd291b65e9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1503520598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1503520598
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.3459985729
Short name	T374
Test name
Test status
Simulation time	58914744 ps
CPU time	1.26 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:45:51 PM PDT 24
Peak memory	201992 kb
Host	smart-4b31a1f4-b945-4ee7-8d31-35ddc803ed0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3459985729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3459985729
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.249889504
Short name	T738
Test name
Test status
Simulation time	2206802309 ps
CPU time	10.3 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	202076 kb
Host	smart-c0bb125f-8366-4f4a-a780-d04a99f4dabf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=249889504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.249889504
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3451531969
Short name	T647
Test name
Test status
Simulation time	2093589795 ps
CPU time	10.32 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:45:54 PM PDT 24
Peak memory	201948 kb
Host	smart-31905d9b-4030-4e14-a6ad-cc78a15e6650
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3451531969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3451531969
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2736157832
Short name	T298
Test name
Test status
Simulation time	8212630 ps
CPU time	1.05 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201944 kb
Host	smart-b21c0ee8-6f60-498e-a555-0165368d9399
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736157832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2736157832
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.1047608328
Short name	T808
Test name
Test status
Simulation time	7028352705 ps
CPU time	65.06 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:46:49 PM PDT 24
Peak memory	204096 kb
Host	smart-d97a59e1-b208-4a4d-a433-0c0425b44514
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1047608328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1047608328
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1381780480
Short name	T410
Test name
Test status
Simulation time	211884263 ps
CPU time	16.07 seconds
Started	May 30 12:45:40 PM PDT 24
Finished	May 30 12:45:58 PM PDT 24
Peak memory	201980 kb
Host	smart-7fc8a95a-0cfd-4abe-8939-11139f449c86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1381780480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1381780480
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2842458161
Short name	T277
Test name
Test status
Simulation time	201054279 ps
CPU time	13.23 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:56 PM PDT 24
Peak memory	203008 kb
Host	smart-f051ad04-7b4b-4c69-a057-fe840d33a0b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2842458161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2842458161
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.561557977
Short name	T758
Test name
Test status
Simulation time	323045265 ps
CPU time	26.97 seconds
Started	May 30 12:45:46 PM PDT 24
Finished	May 30 12:46:14 PM PDT 24
Peak memory	203384 kb
Host	smart-108f7689-8743-4d1c-ad57-e7a28481a0d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561557977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.561557977
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.571738841
Short name	T174
Test name
Test status
Simulation time	1236469905 ps
CPU time	7.26 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:49 PM PDT 24
Peak memory	201964 kb
Host	smart-fe13f2af-7217-4958-ace8-14d7862dbec4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571738841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.571738841
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2860025246
Short name	T787
Test name
Test status
Simulation time	660230499 ps
CPU time	9.24 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:54 PM PDT 24
Peak memory	201952 kb
Host	smart-f585563a-9dcd-40f2-86b9-d932c14df076
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860025246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2860025246
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2108727089
Short name	T155
Test name
Test status
Simulation time	105094579116 ps
CPU time	257.25 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:48:59 PM PDT 24
Peak memory	203568 kb
Host	smart-7337c7f3-da4c-4d09-82a5-09247a7c11e2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2108727089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2108727089
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4247238626
Short name	T349
Test name
Test status
Simulation time	252872879 ps
CPU time	2.89 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:44:46 PM PDT 24
Peak memory	201904 kb
Host	smart-4ba213d8-eb11-4398-85a3-2b10d17b28d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4247238626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4247238626
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.159811639
Short name	T613
Test name
Test status
Simulation time	1015058200 ps
CPU time	10.47 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:44:54 PM PDT 24
Peak memory	201992 kb
Host	smart-c8b9b565-ab51-4ca5-89b0-0237e20f8762
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=159811639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.159811639
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.3527187586
Short name	T608
Test name
Test status
Simulation time	765158730 ps
CPU time	11.51 seconds
Started	May 30 12:44:39 PM PDT 24
Finished	May 30 12:44:51 PM PDT 24
Peak memory	201904 kb
Host	smart-8ddfec39-69e0-4d95-97e0-1c8c5b7f4e7c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527187586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3527187586
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.977344669
Short name	T854
Test name
Test status
Simulation time	49363172233 ps
CPU time	128.55 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	201988 kb
Host	smart-98929e79-53b5-4076-a183-43620e013515
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=977344669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.977344669
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3230730874
Short name	T413
Test name
Test status
Simulation time	14448673399 ps
CPU time	54.03 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201992 kb
Host	smart-dc12f001-86c9-4152-8fee-181838d1c126
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3230730874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3230730874
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.441950869
Short name	T883
Test name
Test status
Simulation time	36967335 ps
CPU time	3.37 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:44:46 PM PDT 24
Peak memory	201928 kb
Host	smart-da8a84c5-de67-439c-b84f-c1182bfa5e3a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441950869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.441950869
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.3503928508
Short name	T759
Test name
Test status
Simulation time	1172488473 ps
CPU time	8.2 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201840 kb
Host	smart-729f7073-f9dc-47f2-bfbf-72c397337323
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3503928508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3503928508
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.1511767357
Short name	T403
Test name
Test status
Simulation time	14126294 ps
CPU time	1.18 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:44:45 PM PDT 24
Peak memory	201972 kb
Host	smart-25ea76f3-8f61-4fce-b365-eebd8bcc1015
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1511767357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1511767357
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2670556535
Short name	T278
Test name
Test status
Simulation time	1650059628 ps
CPU time	6.81 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201984 kb
Host	smart-d35b54b6-ff71-450b-b9ca-8c34f71e691b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670556535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2670556535
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.922975218
Short name	T361
Test name
Test status
Simulation time	2074869751 ps
CPU time	6.06 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201960 kb
Host	smart-4b5db477-6926-42e6-a420-aa8edbad04ae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=922975218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.922975218
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.959628160
Short name	T625
Test name
Test status
Simulation time	14157564 ps
CPU time	1.05 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:44:42 PM PDT 24
Peak memory	201960 kb
Host	smart-f1b27872-8db1-4fb0-94cd-e533927b6e72
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959628160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.959628160
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.3030926015
Short name	T299
Test name
Test status
Simulation time	3701439827 ps
CPU time	65.31 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	202012 kb
Host	smart-8a62b5ce-2d08-46f9-b142-340e94d99b9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3030926015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3030926015
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.939565524
Short name	T149
Test name
Test status
Simulation time	3995143525 ps
CPU time	43.44 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:45:26 PM PDT 24
Peak memory	201936 kb
Host	smart-14218a41-ba2e-4260-a157-05a368279e65
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=939565524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.939565524
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2184336532
Short name	T229
Test name
Test status
Simulation time	401899452 ps
CPU time	62.56 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	204268 kb
Host	smart-90b358de-9864-49dd-9497-2746b2b6d932
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2184336532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.2184336532
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2531751746
Short name	T642
Test name
Test status
Simulation time	96335734 ps
CPU time	8.67 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201912 kb
Host	smart-7da025ce-c38e-4c71-bcd4-e041869162d7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2531751746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.2531751746
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3282088093
Short name	T671
Test name
Test status
Simulation time	157385783 ps
CPU time	7.47 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:44:53 PM PDT 24
Peak memory	201944 kb
Host	smart-3674e957-9244-4f99-9a7b-6ce5fbb6144b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3282088093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3282088093
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.4250319393
Short name	T137
Test name
Test status
Simulation time	210807782 ps
CPU time	4.85 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	202012 kb
Host	smart-ee3219d6-daf8-4b11-8f8e-1ff0b69892d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4250319393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.4250319393
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3077019591
Short name	T824
Test name
Test status
Simulation time	108570298440 ps
CPU time	251.67 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:49:56 PM PDT 24
Peak memory	203016 kb
Host	smart-96ec89e3-2d3b-4376-a13a-e1a890a5d221
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3077019591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.3077019591
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.364057481
Short name	T868
Test name
Test status
Simulation time	1786508763 ps
CPU time	11.22 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:46:05 PM PDT 24
Peak memory	201988 kb
Host	smart-57714fd4-19c0-4d99-8583-82dfbb2b7317
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364057481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.364057481
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.650397230
Short name	T409
Test name
Test status
Simulation time	143439416 ps
CPU time	1.98 seconds
Started	May 30 12:45:40 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201988 kb
Host	smart-4ffb6b8b-b78e-4ad0-ac85-fd9ce4b701fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=650397230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.650397230
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.2933863634
Short name	T593
Test name
Test status
Simulation time	24439645 ps
CPU time	1.98 seconds
Started	May 30 12:45:45 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	201972 kb
Host	smart-c94c8955-0316-4000-b668-92bace0dd431
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2933863634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2933863634
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2738626700
Short name	T522
Test name
Test status
Simulation time	116165118689 ps
CPU time	142.85 seconds
Started	May 30 12:45:40 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	202060 kb
Host	smart-e993736d-7dcc-4746-a392-aae4a280fb4e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738626700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2738626700
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1606956330
Short name	T157
Test name
Test status
Simulation time	23421087982 ps
CPU time	118.95 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:47:53 PM PDT 24
Peak memory	202056 kb
Host	smart-3e0e6192-6ca1-45ab-a73a-a790d5912c06
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1606956330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1606956330
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.4090830953
Short name	T175
Test name
Test status
Simulation time	52536588 ps
CPU time	4.08 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201992 kb
Host	smart-10f97ad1-f303-4b0e-ac90-4355cc11a295
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090830953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.4090830953
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.2649352589
Short name	T657
Test name
Test status
Simulation time	105015862 ps
CPU time	5.34 seconds
Started	May 30 12:45:44 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	201928 kb
Host	smart-05e386d6-68a0-4254-81e6-ad81a2753fca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649352589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2649352589
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.1736591549
Short name	T263
Test name
Test status
Simulation time	49387850 ps
CPU time	1.41 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201920 kb
Host	smart-87f2c7b9-d7ff-4b84-be2a-bb891d957dc2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1736591549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1736591549
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2376908895
Short name	T362
Test name
Test status
Simulation time	2443108358 ps
CPU time	7.1 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	202056 kb
Host	smart-37fe3e95-3b0d-4f50-8c72-6a5b3bbe80f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376908895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2376908895
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1932191930
Short name	T432
Test name
Test status
Simulation time	8824896121 ps
CPU time	8.03 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:46:02 PM PDT 24
Peak memory	202052 kb
Host	smart-119c8867-9188-4a03-83b8-4efb5df1bda6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1932191930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1932191930
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1391988090
Short name	T270
Test name
Test status
Simulation time	8432790 ps
CPU time	1.1 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:45:51 PM PDT 24
Peak memory	201992 kb
Host	smart-9cc2cff5-a32c-4198-ba61-3434c69f6469
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391988090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1391988090
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.403491871
Short name	T678
Test name
Test status
Simulation time	6871546026 ps
CPU time	41.27 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	202060 kb
Host	smart-1616015e-9433-426c-97f1-2606c916b062
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=403491871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.403491871
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1053659130
Short name	T605
Test name
Test status
Simulation time	192667256 ps
CPU time	14.18 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:45:57 PM PDT 24
Peak memory	203044 kb
Host	smart-6617dfca-570f-4528-a656-fafc0a492d56
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1053659130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1053659130
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1966374193
Short name	T150
Test name
Test status
Simulation time	276620989 ps
CPU time	26.14 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:46:10 PM PDT 24
Peak memory	203000 kb
Host	smart-5c6d64bf-0177-4925-9ea8-a5eb4bdf33a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966374193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1966374193
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1998771972
Short name	T679
Test name
Test status
Simulation time	1323386597 ps
CPU time	10.31 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201908 kb
Host	smart-b256ddbf-f207-4048-85e6-a655742e5a93
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1998771972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1998771972
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2008106509
Short name	T291
Test name
Test status
Simulation time	418293676 ps
CPU time	4.91 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:45:49 PM PDT 24
Peak memory	201928 kb
Host	smart-220f9c69-8daa-409a-9fad-a44a7aee9548
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2008106509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2008106509
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3996877625
Short name	T172
Test name
Test status
Simulation time	49301118853 ps
CPU time	182.09 seconds
Started	May 30 12:45:46 PM PDT 24
Finished	May 30 12:48:50 PM PDT 24
Peak memory	203076 kb
Host	smart-68637b80-be8b-41fe-b934-2e99f15bc23c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3996877625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3996877625
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2906667661
Short name	T234
Test name
Test status
Simulation time	63448749 ps
CPU time	6.4 seconds
Started	May 30 12:45:47 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201996 kb
Host	smart-e338a0f4-0d7f-440e-a037-d5e775786f3a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2906667661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2906667661
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.1330442939
Short name	T723
Test name
Test status
Simulation time	33508101 ps
CPU time	2.21 seconds
Started	May 30 12:45:47 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	201988 kb
Host	smart-85a8fd72-a6a6-4f3d-bc2f-d5c4106eb31f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1330442939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1330442939
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.542683846
Short name	T326
Test name
Test status
Simulation time	226354404 ps
CPU time	3.57 seconds
Started	May 30 12:45:42 PM PDT 24
Finished	May 30 12:45:47 PM PDT 24
Peak memory	202020 kb
Host	smart-5b55bd66-df66-4037-8b9b-2f499ce39158
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=542683846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.542683846
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3512614471
Short name	T785
Test name
Test status
Simulation time	41594503034 ps
CPU time	71.45 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:46:56 PM PDT 24
Peak memory	202076 kb
Host	smart-d33e35e8-78eb-4cf2-b8ab-6fbbc4e2b2d1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512614471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3512614471
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.174660769
Short name	T873
Test name
Test status
Simulation time	83616994601 ps
CPU time	100.32 seconds
Started	May 30 12:45:46 PM PDT 24
Finished	May 30 12:47:27 PM PDT 24
Peak memory	202060 kb
Host	smart-3369c832-8119-4ef5-ab2c-4f0e1ecddd12
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=174660769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.174660769
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.150459524
Short name	T644
Test name
Test status
Simulation time	204253556 ps
CPU time	4.66 seconds
Started	May 30 12:45:44 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	201964 kb
Host	smart-51b88058-78c4-4611-a3f0-a2714ff61b8d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150459524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.150459524
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.906224554
Short name	T275
Test name
Test status
Simulation time	5391748526 ps
CPU time	12.95 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:46:04 PM PDT 24
Peak memory	202064 kb
Host	smart-cdb68b5c-5bd4-4b55-b377-446941dcc191
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=906224554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.906224554
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.686907295
Short name	T596
Test name
Test status
Simulation time	11306879 ps
CPU time	1.37 seconds
Started	May 30 12:45:48 PM PDT 24
Finished	May 30 12:45:50 PM PDT 24
Peak memory	201980 kb
Host	smart-929ba6aa-57f5-41b7-8870-f0d90366b69f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686907295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.686907295
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1818889822
Short name	T819
Test name
Test status
Simulation time	7445186355 ps
CPU time	10.38 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:46:02 PM PDT 24
Peak memory	202064 kb
Host	smart-f36a053e-fdcd-4227-86fb-e616a923d3e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818889822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1818889822
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3382192185
Short name	T255
Test name
Test status
Simulation time	829211767 ps
CPU time	6.71 seconds
Started	May 30 12:45:45 PM PDT 24
Finished	May 30 12:45:53 PM PDT 24
Peak memory	201884 kb
Host	smart-97011a2e-75fc-49f2-bc07-70471e239425
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3382192185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3382192185
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2905737763
Short name	T518
Test name
Test status
Simulation time	13651538 ps
CPU time	1.25 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	201916 kb
Host	smart-6967edeb-b4c3-4b48-9de4-80678193c2e3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905737763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2905737763
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.3579635676
Short name	T661
Test name
Test status
Simulation time	1116152414 ps
CPU time	14.97 seconds
Started	May 30 12:45:44 PM PDT 24
Finished	May 30 12:46:00 PM PDT 24
Peak memory	201972 kb
Host	smart-3ac8ce89-8340-4d03-9730-bc4e3a322a4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3579635676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3579635676
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3370192143
Short name	T426
Test name
Test status
Simulation time	130479282 ps
CPU time	9.03 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:46:02 PM PDT 24
Peak memory	201976 kb
Host	smart-4af40713-df9c-49b1-a744-0373d2eb2586
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3370192143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3370192143
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3984185890
Short name	T227
Test name
Test status
Simulation time	318032538 ps
CPU time	57.22 seconds
Started	May 30 12:45:46 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	204012 kb
Host	smart-52965d37-7908-4c0a-ad4b-5e3d2d767713
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3984185890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3984185890
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1233830119
Short name	T834
Test name
Test status
Simulation time	4378434300 ps
CPU time	113.76 seconds
Started	May 30 12:45:46 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	208012 kb
Host	smart-7ce48bcd-50c7-43f7-b3db-ceef48492285
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1233830119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1233830119
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.413018036
Short name	T332
Test name
Test status
Simulation time	587707258 ps
CPU time	8.09 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:45:58 PM PDT 24
Peak memory	201992 kb
Host	smart-734733d4-6ee0-4c86-a072-b341fa6465b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413018036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.413018036
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2300286727
Short name	T131
Test name
Test status
Simulation time	66595637 ps
CPU time	8.28 seconds
Started	May 30 12:45:44 PM PDT 24
Finished	May 30 12:45:54 PM PDT 24
Peak memory	201888 kb
Host	smart-417e1979-c86c-4475-ab72-f43e26d4796c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300286727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2300286727
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.527828425
Short name	T135
Test name
Test status
Simulation time	16487692727 ps
CPU time	106.98 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:47:37 PM PDT 24
Peak memory	201988 kb
Host	smart-94621b08-959e-4ed9-8d12-2078eef187f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=527828425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slo w_rsp.527828425
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.23314016
Short name	T878
Test name
Test status
Simulation time	65829412 ps
CPU time	1.8 seconds
Started	May 30 12:45:55 PM PDT 24
Finished	May 30 12:45:58 PM PDT 24
Peak memory	201884 kb
Host	smart-6c88050e-a4dd-488e-a835-0b0bf3d03f51
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=23314016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.23314016
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.2045770137
Short name	T727
Test name
Test status
Simulation time	375652107 ps
CPU time	3.73 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:45:56 PM PDT 24
Peak memory	201976 kb
Host	smart-71407186-4286-4e84-8a52-648ca0a3bf16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2045770137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2045770137
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.3127667400
Short name	T30
Test name
Test status
Simulation time	198574097 ps
CPU time	3.57 seconds
Started	May 30 12:45:43 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	202012 kb
Host	smart-dd7ef01a-5cb1-4e6c-a13b-1f93407c701c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127667400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3127667400
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.892822048
Short name	T118
Test name
Test status
Simulation time	66399324103 ps
CPU time	132.73 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:48:05 PM PDT 24
Peak memory	202056 kb
Host	smart-a4b646c1-5f3b-4c52-9d7c-177caa011637
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=892822048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.892822048
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2179760142
Short name	T423
Test name
Test status
Simulation time	13955300543 ps
CPU time	75.59 seconds
Started	May 30 12:45:41 PM PDT 24
Finished	May 30 12:46:58 PM PDT 24
Peak memory	202056 kb
Host	smart-129471f2-3d44-4a55-b0ca-f7cd478c8d85
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2179760142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2179760142
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2019193878
Short name	T285
Test name
Test status
Simulation time	49319835 ps
CPU time	2.53 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201976 kb
Host	smart-66aa718d-1de6-4521-885c-da2136c5f34f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019193878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2019193878
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.2481581942
Short name	T638
Test name
Test status
Simulation time	116000853 ps
CPU time	3.67 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201912 kb
Host	smart-67fa6336-7dff-4860-b029-54c0cb88db6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2481581942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2481581942
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.1662252418
Short name	T280
Test name
Test status
Simulation time	12617852 ps
CPU time	1.14 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:45:53 PM PDT 24
Peak memory	201980 kb
Host	smart-286b96ba-e913-45fb-8d73-8281f01b1a43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1662252418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1662252418
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2507402837
Short name	T301
Test name
Test status
Simulation time	3074683377 ps
CPU time	12.38 seconds
Started	May 30 12:45:44 PM PDT 24
Finished	May 30 12:45:58 PM PDT 24
Peak memory	201948 kb
Host	smart-7ae9d563-a520-4d18-94a0-74d538b67527
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507402837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2507402837
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3154854766
Short name	T460
Test name
Test status
Simulation time	915013445 ps
CPU time	6.59 seconds
Started	May 30 12:45:45 PM PDT 24
Finished	May 30 12:45:53 PM PDT 24
Peak memory	201892 kb
Host	smart-e77580ec-267f-4ff6-8e29-8c28ac66e24c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3154854766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3154854766
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1502755351
Short name	T715
Test name
Test status
Simulation time	9423425 ps
CPU time	1.09 seconds
Started	May 30 12:45:46 PM PDT 24
Finished	May 30 12:45:48 PM PDT 24
Peak memory	201868 kb
Host	smart-c8abcca4-6fc5-4951-885d-5987094709c9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502755351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1502755351
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.1354934193
Short name	T750
Test name
Test status
Simulation time	4776645982 ps
CPU time	45.97 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	205096 kb
Host	smart-52a58489-8aee-48dd-965b-3c44f23ff63e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1354934193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1354934193
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.577165622
Short name	T293
Test name
Test status
Simulation time	3425290496 ps
CPU time	16.54 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:46:09 PM PDT 24
Peak memory	202056 kb
Host	smart-8ba2b5f4-0461-4b63-81d1-45ea4fa069a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=577165622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.577165622
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.375979428
Short name	T724
Test name
Test status
Simulation time	388384548 ps
CPU time	30.41 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:46:22 PM PDT 24
Peak memory	203984 kb
Host	smart-07cca158-c052-4b9d-a947-959bbd919240
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=375979428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.375979428
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1543413500
Short name	T577
Test name
Test status
Simulation time	6140601941 ps
CPU time	95.22 seconds
Started	May 30 12:46:02 PM PDT 24
Finished	May 30 12:47:38 PM PDT 24
Peak memory	204460 kb
Host	smart-9976d0a0-eadf-42da-9635-025432725dbf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1543413500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.1543413500
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.162930026
Short name	T479
Test name
Test status
Simulation time	126160135 ps
CPU time	7.77 seconds
Started	May 30 12:45:54 PM PDT 24
Finished	May 30 12:46:03 PM PDT 24
Peak memory	201828 kb
Host	smart-cf17c857-7016-43a7-bc50-6903b2bafd6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=162930026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.162930026
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.830923820
Short name	T335
Test name
Test status
Simulation time	313830612 ps
CPU time	12.17 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:46:04 PM PDT 24
Peak memory	201952 kb
Host	smart-eb9e4abc-31a2-4643-b56d-3c2a7639ad58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=830923820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.830923820
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1547594154
Short name	T209
Test name
Test status
Simulation time	41021217139 ps
CPU time	123.1 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:47:54 PM PDT 24
Peak memory	202148 kb
Host	smart-05afb1ac-3d27-4306-b37a-8d05ad279e8f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1547594154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1547594154
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.597656696
Short name	T294
Test name
Test status
Simulation time	581649138 ps
CPU time	9.84 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:46:13 PM PDT 24
Peak memory	201928 kb
Host	smart-6860d581-48fe-44ac-93ef-b1aa60c5b795
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=597656696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.597656696
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.518359684
Short name	T542
Test name
Test status
Simulation time	48324248 ps
CPU time	3.96 seconds
Started	May 30 12:45:54 PM PDT 24
Finished	May 30 12:45:59 PM PDT 24
Peak memory	201988 kb
Host	smart-6185ffdc-e4a3-4b34-aa97-8c0b64e74a59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518359684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.518359684
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.2819617588
Short name	T168
Test name
Test status
Simulation time	540425920 ps
CPU time	11.53 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:46:06 PM PDT 24
Peak memory	201832 kb
Host	smart-740f0953-648d-443e-88c7-decc3019ab6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2819617588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2819617588
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.759604551
Short name	T434
Test name
Test status
Simulation time	22560870575 ps
CPU time	63.8 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	201992 kb
Host	smart-bad42517-d11f-4691-990c-0b5afbeeeddd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=759604551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.759604551
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.866770399
Short name	T289
Test name
Test status
Simulation time	24201367555 ps
CPU time	23.06 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:46:16 PM PDT 24
Peak memory	201964 kb
Host	smart-78fae374-fcde-4791-b904-872ed7ace073
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=866770399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.866770399
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2610819
Short name	T314
Test name
Test status
Simulation time	42002961 ps
CPU time	5.73 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:45:57 PM PDT 24
Peak memory	201920 kb
Host	smart-eba0ca4b-1f0a-46cd-9181-a439e4040d69
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2610819
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.3168810629
Short name	T880
Test name
Test status
Simulation time	56253532 ps
CPU time	4.92 seconds
Started	May 30 12:46:02 PM PDT 24
Finished	May 30 12:46:07 PM PDT 24
Peak memory	201928 kb
Host	smart-974737d6-4804-449b-a6b4-65a5cc55f2b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3168810629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3168810629
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.1223961154
Short name	T404
Test name
Test status
Simulation time	54582888 ps
CPU time	1.63 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201996 kb
Host	smart-18a050a2-8ff5-4a6e-8657-fed62e928b6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223961154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1223961154
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3920765676
Short name	T232
Test name
Test status
Simulation time	16762255408 ps
CPU time	11.84 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:46:04 PM PDT 24
Peak memory	202036 kb
Host	smart-d00b31af-cbea-48c5-bac2-6a3fa5c78a5b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920765676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3920765676
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.402274568
Short name	T811
Test name
Test status
Simulation time	2318188995 ps
CPU time	12.76 seconds
Started	May 30 12:45:54 PM PDT 24
Finished	May 30 12:46:08 PM PDT 24
Peak memory	202048 kb
Host	smart-eb220282-5fa4-4b13-b3e7-939613615038
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=402274568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.402274568
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.865673395
Short name	T619
Test name
Test status
Simulation time	12020953 ps
CPU time	1.1 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:45:51 PM PDT 24
Peak memory	201960 kb
Host	smart-332312d6-51cf-4660-808c-fb53bc49c8d1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865673395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.865673395
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.1929713607
Short name	T307
Test name
Test status
Simulation time	592351472 ps
CPU time	23.2 seconds
Started	May 30 12:46:02 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201936 kb
Host	smart-ca4cbe51-2504-4c19-9e02-cff140611990
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1929713607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1929713607
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1420140924
Short name	T297
Test name
Test status
Simulation time	99111275 ps
CPU time	4.23 seconds
Started	May 30 12:46:02 PM PDT 24
Finished	May 30 12:46:07 PM PDT 24
Peak memory	201916 kb
Host	smart-41155054-eec6-4dc1-a5cf-fa9a40f484c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420140924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1420140924
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3072116984
Short name	T770
Test name
Test status
Simulation time	7257103122 ps
CPU time	197.5 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:49:12 PM PDT 24
Peak memory	207264 kb
Host	smart-5e519c00-5c49-4c26-9eeb-f81e5d51bca5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3072116984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3072116984
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2993646927
Short name	T777
Test name
Test status
Simulation time	3233193734 ps
CPU time	90.03 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:47:20 PM PDT 24
Peak memory	206372 kb
Host	smart-58aae7f0-bfc8-4784-9afb-fbdeed0a818b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2993646927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.2993646927
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3645053605
Short name	T93
Test name
Test status
Simulation time	3595981902 ps
CPU time	8.82 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:46:01 PM PDT 24
Peak memory	202064 kb
Host	smart-12fe74c8-68ec-45d8-bdd0-760ec422ac29
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3645053605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3645053605
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2073702620
Short name	T765
Test name
Test status
Simulation time	304979900 ps
CPU time	5.56 seconds
Started	May 30 12:45:54 PM PDT 24
Finished	May 30 12:46:00 PM PDT 24
Peak memory	201996 kb
Host	smart-6c9fe088-87a8-48b9-82cf-edf026dc3de3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073702620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2073702620
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2327410487
Short name	T395
Test name
Test status
Simulation time	27397802 ps
CPU time	2.37 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:45:57 PM PDT 24
Peak memory	201968 kb
Host	smart-2e183703-e94b-49ea-a1dd-38769e8e1be3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2327410487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2327410487
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.2329611955
Short name	T885
Test name
Test status
Simulation time	820846161 ps
CPU time	7.29 seconds
Started	May 30 12:46:02 PM PDT 24
Finished	May 30 12:46:10 PM PDT 24
Peak memory	201920 kb
Host	smart-63b512eb-9246-4aab-abc3-8cfe06d55d89
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2329611955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2329611955
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.3265614189
Short name	T451
Test name
Test status
Simulation time	70958349 ps
CPU time	4.74 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:45:59 PM PDT 24
Peak memory	201944 kb
Host	smart-33fc0eba-f400-4c86-bd42-b328878377ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3265614189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3265614189
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3307235727
Short name	T98
Test name
Test status
Simulation time	183448481006 ps
CPU time	104.21 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:47:37 PM PDT 24
Peak memory	202044 kb
Host	smart-3452515b-2cd4-40a1-b40a-42f64b5558df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307235727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3307235727
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1735945505
Short name	T143
Test name
Test status
Simulation time	21887500832 ps
CPU time	101.4 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:47:36 PM PDT 24
Peak memory	201972 kb
Host	smart-2e3f2aaa-4a96-40e8-9754-e7a60eaf5eb2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1735945505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1735945505
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.843571632
Short name	T882
Test name
Test status
Simulation time	28733693 ps
CPU time	2.91 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:45:57 PM PDT 24
Peak memory	202000 kb
Host	smart-a74783ab-6211-4703-8cc6-529fb71d8882
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843571632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.843571632
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.3151413584
Short name	T37
Test name
Test status
Simulation time	501039191 ps
CPU time	7.18 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:45:58 PM PDT 24
Peak memory	201960 kb
Host	smart-27646dc6-6f79-4445-8ad3-9da9173b90b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151413584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3151413584
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.3288145780
Short name	T31
Test name
Test status
Simulation time	518785140 ps
CPU time	1.84 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:45:52 PM PDT 24
Peak memory	201980 kb
Host	smart-63716a60-df85-47a6-8a82-37add6035e10
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288145780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3288145780
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1813918561
Short name	T786
Test name
Test status
Simulation time	2140562148 ps
CPU time	7.98 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:46:11 PM PDT 24
Peak memory	201680 kb
Host	smart-170caa91-31c5-44d5-abd4-8f49524c098c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813918561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1813918561
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2864679270
Short name	T695
Test name
Test status
Simulation time	4168145449 ps
CPU time	9.81 seconds
Started	May 30 12:45:51 PM PDT 24
Finished	May 30 12:46:01 PM PDT 24
Peak memory	202076 kb
Host	smart-9397540e-9da1-47da-86dd-46ec1a5f6bb0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2864679270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2864679270
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1648505111
Short name	T539
Test name
Test status
Simulation time	10634261 ps
CPU time	1.22 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:45:52 PM PDT 24
Peak memory	201892 kb
Host	smart-940073ba-6cff-4477-986f-57dc187ee333
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648505111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1648505111
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.2770549885
Short name	T705
Test name
Test status
Simulation time	2933383724 ps
CPU time	39.8 seconds
Started	May 30 12:45:50 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	203124 kb
Host	smart-940e764c-5367-47a2-9782-308dd641b895
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2770549885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2770549885
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2147262802
Short name	T745
Test name
Test status
Simulation time	145783734 ps
CPU time	5.92 seconds
Started	May 30 12:45:55 PM PDT 24
Finished	May 30 12:46:02 PM PDT 24
Peak memory	201872 kb
Host	smart-0d031640-e53d-446e-9698-2d8a016ca278
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2147262802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2147262802
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1729804752
Short name	T329
Test name
Test status
Simulation time	7805454 ps
CPU time	7.08 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:45:57 PM PDT 24
Peak memory	201940 kb
Host	smart-ae612924-d144-410d-a5e8-79f6bd878523
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1729804752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.1729804752
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2560410951
Short name	T879
Test name
Test status
Simulation time	316403045 ps
CPU time	45.7 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:46:50 PM PDT 24
Peak memory	203372 kb
Host	smart-1e9ac28c-23cf-4db9-93ac-03700d14d61c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2560410951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2560410951
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2534220792
Short name	T683
Test name
Test status
Simulation time	1721012080 ps
CPU time	6.49 seconds
Started	May 30 12:45:54 PM PDT 24
Finished	May 30 12:46:01 PM PDT 24
Peak memory	201992 kb
Host	smart-1d4c6a89-49bc-47cf-8b6d-80349ec18b1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534220792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2534220792
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1096723286
Short name	T185
Test name
Test status
Simulation time	15918241 ps
CPU time	2.35 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:46:06 PM PDT 24
Peak memory	201964 kb
Host	smart-477d28cf-3ac7-4f13-a2f1-4f84945adf05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1096723286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1096723286
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3366499606
Short name	T22
Test name
Test status
Simulation time	9907668859 ps
CPU time	52.46 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:46:56 PM PDT 24
Peak memory	202016 kb
Host	smart-d6425cb3-6f10-4b53-beaf-62ecc34ba69c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3366499606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.3366499606
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1926674528
Short name	T710
Test name
Test status
Simulation time	14351071 ps
CPU time	1.1 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:06 PM PDT 24
Peak memory	202008 kb
Host	smart-467c024e-9bb9-4618-900c-59173ac845ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926674528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1926674528
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.899931456
Short name	T487
Test name
Test status
Simulation time	64241640 ps
CPU time	8.27 seconds
Started	May 30 12:46:06 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	201976 kb
Host	smart-ae65b203-b054-42cd-9566-0a690c4db281
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=899931456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.899931456
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.1909601771
Short name	T799
Test name
Test status
Simulation time	161824855 ps
CPU time	5.9 seconds
Started	May 30 12:45:53 PM PDT 24
Finished	May 30 12:46:00 PM PDT 24
Peak memory	201976 kb
Host	smart-9deec420-ccb6-4284-9a40-63d39301e4d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909601771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1909601771
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2613689184
Short name	T159
Test name
Test status
Simulation time	33973102076 ps
CPU time	84.05 seconds
Started	May 30 12:46:06 PM PDT 24
Finished	May 30 12:47:31 PM PDT 24
Peak memory	202048 kb
Host	smart-9355cef5-49d9-4009-8202-2aa13865c8eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613689184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2613689184
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3990395134
Short name	T421
Test name
Test status
Simulation time	5319378146 ps
CPU time	17.42 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:23 PM PDT 24
Peak memory	202036 kb
Host	smart-32de70c5-8c65-4914-aa5f-bb5c95e2d978
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3990395134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3990395134
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.214443250
Short name	T61
Test name
Test status
Simulation time	32643351 ps
CPU time	2.5 seconds
Started	May 30 12:45:54 PM PDT 24
Finished	May 30 12:45:57 PM PDT 24
Peak memory	201980 kb
Host	smart-13f59355-26d2-495e-85fc-78b5be293bcc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214443250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.214443250
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.406984105
Short name	T744
Test name
Test status
Simulation time	22681121 ps
CPU time	2.46 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:08 PM PDT 24
Peak memory	201960 kb
Host	smart-ade4222c-e197-47f2-b723-e6a5bb90f549
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406984105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.406984105
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.2406730351
Short name	T654
Test name
Test status
Simulation time	50182470 ps
CPU time	1.41 seconds
Started	May 30 12:45:49 PM PDT 24
Finished	May 30 12:45:51 PM PDT 24
Peak memory	201992 kb
Host	smart-e4528396-39f7-414c-8733-8adf2211c075
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2406730351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2406730351
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2878305120
Short name	T116
Test name
Test status
Simulation time	8279406128 ps
CPU time	11.79 seconds
Started	May 30 12:46:02 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	201988 kb
Host	smart-495189ca-f7b6-49e0-8144-3b53451096a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878305120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2878305120
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1564150871
Short name	T743
Test name
Test status
Simulation time	1707747405 ps
CPU time	10.78 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:46:03 PM PDT 24
Peak memory	202012 kb
Host	smart-74552b83-30e8-4fb9-8e9a-aaf424e626e4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1564150871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1564150871
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2711425225
Short name	T712
Test name
Test status
Simulation time	9732001 ps
CPU time	1.17 seconds
Started	May 30 12:45:52 PM PDT 24
Finished	May 30 12:45:55 PM PDT 24
Peak memory	201892 kb
Host	smart-b4047b1d-cf2f-4323-8059-9d336fb38305
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711425225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2711425225
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.553573848
Short name	T375
Test name
Test status
Simulation time	1314535071 ps
CPU time	8.07 seconds
Started	May 30 12:46:05 PM PDT 24
Finished	May 30 12:46:14 PM PDT 24
Peak memory	201996 kb
Host	smart-cd86dac2-6e17-4a68-8dcb-04f2a6cbfef1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=553573848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.553573848
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3519657010
Short name	T439
Test name
Test status
Simulation time	343920398 ps
CPU time	6.65 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:12 PM PDT 24
Peak memory	201960 kb
Host	smart-2369d190-67d0-47f9-97e4-adfc23dd3f70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3519657010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3519657010
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1460172159
Short name	T130
Test name
Test status
Simulation time	637042979 ps
CPU time	58.81 seconds
Started	May 30 12:46:06 PM PDT 24
Finished	May 30 12:47:06 PM PDT 24
Peak memory	203944 kb
Host	smart-3e338740-75fa-4ab6-85fc-e798dc9aadbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460172159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1460172159
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.742096210
Short name	T523
Test name
Test status
Simulation time	120231783 ps
CPU time	20.69 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201904 kb
Host	smart-9935f8ed-ed4f-462c-ac6b-6f07250b80f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742096210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.742096210
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3505545043
Short name	T267
Test name
Test status
Simulation time	735854911 ps
CPU time	5.7 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:46:10 PM PDT 24
Peak memory	201924 kb
Host	smart-ee828d87-0cdd-4485-871c-a8292eb8ac2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3505545043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3505545043
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.415121607
Short name	T14
Test name
Test status
Simulation time	11251852 ps
CPU time	1.2 seconds
Started	May 30 12:46:05 PM PDT 24
Finished	May 30 12:46:07 PM PDT 24
Peak memory	201904 kb
Host	smart-709fcb19-b8bb-426e-ba3e-68c4c9e74f65
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=415121607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.415121607
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.980760436
Short name	T107
Test name
Test status
Simulation time	28838223797 ps
CPU time	195.72 seconds
Started	May 30 12:46:08 PM PDT 24
Finished	May 30 12:49:25 PM PDT 24
Peak memory	203232 kb
Host	smart-ddebfac4-efc2-4922-9ab2-71c7694290fc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=980760436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.980760436
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2924680989
Short name	T427
Test name
Test status
Simulation time	414968503 ps
CPU time	4.34 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	201976 kb
Host	smart-7fa55854-41ec-4fa2-910d-e50f3b4e5655
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2924680989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2924680989
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.2507476860
Short name	T894
Test name
Test status
Simulation time	710299592 ps
CPU time	5.21 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	201980 kb
Host	smart-12a60d90-ff13-4eb0-ad44-026a34a45d79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2507476860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2507476860
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.1243446216
Short name	T337
Test name
Test status
Simulation time	57954143 ps
CPU time	5.38 seconds
Started	May 30 12:46:05 PM PDT 24
Finished	May 30 12:46:11 PM PDT 24
Peak memory	201980 kb
Host	smart-81ed9069-ad31-49df-a257-4f8bc56a644e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1243446216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1243446216
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1453897574
Short name	T534
Test name
Test status
Simulation time	26579082979 ps
CPU time	107.61 seconds
Started	May 30 12:46:03 PM PDT 24
Finished	May 30 12:47:51 PM PDT 24
Peak memory	202076 kb
Host	smart-97b89ccc-c54b-41a6-a526-7bbe246ee513
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453897574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1453897574
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.905544172
Short name	T866
Test name
Test status
Simulation time	33284022426 ps
CPU time	163.13 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:48:48 PM PDT 24
Peak memory	201992 kb
Host	smart-8b75c36d-8f59-4311-ade4-2721073887dc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=905544172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.905544172
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2817217135
Short name	T592
Test name
Test status
Simulation time	27739273 ps
CPU time	3.27 seconds
Started	May 30 12:46:07 PM PDT 24
Finished	May 30 12:46:11 PM PDT 24
Peak memory	201908 kb
Host	smart-e964f0ea-5a63-4e6d-b5f8-796d87a477b1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817217135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2817217135
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.3613811025
Short name	T456
Test name
Test status
Simulation time	1194764900 ps
CPU time	8.69 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:29 PM PDT 24
Peak memory	201948 kb
Host	smart-6af726ec-102b-4005-8b0b-6e19731173e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3613811025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3613811025
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.378517364
Short name	T852
Test name
Test status
Simulation time	125959040 ps
CPU time	1.57 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:07 PM PDT 24
Peak memory	202004 kb
Host	smart-e423c110-c324-4e9f-841c-4e06fc63b330
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=378517364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.378517364
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3934149334
Short name	T484
Test name
Test status
Simulation time	2323172206 ps
CPU time	6.32 seconds
Started	May 30 12:46:08 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	202064 kb
Host	smart-b9b0c5f9-663e-4958-a50d-b3cc29075770
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934149334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3934149334
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.967113643
Short name	T812
Test name
Test status
Simulation time	6181095497 ps
CPU time	9.51 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	202056 kb
Host	smart-2a56e265-17ab-4d6a-bad3-e494ba9b06d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=967113643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.967113643
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1355452598
Short name	T32
Test name
Test status
Simulation time	14521495 ps
CPU time	1.23 seconds
Started	May 30 12:46:04 PM PDT 24
Finished	May 30 12:46:07 PM PDT 24
Peak memory	202040 kb
Host	smart-04da9e29-c072-446f-a46f-0562b5d17e44
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355452598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1355452598
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.1547105969
Short name	T578
Test name
Test status
Simulation time	3817212752 ps
CPU time	64.82 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:47:28 PM PDT 24
Peak memory	203644 kb
Host	smart-2fb28d2b-3df9-485f-8f91-a5adb12d5ba6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1547105969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1547105969
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4277653000
Short name	T884
Test name
Test status
Simulation time	2558832265 ps
CPU time	29.72 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	201808 kb
Host	smart-b7ff64f9-724f-4d1d-9950-5a185193c8e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4277653000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4277653000
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.878377330
Short name	T360
Test name
Test status
Simulation time	221537604 ps
CPU time	15.54 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:36 PM PDT 24
Peak memory	203012 kb
Host	smart-8c51025e-7067-4ba7-9f50-d7ff63422cc9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=878377330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.878377330
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3940353219
Short name	T486
Test name
Test status
Simulation time	3978553349 ps
CPU time	116.98 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	204924 kb
Host	smart-e1e8ca33-7ed9-4b2a-9a1f-2d6fd037b447
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940353219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3940353219
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1885225427
Short name	T890
Test name
Test status
Simulation time	1177290545 ps
CPU time	6.11 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:28 PM PDT 24
Peak memory	201736 kb
Host	smart-8bee4c56-f9f6-4304-b289-099d08061856
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1885225427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1885225427
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.4065459994
Short name	T114
Test name
Test status
Simulation time	154757392 ps
CPU time	3.61 seconds
Started	May 30 12:46:17 PM PDT 24
Finished	May 30 12:46:22 PM PDT 24
Peak memory	202040 kb
Host	smart-6187fcfe-8179-4bd3-9b83-685b5ca7a19b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4065459994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.4065459994
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.643289398
Short name	T356
Test name
Test status
Simulation time	55781868 ps
CPU time	1.58 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:46:20 PM PDT 24
Peak memory	202008 kb
Host	smart-262e5344-30e1-4a16-ad7b-611795fef618
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=643289398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.643289398
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.1191127259
Short name	T189
Test name
Test status
Simulation time	429323664 ps
CPU time	5.35 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201996 kb
Host	smart-21542b27-c79c-40fc-9ed0-97c2a54a46eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1191127259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1191127259
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.412770392
Short name	T176
Test name
Test status
Simulation time	810211170 ps
CPU time	8.06 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:29 PM PDT 24
Peak memory	201840 kb
Host	smart-0475e0bf-f06e-4eef-a170-a823e1d2d33d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=412770392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.412770392
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2631342241
Short name	T345
Test name
Test status
Simulation time	36331349728 ps
CPU time	132.98 seconds
Started	May 30 12:46:17 PM PDT 24
Finished	May 30 12:48:31 PM PDT 24
Peak memory	201980 kb
Host	smart-1af97ae8-f5ee-45e1-90ec-0de6de189e7e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631342241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2631342241
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3455724871
Short name	T71
Test name
Test status
Simulation time	34310130415 ps
CPU time	172.84 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:49:11 PM PDT 24
Peak memory	201996 kb
Host	smart-8188c399-bb9b-4de8-afb5-4375423ab79f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3455724871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3455724871
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.7566366
Short name	T690
Test name
Test status
Simulation time	90123490 ps
CPU time	6.89 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:28 PM PDT 24
Peak memory	201980 kb
Host	smart-0d7aa3b8-e7e0-415b-bd03-597f6172e081
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7566366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.7566366
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.284909894
Short name	T693
Test name
Test status
Simulation time	2294227885 ps
CPU time	10.51 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:32 PM PDT 24
Peak memory	201984 kb
Host	smart-d6e689b0-1d20-45ec-a559-cf4b3b33cd40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=284909894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.284909894
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.2313180925
Short name	T177
Test name
Test status
Simulation time	275260512 ps
CPU time	1.48 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:23 PM PDT 24
Peak memory	201984 kb
Host	smart-a9b5dc72-6cdd-4be8-8b04-1f19745ab09d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313180925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2313180925
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3124648769
Short name	T673
Test name
Test status
Simulation time	3687266864 ps
CPU time	9.74 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:32 PM PDT 24
Peak memory	201992 kb
Host	smart-6dee685a-dff4-410a-8727-f72ebaba14f9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124648769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3124648769
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4086571504
Short name	T670
Test name
Test status
Simulation time	7992400433 ps
CPU time	8.54 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:46:33 PM PDT 24
Peak memory	201992 kb
Host	smart-0b5c6a0c-5fbe-4ce1-9e26-1b783ca09494
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4086571504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4086571504
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.667481621
Short name	T54
Test name
Test status
Simulation time	13178259 ps
CPU time	1.04 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:21 PM PDT 24
Peak memory	201992 kb
Host	smart-0cb00b45-d604-4a38-9bd1-b92e48657494
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667481621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.667481621
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.917804710
Short name	T480
Test name
Test status
Simulation time	7971740072 ps
CPU time	109.84 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:48:09 PM PDT 24
Peak memory	204712 kb
Host	smart-539815e4-053b-47c5-9ec3-97ebcdcd8ece
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=917804710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.917804710
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.430571478
Short name	T561
Test name
Test status
Simulation time	2974132524 ps
CPU time	32.57 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	202028 kb
Host	smart-2ae898d5-ace8-452b-80d5-a77a0378c1db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=430571478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.430571478
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1991052347
Short name	T699
Test name
Test status
Simulation time	825232309 ps
CPU time	67.34 seconds
Started	May 30 12:46:17 PM PDT 24
Finished	May 30 12:47:25 PM PDT 24
Peak memory	204120 kb
Host	smart-86d0c94a-c7af-49c7-8e71-ab575f66be47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1991052347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.1991052347
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3700399771
Short name	T225
Test name
Test status
Simulation time	543338383 ps
CPU time	53.12 seconds
Started	May 30 12:46:17 PM PDT 24
Finished	May 30 12:47:11 PM PDT 24
Peak memory	204468 kb
Host	smart-d5ef5236-ac1a-4b4c-ad5b-0e3d063682fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700399771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3700399771
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1992514691
Short name	T29
Test name
Test status
Simulation time	1269972335 ps
CPU time	6.39 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:27 PM PDT 24
Peak memory	201972 kb
Host	smart-5df47f45-cad8-4e47-b751-cc886b3e0355
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1992514691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1992514691
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3524861844
Short name	T509
Test name
Test status
Simulation time	27338591 ps
CPU time	4.91 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:27 PM PDT 24
Peak memory	201992 kb
Host	smart-3b45f7d2-7099-4466-aded-a151e0658c5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524861844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3524861844
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.451104262
Short name	T208
Test name
Test status
Simulation time	85596427156 ps
CPU time	174.34 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:49:17 PM PDT 24
Peak memory	203076 kb
Host	smart-c734dc99-ac26-4d8d-a0c9-90b781f6f02b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=451104262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.451104262
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3791476476
Short name	T475
Test name
Test status
Simulation time	481472600 ps
CPU time	2.45 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:23 PM PDT 24
Peak memory	201912 kb
Host	smart-0d8298f0-0b72-4bd7-8888-76f32fad0210
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3791476476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3791476476
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.4116778173
Short name	T718
Test name
Test status
Simulation time	274406327 ps
CPU time	5.77 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	201992 kb
Host	smart-34fd8939-c65e-416d-bcbc-3219a2a5bfb3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4116778173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4116778173
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.3022054210
Short name	T100
Test name
Test status
Simulation time	10139679 ps
CPU time	1.21 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:46:19 PM PDT 24
Peak memory	201976 kb
Host	smart-ed07bab6-76ac-4376-bbed-18bbe24434cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3022054210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3022054210
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3823215647
Short name	T38
Test name
Test status
Simulation time	41318304955 ps
CPU time	155.2 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:49:00 PM PDT 24
Peak memory	201924 kb
Host	smart-be98036c-bc62-42e6-92ff-474583e3e9ee
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823215647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3823215647
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.791430709
Short name	T874
Test name
Test status
Simulation time	80313739947 ps
CPU time	160.27 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:49:02 PM PDT 24
Peak memory	202032 kb
Host	smart-270bed7c-477b-4355-a815-1f3b6fd10e7d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=791430709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.791430709
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1141385247
Short name	T660
Test name
Test status
Simulation time	30721830 ps
CPU time	2.6 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:27 PM PDT 24
Peak memory	201852 kb
Host	smart-9b47b88c-23ec-499c-b405-b8a8fdb9dcca
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141385247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1141385247
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.3094097551
Short name	T238
Test name
Test status
Simulation time	2245902040 ps
CPU time	11.77 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:46:30 PM PDT 24
Peak memory	202068 kb
Host	smart-daedfebe-f6f2-4f07-af87-6f73c0b0bee1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094097551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3094097551
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.1683236852
Short name	T249
Test name
Test status
Simulation time	13241219 ps
CPU time	1.35 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:21 PM PDT 24
Peak memory	201912 kb
Host	smart-d9508318-0c53-4df4-b0e2-f30f808c6069
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683236852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1683236852
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.327050614
Short name	T388
Test name
Test status
Simulation time	1421022639 ps
CPU time	7.19 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:27 PM PDT 24
Peak memory	202004 kb
Host	smart-10e5c9e2-8107-4a23-a042-f648b52e0cec
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=327050614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.327050614
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3714731059
Short name	T634
Test name
Test status
Simulation time	3033520311 ps
CPU time	6.34 seconds
Started	May 30 12:46:17 PM PDT 24
Finished	May 30 12:46:23 PM PDT 24
Peak memory	202000 kb
Host	smart-82ab20cf-f2f7-4b7d-9daf-b38b0c590cb0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3714731059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3714731059
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1799189417
Short name	T245
Test name
Test status
Simulation time	19968188 ps
CPU time	1.18 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:22 PM PDT 24
Peak memory	202008 kb
Host	smart-29cc2957-999c-4611-add2-bee494a89576
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799189417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1799189417
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.2286898432
Short name	T729
Test name
Test status
Simulation time	1276052554 ps
CPU time	45.04 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:47:07 PM PDT 24
Peak memory	202948 kb
Host	smart-9ca7cb37-d28c-48be-a6a2-d8f1a5c6ff4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2286898432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2286898432
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1062313408
Short name	T483
Test name
Test status
Simulation time	857195654 ps
CPU time	11.1 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:33 PM PDT 24
Peak memory	201916 kb
Host	smart-a26fbe69-56f5-48b1-85ff-68f294e4fa53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1062313408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1062313408
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3283459619
Short name	T11
Test name
Test status
Simulation time	451627361 ps
CPU time	125.1 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	205844 kb
Host	smart-3ef6f55e-e5eb-4bdf-a373-5c9d453fc47e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3283459619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.3283459619
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.217143532
Short name	T224
Test name
Test status
Simulation time	1963143802 ps
CPU time	45.99 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:47:08 PM PDT 24
Peak memory	203204 kb
Host	smart-5d0a4ca1-3356-4db2-a1f4-fe0628e22cc1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=217143532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res et_error.217143532
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.416583736
Short name	T667
Test name
Test status
Simulation time	1896772132 ps
CPU time	8.02 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	201868 kb
Host	smart-90b7d510-2294-41c4-82bb-adf851eb79f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=416583736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.416583736
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.4205533567
Short name	T65
Test name
Test status
Simulation time	4728403172 ps
CPU time	16.94 seconds
Started	May 30 12:46:19 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	202076 kb
Host	smart-b392a8a8-3ab1-492e-adc8-14a7438d4231
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4205533567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.4205533567
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3866270418
Short name	T876
Test name
Test status
Simulation time	536542013 ps
CPU time	7.74 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:29 PM PDT 24
Peak memory	201916 kb
Host	smart-f7d84543-9705-4ef7-a2f9-86e6ce8d38f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3866270418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3866270418
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.3390419887
Short name	T16
Test name
Test status
Simulation time	1149071293 ps
CPU time	12.23 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:33 PM PDT 24
Peak memory	201932 kb
Host	smart-8215f2a5-af03-4852-a50e-b2d52ad6b5f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3390419887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3390419887
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.2543807263
Short name	T330
Test name
Test status
Simulation time	3487011505 ps
CPU time	10.91 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:33 PM PDT 24
Peak memory	202044 kb
Host	smart-ac283cde-f8d8-43a5-8547-4e87297e3633
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2543807263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2543807263
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.138294878
Short name	T72
Test name
Test status
Simulation time	18487383435 ps
CPU time	55.9 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:47:19 PM PDT 24
Peak memory	202044 kb
Host	smart-88c0f85d-71b5-4104-b5f2-59fc3d39d22a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=138294878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.138294878
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.381547553
Short name	T377
Test name
Test status
Simulation time	118429470 ps
CPU time	9.94 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:46:33 PM PDT 24
Peak memory	201896 kb
Host	smart-a97a377f-046f-4a47-9c6e-e421227c0b62
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381547553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.381547553
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.1059794876
Short name	T839
Test name
Test status
Simulation time	862027908 ps
CPU time	12.37 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:35 PM PDT 24
Peak memory	202012 kb
Host	smart-a523c19d-946c-47ac-81b9-340306ebf718
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1059794876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1059794876
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.2138589419
Short name	T139
Test name
Test status
Simulation time	108431440 ps
CPU time	1.54 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:24 PM PDT 24
Peak memory	201904 kb
Host	smart-58e1a636-082f-4408-a4bd-72d9708040fa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2138589419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2138589419
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1467442121
Short name	T636
Test name
Test status
Simulation time	1811474447 ps
CPU time	8.26 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:30 PM PDT 24
Peak memory	201916 kb
Host	smart-2fce9b67-346c-4b66-add0-4ab8ed284315
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467442121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1467442121
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.359541082
Short name	T284
Test name
Test status
Simulation time	5788626657 ps
CPU time	8.07 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	201972 kb
Host	smart-15a3428d-f004-4d82-9651-aecd944ad867
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=359541082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.359541082
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3240614204
Short name	T867
Test name
Test status
Simulation time	37440796 ps
CPU time	1.24 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:24 PM PDT 24
Peak memory	201976 kb
Host	smart-32524014-ea27-4cdd-8bb5-e2109e0d930c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240614204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3240614204
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.1509759166
Short name	T898
Test name
Test status
Simulation time	435054975 ps
CPU time	39.29 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:47:02 PM PDT 24
Peak memory	203028 kb
Host	smart-4316a7e6-6a44-4f31-b164-4f8bf42a9d9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1509759166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1509759166
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1255525188
Short name	T540
Test name
Test status
Simulation time	91827213 ps
CPU time	5.27 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201992 kb
Host	smart-0f7616e9-b2d2-4aa5-bae8-fa675b4e883f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1255525188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1255525188
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1841098586
Short name	T7
Test name
Test status
Simulation time	16542420869 ps
CPU time	92.48 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:47:54 PM PDT 24
Peak memory	205992 kb
Host	smart-8c5c6f5d-d94d-48da-8415-b39229ddd394
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841098586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.1841098586
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3101915407
Short name	T504
Test name
Test status
Simulation time	237110545 ps
CPU time	3.94 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	202000 kb
Host	smart-59c59fe7-4e6e-415f-b09e-7fcf781a40fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3101915407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3101915407
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1533986799
Short name	T138
Test name
Test status
Simulation time	16446823 ps
CPU time	1.71 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:46 PM PDT 24
Peak memory	202008 kb
Host	smart-340b921b-6b54-41d4-8b42-a891ffc09ac1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1533986799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1533986799
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1342883628
Short name	T875
Test name
Test status
Simulation time	34925901404 ps
CPU time	155.88 seconds
Started	May 30 12:44:44 PM PDT 24
Finished	May 30 12:47:21 PM PDT 24
Peak memory	203092 kb
Host	smart-5690f0a7-c89e-4e96-a1fb-906469e0a5c4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1342883628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1342883628
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2213439298
Short name	T806
Test name
Test status
Simulation time	420131075 ps
CPU time	3.43 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:44:45 PM PDT 24
Peak memory	202004 kb
Host	smart-f3b2c71e-cf80-45d3-8cb7-7bd361a2c452
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2213439298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2213439298
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.1514377453
Short name	T832
Test name
Test status
Simulation time	66871958 ps
CPU time	5.91 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:44:50 PM PDT 24
Peak memory	201980 kb
Host	smart-ee23dc58-5b83-45bf-811f-5648093ed059
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1514377453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1514377453
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.119782072
Short name	T709
Test name
Test status
Simulation time	367564281 ps
CPU time	7.8 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:53 PM PDT 24
Peak memory	201924 kb
Host	smart-2f149fce-cf6d-4565-97f9-b8e02462320a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=119782072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.119782072
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2638122815
Short name	T840
Test name
Test status
Simulation time	21332614611 ps
CPU time	84.42 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:46:06 PM PDT 24
Peak memory	202004 kb
Host	smart-18c88fc0-c958-4476-b0f9-4a83446d90c2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638122815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2638122815
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3140402193
Short name	T171
Test name
Test status
Simulation time	8869998958 ps
CPU time	50.68 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:45:34 PM PDT 24
Peak memory	202056 kb
Host	smart-f68e59a1-354a-4443-8a63-b1443b878ade
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3140402193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3140402193
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2799517375
Short name	T792
Test name
Test status
Simulation time	50129130 ps
CPU time	4.81 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:44:48 PM PDT 24
Peak memory	201896 kb
Host	smart-7c301e0c-6db4-4211-9fdf-57af63001478
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799517375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2799517375
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.2864433964
Short name	T324
Test name
Test status
Simulation time	1334191476 ps
CPU time	12.95 seconds
Started	May 30 12:44:47 PM PDT 24
Finished	May 30 12:45:00 PM PDT 24
Peak memory	201992 kb
Host	smart-2ac7f2af-e998-4067-a415-14ab792d1a82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864433964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2864433964
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.3994237679
Short name	T64
Test name
Test status
Simulation time	8313079 ps
CPU time	0.98 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:44:42 PM PDT 24
Peak memory	201964 kb
Host	smart-2d2b34bb-4422-4366-9bbc-c04fcbbfcaa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3994237679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3994237679
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1275352539
Short name	T414
Test name
Test status
Simulation time	3098817453 ps
CPU time	7.57 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	202064 kb
Host	smart-468fab22-8627-4c3b-b49c-ff0e35d4060a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275352539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1275352539
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3104946375
Short name	T728
Test name
Test status
Simulation time	1444988137 ps
CPU time	10.75 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201940 kb
Host	smart-68d8d2f2-47d1-43b4-b628-062bad18c673
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3104946375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3104946375
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1371078320
Short name	T465
Test name
Test status
Simulation time	8221569 ps
CPU time	1.16 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:46 PM PDT 24
Peak memory	202008 kb
Host	smart-da8fe94f-f6a1-41cc-b12f-2bac512a43f2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371078320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1371078320
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.2200338483
Short name	T204
Test name
Test status
Simulation time	2149615337 ps
CPU time	28.77 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:45:12 PM PDT 24
Peak memory	202976 kb
Host	smart-3e02c7d6-af6e-47f9-a630-da2eedd2c733
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200338483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2200338483
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2071157771
Short name	T603
Test name
Test status
Simulation time	238366503 ps
CPU time	34.67 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:45:18 PM PDT 24
Peak memory	201968 kb
Host	smart-1c80d40b-4adc-49a3-a400-7644922fa1b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2071157771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2071157771
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3884048975
Short name	T789
Test name
Test status
Simulation time	506198968 ps
CPU time	35.1 seconds
Started	May 30 12:44:44 PM PDT 24
Finished	May 30 12:45:21 PM PDT 24
Peak memory	204332 kb
Host	smart-3d430d30-84fc-482a-91fd-a869610bb049
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3884048975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3884048975
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1752342419
Short name	T13
Test name
Test status
Simulation time	259436576 ps
CPU time	26.89 seconds
Started	May 30 12:44:39 PM PDT 24
Finished	May 30 12:45:07 PM PDT 24
Peak memory	203216 kb
Host	smart-f6f65d0c-43a5-4e34-ad32-dd2a6b749d34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1752342419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1752342419
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1690785807
Short name	T794
Test name
Test status
Simulation time	2052416755 ps
CPU time	5.28 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:44:47 PM PDT 24
Peak memory	201908 kb
Host	smart-7bda7847-8b29-452a-8d12-79c245cf7be7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690785807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1690785807
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2381937165
Short name	T548
Test name
Test status
Simulation time	54032252 ps
CPU time	12.77 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:46:38 PM PDT 24
Peak memory	201908 kb
Host	smart-47c75568-45c6-4be2-9e66-f8b7d619f42b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2381937165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2381937165
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2852682013
Short name	T574
Test name
Test status
Simulation time	650988305 ps
CPU time	8.5 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:33 PM PDT 24
Peak memory	201900 kb
Host	smart-9c030f82-7e87-4ca6-82af-670f557f80f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2852682013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2852682013
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.671951748
Short name	T336
Test name
Test status
Simulation time	17911354 ps
CPU time	1.84 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201912 kb
Host	smart-77b69cbe-f9b3-4b3e-84c3-876a8f744e86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=671951748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.671951748
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.3332107992
Short name	T838
Test name
Test status
Simulation time	100023812 ps
CPU time	2.63 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	202008 kb
Host	smart-e72808f7-514d-4f5b-a343-21e2f953e885
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3332107992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3332107992
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2036225550
Short name	T763
Test name
Test status
Simulation time	41946034094 ps
CPU time	122.25 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:48:26 PM PDT 24
Peak memory	202016 kb
Host	smart-aef1e953-fc31-4299-bea2-1909469c270f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036225550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2036225550
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3193134215
Short name	T501
Test name
Test status
Simulation time	24525745060 ps
CPU time	85.84 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:47:50 PM PDT 24
Peak memory	201544 kb
Host	smart-5eb0dccd-4633-4126-af42-017c6e18574d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3193134215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3193134215
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3447648
Short name	T507
Test name
Test status
Simulation time	22517723 ps
CPU time	2.4 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:27 PM PDT 24
Peak memory	201948 kb
Host	smart-cee93421-32f6-4d4d-a650-2c21b1741f8e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3447648
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.2199074214
Short name	T733
Test name
Test status
Simulation time	328869717 ps
CPU time	5.56 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:30 PM PDT 24
Peak memory	201900 kb
Host	smart-110bc094-6b0e-4f16-97c6-f95b5e815616
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2199074214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2199074214
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.95207260
Short name	T471
Test name
Test status
Simulation time	8815209 ps
CPU time	1.05 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:46:24 PM PDT 24
Peak memory	201840 kb
Host	smart-0ea8f080-918d-46f1-a79f-10bca3f21e1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95207260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.95207260
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3166984794
Short name	T818
Test name
Test status
Simulation time	3613749937 ps
CPU time	8 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	202076 kb
Host	smart-fd28c37a-1c7c-4b58-8a73-b124089a4eb0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166984794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3166984794
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2225124935
Short name	T700
Test name
Test status
Simulation time	2523691363 ps
CPU time	14.53 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201568 kb
Host	smart-f54bf2e9-26fd-4dc3-bdda-0155447d8fa5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2225124935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2225124935
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2664558215
Short name	T740
Test name
Test status
Simulation time	8777155 ps
CPU time	1.12 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:22 PM PDT 24
Peak memory	201988 kb
Host	smart-2f406c5b-6cac-41db-9d8f-bff1d9807593
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664558215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2664558215
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.2566646698
Short name	T649
Test name
Test status
Simulation time	3149618734 ps
CPU time	60.44 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:47:26 PM PDT 24
Peak memory	201968 kb
Host	smart-bb99b397-6d69-42e1-9aec-e5faa1743933
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2566646698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2566646698
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1942505731
Short name	T433
Test name
Test status
Simulation time	2790910759 ps
CPU time	30.94 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	201980 kb
Host	smart-a19eb988-8f0f-420a-a054-321031773331
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942505731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1942505731
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2175718082
Short name	T870
Test name
Test status
Simulation time	465016171 ps
CPU time	34.51 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:59 PM PDT 24
Peak memory	204088 kb
Host	smart-12c84cdf-e47d-4143-b966-fa2bd247721c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2175718082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2175718082
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2838038425
Short name	T221
Test name
Test status
Simulation time	15081548001 ps
CPU time	116.5 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:48:19 PM PDT 24
Peak memory	205120 kb
Host	smart-488f91c9-2b4c-48e2-9d31-c9657d44f1bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2838038425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2838038425
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.926533093
Short name	T265
Test name
Test status
Simulation time	949745125 ps
CPU time	12.37 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:36 PM PDT 24
Peak memory	201916 kb
Host	smart-74c87e9c-074e-4939-874e-b35cf7b3689d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=926533093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.926533093
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1956570336
Short name	T796
Test name
Test status
Simulation time	623459970 ps
CPU time	9.42 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:46:34 PM PDT 24
Peak memory	201972 kb
Host	smart-ce44042f-dc57-44f9-b54e-b9d663380334
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956570336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1956570336
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.277230242
Short name	T212
Test name
Test status
Simulation time	22515842078 ps
CPU time	173.93 seconds
Started	May 30 12:46:18 PM PDT 24
Finished	May 30 12:49:13 PM PDT 24
Peak memory	203012 kb
Host	smart-caa777db-d73f-40c2-899a-346b5832965e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=277230242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.277230242
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.882353240
Short name	T626
Test name
Test status
Simulation time	1712020352 ps
CPU time	10.66 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:43 PM PDT 24
Peak memory	202008 kb
Host	smart-c73179d0-f33b-4aad-9cfe-f03feef92f11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=882353240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.882353240
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.1551389666
Short name	T631
Test name
Test status
Simulation time	175844980 ps
CPU time	7.5 seconds
Started	May 30 12:46:22 PM PDT 24
Finished	May 30 12:46:31 PM PDT 24
Peak memory	201968 kb
Host	smart-fbd4a10b-c9e3-47fc-ac3a-13627d32d8d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1551389666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1551389666
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.1812306691
Short name	T881
Test name
Test status
Simulation time	133956614 ps
CPU time	7.13 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:46:32 PM PDT 24
Peak memory	201892 kb
Host	smart-220a128f-c901-4968-8f91-f281defcd91a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1812306691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1812306691
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.846540630
Short name	T731
Test name
Test status
Simulation time	23842212622 ps
CPU time	92.62 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:47:58 PM PDT 24
Peak memory	202020 kb
Host	smart-1377aa6b-13ce-4b50-ab4a-901ce50ef431
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=846540630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.846540630
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2637265950
Short name	T325
Test name
Test status
Simulation time	9587321319 ps
CPU time	76.02 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	201964 kb
Host	smart-a6c95bf2-3e39-49e1-a1cc-b5a97ae76a22
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2637265950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2637265950
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.577972089
Short name	T614
Test name
Test status
Simulation time	15446675 ps
CPU time	1.88 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201996 kb
Host	smart-8d2a63e4-a64b-4a65-8daa-4b9e33769ed9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577972089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.577972089
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.1553425696
Short name	T385
Test name
Test status
Simulation time	402117926 ps
CPU time	5.2 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201908 kb
Host	smart-f00371d9-cd31-4ff2-bd77-a0174ac8d83c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1553425696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1553425696
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.1231116906
Short name	T477
Test name
Test status
Simulation time	11302316 ps
CPU time	1.16 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:46:26 PM PDT 24
Peak memory	201888 kb
Host	smart-48d6f99e-f11f-40e0-aed2-170fc04620ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1231116906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1231116906
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3060219589
Short name	T182
Test name
Test status
Simulation time	8844447505 ps
CPU time	14.38 seconds
Started	May 30 12:46:24 PM PDT 24
Finished	May 30 12:46:40 PM PDT 24
Peak memory	201960 kb
Host	smart-ab5609ee-c642-49cb-b148-f67520a97fb4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060219589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3060219589
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1040944482
Short name	T478
Test name
Test status
Simulation time	2670970108 ps
CPU time	6.81 seconds
Started	May 30 12:46:21 PM PDT 24
Finished	May 30 12:46:29 PM PDT 24
Peak memory	201976 kb
Host	smart-fda15305-f752-485d-9d8d-4d55ba3ac61d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1040944482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1040944482
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3320728489
Short name	T436
Test name
Test status
Simulation time	7724893 ps
CPU time	1.04 seconds
Started	May 30 12:46:23 PM PDT 24
Finished	May 30 12:46:25 PM PDT 24
Peak memory	201900 kb
Host	smart-509d1f92-582d-48b0-a289-e06b2820fa4c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320728489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3320728489
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.460837840
Short name	T804
Test name
Test status
Simulation time	1237492302 ps
CPU time	10.92 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:44 PM PDT 24
Peak memory	201948 kb
Host	smart-2c7e2c13-61fa-448d-a676-8c6b79ae9e1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=460837840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.460837840
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1679555337
Short name	T431
Test name
Test status
Simulation time	893877158 ps
CPU time	13.33 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	202000 kb
Host	smart-592ac2d3-09ef-4d9e-8ba2-6d0a2a4ba585
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1679555337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1679555337
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.308376535
Short name	T859
Test name
Test status
Simulation time	9615415329 ps
CPU time	140.83 seconds
Started	May 30 12:46:31 PM PDT 24
Finished	May 30 12:48:53 PM PDT 24
Peak memory	204448 kb
Host	smart-755ffa53-31e7-45c3-8d55-ccb2e288cac8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308376535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand _reset.308376535
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3420109066
Short name	T417
Test name
Test status
Simulation time	69922246 ps
CPU time	7.26 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	202012 kb
Host	smart-1c36fcbf-3f1d-4aaf-81a8-d5c396264940
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3420109066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.3420109066
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4149322876
Short name	T140
Test name
Test status
Simulation time	516880032 ps
CPU time	7.52 seconds
Started	May 30 12:46:20 PM PDT 24
Finished	May 30 12:46:28 PM PDT 24
Peak memory	201904 kb
Host	smart-304f7c4b-b797-4da4-9525-ef48afd719d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4149322876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4149322876
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1068165419
Short name	T205
Test name
Test status
Simulation time	1027881707 ps
CPU time	9.52 seconds
Started	May 30 12:46:31 PM PDT 24
Finished	May 30 12:46:41 PM PDT 24
Peak memory	201980 kb
Host	smart-c893cf1c-f36a-4aad-95e8-6b0264252725
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1068165419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1068165419
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3854479259
Short name	T194
Test name
Test status
Simulation time	23559423682 ps
CPU time	128.86 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:48:49 PM PDT 24
Peak memory	202864 kb
Host	smart-ef8fd9ed-81ce-4f3f-95d6-a1abc3df62e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3854479259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.3854479259
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1646225143
Short name	T233
Test name
Test status
Simulation time	58033246 ps
CPU time	1.3 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:36 PM PDT 24
Peak memory	202008 kb
Host	smart-91a66aa9-e2f1-4fcf-96c8-c4b39c18fe83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646225143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1646225143
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.600879566
Short name	T588
Test name
Test status
Simulation time	128688845 ps
CPU time	2.05 seconds
Started	May 30 12:46:31 PM PDT 24
Finished	May 30 12:46:34 PM PDT 24
Peak memory	201896 kb
Host	smart-80af9621-9875-4cc1-82b1-c8f1913081b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=600879566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.600879566
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.1457263722
Short name	T153
Test name
Test status
Simulation time	79232225 ps
CPU time	5.65 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201988 kb
Host	smart-f468af9f-7ce8-4837-94f3-e96699025cba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1457263722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1457263722
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2979593762
Short name	T83
Test name
Test status
Simulation time	7200561888 ps
CPU time	32.17 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:47:06 PM PDT 24
Peak memory	202088 kb
Host	smart-3358d886-7190-45d0-a0f5-41ba3874c7e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979593762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2979593762
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2246215983
Short name	T694
Test name
Test status
Simulation time	29161845204 ps
CPU time	95.77 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	202068 kb
Host	smart-43b62ee9-9f49-44dd-b4a9-e07b4fa632ed
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2246215983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2246215983
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2259474298
Short name	T525
Test name
Test status
Simulation time	67736149 ps
CPU time	6.25 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:40 PM PDT 24
Peak memory	201900 kb
Host	smart-4a563cf1-7586-410c-948d-fce63e331a4f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259474298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2259474298
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.858313868
Short name	T755
Test name
Test status
Simulation time	665748424 ps
CPU time	2.79 seconds
Started	May 30 12:46:30 PM PDT 24
Finished	May 30 12:46:34 PM PDT 24
Peak memory	202040 kb
Host	smart-8de91d9a-529e-4861-ac8d-dbf64555faa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858313868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.858313868
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.1677975531
Short name	T322
Test name
Test status
Simulation time	84543716 ps
CPU time	1.35 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:34 PM PDT 24
Peak memory	201872 kb
Host	smart-6fcdd83a-5ca9-415f-a772-ef101a0a5ca7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1677975531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1677975531
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1711276600
Short name	T310
Test name
Test status
Simulation time	2905882207 ps
CPU time	11.95 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	202020 kb
Host	smart-a5ba0d90-dab2-478b-976e-b5018bb390d5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711276600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1711276600
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2367056308
Short name	T105
Test name
Test status
Simulation time	948390308 ps
CPU time	5.83 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:40 PM PDT 24
Peak memory	202004 kb
Host	smart-8eabfec9-5bed-4445-96bb-93eed3cb2a60
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2367056308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2367056308
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1659577676
Short name	T570
Test name
Test status
Simulation time	8503202 ps
CPU time	1.11 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	201964 kb
Host	smart-2e922c42-c755-4831-a393-89bba64d0389
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659577676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1659577676
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.2639350281
Short name	T203
Test name
Test status
Simulation time	5515180955 ps
CPU time	69.92 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	204744 kb
Host	smart-d0050dc7-14e4-4a31-9e1d-ca4f065e1e24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639350281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2639350281
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1559730564
Short name	T498
Test name
Test status
Simulation time	24165438985 ps
CPU time	44.44 seconds
Started	May 30 12:46:30 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	202032 kb
Host	smart-76c7f232-007c-4632-8d05-1d05cce8120e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1559730564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1559730564
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1201814186
Short name	T635
Test name
Test status
Simulation time	83541250 ps
CPU time	13.67 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201928 kb
Host	smart-f2f22082-c300-4b47-aa0c-1e9ee2c9b668
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1201814186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1201814186
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2968479000
Short name	T557
Test name
Test status
Simulation time	113844197 ps
CPU time	3.83 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	201924 kb
Host	smart-0f6fce6f-a327-4c18-aced-8229f7bee88c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2968479000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2968479000
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.594045059
Short name	T706
Test name
Test status
Simulation time	203519424 ps
CPU time	9.26 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	202008 kb
Host	smart-8f32cbc5-7105-44ef-8ac6-a86104b41272
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=594045059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.594045059
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3548521217
Short name	T179
Test name
Test status
Simulation time	37891238536 ps
CPU time	185.48 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:49:39 PM PDT 24
Peak memory	203488 kb
Host	smart-068ec8b5-889c-40ed-a0f6-7462176943b8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3548521217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3548521217
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.774175179
Short name	T2
Test name
Test status
Simulation time	726710384 ps
CPU time	7.48 seconds
Started	May 30 12:46:34 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	202000 kb
Host	smart-3b3f2002-388e-423f-b02d-c09073db0b3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=774175179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.774175179
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.3708019105
Short name	T538
Test name
Test status
Simulation time	339875142 ps
CPU time	4.22 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	201948 kb
Host	smart-5d53229b-7904-4561-ae53-737315847414
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3708019105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3708019105
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.1173515124
Short name	T386
Test name
Test status
Simulation time	2204123234 ps
CPU time	11.07 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	202044 kb
Host	smart-b80c3cab-5a12-48c4-8a18-dfd34eb2d53a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173515124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1173515124
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3388387266
Short name	T50
Test name
Test status
Simulation time	15796844655 ps
CPU time	52.81 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:47:27 PM PDT 24
Peak memory	201992 kb
Host	smart-085196c9-2780-4104-8459-46c2ab6c0018
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388387266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3388387266
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3205500001
Short name	T624
Test name
Test status
Simulation time	26710281893 ps
CPU time	94.77 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	201972 kb
Host	smart-31971221-970f-494b-964b-ce15699c7c6e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3205500001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3205500001
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1389440087
Short name	T272
Test name
Test status
Simulation time	17185859 ps
CPU time	2.44 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:38 PM PDT 24
Peak memory	201964 kb
Host	smart-561e3d65-333a-4189-84e4-2321b023117f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389440087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1389440087
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.466194295
Short name	T846
Test name
Test status
Simulation time	245984193 ps
CPU time	3.08 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:38 PM PDT 24
Peak memory	202008 kb
Host	smart-051934d0-3642-4d6e-9bf4-b103dcc4b219
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=466194295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.466194295
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.2466886355
Short name	T664
Test name
Test status
Simulation time	12877214 ps
CPU time	1.19 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:36 PM PDT 24
Peak memory	201984 kb
Host	smart-bef908a6-0a06-4dbb-90a9-d84e3bf47449
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2466886355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2466886355
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1176352476
Short name	T611
Test name
Test status
Simulation time	2373499248 ps
CPU time	11.88 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	201988 kb
Host	smart-5f9fdf0c-f62b-4c1f-b85e-1e88e25c2869
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176352476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1176352476
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2115809045
Short name	T474
Test name
Test status
Simulation time	1381985544 ps
CPU time	7.33 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:40 PM PDT 24
Peak memory	202016 kb
Host	smart-43909413-a365-40e7-9b63-33dfaf8db109
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2115809045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2115809045
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.149539466
Short name	T382
Test name
Test status
Simulation time	19888595 ps
CPU time	1.24 seconds
Started	May 30 12:46:34 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	201988 kb
Host	smart-8ba83154-5203-4de5-9c2d-3bf7e9c56796
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149539466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.149539466
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.535293877
Short name	T169
Test name
Test status
Simulation time	9390378775 ps
CPU time	49.88 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:47:27 PM PDT 24
Peak memory	203080 kb
Host	smart-672a75cd-157d-4c79-86e6-d1485f25b910
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=535293877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.535293877
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1951876509
Short name	T132
Test name
Test status
Simulation time	3128048862 ps
CPU time	35.62 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:47:11 PM PDT 24
Peak memory	202020 kb
Host	smart-9f9568c9-2220-494c-a343-78a52da79124
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951876509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1951876509
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4267808643
Short name	T216
Test name
Test status
Simulation time	138636391 ps
CPU time	16.95 seconds
Started	May 30 12:46:34 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	203012 kb
Host	smart-ba6d7580-8979-420d-bc26-24e7c74dba43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4267808643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.4267808643
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2646706092
Short name	T402
Test name
Test status
Simulation time	232728502 ps
CPU time	19.34 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:54 PM PDT 24
Peak memory	202968 kb
Host	smart-8200dca1-1098-45c6-a65a-e87f0958b82f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646706092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2646706092
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4289734068
Short name	T300
Test name
Test status
Simulation time	46116375 ps
CPU time	1.27 seconds
Started	May 30 12:46:34 PM PDT 24
Finished	May 30 12:46:37 PM PDT 24
Peak memory	201156 kb
Host	smart-9272c398-e6a3-46a3-a2d9-1913f48f1412
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4289734068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4289734068
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1427441026
Short name	T167
Test name
Test status
Simulation time	82417578 ps
CPU time	14.86 seconds
Started	May 30 12:46:32 PM PDT 24
Finished	May 30 12:46:48 PM PDT 24
Peak memory	201964 kb
Host	smart-b32ca2c6-c5be-4290-9f6a-dc5c6aa76c8f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1427441026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1427441026
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.437455577
Short name	T213
Test name
Test status
Simulation time	43071960389 ps
CPU time	99.06 seconds
Started	May 30 12:46:34 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	201012 kb
Host	smart-d62e9693-efb4-4e72-8b89-7ad291a07df3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=437455577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.437455577
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.846875979
Short name	T725
Test name
Test status
Simulation time	19934775 ps
CPU time	1.73 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201672 kb
Host	smart-a307765a-b2b8-43f1-b2c8-c7d7b8701930
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=846875979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.846875979
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.4034638033
Short name	T689
Test name
Test status
Simulation time	59369609 ps
CPU time	7.81 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:48 PM PDT 24
Peak memory	201464 kb
Host	smart-8dedd9c6-5447-43c2-b3b9-c6082df6a6bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4034638033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4034638033
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.2911777124
Short name	T166
Test name
Test status
Simulation time	9283112 ps
CPU time	1.11 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:41 PM PDT 24
Peak memory	202008 kb
Host	smart-a6de52bd-b0db-4104-9e1c-1eb128faf3d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2911777124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2911777124
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.521601576
Short name	T186
Test name
Test status
Simulation time	42167256900 ps
CPU time	129.4 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:48:49 PM PDT 24
Peak memory	202072 kb
Host	smart-4e68fb23-2a3c-46a8-bf3c-272ce702b496
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=521601576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.521601576
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.330897246
Short name	T601
Test name
Test status
Simulation time	30155177726 ps
CPU time	158.81 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:49:19 PM PDT 24
Peak memory	201948 kb
Host	smart-df3690cb-80e6-41fe-9ffb-ad0fae7de6e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=330897246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.330897246
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3994437666
Short name	T351
Test name
Test status
Simulation time	43536849 ps
CPU time	2.63 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201988 kb
Host	smart-0c05089b-3037-4631-b869-db7c7934084a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994437666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3994437666
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.4038526131
Short name	T425
Test name
Test status
Simulation time	77640970 ps
CPU time	2.46 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	201996 kb
Host	smart-8faf7332-47f6-4674-979c-188afe87efd9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4038526131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4038526131
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.339422691
Short name	T462
Test name
Test status
Simulation time	9742610 ps
CPU time	1.23 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:36 PM PDT 24
Peak memory	201916 kb
Host	smart-8a9e772a-dd31-4fd1-9914-1c1917971ae6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=339422691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.339422691
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1645076080
Short name	T704
Test name
Test status
Simulation time	1981753638 ps
CPU time	6.13 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	202012 kb
Host	smart-215f7be3-a218-4aed-a38a-97b5189d31e4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645076080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1645076080
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2208687275
Short name	T241
Test name
Test status
Simulation time	1991491489 ps
CPU time	5.2 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	202000 kb
Host	smart-df0fc453-da42-44e2-a545-f5cf34597052
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2208687275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2208687275
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3292774634
Short name	T183
Test name
Test status
Simulation time	8782816 ps
CPU time	1.14 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201992 kb
Host	smart-751d2a35-f715-4b23-b625-08f6f9b058b1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292774634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3292774634
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.844993937
Short name	T148
Test name
Test status
Simulation time	21057660079 ps
CPU time	67.26 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	205156 kb
Host	smart-10267957-87f9-4056-acef-16bdb478ed20
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=844993937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.844993937
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1733786349
Short name	T862
Test name
Test status
Simulation time	1014793623 ps
CPU time	24.79 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:47:03 PM PDT 24
Peak memory	201972 kb
Host	smart-eee39da2-2e86-4493-b9f2-ccd1c00ab586
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1733786349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1733786349
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1467083801
Short name	T857
Test name
Test status
Simulation time	3411180379 ps
CPU time	72.98 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:47:51 PM PDT 24
Peak memory	204476 kb
Host	smart-ca1358de-46f1-4603-874b-e4ca7cd640b9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467083801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1467083801
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.478211918
Short name	T75
Test name
Test status
Simulation time	381811681 ps
CPU time	51.9 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:47:30 PM PDT 24
Peak memory	203688 kb
Host	smart-59eebb64-15c9-48d5-9151-a9255c39216a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=478211918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.478211918
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1680243277
Short name	T401
Test name
Test status
Simulation time	34575221 ps
CPU time	4.11 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:43 PM PDT 24
Peak memory	201984 kb
Host	smart-cdb56599-cc3c-4fda-9cc5-73f302ac4741
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680243277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1680243277
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3764682209
Short name	T303
Test name
Test status
Simulation time	95667421 ps
CPU time	5.11 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:41 PM PDT 24
Peak memory	202012 kb
Host	smart-e46286e3-8ff2-48a0-925c-d23481fc41f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3764682209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3764682209
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.4123855516
Short name	T551
Test name
Test status
Simulation time	9275849197 ps
CPU time	15.13 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	201596 kb
Host	smart-cc1997a1-dae2-4987-883d-898931c9dc2c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4123855516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.4123855516
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4268227882
Short name	T306
Test name
Test status
Simulation time	25681520 ps
CPU time	2.33 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:41 PM PDT 24
Peak memory	201940 kb
Host	smart-a15ce14a-dda9-4163-81ae-c86e1bb9cfae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4268227882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4268227882
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.3456163136
Short name	T180
Test name
Test status
Simulation time	795551514 ps
CPU time	13.23 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:46:49 PM PDT 24
Peak memory	201992 kb
Host	smart-24da059f-85c6-42b6-a4e0-7193720a83c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3456163136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3456163136
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.3357438215
Short name	T420
Test name
Test status
Simulation time	1405908308 ps
CPU time	13.98 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201968 kb
Host	smart-d6fc6387-b999-4ea8-a947-76a3cdfd12da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3357438215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3357438215
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3853553834
Short name	T833
Test name
Test status
Simulation time	15431728239 ps
CPU time	57.39 seconds
Started	May 30 12:46:35 PM PDT 24
Finished	May 30 12:47:33 PM PDT 24
Peak memory	202080 kb
Host	smart-970417ee-9d0b-43ed-80d7-f111d359a2ae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853553834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3853553834
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2721137757
Short name	T82
Test name
Test status
Simulation time	173263466228 ps
CPU time	144.55 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:48:59 PM PDT 24
Peak memory	202056 kb
Host	smart-7adb5402-6f56-46ff-b22f-496deefdef2d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2721137757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2721137757
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3948724896
Short name	T566
Test name
Test status
Simulation time	65275722 ps
CPU time	8.72 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:49 PM PDT 24
Peak memory	201868 kb
Host	smart-ee8fea1a-88da-4bfe-bafd-cfb16d4c2168
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948724896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3948724896
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.2348416732
Short name	T559
Test name
Test status
Simulation time	149495911 ps
CPU time	6.15 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	201884 kb
Host	smart-9960a2cc-95d1-48f9-a129-f59f6d1e064a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348416732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2348416732
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.1609740672
Short name	T84
Test name
Test status
Simulation time	82501756 ps
CPU time	1.68 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201984 kb
Host	smart-8f83563e-63a8-4c07-8030-786699029f7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1609740672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1609740672
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.950531122
Short name	T437
Test name
Test status
Simulation time	4311930703 ps
CPU time	7.21 seconds
Started	May 30 12:46:34 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	202072 kb
Host	smart-6da58af7-00b2-4517-97df-936868370555
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=950531122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.950531122
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2991188428
Short name	T343
Test name
Test status
Simulation time	1910553996 ps
CPU time	10.21 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201972 kb
Host	smart-d1a67179-941d-49be-874c-dbefc3eb9e4d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2991188428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2991188428
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.130980794
Short name	T521
Test name
Test status
Simulation time	8758443 ps
CPU time	1.1 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:41 PM PDT 24
Peak memory	201888 kb
Host	smart-84ec7dd8-0fbb-4c99-9efd-fa6908724ccd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130980794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.130980794
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.3383174676
Short name	T286
Test name
Test status
Simulation time	818458431 ps
CPU time	6.82 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201988 kb
Host	smart-45bd0527-b407-4b06-9709-2697fc5d375f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3383174676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3383174676
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.546320296
Short name	T791
Test name
Test status
Simulation time	1176133033 ps
CPU time	22.18 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:47:03 PM PDT 24
Peak memory	201920 kb
Host	smart-0e3e47d2-143b-402c-a047-523815664f98
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546320296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.546320296
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2282860343
Short name	T60
Test name
Test status
Simulation time	102728211 ps
CPU time	12.84 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:53 PM PDT 24
Peak memory	201996 kb
Host	smart-aa3be3e9-f965-4f44-b792-c776cb307db1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282860343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.2282860343
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1017586183
Short name	T10
Test name
Test status
Simulation time	350332945 ps
CPU time	70.45 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:47:49 PM PDT 24
Peak memory	206236 kb
Host	smart-8c0d33f5-32af-4203-8bfa-238ceaeee491
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017586183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1017586183
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2236194862
Short name	T864
Test name
Test status
Simulation time	666077204 ps
CPU time	7.26 seconds
Started	May 30 12:46:38 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201988 kb
Host	smart-27392448-1b10-49e7-a19b-64c3b425d163
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2236194862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2236194862
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.442954008
Short name	T68
Test name
Test status
Simulation time	121786410 ps
CPU time	1.9 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	201872 kb
Host	smart-5b6c59ee-4180-4f1a-b83d-7b31b28956e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=442954008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.442954008
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1797144122
Short name	T780
Test name
Test status
Simulation time	6154302555 ps
CPU time	37.55 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:47:18 PM PDT 24
Peak memory	201916 kb
Host	smart-dbeec87c-6daf-4c41-a4e0-cd1ddd95d330
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1797144122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1797144122
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1699870692
Short name	T618
Test name
Test status
Simulation time	675511668 ps
CPU time	8.8 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:49 PM PDT 24
Peak memory	201948 kb
Host	smart-edce79f9-fe81-41b1-bf3d-b84d5b648bbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699870692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1699870692
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.786236163
Short name	T630
Test name
Test status
Simulation time	226567394 ps
CPU time	2.26 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	201776 kb
Host	smart-6937dd81-92ff-4abc-8e96-b81785bca147
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=786236163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.786236163
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.187393305
Short name	T51
Test name
Test status
Simulation time	460834695 ps
CPU time	9.96 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:50 PM PDT 24
Peak memory	201956 kb
Host	smart-24afb00e-6c87-4210-909a-96bbadf515a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=187393305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.187393305
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3485018035
Short name	T716
Test name
Test status
Simulation time	68768509418 ps
CPU time	52.91 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:47:33 PM PDT 24
Peak memory	201956 kb
Host	smart-385e1f11-0012-47ba-b910-537dbc817e31
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485018035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3485018035
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1122801885
Short name	T672
Test name
Test status
Simulation time	14289391999 ps
CPU time	95.22 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	201952 kb
Host	smart-920cd3ca-7da5-4e35-88d0-5999380f95d9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1122801885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1122801885
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2385170122
Short name	T123
Test name
Test status
Simulation time	55747279 ps
CPU time	6.03 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	201948 kb
Host	smart-6abdb6ad-67b4-4bf5-b442-a6de8631eeb9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385170122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2385170122
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2426584555
Short name	T887
Test name
Test status
Simulation time	88560761 ps
CPU time	1.52 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201980 kb
Host	smart-c81fbe8f-8462-48c0-b598-5c2fb3922909
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426584555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2426584555
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.1693225672
Short name	T19
Test name
Test status
Simulation time	8415493 ps
CPU time	1.07 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201932 kb
Host	smart-782142d7-3bcf-4200-a4a3-5bd28842ed93
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1693225672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1693225672
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1238997790
Short name	T355
Test name
Test status
Simulation time	1819528737 ps
CPU time	8.52 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:49 PM PDT 24
Peak memory	201960 kb
Host	smart-5eba916c-b740-4bed-8db4-3fdfb0fbca52
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238997790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1238997790
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1861007036
Short name	T127
Test name
Test status
Simulation time	1141457209 ps
CPU time	4.9 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	201956 kb
Host	smart-6ba6359b-4d06-4c48-a91c-2f33c78fd64b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1861007036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1861007036
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.4068707117
Short name	T443
Test name
Test status
Simulation time	7774469 ps
CPU time	1 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:41 PM PDT 24
Peak memory	201940 kb
Host	smart-3ea76924-f098-46f6-91a8-3d23e2a5ba8b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068707117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.4068707117
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.305965002
Short name	T319
Test name
Test status
Simulation time	68650636 ps
CPU time	9.13 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201948 kb
Host	smart-1a9fe455-80fd-4892-beaf-5938e2c7c9da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=305965002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.305965002
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1472350250
Short name	T827
Test name
Test status
Simulation time	637712450 ps
CPU time	41.77 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:47:20 PM PDT 24
Peak memory	202968 kb
Host	smart-b130a9f8-c8e5-455c-a510-99ba7a431cd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1472350250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1472350250
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.900379338
Short name	T152
Test name
Test status
Simulation time	7054994 ps
CPU time	1.79 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201916 kb
Host	smart-c4c2a525-8172-4430-a690-eed2625cb71a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=900379338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand _reset.900379338
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1709773686
Short name	T652
Test name
Test status
Simulation time	62484076 ps
CPU time	8.24 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	201972 kb
Host	smart-46b5632c-70b5-4e70-b2b9-c6c77e1cae61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1709773686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1709773686
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1506116286
Short name	T147
Test name
Test status
Simulation time	160624043 ps
CPU time	6.35 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:44 PM PDT 24
Peak memory	201952 kb
Host	smart-738fcc86-058d-40a5-b831-7d4a60176ca8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1506116286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1506116286
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.512190071
Short name	T366
Test name
Test status
Simulation time	70053809 ps
CPU time	5.28 seconds
Started	May 30 12:46:45 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	202000 kb
Host	smart-38f53383-120a-4c50-8958-7712c3e7a1a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=512190071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.512190071
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1437725565
Short name	T851
Test name
Test status
Simulation time	23888790150 ps
CPU time	135.84 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:49:07 PM PDT 24
Peak memory	202692 kb
Host	smart-99092631-d180-4dcc-b70e-1cd6fa12a96d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1437725565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1437725565
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1801358687
Short name	T772
Test name
Test status
Simulation time	381317903 ps
CPU time	3.99 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:46:56 PM PDT 24
Peak memory	201992 kb
Host	smart-4d08ca86-0b6e-479f-ae9d-6f35c4499e90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1801358687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1801358687
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.50609355
Short name	T756
Test name
Test status
Simulation time	2706030320 ps
CPU time	13.25 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:47:05 PM PDT 24
Peak memory	201968 kb
Host	smart-b5898b52-783d-473e-87ff-9be60491b267
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=50609355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.50609355
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.4071071366
Short name	T816
Test name
Test status
Simulation time	322364162 ps
CPU time	7.15 seconds
Started	May 30 12:46:47 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	201972 kb
Host	smart-81441b2b-b148-4eff-b658-12469fb8bbbe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4071071366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.4071071366
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2525798106
Short name	T847
Test name
Test status
Simulation time	11018401116 ps
CPU time	16.72 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:47:07 PM PDT 24
Peak memory	202040 kb
Host	smart-3a659e74-6e14-4c25-a78a-0643f3baf04c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525798106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2525798106
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1733649265
Short name	T106
Test name
Test status
Simulation time	30770511115 ps
CPU time	168.88 seconds
Started	May 30 12:46:44 PM PDT 24
Finished	May 30 12:49:34 PM PDT 24
Peak memory	201908 kb
Host	smart-87531b45-070b-45d2-9f4c-c4e2ab96866c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1733649265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1733649265
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2430684522
Short name	T822
Test name
Test status
Simulation time	120191849 ps
CPU time	5.73 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:02 PM PDT 24
Peak memory	201996 kb
Host	smart-7eb41b82-c561-4eb8-a469-52c017bbd4fd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430684522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2430684522
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.3086483709
Short name	T367
Test name
Test status
Simulation time	182981531 ps
CPU time	1.76 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201968 kb
Host	smart-f6ce075e-d995-47c7-8b2d-5601da75c1a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3086483709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3086483709
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.89409383
Short name	T529
Test name
Test status
Simulation time	11102303 ps
CPU time	1.15 seconds
Started	May 30 12:46:37 PM PDT 24
Finished	May 30 12:46:39 PM PDT 24
Peak memory	201900 kb
Host	smart-9bb1e7e8-221b-4039-8c80-de2294ff9211
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=89409383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.89409383
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2778430150
Short name	T861
Test name
Test status
Simulation time	6153276723 ps
CPU time	9.08 seconds
Started	May 30 12:46:36 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	202032 kb
Host	smart-2f4051ed-a356-4f46-8c53-caee059c13a0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778430150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2778430150
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.598481984
Short name	T78
Test name
Test status
Simulation time	2186466280 ps
CPU time	8.93 seconds
Started	May 30 12:46:33 PM PDT 24
Finished	May 30 12:46:43 PM PDT 24
Peak memory	202020 kb
Host	smart-c1a9b16c-3521-4cf1-b0b8-c42b080d9399
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=598481984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.598481984
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3668873862
Short name	T779
Test name
Test status
Simulation time	21957142 ps
CPU time	1.16 seconds
Started	May 30 12:46:39 PM PDT 24
Finished	May 30 12:46:42 PM PDT 24
Peak memory	201980 kb
Host	smart-0eeab90c-7b13-49d4-bc6e-57dc5fb5a263
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668873862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3668873862
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.413236229
Short name	T258
Test name
Test status
Simulation time	4407855638 ps
CPU time	16.01 seconds
Started	May 30 12:46:46 PM PDT 24
Finished	May 30 12:47:03 PM PDT 24
Peak memory	201988 kb
Host	smart-b9bdeb81-55b9-4020-8852-5956c6151903
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413236229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.413236229
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2548428170
Short name	T848
Test name
Test status
Simulation time	3035493806 ps
CPU time	37.63 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:47:34 PM PDT 24
Peak memory	202008 kb
Host	smart-17ccb8d4-18ae-40b4-a601-b8bb99549271
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2548428170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2548428170
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2495110008
Short name	T80
Test name
Test status
Simulation time	412439466 ps
CPU time	34.27 seconds
Started	May 30 12:46:47 PM PDT 24
Finished	May 30 12:47:22 PM PDT 24
Peak memory	204344 kb
Host	smart-7ed4e976-ea21-42b4-8836-1cd98586d7dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2495110008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.2495110008
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3196829220
Short name	T206
Test name
Test status
Simulation time	16896024220 ps
CPU time	243.26 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:50:54 PM PDT 24
Peak memory	210112 kb
Host	smart-c699c807-241f-4980-a2ed-7be28b4fc6fe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3196829220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3196829220
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2764659223
Short name	T494
Test name
Test status
Simulation time	1362682315 ps
CPU time	10.79 seconds
Started	May 30 12:46:47 PM PDT 24
Finished	May 30 12:46:59 PM PDT 24
Peak memory	201876 kb
Host	smart-e6a28e2e-dfc9-4f6e-ba4c-01a2de46de29
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2764659223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2764659223
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2419652577
Short name	T52
Test name
Test status
Simulation time	93072108 ps
CPU time	10.02 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:46:53 PM PDT 24
Peak memory	202040 kb
Host	smart-a194a5ae-5d16-4eef-ae98-f1dffe694a12
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419652577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2419652577
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2664880802
Short name	T55
Test name
Test status
Simulation time	25141686566 ps
CPU time	130.95 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:49:08 PM PDT 24
Peak memory	203092 kb
Host	smart-fd638710-0a1c-47f4-b44e-c2cef13970f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2664880802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2664880802
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3380331126
Short name	T891
Test name
Test status
Simulation time	37469171 ps
CPU time	3.52 seconds
Started	May 30 12:46:46 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201980 kb
Host	smart-a496b2c6-d642-4f18-af3e-177ecd5e1c79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3380331126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3380331126
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.3918869663
Short name	T311
Test name
Test status
Simulation time	139504112 ps
CPU time	4.09 seconds
Started	May 30 12:46:44 PM PDT 24
Finished	May 30 12:46:48 PM PDT 24
Peak memory	201992 kb
Host	smart-66f7093e-de39-4b39-9694-3d9ebfebe489
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918869663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3918869663
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.3718918619
Short name	T505
Test name
Test status
Simulation time	517921050 ps
CPU time	3.86 seconds
Started	May 30 12:46:46 PM PDT 24
Finished	May 30 12:46:50 PM PDT 24
Peak memory	201932 kb
Host	smart-449d5ca3-b2d3-49fa-aff3-b850b219778a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3718918619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3718918619
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3344222120
Short name	T287
Test name
Test status
Simulation time	48988546950 ps
CPU time	101.23 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:48:25 PM PDT 24
Peak memory	202080 kb
Host	smart-ac7b47cf-4c9a-4ccd-bc03-1cd3fa2c0b6d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344222120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3344222120
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1294968223
Short name	T708
Test name
Test status
Simulation time	6585550010 ps
CPU time	51.57 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:47:35 PM PDT 24
Peak memory	202016 kb
Host	smart-526c2e93-28c1-46c8-af21-ddc7bc684076
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1294968223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1294968223
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.309609816
Short name	T807
Test name
Test status
Simulation time	66119263 ps
CPU time	9.72 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:47:02 PM PDT 24
Peak memory	201976 kb
Host	smart-cfa350ba-abae-4113-aa89-e08bb8283535
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309609816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.309609816
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.3076586536
Short name	T773
Test name
Test status
Simulation time	1236799562 ps
CPU time	6.46 seconds
Started	May 30 12:46:45 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	201840 kb
Host	smart-aa90c133-ca81-491a-a1b8-d78a3d5b3806
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3076586536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3076586536
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.1285297438
Short name	T762
Test name
Test status
Simulation time	98515167 ps
CPU time	1.49 seconds
Started	May 30 12:46:44 PM PDT 24
Finished	May 30 12:46:46 PM PDT 24
Peak memory	201904 kb
Host	smart-d3540b48-3d3e-4cdf-8dde-daaca2df7410
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1285297438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1285297438
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.331145320
Short name	T124
Test name
Test status
Simulation time	11207035285 ps
CPU time	7.89 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	202020 kb
Host	smart-3b293750-3770-4797-bede-a2ac1defb185
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=331145320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.331145320
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3681144680
Short name	T430
Test name
Test status
Simulation time	3790221563 ps
CPU time	7.48 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201964 kb
Host	smart-ebe162b6-4d64-402f-a921-dca01dad1ffb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3681144680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3681144680
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1162255823
Short name	T499
Test name
Test status
Simulation time	15910723 ps
CPU time	1.28 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:46:58 PM PDT 24
Peak memory	201996 kb
Host	smart-8dbea73e-4962-412b-994d-06749b9435eb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162255823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1162255823
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.360760911
Short name	T648
Test name
Test status
Simulation time	24094311 ps
CPU time	3.35 seconds
Started	May 30 12:46:46 PM PDT 24
Finished	May 30 12:46:50 PM PDT 24
Peak memory	201924 kb
Host	smart-d185f066-ef5c-4f0c-9bf2-68bea1a21d77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=360760911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.360760911
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2314744313
Short name	T651
Test name
Test status
Simulation time	778852545 ps
CPU time	24.03 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	202000 kb
Host	smart-9e03909e-5ca0-4711-9ab0-1be4c195e597
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2314744313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2314744313
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.483596058
Short name	T849
Test name
Test status
Simulation time	307752888 ps
CPU time	71.98 seconds
Started	May 30 12:46:48 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	206800 kb
Host	smart-10af51bb-9fe0-4e63-85b9-eed9fbe19abc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=483596058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand _reset.483596058
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1552106437
Short name	T158
Test name
Test status
Simulation time	46162476 ps
CPU time	10.47 seconds
Started	May 30 12:46:46 PM PDT 24
Finished	May 30 12:46:58 PM PDT 24
Peak memory	201992 kb
Host	smart-aec70427-3713-4ef8-ba6d-bce6f211049b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1552106437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1552106437
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1289732983
Short name	T537
Test name
Test status
Simulation time	216789950 ps
CPU time	4.01 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:46:54 PM PDT 24
Peak memory	201968 kb
Host	smart-e26541fa-4d62-4464-97c3-b93d657ea8fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289732983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1289732983
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3924039823
Short name	T41
Test name
Test status
Simulation time	323540979 ps
CPU time	2.52 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:46:54 PM PDT 24
Peak memory	202016 kb
Host	smart-398089c3-1b3e-497c-88cd-5f78288ada02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3924039823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3924039823
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2417044793
Short name	T197
Test name
Test status
Simulation time	37418867679 ps
CPU time	148.54 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:49:13 PM PDT 24
Peak memory	203044 kb
Host	smart-1a40a84b-a320-48ba-9708-9e7bbe79bca4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2417044793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.2417044793
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3571685378
Short name	T872
Test name
Test status
Simulation time	312122332 ps
CPU time	1.43 seconds
Started	May 30 12:46:44 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201972 kb
Host	smart-7cb7874b-aadf-4e61-85f8-9e461c05f5c1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3571685378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3571685378
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.748612308
Short name	T405
Test name
Test status
Simulation time	63000435 ps
CPU time	4.75 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:46:57 PM PDT 24
Peak memory	201908 kb
Host	smart-aeff785a-6266-4b19-b4f4-99b75a5181ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=748612308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.748612308
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.2539610730
Short name	T782
Test name
Test status
Simulation time	60586191 ps
CPU time	4.78 seconds
Started	May 30 12:46:47 PM PDT 24
Finished	May 30 12:46:53 PM PDT 24
Peak memory	201492 kb
Host	smart-d61a732c-a9cf-4b96-ae4b-dc0ba106e678
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2539610730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2539610730
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3002596237
Short name	T165
Test name
Test status
Simulation time	39431514281 ps
CPU time	139.34 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:49:11 PM PDT 24
Peak memory	202056 kb
Host	smart-24f5e648-51ae-4a25-aece-a5176a0ff0f5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002596237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3002596237
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4240117375
Short name	T406
Test name
Test status
Simulation time	13805652795 ps
CPU time	42.56 seconds
Started	May 30 12:46:48 PM PDT 24
Finished	May 30 12:47:31 PM PDT 24
Peak memory	201996 kb
Host	smart-9759bf46-1c76-47b3-ade5-67a9d4115c00
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4240117375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4240117375
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.640013756
Short name	T602
Test name
Test status
Simulation time	38388076 ps
CPU time	4.98 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:47:01 PM PDT 24
Peak memory	201908 kb
Host	smart-447f602e-4feb-463b-bfed-9d62e0bd1f1a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640013756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.640013756
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.303512119
Short name	T129
Test name
Test status
Simulation time	103386367 ps
CPU time	1.57 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201976 kb
Host	smart-5c1ac8cc-9051-4f56-8ed4-5f7adbd8d3b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303512119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.303512119
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.3312571202
Short name	T379
Test name
Test status
Simulation time	8343911 ps
CPU time	1.14 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:46:53 PM PDT 24
Peak memory	201980 kb
Host	smart-3fda713a-0f2d-440d-8f7a-608efc7833e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3312571202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3312571202
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.4223184632
Short name	T445
Test name
Test status
Simulation time	1815048937 ps
CPU time	8.37 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:46:52 PM PDT 24
Peak memory	201984 kb
Host	smart-b38c2b2e-e9f3-4b2c-9fc0-0c8ee4f1f53c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223184632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.4223184632
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1450604639
Short name	T820
Test name
Test status
Simulation time	2409890632 ps
CPU time	8.71 seconds
Started	May 30 12:46:48 PM PDT 24
Finished	May 30 12:46:57 PM PDT 24
Peak memory	202044 kb
Host	smart-e00a0df4-cc21-4e89-8baa-e681776a194c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1450604639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1450604639
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2447574855
Short name	T246
Test name
Test status
Simulation time	9340362 ps
CPU time	1.08 seconds
Started	May 30 12:46:45 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201984 kb
Host	smart-e4e2a21a-e42b-4b1c-853c-86a5797f66c8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447574855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2447574855
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.4238795824
Short name	T214
Test name
Test status
Simulation time	2567898261 ps
CPU time	29.99 seconds
Started	May 30 12:46:48 PM PDT 24
Finished	May 30 12:47:18 PM PDT 24
Peak memory	203124 kb
Host	smart-872a6983-e2b6-483f-9d2f-c46a3adbf219
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4238795824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4238795824
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2103413738
Short name	T581
Test name
Test status
Simulation time	227649968 ps
CPU time	5.1 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:46:49 PM PDT 24
Peak memory	202000 kb
Host	smart-ce13333b-b0f2-48d6-867f-47b843f3c10e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103413738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2103413738
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4272295802
Short name	T33
Test name
Test status
Simulation time	1120064485 ps
CPU time	147.21 seconds
Started	May 30 12:46:46 PM PDT 24
Finished	May 30 12:49:14 PM PDT 24
Peak memory	204340 kb
Host	smart-680a41eb-b7ab-4740-b998-2e424fd1c5c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272295802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.4272295802
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.492461163
Short name	T742
Test name
Test status
Simulation time	16391195952 ps
CPU time	131.01 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:49:08 PM PDT 24
Peak memory	206192 kb
Host	smart-326d5fea-a8a7-43f3-b850-df4d5bd9538b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=492461163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res et_error.492461163
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.20278404
Short name	T676
Test name
Test status
Simulation time	105588077 ps
CPU time	6.29 seconds
Started	May 30 12:46:47 PM PDT 24
Finished	May 30 12:46:54 PM PDT 24
Peak memory	201524 kb
Host	smart-3bc6d8ea-7797-4b85-9a89-41b3d995a07a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20278404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.20278404
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2088855819
Short name	T681
Test name
Test status
Simulation time	67676499 ps
CPU time	8.26 seconds
Started	May 30 12:44:46 PM PDT 24
Finished	May 30 12:44:55 PM PDT 24
Peak memory	201996 kb
Host	smart-c819d7bd-431e-4634-aa7b-0ad77fbb19d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2088855819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2088855819
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1199673310
Short name	T493
Test name
Test status
Simulation time	131538396000 ps
CPU time	176.12 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:47:39 PM PDT 24
Peak memory	202988 kb
Host	smart-8a4ae31d-dc73-493a-b533-f45fc66ee7c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1199673310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.1199673310
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.16042625
Short name	T257
Test name
Test status
Simulation time	525819882 ps
CPU time	9.09 seconds
Started	May 30 12:44:44 PM PDT 24
Finished	May 30 12:44:55 PM PDT 24
Peak memory	201932 kb
Host	smart-7970041f-e6a3-4653-bc35-feb9399746e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=16042625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.16042625
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.2783898152
Short name	T844
Test name
Test status
Simulation time	589067909 ps
CPU time	6.64 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:44:53 PM PDT 24
Peak memory	201956 kb
Host	smart-5fa69a31-ac2e-4adf-b10f-8996e22c2336
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2783898152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2783898152
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.3829566425
Short name	T736
Test name
Test status
Simulation time	525605453 ps
CPU time	3.61 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:48 PM PDT 24
Peak memory	201928 kb
Host	smart-3f6b1976-3b4e-4a1e-b20c-52c95ee1b36a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3829566425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3829566425
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1719214244
Short name	T563
Test name
Test status
Simulation time	2185937682 ps
CPU time	9.29 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201972 kb
Host	smart-38f5f649-8eec-4133-a3e7-23c84eec19aa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719214244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1719214244
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.4062023108
Short name	T400
Test name
Test status
Simulation time	5218291850 ps
CPU time	38.58 seconds
Started	May 30 12:44:46 PM PDT 24
Finished	May 30 12:45:25 PM PDT 24
Peak memory	202056 kb
Host	smart-587c6d29-d80c-47cf-8731-24f4ae21e33d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4062023108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4062023108
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2828426200
Short name	T571
Test name
Test status
Simulation time	51655729 ps
CPU time	5.43 seconds
Started	May 30 12:44:44 PM PDT 24
Finished	May 30 12:44:50 PM PDT 24
Peak memory	201976 kb
Host	smart-5446dc02-75b0-4e3c-82f4-41126f6944d6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828426200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2828426200
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.3163287902
Short name	T658
Test name
Test status
Simulation time	1258779553 ps
CPU time	10.44 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:44:56 PM PDT 24
Peak memory	201888 kb
Host	smart-59cf3ed0-6fbc-4828-bfd1-e9e96c01fb16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163287902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3163287902
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.2287077527
Short name	T680
Test name
Test status
Simulation time	56746867 ps
CPU time	1.65 seconds
Started	May 30 12:44:40 PM PDT 24
Finished	May 30 12:44:43 PM PDT 24
Peak memory	201984 kb
Host	smart-a460bc31-3e95-4639-b785-d91eeff70db1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2287077527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2287077527
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.634709591
Short name	T783
Test name
Test status
Simulation time	3148287680 ps
CPU time	10.81 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:55 PM PDT 24
Peak memory	202056 kb
Host	smart-96f64071-32f9-42c1-b11b-814db96bc214
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=634709591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.634709591
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2335413919
Short name	T239
Test name
Test status
Simulation time	1414692524 ps
CPU time	4.98 seconds
Started	May 30 12:44:41 PM PDT 24
Finished	May 30 12:44:48 PM PDT 24
Peak memory	202036 kb
Host	smart-83cb9102-c7ea-4f2d-ad38-650a348ca8f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2335413919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2335413919
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2166102974
Short name	T313
Test name
Test status
Simulation time	12511035 ps
CPU time	1.02 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:44:44 PM PDT 24
Peak memory	201984 kb
Host	smart-c0a14a4f-6026-4b59-871a-e762077e3dc9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166102974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2166102974
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.271537637
Short name	T373
Test name
Test status
Simulation time	3104806075 ps
CPU time	26.84 seconds
Started	May 30 12:44:42 PM PDT 24
Finished	May 30 12:45:11 PM PDT 24
Peak memory	202912 kb
Host	smart-267f4670-da46-48b7-b276-840a215f07bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=271537637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.271537637
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2522088245
Short name	T641
Test name
Test status
Simulation time	15959747273 ps
CPU time	100.25 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:46:27 PM PDT 24
Peak memory	204244 kb
Host	smart-79976385-18b6-404a-9f90-7294d4a59525
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2522088245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2522088245
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2152699729
Short name	T181
Test name
Test status
Simulation time	2500031431 ps
CPU time	87.27 seconds
Started	May 30 12:44:46 PM PDT 24
Finished	May 30 12:46:15 PM PDT 24
Peak memory	205492 kb
Host	smart-1b60c05b-d1d4-4ded-995d-79c1198b9684
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2152699729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2152699729
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1438536412
Short name	T790
Test name
Test status
Simulation time	1609373432 ps
CPU time	121.88 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:46:48 PM PDT 24
Peak memory	204816 kb
Host	smart-0fb011cb-d4bc-4253-9ffd-df9403d41998
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1438536412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1438536412
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1181799659
Short name	T468
Test name
Test status
Simulation time	42991158 ps
CPU time	3.93 seconds
Started	May 30 12:44:47 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201960 kb
Host	smart-b4487502-c9ff-493e-9a18-576caed0aa0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1181799659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1181799659
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.648320709
Short name	T617
Test name
Test status
Simulation time	61349201 ps
CPU time	2.01 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:46:53 PM PDT 24
Peak memory	201924 kb
Host	smart-4214104d-4434-497e-8841-0047d4412421
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=648320709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.648320709
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1977625710
Short name	T764
Test name
Test status
Simulation time	133534241242 ps
CPU time	185.7 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:50:02 PM PDT 24
Peak memory	203040 kb
Host	smart-477d3775-763b-4979-8ca0-0aeb424c568a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1977625710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1977625710
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.201833214
Short name	T568
Test name
Test status
Simulation time	170335777 ps
CPU time	1.35 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	201928 kb
Host	smart-365f31e9-c2f5-43af-9c4d-209deab3806a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=201833214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.201833214
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.1933407092
Short name	T606
Test name
Test status
Simulation time	219301997 ps
CPU time	4.08 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:46:56 PM PDT 24
Peak memory	201796 kb
Host	smart-574ae3d7-f788-4246-a25a-19bce4380db7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1933407092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1933407092
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.2175275955
Short name	T645
Test name
Test status
Simulation time	268879021 ps
CPU time	3.74 seconds
Started	May 30 12:46:51 PM PDT 24
Finished	May 30 12:46:55 PM PDT 24
Peak memory	201912 kb
Host	smart-63d0ddda-ab02-4784-894b-e5a6e4f8e60a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2175275955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2175275955
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3695381415
Short name	T190
Test name
Test status
Simulation time	30839862236 ps
CPU time	88.85 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	201976 kb
Host	smart-756e9902-bfc4-4373-bb30-60caa9ab4a85
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695381415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3695381415
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1149458234
Short name	T889
Test name
Test status
Simulation time	3298021391 ps
CPU time	23.24 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	202076 kb
Host	smart-8d459718-abae-4f22-8242-134b0d3cf882
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1149458234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1149458234
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.241658407
Short name	T364
Test name
Test status
Simulation time	55283840 ps
CPU time	2.8 seconds
Started	May 30 12:46:47 PM PDT 24
Finished	May 30 12:46:51 PM PDT 24
Peak memory	202000 kb
Host	smart-72e96101-c8d7-4e45-95f7-6e7c9a831bbd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241658407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.241658407
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.2847098188
Short name	T533
Test name
Test status
Simulation time	344922923 ps
CPU time	4.27 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:46:54 PM PDT 24
Peak memory	201928 kb
Host	smart-d4a8b4be-cad5-41e7-bdfe-e5113832616a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2847098188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2847098188
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.2505290486
Short name	T535
Test name
Test status
Simulation time	51589863 ps
CPU time	1.32 seconds
Started	May 30 12:46:42 PM PDT 24
Finished	May 30 12:46:45 PM PDT 24
Peak memory	201912 kb
Host	smart-2a5c8965-b835-48f2-a32a-0bf028e73022
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2505290486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2505290486
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1893208266
Short name	T25
Test name
Test status
Simulation time	2821251229 ps
CPU time	9.71 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:06 PM PDT 24
Peak memory	202068 kb
Host	smart-9fbc952a-d032-4517-ad40-7e9782e3246a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893208266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1893208266
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.554424952
Short name	T288
Test name
Test status
Simulation time	1548462773 ps
CPU time	6.16 seconds
Started	May 30 12:46:43 PM PDT 24
Finished	May 30 12:46:50 PM PDT 24
Peak memory	201980 kb
Host	smart-17d99ba4-7295-436e-8bbc-86a44784d475
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=554424952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.554424952
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1906002353
Short name	T856
Test name
Test status
Simulation time	9836910 ps
CPU time	1.12 seconds
Started	May 30 12:46:45 PM PDT 24
Finished	May 30 12:46:47 PM PDT 24
Peak memory	201996 kb
Host	smart-fffdf6e7-a559-4e5d-9b52-446af14c1f67
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906002353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1906002353
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.2419206961
Short name	T515
Test name
Test status
Simulation time	5944508423 ps
CPU time	44.28 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:47:33 PM PDT 24
Peak memory	203000 kb
Host	smart-6c43f874-6cf2-4b0f-8551-acf832ec5681
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2419206961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2419206961
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3172208048
Short name	T47
Test name
Test status
Simulation time	543602243 ps
CPU time	9.89 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:07 PM PDT 24
Peak memory	201996 kb
Host	smart-209b2bfb-265a-4688-bd18-6aa419b77d29
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3172208048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3172208048
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2300598676
Short name	T825
Test name
Test status
Simulation time	2108311748 ps
CPU time	67.92 seconds
Started	May 30 12:46:49 PM PDT 24
Finished	May 30 12:47:57 PM PDT 24
Peak memory	204304 kb
Host	smart-eedcf18d-2054-44cc-b1df-27e6189971d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300598676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2300598676
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3802690634
Short name	T467
Test name
Test status
Simulation time	7231794760 ps
CPU time	99.25 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	204984 kb
Host	smart-7c30ab3c-9ed1-4290-96ef-2f4ba528d443
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3802690634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3802690634
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.825886984
Short name	T473
Test name
Test status
Simulation time	495691874 ps
CPU time	7.58 seconds
Started	May 30 12:46:50 PM PDT 24
Finished	May 30 12:46:59 PM PDT 24
Peak memory	201912 kb
Host	smart-1a41caa4-5e1e-449b-ab91-e77e7c3e2b31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825886984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.825886984
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3241803241
Short name	T45
Test name
Test status
Simulation time	84447322 ps
CPU time	1.83 seconds
Started	May 30 12:46:54 PM PDT 24
Finished	May 30 12:46:57 PM PDT 24
Peak memory	201984 kb
Host	smart-cff79782-ac0b-47d9-989b-76e776ecaf0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3241803241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3241803241
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1554817235
Short name	T633
Test name
Test status
Simulation time	43751974 ps
CPU time	4.05 seconds
Started	May 30 12:47:00 PM PDT 24
Finished	May 30 12:47:05 PM PDT 24
Peak memory	201988 kb
Host	smart-d626c55a-c76a-4005-b3cd-d1748afabfd8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1554817235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1554817235
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.1271527222
Short name	T841
Test name
Test status
Simulation time	1162466076 ps
CPU time	13.25 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:17 PM PDT 24
Peak memory	202012 kb
Host	smart-f9ce3a00-6993-4949-b0a9-d6df044397a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1271527222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1271527222
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.1784377987
Short name	T440
Test name
Test status
Simulation time	711366943 ps
CPU time	9.92 seconds
Started	May 30 12:47:00 PM PDT 24
Finished	May 30 12:47:11 PM PDT 24
Peak memory	201904 kb
Host	smart-7d524ff6-461a-4b3d-9877-d7b8aeaf7c33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784377987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1784377987
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3276501610
Short name	T89
Test name
Test status
Simulation time	14517159899 ps
CPU time	59.83 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:56 PM PDT 24
Peak memory	201972 kb
Host	smart-a49d8e11-64aa-4b27-b611-b472e1da5811
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276501610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3276501610
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2841920396
Short name	T666
Test name
Test status
Simulation time	16522890029 ps
CPU time	36.24 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:33 PM PDT 24
Peak memory	202044 kb
Host	smart-ee0fe0fb-466c-4545-9f82-df82c6827c72
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2841920396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2841920396
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2606509152
Short name	T707
Test name
Test status
Simulation time	94557645 ps
CPU time	7.82 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:05 PM PDT 24
Peak memory	201904 kb
Host	smart-2b2cc3e9-1b13-4b89-9e23-8a1fcc57636c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606509152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2606509152
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.472852829
Short name	T18
Test name
Test status
Simulation time	1441708283 ps
CPU time	8.6 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:47:04 PM PDT 24
Peak memory	201916 kb
Host	smart-36647d36-2a83-4308-91c3-5aaa12ae653b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=472852829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.472852829
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.240853140
Short name	T103
Test name
Test status
Simulation time	108663829 ps
CPU time	1.28 seconds
Started	May 30 12:46:57 PM PDT 24
Finished	May 30 12:47:00 PM PDT 24
Peak memory	201976 kb
Host	smart-4731bb3c-5889-4df1-b848-ccbe95fa3235
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=240853140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.240853140
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3623627565
Short name	T42
Test name
Test status
Simulation time	6033502015 ps
CPU time	11.29 seconds
Started	May 30 12:47:00 PM PDT 24
Finished	May 30 12:47:12 PM PDT 24
Peak memory	202056 kb
Host	smart-c991e691-401c-49c8-be9a-08c00f5008b2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623627565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3623627565
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2382882542
Short name	T567
Test name
Test status
Simulation time	1572043802 ps
CPU time	7.82 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:47:03 PM PDT 24
Peak memory	201924 kb
Host	smart-d48fd1a4-98e4-42ae-b6a3-351b1eff9169
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2382882542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2382882542
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1334464001
Short name	T261
Test name
Test status
Simulation time	13548286 ps
CPU time	1.1 seconds
Started	May 30 12:47:01 PM PDT 24
Finished	May 30 12:47:03 PM PDT 24
Peak memory	201980 kb
Host	smart-c516444b-7762-4dee-85f0-a5f762b1382d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334464001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1334464001
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.2502472409
Short name	T354
Test name
Test status
Simulation time	115032060 ps
CPU time	11.35 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	202004 kb
Host	smart-591de083-161b-4276-99f9-12d63daacb00
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2502472409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2502472409
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1481263452
Short name	T252
Test name
Test status
Simulation time	207337430 ps
CPU time	20.02 seconds
Started	May 30 12:46:59 PM PDT 24
Finished	May 30 12:47:20 PM PDT 24
Peak memory	201980 kb
Host	smart-6d63c8d8-f99d-4f5c-8171-dc2d1dc73e0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1481263452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1481263452
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2825758752
Short name	T817
Test name
Test status
Simulation time	181794670 ps
CPU time	27.67 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:47:23 PM PDT 24
Peak memory	203252 kb
Host	smart-1d4d9d67-a254-40c9-ae0b-319b5034c98f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2825758752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.2825758752
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4157269143
Short name	T371
Test name
Test status
Simulation time	185754622 ps
CPU time	23.57 seconds
Started	May 30 12:46:57 PM PDT 24
Finished	May 30 12:47:21 PM PDT 24
Peak memory	204052 kb
Host	smart-12554532-fc2f-4e73-b165-e7c8c668c854
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4157269143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.4157269143
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2721217090
Short name	T59
Test name
Test status
Simulation time	541059938 ps
CPU time	12.07 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:09 PM PDT 24
Peak memory	201928 kb
Host	smart-03ff662e-df90-484f-aba7-2da970df4c6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2721217090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2721217090
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2766775313
Short name	T117
Test name
Test status
Simulation time	4999987601 ps
CPU time	13.07 seconds
Started	May 30 12:46:59 PM PDT 24
Finished	May 30 12:47:13 PM PDT 24
Peak memory	202036 kb
Host	smart-cc1b1f66-0d8b-4f51-949e-518457095952
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2766775313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2766775313
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3028186703
Short name	T70
Test name
Test status
Simulation time	52311514832 ps
CPU time	370.35 seconds
Started	May 30 12:46:58 PM PDT 24
Finished	May 30 12:53:09 PM PDT 24
Peak memory	203100 kb
Host	smart-076f72b4-9321-4127-b25e-31512b1d397c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3028186703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3028186703
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2754126491
Short name	T653
Test name
Test status
Simulation time	340583348 ps
CPU time	3.59 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:07 PM PDT 24
Peak memory	201916 kb
Host	smart-3121d7c1-66a1-4aeb-af67-ad1f7a5950f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2754126491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2754126491
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.960816733
Short name	T3
Test name
Test status
Simulation time	1920080782 ps
CPU time	4.61 seconds
Started	May 30 12:46:59 PM PDT 24
Finished	May 30 12:47:04 PM PDT 24
Peak memory	201976 kb
Host	smart-31e468d2-fd26-4314-b0b1-ec6aa8a61adf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960816733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.960816733
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.46181296
Short name	T609
Test name
Test status
Simulation time	623839519 ps
CPU time	11.9 seconds
Started	May 30 12:47:01 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	202016 kb
Host	smart-72e86600-224f-435e-b277-21be9786ae1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=46181296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.46181296
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3638369829
Short name	T160
Test name
Test status
Simulation time	21054804211 ps
CPU time	103.53 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:48:46 PM PDT 24
Peak memory	202068 kb
Host	smart-5e4c4571-088a-4f6d-8fce-bdb414d4de9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638369829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3638369829
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.295037072
Short name	T162
Test name
Test status
Simulation time	1680687597 ps
CPU time	10.48 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	202012 kb
Host	smart-3748349e-a20f-4b23-a5e5-aa741f2f11b1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=295037072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.295037072
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3030039691
Short name	T316
Test name
Test status
Simulation time	135103612 ps
CPU time	9.31 seconds
Started	May 30 12:46:59 PM PDT 24
Finished	May 30 12:47:09 PM PDT 24
Peak memory	201916 kb
Host	smart-edda05db-52bb-4aa6-8dd6-a5e761431b52
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030039691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3030039691
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.31077061
Short name	T754
Test name
Test status
Simulation time	33799569 ps
CPU time	2.75 seconds
Started	May 30 12:46:57 PM PDT 24
Finished	May 30 12:47:00 PM PDT 24
Peak memory	202004 kb
Host	smart-fea1c604-aadf-4665-b2ee-1a642661bc0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=31077061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.31077061
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.1426624639
Short name	T67
Test name
Test status
Simulation time	8592571 ps
CPU time	1.01 seconds
Started	May 30 12:46:54 PM PDT 24
Finished	May 30 12:46:56 PM PDT 24
Peak memory	202024 kb
Host	smart-1f0aa00a-9e31-4536-b0cb-9387bd87f20c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1426624639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1426624639
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2590310444
Short name	T399
Test name
Test status
Simulation time	2418869956 ps
CPU time	9.3 seconds
Started	May 30 12:47:00 PM PDT 24
Finished	May 30 12:47:10 PM PDT 24
Peak memory	202056 kb
Host	smart-1caf20b7-db05-468d-a037-4d37429d8851
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590310444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2590310444
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1185205030
Short name	T516
Test name
Test status
Simulation time	984820628 ps
CPU time	7.98 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:11 PM PDT 24
Peak memory	202016 kb
Host	smart-aac0c122-af9d-4811-adf8-f1976171558f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1185205030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1185205030
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.623641481
Short name	T384
Test name
Test status
Simulation time	8431929 ps
CPU time	1.13 seconds
Started	May 30 12:46:58 PM PDT 24
Finished	May 30 12:47:00 PM PDT 24
Peak memory	201924 kb
Host	smart-2428e775-ac18-4ccb-9a29-8a8ac3c42e9b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623641481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.623641481
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.2843883181
Short name	T492
Test name
Test status
Simulation time	2751584583 ps
CPU time	53.41 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:51 PM PDT 24
Peak memory	203088 kb
Host	smart-c28012b6-ebf3-4825-bb9b-10076de497f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2843883181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2843883181
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3628683013
Short name	T801
Test name
Test status
Simulation time	5593114893 ps
CPU time	35.9 seconds
Started	May 30 12:46:58 PM PDT 24
Finished	May 30 12:47:35 PM PDT 24
Peak memory	202052 kb
Host	smart-9ba3d394-8ea3-4668-b1a1-0f37ab51d1a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628683013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3628683013
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1211502986
Short name	T526
Test name
Test status
Simulation time	4665219976 ps
CPU time	162.55 seconds
Started	May 30 12:46:57 PM PDT 24
Finished	May 30 12:49:40 PM PDT 24
Peak memory	206008 kb
Host	smart-b21d74a4-7be3-4978-809d-01e1836289c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1211502986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1211502986
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2460695464
Short name	T396
Test name
Test status
Simulation time	5831891041 ps
CPU time	40.72 seconds
Started	May 30 12:46:57 PM PDT 24
Finished	May 30 12:47:38 PM PDT 24
Peak memory	204068 kb
Host	smart-e7363919-947d-4d61-ba81-d2caab016360
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2460695464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.2460695464
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1461701023
Short name	T886
Test name
Test status
Simulation time	54040754 ps
CPU time	5.04 seconds
Started	May 30 12:47:01 PM PDT 24
Finished	May 30 12:47:07 PM PDT 24
Peak memory	201984 kb
Host	smart-93d60c46-2658-4232-bb09-6e5e681ac5a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461701023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1461701023
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2347962886
Short name	T761
Test name
Test status
Simulation time	801416501 ps
CPU time	12.54 seconds
Started	May 30 12:46:59 PM PDT 24
Finished	May 30 12:47:12 PM PDT 24
Peak memory	202008 kb
Host	smart-e0e98121-a329-4df7-84f0-ebcd9104b4df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347962886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2347962886
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1822280192
Short name	T210
Test name
Test status
Simulation time	320125385322 ps
CPU time	257.07 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	203092 kb
Host	smart-629f4dc8-4bc3-4991-ae17-de3fb84941b2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1822280192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.1822280192
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.859987602
Short name	T250
Test name
Test status
Simulation time	231311840 ps
CPU time	4.72 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:16 PM PDT 24
Peak memory	201992 kb
Host	smart-53c294e7-5683-483f-b62d-f864cc6f1fcd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=859987602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.859987602
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.733030322
Short name	T771
Test name
Test status
Simulation time	59047022 ps
CPU time	5.59 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:17 PM PDT 24
Peak memory	202000 kb
Host	smart-c0f52432-d8a4-42e3-96f4-9af2979295eb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733030322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.733030322
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.2731069029
Short name	T495
Test name
Test status
Simulation time	248765628 ps
CPU time	2.79 seconds
Started	May 30 12:47:00 PM PDT 24
Finished	May 30 12:47:03 PM PDT 24
Peak memory	201908 kb
Host	smart-81dc87e9-ccb4-4f26-83d0-f8ad576fb708
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2731069029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2731069029
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.604124125
Short name	T472
Test name
Test status
Simulation time	30971658328 ps
CPU time	144.98 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:49:21 PM PDT 24
Peak memory	202060 kb
Host	smart-acbb6a93-44dc-418b-8e36-4d2c4b6299a6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=604124125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.604124125
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3098274338
Short name	T583
Test name
Test status
Simulation time	10017855540 ps
CPU time	74.93 seconds
Started	May 30 12:46:58 PM PDT 24
Finished	May 30 12:48:13 PM PDT 24
Peak memory	202080 kb
Host	smart-f593e0ce-c9f9-4acf-ad52-b586009d160c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3098274338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3098274338
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2490202020
Short name	T101
Test name
Test status
Simulation time	67900501 ps
CPU time	4.57 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:07 PM PDT 24
Peak memory	201916 kb
Host	smart-4acbcf79-373a-4fd0-bcfb-df62dd2488fd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490202020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2490202020
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.3314382975
Short name	T843
Test name
Test status
Simulation time	19917248 ps
CPU time	1.77 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:13 PM PDT 24
Peak memory	201928 kb
Host	smart-89d59361-f128-4fd5-89ab-1b008be7b7e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314382975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3314382975
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.2874022380
Short name	T419
Test name
Test status
Simulation time	9244146 ps
CPU time	1.12 seconds
Started	May 30 12:47:00 PM PDT 24
Finished	May 30 12:47:02 PM PDT 24
Peak memory	201904 kb
Host	smart-c69b8da4-ae0a-43d6-b5cc-7304088a9823
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2874022380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2874022380
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2974089999
Short name	T510
Test name
Test status
Simulation time	11533739372 ps
CPU time	9.55 seconds
Started	May 30 12:46:55 PM PDT 24
Finished	May 30 12:47:05 PM PDT 24
Peak memory	202072 kb
Host	smart-96c2f4a0-4734-4bb1-984c-350d3bd00d69
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974089999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2974089999
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3835306574
Short name	T49
Test name
Test status
Simulation time	1240987783 ps
CPU time	7.84 seconds
Started	May 30 12:46:56 PM PDT 24
Finished	May 30 12:47:05 PM PDT 24
Peak memory	202020 kb
Host	smart-a0d3b371-e412-4532-b170-3b9038a58a84
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3835306574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3835306574
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3666348409
Short name	T142
Test name
Test status
Simulation time	13067125 ps
CPU time	1.14 seconds
Started	May 30 12:47:02 PM PDT 24
Finished	May 30 12:47:04 PM PDT 24
Peak memory	201992 kb
Host	smart-d8c4fc0c-7a09-4071-ba13-840fa64af641
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666348409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3666348409
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.1009620915
Short name	T268
Test name
Test status
Simulation time	1359905461 ps
CPU time	9.15 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:20 PM PDT 24
Peak memory	201916 kb
Host	smart-25cb01e6-2585-46d8-8639-0c6a216fc305
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1009620915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1009620915
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.983884121
Short name	T860
Test name
Test status
Simulation time	2476647997 ps
CPU time	76.71 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:48:27 PM PDT 24
Peak memory	204668 kb
Host	smart-229cf09c-13e3-4f87-be53-b3e737a72271
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=983884121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand _reset.983884121
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3634216795
Short name	T442
Test name
Test status
Simulation time	422211468 ps
CPU time	34.92 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:45 PM PDT 24
Peak memory	203020 kb
Host	smart-7e17b37b-f54d-4202-a036-af4c57fc5154
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3634216795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3634216795
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1761855878
Short name	T317
Test name
Test status
Simulation time	599533059 ps
CPU time	7.83 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:18 PM PDT 24
Peak memory	201916 kb
Host	smart-75115808-6f4a-483b-b456-2d7a5cc40ae3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1761855878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1761855878
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2625963469
Short name	T104
Test name
Test status
Simulation time	472404124 ps
CPU time	10.35 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:23 PM PDT 24
Peak memory	201916 kb
Host	smart-776b1e7f-bc92-4e49-ae4c-f927b0420f38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2625963469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2625963469
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3913050980
Short name	T575
Test name
Test status
Simulation time	62077870108 ps
CPU time	119.54 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:49:12 PM PDT 24
Peak memory	202056 kb
Host	smart-0770ea82-f651-4ae0-b20f-8a3ebf64afc4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3913050980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3913050980
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4129416601
Short name	T757
Test name
Test status
Simulation time	1229246291 ps
CPU time	10.97 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:23 PM PDT 24
Peak memory	201984 kb
Host	smart-72fd71ae-715e-4672-8883-a5905faede17
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4129416601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.4129416601
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.1180860306
Short name	T778
Test name
Test status
Simulation time	87302767 ps
CPU time	4.45 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:17 PM PDT 24
Peak memory	201908 kb
Host	smart-1310b6dd-d597-49a7-9fa2-55bcb048f794
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1180860306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1180860306
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.1902227236
Short name	T450
Test name
Test status
Simulation time	60683198 ps
CPU time	1.43 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	201924 kb
Host	smart-74b90a6e-c038-4776-87bf-d276fd663ad9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1902227236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1902227236
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.4018056374
Short name	T302
Test name
Test status
Simulation time	18583705825 ps
CPU time	17.78 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:31 PM PDT 24
Peak memory	201976 kb
Host	smart-b9e636c9-846c-4a9e-93a4-1ac2a415b390
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018056374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.4018056374
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1993361147
Short name	T573
Test name
Test status
Simulation time	12100558422 ps
CPU time	81.01 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	202056 kb
Host	smart-9f994c6b-cada-49aa-bd8f-5a02038aef19
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1993361147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1993361147
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.382243121
Short name	T121
Test name
Test status
Simulation time	167775934 ps
CPU time	2.95 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	201964 kb
Host	smart-cc1bad52-da53-4444-b620-20187771066a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382243121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.382243121
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.4236622073
Short name	T339
Test name
Test status
Simulation time	1728026898 ps
CPU time	12.09 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:25 PM PDT 24
Peak memory	201928 kb
Host	smart-e94d0b84-08e9-4011-8a9e-e73be24b9cb3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4236622073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4236622073
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.496424083
Short name	T315
Test name
Test status
Simulation time	102640262 ps
CPU time	1.39 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:13 PM PDT 24
Peak memory	201836 kb
Host	smart-2b9bd413-6ee7-4055-b1e5-a3c508c6b0b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=496424083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.496424083
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1139076382
Short name	T21
Test name
Test status
Simulation time	2468378141 ps
CPU time	10.3 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:24 PM PDT 24
Peak memory	201972 kb
Host	smart-87a41abb-cce5-42f2-b499-942e97f65205
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139076382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1139076382
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1680859922
Short name	T372
Test name
Test status
Simulation time	972932689 ps
CPU time	6.45 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:19 PM PDT 24
Peak memory	201908 kb
Host	smart-4d58a446-e2a5-4a05-9d6b-9250f29564e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1680859922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1680859922
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2607241279
Short name	T532
Test name
Test status
Simulation time	14282481 ps
CPU time	1.24 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	201900 kb
Host	smart-6fddcccf-d9a3-4ad3-bb5d-a9e904c9e078
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607241279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2607241279
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.1011423699
Short name	T309
Test name
Test status
Simulation time	762726975 ps
CPU time	16.44 seconds
Started	May 30 12:47:16 PM PDT 24
Finished	May 30 12:47:33 PM PDT 24
Peak memory	203036 kb
Host	smart-6675d741-7448-4f2d-bd7b-50f27a2a7cc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011423699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1011423699
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.443533246
Short name	T748
Test name
Test status
Simulation time	1767984740 ps
CPU time	14.28 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:26 PM PDT 24
Peak memory	201976 kb
Host	smart-abbdaae4-ad7b-4317-8c1d-07cac8044627
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=443533246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.443533246
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1976472225
Short name	T697
Test name
Test status
Simulation time	9969399130 ps
CPU time	98.9 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:48:51 PM PDT 24
Peak memory	205536 kb
Host	smart-86e08a33-5015-4f48-9f4c-6ad7874e3044
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976472225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.1976472225
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3605136080
Short name	T17
Test name
Test status
Simulation time	1471367055 ps
CPU time	53.92 seconds
Started	May 30 12:47:14 PM PDT 24
Finished	May 30 12:48:10 PM PDT 24
Peak memory	203952 kb
Host	smart-affb41b6-6caf-4d8c-ab1c-8456b794f0c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605136080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.3605136080
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1791009190
Short name	T511
Test name
Test status
Simulation time	276149417 ps
CPU time	5.95 seconds
Started	May 30 12:47:16 PM PDT 24
Finished	May 30 12:47:23 PM PDT 24
Peak memory	202008 kb
Host	smart-e846a1fb-d018-4d73-9636-c554af7caddd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1791009190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1791009190
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2968084698
Short name	T459
Test name
Test status
Simulation time	4039692818 ps
CPU time	19.66 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:30 PM PDT 24
Peak memory	201952 kb
Host	smart-6ee7a900-0c6e-449b-9c9f-3f60681822bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2968084698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2968084698
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2816756608
Short name	T207
Test name
Test status
Simulation time	37566878446 ps
CPU time	116.92 seconds
Started	May 30 12:47:13 PM PDT 24
Finished	May 30 12:49:11 PM PDT 24
Peak memory	203108 kb
Host	smart-8e463486-6a73-4e54-a296-580aa8bba384
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2816756608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2816756608
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2465010739
Short name	T237
Test name
Test status
Simulation time	370079194 ps
CPU time	2.86 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:13 PM PDT 24
Peak memory	201936 kb
Host	smart-b788a158-7cd3-47c5-92b6-e775d3e6ef14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2465010739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2465010739
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.2344183829
Short name	T296
Test name
Test status
Simulation time	49103795 ps
CPU time	5.03 seconds
Started	May 30 12:47:03 PM PDT 24
Finished	May 30 12:47:09 PM PDT 24
Peak memory	201892 kb
Host	smart-e7df40b0-e108-4cd6-94d3-e60bfbbc3af3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2344183829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2344183829
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.122044659
Short name	T184
Test name
Test status
Simulation time	451293756 ps
CPU time	4.44 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	202008 kb
Host	smart-a9df9d86-6cea-4801-a0dd-1a8777102d01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=122044659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.122044659
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.4132762062
Short name	T397
Test name
Test status
Simulation time	40237384334 ps
CPU time	77.56 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	202004 kb
Host	smart-12ed363f-5811-4f5c-ac85-492d99bf408e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132762062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4132762062
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.262272737
Short name	T610
Test name
Test status
Simulation time	19712418704 ps
CPU time	128.18 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:49:20 PM PDT 24
Peak memory	202044 kb
Host	smart-afa4b4b1-e4fc-4b10-92ce-dc8db197f2d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=262272737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.262272737
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2184904812
Short name	T698
Test name
Test status
Simulation time	71545267 ps
CPU time	5.3 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	201960 kb
Host	smart-fdd70a48-7fcd-4748-8d9f-6811ce519b0a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184904812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2184904812
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.3607784218
Short name	T76
Test name
Test status
Simulation time	45992874 ps
CPU time	4.39 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	201904 kb
Host	smart-eb16efac-741a-4074-90ba-b316828e79d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607784218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3607784218
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.1782786090
Short name	T541
Test name
Test status
Simulation time	100841873 ps
CPU time	1.39 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	201932 kb
Host	smart-713fdeb5-5cc4-41ab-ab88-6a96fd07e84f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1782786090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1782786090
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1443582077
Short name	T470
Test name
Test status
Simulation time	3667790810 ps
CPU time	13.7 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:25 PM PDT 24
Peak memory	201992 kb
Host	smart-328a2769-4b46-4f6a-ada4-735a5861c8db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443582077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1443582077
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1679279399
Short name	T23
Test name
Test status
Simulation time	1727796196 ps
CPU time	7.91 seconds
Started	May 30 12:47:13 PM PDT 24
Finished	May 30 12:47:22 PM PDT 24
Peak memory	201912 kb
Host	smart-fcc129d3-0a09-4f7d-8ece-0c99c8394aba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1679279399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1679279399
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.447542492
Short name	T144
Test name
Test status
Simulation time	13105828 ps
CPU time	1.06 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:14 PM PDT 24
Peak memory	202008 kb
Host	smart-1ccd22b2-effb-4f00-9d82-13a53fd0c28e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447542492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.447542492
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.2831126341
Short name	T191
Test name
Test status
Simulation time	153233252 ps
CPU time	2.9 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	201924 kb
Host	smart-11a47c27-5108-485b-95a8-c272d7039d43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2831126341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2831126341
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1430315484
Short name	T398
Test name
Test status
Simulation time	1056827549 ps
CPU time	47.65 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:58 PM PDT 24
Peak memory	201916 kb
Host	smart-9ea95b86-157a-4448-851b-d14c16670b82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1430315484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1430315484
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1115867264
Short name	T579
Test name
Test status
Simulation time	1312984395 ps
CPU time	113.34 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:49:04 PM PDT 24
Peak memory	206008 kb
Host	smart-dd43f7b2-2f44-406e-8ab5-ff3b0f135a0c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1115867264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1115867264
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3119362742
Short name	T482
Test name
Test status
Simulation time	424026153 ps
CPU time	45.72 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:57 PM PDT 24
Peak memory	203300 kb
Host	smart-37edee1d-2ca2-4c0f-ae15-0c82640c8694
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3119362742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3119362742
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3439296385
Short name	T469
Test name
Test status
Simulation time	224653870 ps
CPU time	4.75 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:16 PM PDT 24
Peak memory	201836 kb
Host	smart-52e3c295-be20-4cf4-9110-59ff3a9f6970
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3439296385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3439296385
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1587753364
Short name	T836
Test name
Test status
Simulation time	4359867812 ps
CPU time	17.68 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:27 PM PDT 24
Peak memory	202072 kb
Host	smart-7735e3a9-6108-4eea-8585-6e3d8b70ffa7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1587753364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1587753364
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.775200915
Short name	T776
Test name
Test status
Simulation time	19758368508 ps
CPU time	152.71 seconds
Started	May 30 12:47:15 PM PDT 24
Finished	May 30 12:49:49 PM PDT 24
Peak memory	203092 kb
Host	smart-f6ecb02d-7aad-4fae-b400-a0d9be1f6d26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=775200915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.775200915
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3955318544
Short name	T243
Test name
Test status
Simulation time	38882088 ps
CPU time	1.21 seconds
Started	May 30 12:47:15 PM PDT 24
Finished	May 30 12:47:17 PM PDT 24
Peak memory	202000 kb
Host	smart-b31fa5e0-5e8b-498a-bc17-b1513e222f37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3955318544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3955318544
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.3215931173
Short name	T490
Test name
Test status
Simulation time	212837315 ps
CPU time	4.4 seconds
Started	May 30 12:47:12 PM PDT 24
Finished	May 30 12:47:17 PM PDT 24
Peak memory	201996 kb
Host	smart-63c3bc23-631e-4143-a123-8745cfed813d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215931173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3215931173
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.1622032223
Short name	T119
Test name
Test status
Simulation time	4088586478 ps
CPU time	13.33 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:26 PM PDT 24
Peak memory	202060 kb
Host	smart-e2ae1468-5f53-4fce-820b-cb956f4fef9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1622032223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1622032223
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2631106421
Short name	T260
Test name
Test status
Simulation time	3727481506 ps
CPU time	19.44 seconds
Started	May 30 12:47:11 PM PDT 24
Finished	May 30 12:47:31 PM PDT 24
Peak memory	201992 kb
Host	smart-c6b20fc1-f798-4f86-bf60-fa3f9c141979
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631106421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2631106421
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2488838438
Short name	T90
Test name
Test status
Simulation time	56392606489 ps
CPU time	192.95 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:50:23 PM PDT 24
Peak memory	202080 kb
Host	smart-dce8cf6d-78cd-444d-b690-d9bc945199d2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2488838438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2488838438
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3929120126
Short name	T66
Test name
Test status
Simulation time	52155322 ps
CPU time	4.63 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:16 PM PDT 24
Peak memory	201944 kb
Host	smart-2772305d-82a2-4ee5-9318-417238750202
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929120126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3929120126
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.1940666118
Short name	T282
Test name
Test status
Simulation time	724623667 ps
CPU time	8.74 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:20 PM PDT 24
Peak memory	201992 kb
Host	smart-6292d47b-b792-43d5-834f-6479c061b764
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940666118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1940666118
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.2253273752
Short name	T877
Test name
Test status
Simulation time	199274264 ps
CPU time	1.65 seconds
Started	May 30 12:47:13 PM PDT 24
Finished	May 30 12:47:15 PM PDT 24
Peak memory	202008 kb
Host	smart-165c4e6d-b1e1-438f-a5be-cfb21dcd82fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2253273752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2253273752
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1040845057
Short name	T752
Test name
Test status
Simulation time	3948340286 ps
CPU time	8.75 seconds
Started	May 30 12:47:13 PM PDT 24
Finished	May 30 12:47:24 PM PDT 24
Peak memory	201980 kb
Host	smart-c26d7f82-0a0c-4d9c-bca6-8996e849eeea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040845057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1040845057
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1279900440
Short name	T496
Test name
Test status
Simulation time	981736365 ps
CPU time	7.29 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:19 PM PDT 24
Peak memory	201948 kb
Host	smart-6d38c5fb-1254-4eb8-8e9e-cdee2c1b14b5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1279900440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1279900440
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3079170046
Short name	T830
Test name
Test status
Simulation time	8472059 ps
CPU time	1.08 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:12 PM PDT 24
Peak memory	201968 kb
Host	smart-e9efee40-eef5-41a6-a2e1-2079b708d252
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079170046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3079170046
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.2697920141
Short name	T714
Test name
Test status
Simulation time	4166700144 ps
CPU time	46.93 seconds
Started	May 30 12:47:10 PM PDT 24
Finished	May 30 12:47:58 PM PDT 24
Peak memory	203088 kb
Host	smart-e38c4319-59d1-4dbc-9349-7723daa470dc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2697920141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2697920141
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.24940499
Short name	T448
Test name
Test status
Simulation time	2314934586 ps
CPU time	38.73 seconds
Started	May 30 12:47:14 PM PDT 24
Finished	May 30 12:47:54 PM PDT 24
Peak memory	201968 kb
Host	smart-180b00a1-ade3-4d7a-80ff-29ced3ec7c19
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=24940499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.24940499
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.377009105
Short name	T721
Test name
Test status
Simulation time	280244551 ps
CPU time	46.37 seconds
Started	May 30 12:47:09 PM PDT 24
Finished	May 30 12:47:57 PM PDT 24
Peak memory	204168 kb
Host	smart-be41a8cc-f354-4c5e-a191-f73d2b36344b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=377009105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand _reset.377009105
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.224911628
Short name	T217
Test name
Test status
Simulation time	239879115 ps
CPU time	39.21 seconds
Started	May 30 12:47:32 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	203968 kb
Host	smart-bc78c5e0-a59f-4620-bcef-2464ea50205c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=224911628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.224911628
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2553485873
Short name	T580
Test name
Test status
Simulation time	718902917 ps
CPU time	8.71 seconds
Started	May 30 12:47:13 PM PDT 24
Finished	May 30 12:47:24 PM PDT 24
Peak memory	201988 kb
Host	smart-fc3b9ca6-f4fd-4eae-baf9-217165cf7b92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2553485873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2553485873
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.505671299
Short name	T753
Test name
Test status
Simulation time	223179526 ps
CPU time	10.74 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:47 PM PDT 24
Peak memory	202004 kb
Host	smart-b10b139a-36c8-43b5-9279-5f4cc74a34c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=505671299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.505671299
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2516770563
Short name	T102
Test name
Test status
Simulation time	34864097166 ps
CPU time	121.36 seconds
Started	May 30 12:47:33 PM PDT 24
Finished	May 30 12:49:35 PM PDT 24
Peak memory	202080 kb
Host	smart-1b4dc62f-665e-4f63-9f9c-d1aeb5c79743
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2516770563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2516770563
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4105882869
Short name	T545
Test name
Test status
Simulation time	52173703 ps
CPU time	3.76 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:40 PM PDT 24
Peak memory	201984 kb
Host	smart-c92f8641-13c5-4b4f-a67f-54d32f18a635
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4105882869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4105882869
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.2279270518
Short name	T502
Test name
Test status
Simulation time	250133680 ps
CPU time	3.92 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:39 PM PDT 24
Peak memory	201996 kb
Host	smart-a670484a-12ba-4bb4-b7b4-019864db0e1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2279270518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2279270518
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.3008730636
Short name	T826
Test name
Test status
Simulation time	2155055255 ps
CPU time	7.84 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	202036 kb
Host	smart-a1f3b37a-ec7a-4fb5-a82c-0a0c6eb68a02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008730636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3008730636
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3405819670
Short name	T85
Test name
Test status
Simulation time	43845159127 ps
CPU time	205.2 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:51:02 PM PDT 24
Peak memory	201908 kb
Host	smart-4703cf57-5a6c-47e9-838d-c094584a85ec
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405819670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3405819670
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1993698173
Short name	T145
Test name
Test status
Simulation time	41515589014 ps
CPU time	143.65 seconds
Started	May 30 12:47:32 PM PDT 24
Finished	May 30 12:49:57 PM PDT 24
Peak memory	201972 kb
Host	smart-498e82ec-6646-440b-a8c8-2b6d69ae9a9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1993698173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1993698173
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1282648343
Short name	T338
Test name
Test status
Simulation time	78431726 ps
CPU time	2.95 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:39 PM PDT 24
Peak memory	201976 kb
Host	smart-08b3ddf7-84ec-41ba-8886-31c62ae6b569
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282648343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1282648343
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.1512630222
Short name	T663
Test name
Test status
Simulation time	57752134 ps
CPU time	4.02 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:40 PM PDT 24
Peak memory	202008 kb
Host	smart-c9323bd3-a576-44a6-8609-cfd3e957b069
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1512630222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1512630222
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.3011144133
Short name	T187
Test name
Test status
Simulation time	9713212 ps
CPU time	1.1 seconds
Started	May 30 12:47:33 PM PDT 24
Finished	May 30 12:47:35 PM PDT 24
Peak memory	201896 kb
Host	smart-835e750e-22a5-4a8d-bf07-51dbb8019ae0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3011144133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3011144133
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3155372194
Short name	T696
Test name
Test status
Simulation time	2255242638 ps
CPU time	8.93 seconds
Started	May 30 12:47:34 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	202072 kb
Host	smart-c8436807-4253-491e-b972-00f752198cc2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155372194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3155372194
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2984755467
Short name	T656
Test name
Test status
Simulation time	6165607316 ps
CPU time	14.15 seconds
Started	May 30 12:47:34 PM PDT 24
Finished	May 30 12:47:49 PM PDT 24
Peak memory	201968 kb
Host	smart-4c7a364a-f4a2-46aa-841c-0ef7b3499894
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2984755467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2984755467
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.20998002
Short name	T488
Test name
Test status
Simulation time	10691434 ps
CPU time	1.11 seconds
Started	May 30 12:47:32 PM PDT 24
Finished	May 30 12:47:35 PM PDT 24
Peak memory	201996 kb
Host	smart-d54d17a9-26ab-49c4-9e21-d9e24c3cf738
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.20998002
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.2539264745
Short name	T544
Test name
Test status
Simulation time	171436726 ps
CPU time	10.89 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:47 PM PDT 24
Peak memory	202056 kb
Host	smart-7dc022e3-4667-4057-b464-7f49a8ac2e0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2539264745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2539264745
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1982843169
Short name	T831
Test name
Test status
Simulation time	1170648158 ps
CPU time	17.51 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:53 PM PDT 24
Peak memory	201912 kb
Host	smart-c04a21f2-0895-4a9f-9d96-727edcd90ab0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1982843169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1982843169
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2713796392
Short name	T226
Test name
Test status
Simulation time	5156268785 ps
CPU time	103.32 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:49:19 PM PDT 24
Peak memory	205080 kb
Host	smart-fdd195b6-7bf6-444f-90a2-a4f513c775e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2713796392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2713796392
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2756265160
Short name	T146
Test name
Test status
Simulation time	68810914 ps
CPU time	6.7 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:42 PM PDT 24
Peak memory	202008 kb
Host	smart-a69f1ca1-c2db-46da-aee2-86778dc5be5b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2756265160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2756265160
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.58579411
Short name	T863
Test name
Test status
Simulation time	1229958583 ps
CPU time	6.4 seconds
Started	May 30 12:47:34 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	201916 kb
Host	smart-31a4b6bf-fc30-4ce1-b290-7000e269ff6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=58579411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.58579411
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.415354634
Short name	T244
Test name
Test status
Simulation time	37841253 ps
CPU time	3.89 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:40 PM PDT 24
Peak memory	201952 kb
Host	smart-0fcc8cba-819d-4ef6-9931-d4cf7717e8bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=415354634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.415354634
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1871825889
Short name	T198
Test name
Test status
Simulation time	119218814878 ps
CPU time	325.69 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:53:04 PM PDT 24
Peak memory	204196 kb
Host	smart-5cf6844c-511c-4c9f-a85f-f1e3818c9d00
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1871825889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1871825889
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1469333877
Short name	T788
Test name
Test status
Simulation time	1260616623 ps
CPU time	10.84 seconds
Started	May 30 12:47:37 PM PDT 24
Finished	May 30 12:47:48 PM PDT 24
Peak memory	201892 kb
Host	smart-cb11f890-53ab-4f25-9f78-0c8b77f0df97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1469333877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1469333877
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.1878397753
Short name	T519
Test name
Test status
Simulation time	41739175 ps
CPU time	3.7 seconds
Started	May 30 12:47:37 PM PDT 24
Finished	May 30 12:47:42 PM PDT 24
Peak memory	201976 kb
Host	smart-773dca02-eac9-481a-b39e-819e3a31f736
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878397753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1878397753
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.190656098
Short name	T781
Test name
Test status
Simulation time	29079789 ps
CPU time	3.87 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:40 PM PDT 24
Peak memory	201944 kb
Host	smart-05881410-828d-4516-82cc-c7d187cc6599
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=190656098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.190656098
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1228646229
Short name	T254
Test name
Test status
Simulation time	133745536285 ps
CPU time	123.84 seconds
Started	May 30 12:47:37 PM PDT 24
Finished	May 30 12:49:42 PM PDT 24
Peak memory	202040 kb
Host	smart-daba69e0-b689-4846-9baf-0434bff09384
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228646229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1228646229
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3035772597
Short name	T283
Test name
Test status
Simulation time	11741131431 ps
CPU time	89.27 seconds
Started	May 30 12:47:37 PM PDT 24
Finished	May 30 12:49:07 PM PDT 24
Peak memory	202040 kb
Host	smart-c1da602a-ddaf-47bc-83c1-565b1e0ce72e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3035772597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3035772597
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2955491096
Short name	T621
Test name
Test status
Simulation time	23024356 ps
CPU time	1.71 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	201964 kb
Host	smart-ceb3a42f-9e58-46cf-bb87-85cf6dacee1e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955491096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2955491096
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.2434739714
Short name	T747
Test name
Test status
Simulation time	1068918244 ps
CPU time	6.76 seconds
Started	May 30 12:47:37 PM PDT 24
Finished	May 30 12:47:45 PM PDT 24
Peak memory	201992 kb
Host	smart-87eb3ef7-1e25-418a-ab0c-38b869536fd6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2434739714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2434739714
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.3143882558
Short name	T353
Test name
Test status
Simulation time	58808746 ps
CPU time	1.5 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:38 PM PDT 24
Peak memory	201960 kb
Host	smart-ba49c678-d89d-4b36-ab00-08ce76bbb6e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3143882558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3143882558
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.998750614
Short name	T586
Test name
Test status
Simulation time	2201866118 ps
CPU time	9.21 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:46 PM PDT 24
Peak memory	201972 kb
Host	smart-0cd99c62-e694-4e86-b4ba-e972473825e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=998750614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.998750614
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.704792058
Short name	T331
Test name
Test status
Simulation time	855240438 ps
CPU time	5.69 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	202000 kb
Host	smart-24552b63-47d5-41a6-894f-12e77d90dd10
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=704792058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.704792058
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2342414906
Short name	T269
Test name
Test status
Simulation time	10723258 ps
CPU time	1.37 seconds
Started	May 30 12:47:35 PM PDT 24
Finished	May 30 12:47:38 PM PDT 24
Peak memory	201984 kb
Host	smart-ef62c4d5-6c74-4412-b356-5699fd798f80
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342414906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2342414906
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.2707737719
Short name	T161
Test name
Test status
Simulation time	2912106654 ps
CPU time	26.69 seconds
Started	May 30 12:47:39 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	202972 kb
Host	smart-2cb0a3b9-1ae3-413b-9654-917b7e4ada18
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2707737719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2707737719
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.404691582
Short name	T702
Test name
Test status
Simulation time	6755201 ps
CPU time	0.78 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:38 PM PDT 24
Peak memory	193720 kb
Host	smart-e8671548-d7a1-438c-82bb-c7edc238bf71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=404691582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.404691582
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1951439795
Short name	T6
Test name
Test status
Simulation time	2319365171 ps
CPU time	123.25 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:49:42 PM PDT 24
Peak memory	205508 kb
Host	smart-ec83d0a5-f39d-4861-afd8-71103d403e01
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951439795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.1951439795
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1736452357
Short name	T815
Test name
Test status
Simulation time	7032641 ps
CPU time	0.77 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:37 PM PDT 24
Peak memory	193688 kb
Host	smart-b0a88ff7-c7e7-4ee9-88e8-789c2967095c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1736452357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1736452357
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.992753063
Short name	T691
Test name
Test status
Simulation time	191432407 ps
CPU time	3.92 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:47:43 PM PDT 24
Peak memory	201880 kb
Host	smart-c9580813-a60d-42d0-9573-89dea00d89a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992753063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.992753063
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2020969625
Short name	T594
Test name
Test status
Simulation time	437562460 ps
CPU time	2.89 seconds
Started	May 30 12:47:41 PM PDT 24
Finished	May 30 12:47:45 PM PDT 24
Peak memory	201980 kb
Host	smart-841eeee3-be1c-4a0d-9ea8-fbdc17402f88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020969625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2020969625
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2552536320
Short name	T53
Test name
Test status
Simulation time	102869105 ps
CPU time	3.19 seconds
Started	May 30 12:47:39 PM PDT 24
Finished	May 30 12:47:43 PM PDT 24
Peak memory	201984 kb
Host	smart-9f378151-7a2d-469c-a0df-45d4afc7c59c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2552536320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2552536320
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.2811593772
Short name	T368
Test name
Test status
Simulation time	938190280 ps
CPU time	11.81 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:47:51 PM PDT 24
Peak memory	201992 kb
Host	smart-cbdc5a3c-76b0-4ee2-8a1e-9296ddf38c6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811593772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2811593772
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.1683149722
Short name	T262
Test name
Test status
Simulation time	5393272014 ps
CPU time	10.81 seconds
Started	May 30 12:47:41 PM PDT 24
Finished	May 30 12:47:53 PM PDT 24
Peak memory	202040 kb
Host	smart-dedaba0e-264b-4584-ab8b-cfbdd13a433c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683149722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1683149722
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2632123258
Short name	T292
Test name
Test status
Simulation time	19069640807 ps
CPU time	74.69 seconds
Started	May 30 12:47:39 PM PDT 24
Finished	May 30 12:48:55 PM PDT 24
Peak memory	202080 kb
Host	smart-192d2874-d463-439c-b542-07a5490787f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2632123258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2632123258
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.672078704
Short name	T637
Test name
Test status
Simulation time	133530337 ps
CPU time	6.57 seconds
Started	May 30 12:47:41 PM PDT 24
Finished	May 30 12:47:49 PM PDT 24
Peak memory	201968 kb
Host	smart-eeb8e9ee-01d8-41bd-8904-a53400fbbbe0
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672078704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.672078704
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.2698859652
Short name	T318
Test name
Test status
Simulation time	760071828 ps
CPU time	7.69 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:47:47 PM PDT 24
Peak memory	201908 kb
Host	smart-055992de-5184-4a28-a3dc-b45e401be751
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2698859652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2698859652
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.2807665212
Short name	T378
Test name
Test status
Simulation time	49639686 ps
CPU time	1.29 seconds
Started	May 30 12:47:39 PM PDT 24
Finished	May 30 12:47:41 PM PDT 24
Peak memory	201892 kb
Host	smart-d1c662b5-799f-4269-8e27-b05716320f2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2807665212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2807665212
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3371618935
Short name	T620
Test name
Test status
Simulation time	2095526634 ps
CPU time	8 seconds
Started	May 30 12:47:40 PM PDT 24
Finished	May 30 12:47:49 PM PDT 24
Peak memory	201980 kb
Host	smart-a940d773-76c6-4a35-9777-3857424ad2cc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371618935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3371618935
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1996316508
Short name	T489
Test name
Test status
Simulation time	1805636301 ps
CPU time	6.53 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	201964 kb
Host	smart-d1e5d681-f729-438a-b697-2b4f852bac95
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1996316508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1996316508
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.949457176
Short name	T344
Test name
Test status
Simulation time	8616137 ps
CPU time	1.1 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:38 PM PDT 24
Peak memory	201964 kb
Host	smart-10d8a677-c7b6-4e43-8543-0e917a8b835e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949457176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.949457176
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.987141426
Short name	T259
Test name
Test status
Simulation time	488274232 ps
CPU time	18.77 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:47:58 PM PDT 24
Peak memory	201980 kb
Host	smart-727e5b13-dd29-4935-95d9-5f8f76ad2fd7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987141426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.987141426
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3809501217
Short name	T415
Test name
Test status
Simulation time	1524750040 ps
CPU time	27.57 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	201912 kb
Host	smart-928bbe3c-ce36-4650-8b7d-a836c267e8ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3809501217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3809501217
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1268309177
Short name	T112
Test name
Test status
Simulation time	9976296310 ps
CPU time	247.89 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:51:47 PM PDT 24
Peak memory	208336 kb
Host	smart-58683112-181e-4b99-9ca3-fa0d7a9af2e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1268309177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1268309177
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3607182979
Short name	T164
Test name
Test status
Simulation time	124759645 ps
CPU time	10.94 seconds
Started	May 30 12:47:36 PM PDT 24
Finished	May 30 12:47:48 PM PDT 24
Peak memory	202008 kb
Host	smart-a461bf7e-6b9a-40a0-8d0a-e95d76daa96b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607182979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3607182979
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.4041499773
Short name	T91
Test name
Test status
Simulation time	495144168 ps
CPU time	4.2 seconds
Started	May 30 12:47:38 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	201980 kb
Host	smart-d1db5a8a-0e65-4298-adba-ccd31e01b295
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041499773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4041499773
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1017788272
Short name	T582
Test name
Test status
Simulation time	44527034 ps
CPU time	9.28 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:45:02 PM PDT 24
Peak memory	201932 kb
Host	smart-a0e4bbbb-96ec-46ec-9740-3add22973ba8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017788272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1017788272
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.819112127
Short name	T108
Test name
Test status
Simulation time	60408070316 ps
CPU time	334.71 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:50:29 PM PDT 24
Peak memory	203048 kb
Host	smart-03df32fa-5488-4554-88d8-e41eeb8a4841
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=819112127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.819112127
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.519656180
Short name	T622
Test name
Test status
Simulation time	1141848375 ps
CPU time	6.3 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:00 PM PDT 24
Peak memory	201976 kb
Host	smart-5e009135-b9a7-43b1-9463-a36df0a78445
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=519656180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.519656180
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.874928721
Short name	T682
Test name
Test status
Simulation time	92226417 ps
CPU time	6.48 seconds
Started	May 30 12:44:59 PM PDT 24
Finished	May 30 12:45:06 PM PDT 24
Peak memory	201916 kb
Host	smart-237e699c-37a0-432d-913c-e1f53e437047
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874928721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.874928721
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.883530794
Short name	T476
Test name
Test status
Simulation time	1723715837 ps
CPU time	5 seconds
Started	May 30 12:44:46 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201984 kb
Host	smart-8db00181-a94b-4413-b359-84746821156b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883530794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.883530794
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4052131474
Short name	T774
Test name
Test status
Simulation time	6088156266 ps
CPU time	10.47 seconds
Started	May 30 12:44:54 PM PDT 24
Finished	May 30 12:45:06 PM PDT 24
Peak memory	202048 kb
Host	smart-b0222e9a-10dc-4dd6-bf6e-3c7a48142e4b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052131474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4052131474
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2405922308
Short name	T264
Test name
Test status
Simulation time	17286470958 ps
CPU time	94 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:46:28 PM PDT 24
Peak memory	202096 kb
Host	smart-ce3109d6-620a-42d5-8f44-06766f6dc62f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2405922308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2405922308
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1431341684
Short name	T813
Test name
Test status
Simulation time	88719545 ps
CPU time	6.89 seconds
Started	May 30 12:44:43 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201976 kb
Host	smart-c9b0169d-e93e-4da5-998c-a066f87e08d1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431341684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1431341684
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.2701689460
Short name	T797
Test name
Test status
Simulation time	850940419 ps
CPU time	10.33 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:45:03 PM PDT 24
Peak memory	201996 kb
Host	smart-ff2d2cf6-bc75-4331-bfa4-cc5b41da761b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2701689460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2701689460
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.607559733
Short name	T320
Test name
Test status
Simulation time	48260650 ps
CPU time	1.47 seconds
Started	May 30 12:44:45 PM PDT 24
Finished	May 30 12:44:47 PM PDT 24
Peak memory	201916 kb
Host	smart-13f2ff4d-e90c-45c2-a1ad-148781256168
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=607559733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.607559733
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1879809522
Short name	T369
Test name
Test status
Simulation time	13477216564 ps
CPU time	12.67 seconds
Started	May 30 12:44:44 PM PDT 24
Finished	May 30 12:44:58 PM PDT 24
Peak memory	202012 kb
Host	smart-5fd11ffe-e481-43f9-ace4-75d42fadf0cc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879809522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1879809522
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2356339657
Short name	T308
Test name
Test status
Simulation time	758165139 ps
CPU time	6.42 seconds
Started	May 30 12:44:44 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201996 kb
Host	smart-7f0052c2-1224-44b4-a52f-e83d8b2c489d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2356339657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2356339657
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2830128472
Short name	T520
Test name
Test status
Simulation time	14188259 ps
CPU time	1.17 seconds
Started	May 30 12:44:46 PM PDT 24
Finished	May 30 12:44:48 PM PDT 24
Peak memory	201972 kb
Host	smart-14d84a91-e32d-4e86-a077-18f49719f118
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830128472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2830128472
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.1934742041
Short name	T746
Test name
Test status
Simulation time	5936196899 ps
CPU time	52.1 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:45:44 PM PDT 24
Peak memory	203196 kb
Host	smart-deccdc2c-9479-4512-8b16-11344e184877
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1934742041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1934742041
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.301789445
Short name	T892
Test name
Test status
Simulation time	2410803236 ps
CPU time	27.3 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:22 PM PDT 24
Peak memory	201936 kb
Host	smart-949dcac7-61f3-44cc-a6c9-0991a6ea7c78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=301789445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.301789445
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3118152316
Short name	T751
Test name
Test status
Simulation time	993226656 ps
CPU time	171.4 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:47:44 PM PDT 24
Peak memory	207728 kb
Host	smart-a778d00b-8ffb-45ac-8436-e693b51a6cd3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118152316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3118152316
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2567822009
Short name	T422
Test name
Test status
Simulation time	542324603 ps
CPU time	34.56 seconds
Started	May 30 12:44:54 PM PDT 24
Finished	May 30 12:45:30 PM PDT 24
Peak memory	203600 kb
Host	smart-9f3098d8-c7e9-468b-9ee2-286dd8f1ccd9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2567822009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.2567822009
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.563117015
Short name	T558
Test name
Test status
Simulation time	527636177 ps
CPU time	9.47 seconds
Started	May 30 12:44:50 PM PDT 24
Finished	May 30 12:45:00 PM PDT 24
Peak memory	202000 kb
Host	smart-dfa0d507-c29d-4395-9844-fc03c66a5610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=563117015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.563117015
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2853620499
Short name	T34
Test name
Test status
Simulation time	1176922308 ps
CPU time	11.44 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	201916 kb
Host	smart-692bcbda-574e-481d-a461-257a91acd5b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853620499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2853620499
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.659514300
Short name	T231
Test name
Test status
Simulation time	88472563 ps
CPU time	3.74 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:44:58 PM PDT 24
Peak memory	201924 kb
Host	smart-21847345-7fd1-4603-9427-65b8e8c2d7da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=659514300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.659514300
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.877089190
Short name	T590
Test name
Test status
Simulation time	1547466218 ps
CPU time	9.96 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:45:03 PM PDT 24
Peak memory	201980 kb
Host	smart-78005f36-90fb-4fe3-afcd-01862ec815a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=877089190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.877089190
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.1724387732
Short name	T837
Test name
Test status
Simulation time	79387556 ps
CPU time	8.05 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:45:01 PM PDT 24
Peak memory	202008 kb
Host	smart-0e64940a-2107-4cd3-8216-f1d0808ae094
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1724387732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1724387732
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3106391911
Short name	T576
Test name
Test status
Simulation time	72138739272 ps
CPU time	125.55 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:46:59 PM PDT 24
Peak memory	202068 kb
Host	smart-83cccf2d-f889-4007-9f56-7eafea627042
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106391911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3106391911
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3283675740
Short name	T141
Test name
Test status
Simulation time	3859784577 ps
CPU time	11.29 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:06 PM PDT 24
Peak memory	201952 kb
Host	smart-7dd8f4c5-57de-48ff-9abd-5dd96d223649
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3283675740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3283675740
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.529950408
Short name	T858
Test name
Test status
Simulation time	441643552 ps
CPU time	8.37 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:45:01 PM PDT 24
Peak memory	202000 kb
Host	smart-b35de19d-42d7-4c1d-ab68-dec14a0d8804
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529950408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.529950408
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.3599205991
Short name	T79
Test name
Test status
Simulation time	1604320625 ps
CPU time	3.6 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:44:58 PM PDT 24
Peak memory	201976 kb
Host	smart-83c39d87-d05a-4f60-baf2-aa36292b5f09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3599205991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3599205991
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.1390802705
Short name	T133
Test name
Test status
Simulation time	9126775 ps
CPU time	1.23 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:44:55 PM PDT 24
Peak memory	202028 kb
Host	smart-1b70553f-d898-4445-88b1-64a3fe07fa4a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1390802705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1390802705
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2354237033
Short name	T461
Test name
Test status
Simulation time	3068364305 ps
CPU time	11.38 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:05 PM PDT 24
Peak memory	202036 kb
Host	smart-7c8bf1d6-572b-4dda-9be8-94143da1e073
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354237033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2354237033
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3258873766
Short name	T236
Test name
Test status
Simulation time	706365990 ps
CPU time	4.71 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:44:56 PM PDT 24
Peak memory	202008 kb
Host	smart-8d547e0b-a985-4a7f-ba70-97c63580508b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3258873766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3258873766
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2810694630
Short name	T550
Test name
Test status
Simulation time	10248140 ps
CPU time	1.28 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:44:55 PM PDT 24
Peak memory	202008 kb
Host	smart-2ec98eeb-7e24-4db3-a474-fd3103e17a73
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810694630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2810694630
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.359814499
Short name	T607
Test name
Test status
Simulation time	4056394234 ps
CPU time	66.6 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:46:00 PM PDT 24
Peak memory	202008 kb
Host	smart-43dfe50a-cc9a-4f54-9ce1-c823e92154e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=359814499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.359814499
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3662511695
Short name	T829
Test name
Test status
Simulation time	2857508686 ps
CPU time	25.6 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:45:17 PM PDT 24
Peak memory	202008 kb
Host	smart-06189c40-2e24-4fd3-aefa-20ca945ad29e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3662511695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3662511695
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.412883963
Short name	T340
Test name
Test status
Simulation time	46415170 ps
CPU time	4.21 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:44:58 PM PDT 24
Peak memory	202000 kb
Host	smart-399794b2-08da-446c-8eb4-6c51412897a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=412883963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.412883963
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.4165533044
Short name	T512
Test name
Test status
Simulation time	9084954 ps
CPU time	3.33 seconds
Started	May 30 12:44:50 PM PDT 24
Finished	May 30 12:44:54 PM PDT 24
Peak memory	201884 kb
Host	smart-ba9913ae-7f02-48a5-9063-92e3aef8e86b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4165533044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.4165533044
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.443740970
Short name	T36
Test name
Test status
Simulation time	414484443 ps
CPU time	6.52 seconds
Started	May 30 12:44:57 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	201156 kb
Host	smart-2644ef2b-0b9c-4ddf-bb8a-85cdc562fdad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=443740970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.443740970
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2539652266
Short name	T178
Test name
Test status
Simulation time	132819220 ps
CPU time	2.4 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:44:55 PM PDT 24
Peak memory	201916 kb
Host	smart-d6f96284-62a1-4e29-b615-52e1cd6cf4f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2539652266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2539652266
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.921521263
Short name	T74
Test name
Test status
Simulation time	5396538349 ps
CPU time	39.29 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	201980 kb
Host	smart-a1695b06-42db-4ff9-bb0c-8b2fe230f757
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=921521263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow _rsp.921521263
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2664932326
Short name	T506
Test name
Test status
Simulation time	3818238842 ps
CPU time	11.49 seconds
Started	May 30 12:44:56 PM PDT 24
Finished	May 30 12:45:08 PM PDT 24
Peak memory	202068 kb
Host	smart-0eb33ae3-3005-429b-8ee6-9301eb39fcdb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664932326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2664932326
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.3354927805
Short name	T327
Test name
Test status
Simulation time	33143734 ps
CPU time	1.77 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:44:56 PM PDT 24
Peak memory	201916 kb
Host	smart-9bd3b078-388e-4ebc-ba62-2b77ab3ecd73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354927805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3354927805
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.4046549832
Short name	T646
Test name
Test status
Simulation time	490643525 ps
CPU time	7.53 seconds
Started	May 30 12:44:56 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	202004 kb
Host	smart-e1ea3ac5-339d-446f-ba52-abe9670d44ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4046549832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4046549832
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3805399761
Short name	T556
Test name
Test status
Simulation time	2065007227 ps
CPU time	7.46 seconds
Started	May 30 12:44:56 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	202028 kb
Host	smart-a10dc377-afd3-4fa7-8066-d558b680e45b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805399761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3805399761
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4228017011
Short name	T86
Test name
Test status
Simulation time	29093498719 ps
CPU time	88.11 seconds
Started	May 30 12:44:54 PM PDT 24
Finished	May 30 12:46:23 PM PDT 24
Peak memory	201956 kb
Host	smart-04301260-d862-41ca-b7a0-5cc37a764fd4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4228017011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4228017011
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.658484989
Short name	T798
Test name
Test status
Simulation time	203267980 ps
CPU time	4.63 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:44:57 PM PDT 24
Peak memory	201992 kb
Host	smart-30be3487-498b-428c-9f2b-92b481c9b233
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658484989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.658484989
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.2216783973
Short name	T46
Test name
Test status
Simulation time	1363847051 ps
CPU time	12.24 seconds
Started	May 30 12:44:51 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	202016 kb
Host	smart-95d64d56-fbd8-48dc-8ef8-47a4a4909d94
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2216783973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2216783973
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.3585184311
Short name	T20
Test name
Test status
Simulation time	13950411 ps
CPU time	1.13 seconds
Started	May 30 12:44:56 PM PDT 24
Finished	May 30 12:44:58 PM PDT 24
Peak memory	201976 kb
Host	smart-93e2c611-9255-4b7a-a521-bfe713ae599f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3585184311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3585184311
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3671690571
Short name	T692
Test name
Test status
Simulation time	2900686731 ps
CPU time	8.36 seconds
Started	May 30 12:44:54 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	202044 kb
Host	smart-c731a460-00da-4223-b55e-919ba3e9bd9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671690571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3671690571
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3032244391
Short name	T281
Test name
Test status
Simulation time	4991935558 ps
CPU time	6.81 seconds
Started	May 30 12:44:56 PM PDT 24
Finished	May 30 12:45:03 PM PDT 24
Peak memory	202076 kb
Host	smart-109a43dc-8aa1-432d-8375-a2ff86d40015
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3032244391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3032244391
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2814639197
Short name	T850
Test name
Test status
Simulation time	11876341 ps
CPU time	1.04 seconds
Started	May 30 12:44:50 PM PDT 24
Finished	May 30 12:44:52 PM PDT 24
Peak memory	201912 kb
Host	smart-6126b949-5b99-4c67-a64b-c2c737749234
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814639197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2814639197
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.1655786899
Short name	T358
Test name
Test status
Simulation time	425284145 ps
CPU time	22.54 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:17 PM PDT 24
Peak memory	201880 kb
Host	smart-e6031dc9-cf62-48c1-8ee3-7f4d59c05070
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1655786899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1655786899
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1343495553
Short name	T407
Test name
Test status
Simulation time	550824941 ps
CPU time	35.45 seconds
Started	May 30 12:44:50 PM PDT 24
Finished	May 30 12:45:26 PM PDT 24
Peak memory	201964 kb
Host	smart-39590d30-d29a-4a94-a1e7-165e63a1052a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1343495553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1343495553
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3586117285
Short name	T228
Test name
Test status
Simulation time	42819093 ps
CPU time	12.55 seconds
Started	May 30 12:44:55 PM PDT 24
Finished	May 30 12:45:08 PM PDT 24
Peak memory	202012 kb
Host	smart-db0abab1-bee5-4fd2-b24b-7e02d515d422
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3586117285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.3586117285
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.973574760
Short name	T569
Test name
Test status
Simulation time	202571310 ps
CPU time	11.95 seconds
Started	May 30 12:44:57 PM PDT 24
Finished	May 30 12:45:10 PM PDT 24
Peak memory	201996 kb
Host	smart-832ea271-c737-4075-b276-e632c848fcde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973574760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese t_error.973574760
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.792808283
Short name	T828
Test name
Test status
Simulation time	571764430 ps
CPU time	8.62 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:03 PM PDT 24
Peak memory	201976 kb
Host	smart-20396dcb-6f82-41e1-9666-0d2b4cef791a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=792808283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.792808283
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.812481213
Short name	T893
Test name
Test status
Simulation time	61081067 ps
CPU time	10 seconds
Started	May 30 12:44:53 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	201912 kb
Host	smart-266b8b54-c247-4fb5-9044-3e39242435bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812481213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.812481213
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2635827999
Short name	T530
Test name
Test status
Simulation time	7503821630 ps
CPU time	37.52 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:46:06 PM PDT 24
Peak memory	202060 kb
Host	smart-749760fc-d38a-4707-85fc-e808b9596541
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2635827999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.2635827999
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.838255965
Short name	T595
Test name
Test status
Simulation time	135920434 ps
CPU time	2.6 seconds
Started	May 30 12:45:20 PM PDT 24
Finished	May 30 12:45:24 PM PDT 24
Peak memory	201960 kb
Host	smart-283325b9-49d5-47a0-be80-567ea5cd87e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=838255965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.838255965
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.416541052
Short name	T256
Test name
Test status
Simulation time	1001690781 ps
CPU time	12.8 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201916 kb
Host	smart-45af630b-81c2-4a53-a4e7-66cd6d65eaa1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=416541052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.416541052
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.1616669191
Short name	T749
Test name
Test status
Simulation time	212913384 ps
CPU time	6.82 seconds
Started	May 30 12:44:54 PM PDT 24
Finished	May 30 12:45:02 PM PDT 24
Peak memory	201992 kb
Host	smart-64e36405-7957-4c4d-8809-14df307436a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1616669191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1616669191
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2648578124
Short name	T99
Test name
Test status
Simulation time	12992289245 ps
CPU time	38.63 seconds
Started	May 30 12:44:57 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201108 kb
Host	smart-70053887-fde1-48bc-abdf-cd0d4d3cc416
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648578124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2648578124
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.61558969
Short name	T92
Test name
Test status
Simulation time	27583373965 ps
CPU time	86.49 seconds
Started	May 30 12:44:55 PM PDT 24
Finished	May 30 12:46:22 PM PDT 24
Peak memory	202008 kb
Host	smart-24b8d1cd-033d-43b4-af8c-41c36a96c908
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=61558969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.61558969
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.970820257
Short name	T279
Test name
Test status
Simulation time	232833755 ps
CPU time	7.32 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:45:01 PM PDT 24
Peak memory	202012 kb
Host	smart-972654fb-a6db-4ef6-b475-a8392b1a25de
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970820257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.970820257
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.2032910563
Short name	T412
Test name
Test status
Simulation time	143814274 ps
CPU time	5.93 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:45:29 PM PDT 24
Peak memory	202012 kb
Host	smart-dcfbc9fc-0525-407f-8cc2-c99eee89454d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2032910563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2032910563
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.2800585135
Short name	T126
Test name
Test status
Simulation time	15684138 ps
CPU time	1.08 seconds
Started	May 30 12:44:56 PM PDT 24
Finished	May 30 12:44:58 PM PDT 24
Peak memory	202008 kb
Host	smart-9489842c-a25c-4cde-851d-337503f546a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2800585135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2800585135
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3376415487
Short name	T554
Test name
Test status
Simulation time	9803496523 ps
CPU time	9.63 seconds
Started	May 30 12:44:54 PM PDT 24
Finished	May 30 12:45:05 PM PDT 24
Peak memory	202056 kb
Host	smart-e969fc5b-4da9-4649-a438-b44277446316
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376415487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3376415487
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.488460743
Short name	T391
Test name
Test status
Simulation time	1705711162 ps
CPU time	6.17 seconds
Started	May 30 12:44:57 PM PDT 24
Finished	May 30 12:45:04 PM PDT 24
Peak memory	202000 kb
Host	smart-d6ab157f-d628-4998-bbf0-5ad7302b0542
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=488460743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.488460743
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3137979307
Short name	T57
Test name
Test status
Simulation time	10549925 ps
CPU time	1.37 seconds
Started	May 30 12:44:52 PM PDT 24
Finished	May 30 12:44:54 PM PDT 24
Peak memory	201896 kb
Host	smart-47b46b2a-161c-4f17-b998-2fd22fd9d166
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137979307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3137979307
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.2143274997
Short name	T408
Test name
Test status
Simulation time	2419061662 ps
CPU time	39.12 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:46:08 PM PDT 24
Peak memory	203064 kb
Host	smart-d1a163d0-ef6a-4040-a20a-72106d891fab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2143274997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2143274997
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.337303085
Short name	T416
Test name
Test status
Simulation time	270541950 ps
CPU time	33.26 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:46:05 PM PDT 24
Peak memory	202984 kb
Host	smart-fb7cb352-743f-43bc-a2f4-4a5f61d8f9aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=337303085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.337303085
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1077048763
Short name	T446
Test name
Test status
Simulation time	624400251 ps
CPU time	45.26 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:46:09 PM PDT 24
Peak memory	204204 kb
Host	smart-68fe4b5a-cfb6-4ec8-99c6-6f296f7fb2d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077048763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.1077048763
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3531709349
Short name	T737
Test name
Test status
Simulation time	928217678 ps
CPU time	113.55 seconds
Started	May 30 12:45:21 PM PDT 24
Finished	May 30 12:47:16 PM PDT 24
Peak memory	207080 kb
Host	smart-5cfe2654-c44b-49df-8b67-265891c0a5bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3531709349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.3531709349
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3678467568
Short name	T458
Test name
Test status
Simulation time	491953431 ps
CPU time	8.4 seconds
Started	May 30 12:45:22 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	201912 kb
Host	smart-4e159633-0a0b-496a-b150-69b5c6e0ff9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3678467568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3678467568
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1441696172
Short name	T111
Test name
Test status
Simulation time	2493974480 ps
CPU time	7.12 seconds
Started	May 30 12:45:21 PM PDT 24
Finished	May 30 12:45:29 PM PDT 24
Peak memory	202024 kb
Host	smart-e3478093-e11b-4996-93b8-be622e480450
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1441696172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1441696172
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.549336248
Short name	T565
Test name
Test status
Simulation time	619702065 ps
CPU time	6.74 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201892 kb
Host	smart-83693667-1b28-48ae-964f-4c74d1957935
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=549336248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.549336248
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.2819727302
Short name	T531
Test name
Test status
Simulation time	6676489624 ps
CPU time	11.95 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:45:41 PM PDT 24
Peak memory	201936 kb
Host	smart-30f3dda9-79fc-4ef3-9a44-ebddc8652e6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2819727302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2819727302
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.2013659784
Short name	T390
Test name
Test status
Simulation time	38456303 ps
CPU time	2.22 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:45:26 PM PDT 24
Peak memory	201920 kb
Host	smart-fb9b2e65-99b7-4d07-bfff-182c8625d476
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2013659784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2013659784
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1004539328
Short name	T370
Test name
Test status
Simulation time	32939386173 ps
CPU time	125.36 seconds
Started	May 30 12:45:26 PM PDT 24
Finished	May 30 12:47:33 PM PDT 24
Peak memory	201968 kb
Host	smart-4c8686b1-195a-46e4-a8be-225fc4953882
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004539328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1004539328
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3455045295
Short name	T553
Test name
Test status
Simulation time	12548467935 ps
CPU time	35.59 seconds
Started	May 30 12:45:25 PM PDT 24
Finished	May 30 12:46:02 PM PDT 24
Peak memory	202056 kb
Host	smart-829e7fca-fbe7-47a7-bc8c-21798d15a780
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3455045295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3455045295
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.4154219222
Short name	T58
Test name
Test status
Simulation time	23581293 ps
CPU time	3.11 seconds
Started	May 30 12:45:31 PM PDT 24
Finished	May 30 12:45:36 PM PDT 24
Peak memory	201960 kb
Host	smart-7bd3eeb3-12cb-4eaf-9bc7-bef1404ff75f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154219222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.4154219222
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.971679268
Short name	T701
Test name
Test status
Simulation time	924723751 ps
CPU time	11.81 seconds
Started	May 30 12:45:29 PM PDT 24
Finished	May 30 12:45:43 PM PDT 24
Peak memory	201976 kb
Host	smart-ead3a143-931f-447e-9c04-74e77a1c655e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=971679268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.971679268
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.2513804005
Short name	T720
Test name
Test status
Simulation time	38145755 ps
CPU time	1.27 seconds
Started	May 30 12:45:30 PM PDT 24
Finished	May 30 12:45:33 PM PDT 24
Peak memory	201936 kb
Host	smart-65395df3-5bc4-4d37-aab1-0de7ffa0bf78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2513804005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2513804005
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2307881509
Short name	T562
Test name
Test status
Simulation time	1333530065 ps
CPU time	5.74 seconds
Started	May 30 12:45:24 PM PDT 24
Finished	May 30 12:45:31 PM PDT 24
Peak memory	201940 kb
Host	smart-9d16a29c-acd6-427b-bb8d-2966544117f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307881509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2307881509
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.4046617420
Short name	T363
Test name
Test status
Simulation time	824623663 ps
CPU time	5.07 seconds
Started	May 30 12:45:35 PM PDT 24
Finished	May 30 12:45:42 PM PDT 24
Peak memory	201980 kb
Host	smart-b84f7593-9ab9-4bd7-a152-3a104443d308
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4046617420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4046617420
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3886627564
Short name	T1
Test name
Test status
Simulation time	16248589 ps
CPU time	1.13 seconds
Started	May 30 12:45:25 PM PDT 24
Finished	May 30 12:45:27 PM PDT 24
Peak memory	202012 kb
Host	smart-23c8a3f1-645d-4a31-8def-0b9945de4c99
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886627564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3886627564
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.1578011868
Short name	T564
Test name
Test status
Simulation time	128461458 ps
CPU time	15.5 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:45:39 PM PDT 24
Peak memory	201948 kb
Host	smart-337c3d7f-b7e8-4788-a47c-4ca6067b433f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1578011868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1578011868
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1028515210
Short name	T435
Test name
Test status
Simulation time	232475254 ps
CPU time	25.07 seconds
Started	May 30 12:45:20 PM PDT 24
Finished	May 30 12:45:46 PM PDT 24
Peak memory	202000 kb
Host	smart-7d66838f-1f4f-416a-8f4c-fad3785fd61e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028515210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1028515210
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2292248041
Short name	T464
Test name
Test status
Simulation time	852589010 ps
CPU time	180.06 seconds
Started	May 30 12:45:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	208832 kb
Host	smart-4b44940e-4f22-4e57-815e-0fa94a46908c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2292248041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.2292248041
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1349498931
Short name	T8
Test name
Test status
Simulation time	310992007 ps
CPU time	31.5 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:45:56 PM PDT 24
Peak memory	203248 kb
Host	smart-250c2212-df3b-4ef0-a176-f668f9c19595
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1349498931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1349498931
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3542951122
Short name	T760
Test name
Test status
Simulation time	862462908 ps
CPU time	13.03 seconds
Started	May 30 12:45:23 PM PDT 24
Finished	May 30 12:45:37 PM PDT 24
Peak memory	201948 kb
Host	smart-af0b1da1-2f16-4088-8f82-979d449ec4f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3542951122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3542951122
Directory	/workspace/9.xbar_unmapped_addr/latest