Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	423	1			T18	1		T63	2		T48	1
all_values[1]	437	1			T18	3		T63	2		T27	2
all_values[2]	451	1			T18	3		T63	1		T29	1
all_values[3]	493	1			T18	2		T63	1		T29	2
all_values[4]	428	1			T18	2		T63	2		T48	2
all_values[5]	490	1			T18	2		T63	1		T27	1
all_values[6]	450	1			T18	2		T48	1		T34	2
all_values[7]	453	1			T18	3		T27	1		T29	1
all_values[8]	430	1			T18	2		T63	1		T29	1
all_values[9]	428	1			T18	2		T63	1		T48	1
all_values[10]	419	1			T18	3		T27	1		T29	1
all_values[11]	464	1			T63	1		T29	1		T82	2
all_values[12]	466	1			T18	1		T63	1		T27	1
all_values[13]	467	1			T27	1		T29	3		T32	2
all_values[14]	487	1			T18	3		T63	1		T27	1
all_values[15]	436	1			T18	3		T63	3		T27	1
all_values[16]	468	1			T18	1		T63	2		T48	1
all_values[17]	466	1			T18	1		T63	1		T32	2
all_values[18]	429	1			T18	5		T63	3		T32	4
all_values[19]	477	1			T18	2		T27	1		T32	8
all_values[20]	462	1			T18	2		T27	1		T29	1
all_values[21]	471	1			T63	2		T29	1		T48	2
all_values[22]	441	1			T18	2		T63	3		T29	1
all_values[23]	420	1			T18	1		T29	1		T34	2
all_values[24]	484	1			T18	2		T63	4		T29	1
all_values[25]	425	1			T18	2		T63	2		T27	1
all_values[26]	475	1			T18	1		T63	3		T27	1