Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	500	1			T40	2		T42	1		T43	1
all_values[1]	467	1			T40	5		T39	1		T42	1
all_values[2]	509	1			T40	9		T42	1		T46	3
all_values[3]	504	1			T2	1		T40	5		T42	1
all_values[4]	470	1			T40	5		T43	1		T46	3
all_values[5]	516	1			T40	5		T42	1		T59	1
all_values[6]	429	1			T40	2		T59	1		T46	7
all_values[7]	440	1			T15	1		T40	5		T46	5
all_values[8]	520	1			T40	5		T43	2		T46	8
all_values[9]	488	1			T15	1		T40	4		T39	1
all_values[10]	473	1			T40	5		T42	1		T43	2
all_values[11]	494	1			T40	2		T59	1		T43	3
all_values[12]	463	1			T40	4		T39	1		T43	1
all_values[13]	467	1			T40	6		T43	1		T46	4
all_values[14]	464	1			T2	1		T40	2		T46	3
all_values[15]	439	1			T40	5		T46	2		T60	2
all_values[16]	534	1			T2	1		T40	14		T39	1
all_values[17]	461	1			T15	1		T40	4		T42	1
all_values[18]	494	1			T40	5		T43	2		T46	5
all_values[19]	503	1			T2	1		T40	9		T43	1
all_values[20]	494	1			T38	1		T40	2		T43	2
all_values[21]	476	1			T40	6		T42	2		T43	1
all_values[22]	447	1			T38	2		T40	3		T43	1
all_values[23]	507	1			T40	4		T42	1		T46	5
all_values[24]	469	1			T2	4		T15	1		T40	10
all_values[25]	510	1			T40	5		T42	1		T46	8
all_values[26]	490	1			T40	6		T42	1		T43	1