Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	389	1			T10	2		T51	3		T34	4
all_values[1]	360	1			T20	3		T34	2		T39	2
all_values[2]	381	1			T10	3		T14	2		T51	4
all_values[3]	416	1			T19	1		T20	3		T34	9
all_values[4]	374	1			T10	1		T14	1		T20	1
all_values[5]	414	1			T14	1		T51	2		T19	1
all_values[6]	383	1			T34	5		T66	5		T268	1
all_values[7]	390	1			T51	2		T20	1		T34	6
all_values[8]	392	1			T10	2		T14	2		T51	3
all_values[9]	413	1			T19	1		T34	3		T66	9
all_values[10]	394	1			T51	3		T34	4		T37	1
all_values[11]	394	1			T51	3		T34	1		T39	1
all_values[12]	407	1			T10	1		T14	1		T51	1
all_values[13]	385	1			T14	1		T51	1		T20	1
all_values[14]	420	1			T10	1		T51	2		T34	5
all_values[15]	414	1			T10	1		T51	1		T20	2
all_values[16]	394	1			T19	2		T20	1		T34	7
all_values[17]	381	1			T14	1		T20	1		T34	2
all_values[18]	351	1			T10	1		T14	1		T34	6
all_values[19]	403	1			T51	2		T20	1		T34	4
all_values[20]	402	1			T51	3		T20	2		T34	4
all_values[21]	372	1			T10	1		T20	2		T34	3
all_values[22]	397	1			T14	1		T51	1		T19	1
all_values[23]	397	1			T19	1		T20	1		T34	6
all_values[24]	397	1			T51	2		T20	1		T34	4
all_values[25]	403	1			T10	1		T34	6		T66	9
all_values[26]	413	1			T10	1		T20	3		T34	4