Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 434 1 T18 1 T14 1 T43 1
all_values[1] 440 1 T43 1 T51 1 T138 3
all_values[2] 427 1 T18 1 T14 1 T21 1
all_values[3] 479 1 T14 1 T43 2 T138 4
all_values[4] 400 1 T18 1 T43 1 T51 5
all_values[5] 387 1 T14 1 T48 1 T51 4
all_values[6] 409 1 T51 2 T52 1 T138 7
all_values[7] 468 1 T21 1 T51 2 T138 5
all_values[8] 417 1 T18 2 T21 1 T43 1
all_values[9] 435 1 T43 1 T50 1 T51 1
all_values[10] 442 1 T2 1 T18 1 T21 2
all_values[11] 401 1 T18 1 T48 1 T51 5
all_values[12] 418 1 T14 1 T39 1 T51 2
all_values[13] 395 1 T2 1 T18 2 T21 1
all_values[14] 411 1 T18 1 T14 1 T21 2
all_values[15] 404 1 T2 1 T51 3 T138 7
all_values[16] 406 1 T43 2 T51 2 T138 5
all_values[17] 412 1 T21 1 T43 2 T51 3
all_values[18] 424 1 T21 1 T50 1 T51 1
all_values[19] 447 1 T18 1 T21 1 T52 1
all_values[20] 448 1 T50 2 T51 1 T138 7
all_values[21] 430 1 T2 1 T50 1 T51 3
all_values[22] 420 1 T43 3 T48 2 T51 6
all_values[23] 408 1 T14 1 T21 1 T51 1
all_values[24] 430 1 T2 1 T14 1 T21 2
all_values[25] 441 1 T43 1 T50 1 T51 2
all_values[26] 397 1 T21 1 T51 1 T138 2

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