Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 495 1 T9 3 T21 1 T239 2
all_values[1] 451 1 T3 2 T9 1 T21 1
all_values[2] 441 1 T3 2 T9 4 T21 1
all_values[3] 482 1 T9 5 T21 3 T26 3
all_values[4] 451 1 T9 7 T18 1 T24 1
all_values[5] 458 1 T3 1 T9 4 T26 1
all_values[6] 449 1 T3 2 T9 5 T24 1
all_values[7] 476 1 T9 2 T21 1 T26 1
all_values[8] 433 1 T3 1 T9 5 T24 2
all_values[9] 474 1 T3 1 T9 6 T21 1
all_values[10] 443 1 T3 1 T9 2 T24 1
all_values[11] 452 1 T3 1 T9 6 T26 1
all_values[12] 451 1 T3 2 T9 4 T21 1
all_values[13] 497 1 T3 3 T9 7 T18 1
all_values[14] 422 1 T3 3 T9 3 T26 3
all_values[15] 472 1 T3 1 T9 8 T21 1
all_values[16] 463 1 T3 1 T9 4 T24 1
all_values[17] 436 1 T3 2 T9 7 T21 2
all_values[18] 473 1 T9 5 T21 1 T26 2
all_values[19] 452 1 T3 3 T9 6 T21 1
all_values[20] 423 1 T3 2 T9 4 T239 1
all_values[21] 475 1 T9 5 T18 1 T24 1
all_values[22] 431 1 T9 4 T21 1 T239 7
all_values[23] 468 1 T9 6 T21 1 T18 1
all_values[24] 478 1 T3 2 T9 2 T18 1
all_values[25] 459 1 T3 1 T9 7 T24 1
all_values[26] 439 1 T9 9 T239 2 T6 3

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