Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	402	1			T1	1		T13	2		T12	6
all_values[1]	400	1			T1	2		T13	1		T19	1
all_values[2]	429	1			T13	3		T12	2		T157	4
all_values[3]	444	1			T13	4		T12	2		T157	7
all_values[4]	409	1			T1	1		T13	4		T12	8
all_values[5]	454	1			T1	2		T13	5		T12	6
all_values[6]	423	1			T16	1		T13	2		T12	4
all_values[7]	405	1			T1	1		T13	8		T12	3
all_values[8]	446	1			T1	1		T13	3		T12	5
all_values[9]	439	1			T1	3		T13	4		T12	5
all_values[10]	432	1			T1	3		T13	3		T12	6
all_values[11]	448	1			T1	1		T13	3		T12	6
all_values[12]	409	1			T13	5		T12	2		T157	3
all_values[13]	448	1			T1	4		T13	3		T12	2
all_values[14]	445	1			T1	2		T13	7		T12	2
all_values[15]	404	1			T1	1		T13	6		T12	5
all_values[16]	405	1			T1	1		T13	8		T12	11
all_values[17]	447	1			T13	6		T12	3		T51	2
all_values[18]	448	1			T1	1		T13	6		T12	4
all_values[19]	442	1			T1	2		T13	4		T12	2
all_values[20]	409	1			T1	1		T13	5		T12	4
all_values[21]	430	1			T1	2		T13	6		T12	4
all_values[22]	425	1			T1	1		T13	4		T12	7
all_values[23]	431	1			T1	1		T13	2		T12	4
all_values[24]	423	1			T1	2		T13	5		T12	7
all_values[25]	456	1			T13	5		T12	3		T51	1
all_values[26]	398	1			T1	2		T13	3		T12	6