Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	469	1			T14	2		T38	1		T40	3
all_values[1]	467	1			T14	5		T13	1		T40	1
all_values[2]	439	1			T22	1		T37	1		T40	2
all_values[3]	456	1			T14	3		T22	3		T40	1
all_values[4]	448	1			T14	2		T13	1		T22	1
all_values[5]	403	1			T14	2		T40	1		T65	2
all_values[6]	452	1			T14	4		T22	1		T38	1
all_values[7]	454	1			T14	6		T37	2		T40	1
all_values[8]	468	1			T14	2		T22	2		T37	1
all_values[9]	460	1			T14	5		T22	1		T37	1
all_values[10]	437	1			T14	1		T38	1		T40	3
all_values[11]	437	1			T14	2		T38	1		T40	6
all_values[12]	451	1			T14	4		T18	1		T22	1
all_values[13]	441	1			T14	3		T22	1		T40	2
all_values[14]	469	1			T14	2		T22	1		T40	4
all_values[15]	463	1			T14	5		T22	1		T38	1
all_values[16]	445	1			T22	1		T40	4		T65	5
all_values[17]	458	1			T14	2		T18	1		T13	1
all_values[18]	447	1			T14	2		T22	2		T37	1
all_values[19]	433	1			T22	1		T38	1		T40	2
all_values[20]	518	1			T14	5		T13	1		T22	2
all_values[21]	439	1			T14	6		T18	1		T22	2
all_values[22]	444	1			T14	3		T13	2		T37	1
all_values[23]	477	1			T14	1		T22	2		T38	1
all_values[24]	429	1			T14	1		T22	1		T40	2
all_values[25]	477	1			T22	1		T37	1		T40	2
all_values[26]	447	1			T14	3		T13	1		T22	2