Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	458	1			T6	1		T24	7		T49	1
all_values[1]	445	1			T3	1		T24	3		T218	1
all_values[2]	451	1			T3	3		T24	5		T74	1
all_values[3]	445	1			T6	2		T24	4		T43	1
all_values[4]	457	1			T24	7		T44	2		T75	1
all_values[5]	445	1			T3	1		T6	1		T24	6
all_values[6]	468	1			T6	1		T24	7		T43	1
all_values[7]	413	1			T3	1		T6	1		T24	1
all_values[8]	443	1			T24	6		T43	2		T44	1
all_values[9]	449	1			T3	2		T24	7		T43	1
all_values[10]	430	1			T24	13		T43	2		T15	2
all_values[11]	439	1			T3	2		T24	10		T49	1
all_values[12]	463	1			T24	6		T218	1		T43	2
all_values[13]	448	1			T6	1		T24	4		T49	1
all_values[14]	431	1			T3	1		T24	7		T218	1
all_values[15]	423	1			T3	1		T24	7		T43	1
all_values[16]	430	1			T3	1		T6	1		T24	7
all_values[17]	433	1			T6	1		T24	8		T49	3
all_values[18]	423	1			T3	1		T6	2		T24	7
all_values[19]	471	1			T3	1		T24	8		T44	1
all_values[20]	434	1			T3	1		T24	8		T218	2
all_values[21]	430	1			T6	2		T24	8		T49	2
all_values[22]	439	1			T6	1		T24	6		T49	1
all_values[23]	418	1			T3	3		T6	1		T24	5
all_values[24]	447	1			T6	1		T24	3		T75	3
all_values[25]	450	1			T6	1		T24	8		T49	1
all_values[26]	465	1			T6	1		T24	8		T43	3