Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 439 1 T4 5 T15 2 T154 2
all_values[1] 456 1 T4 2 T15 4 T23 1
all_values[2] 404 1 T2 1 T3 1 T15 4
all_values[3] 385 1 T4 7 T15 3 T16 2
all_values[4] 417 1 T4 2 T15 4 T23 2
all_values[5] 413 1 T4 5 T15 5 T154 1
all_values[6] 448 1 T3 1 T4 1 T15 7
all_values[7] 451 1 T3 1 T4 5 T15 3
all_values[8] 458 1 T3 1 T4 1 T15 4
all_values[9] 416 1 T4 2 T15 7 T16 1
all_values[10] 424 1 T2 1 T3 3 T4 3
all_values[11] 462 1 T4 3 T15 4 T16 1
all_values[12] 421 1 T3 1 T4 4 T15 3
all_values[13] 438 1 T3 1 T4 2 T15 6
all_values[14] 447 1 T3 1 T4 5 T15 3
all_values[15] 420 1 T2 1 T4 1 T15 7
all_values[16] 436 1 T4 5 T15 5 T154 1
all_values[17] 425 1 T4 1 T15 1 T154 2
all_values[18] 444 1 T3 1 T4 7 T15 6
all_values[19] 431 1 T15 3 T20 1 T154 1
all_values[20] 465 1 T4 2 T15 5 T19 2
all_values[21] 492 1 T3 1 T4 3 T15 5
all_values[22] 444 1 T3 1 T4 5 T15 2
all_values[23] 426 1 T2 1 T4 4 T15 4
all_values[24] 439 1 T4 3 T15 1 T20 1
all_values[25] 465 1 T3 2 T4 3 T15 1
all_values[26] 432 1 T4 2 T15 8 T154 2

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