Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	464	1			T6	4		T63	3		T35	4
all_values[1]	475	1			T6	6		T63	2		T35	4
all_values[2]	493	1			T13	1		T6	1		T63	1
all_values[3]	473	1			T13	1		T6	9		T168	1
all_values[4]	454	1			T13	1		T6	1		T63	5
all_values[5]	468	1			T13	2		T6	3		T168	1
all_values[6]	458	1			T6	4		T168	1		T63	2
all_values[7]	461	1			T6	7		T168	1		T63	1
all_values[8]	462	1			T6	3		T63	2		T35	3
all_values[9]	465	1			T13	1		T6	3		T168	1
all_values[10]	478	1			T13	3		T6	3		T168	1
all_values[11]	421	1			T13	1		T6	6		T63	6
all_values[12]	476	1			T63	2		T35	8		T37	8
all_values[13]	511	1			T6	5		T168	1		T63	3
all_values[14]	494	1			T6	4		T168	1		T63	2
all_values[15]	473	1			T6	4		T63	6		T35	6
all_values[16]	462	1			T13	1		T6	3		T63	1
all_values[17]	464	1			T6	3		T63	3		T35	2
all_values[18]	498	1			T13	1		T6	6		T168	3
all_values[19]	502	1			T6	4		T63	5		T35	3
all_values[20]	450	1			T168	1		T63	2		T35	2
all_values[21]	452	1			T6	3		T168	2		T63	1
all_values[22]	483	1			T13	1		T6	3		T35	5
all_values[23]	473	1			T13	2		T6	4		T168	2
all_values[24]	452	1			T6	4		T168	4		T63	2
all_values[25]	473	1			T13	1		T6	3		T168	1
all_values[26]	442	1			T6	3		T168	2		T63	3