Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 100.00 95.61 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T208 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.798403534 Jun 28 05:27:45 PM PDT 24 Jun 28 05:34:28 PM PDT 24 353396934161 ps
T761 /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3381209416 Jun 28 05:25:12 PM PDT 24 Jun 28 05:30:54 PM PDT 24 51701432128 ps
T762 /workspace/coverage/xbar_build_mode/5.xbar_error_random.1982236495 Jun 28 05:23:59 PM PDT 24 Jun 28 05:24:05 PM PDT 24 391981114 ps
T763 /workspace/coverage/xbar_build_mode/2.xbar_same_source.1981867766 Jun 28 05:23:27 PM PDT 24 Jun 28 05:23:34 PM PDT 24 488846739 ps
T764 /workspace/coverage/xbar_build_mode/45.xbar_smoke.2201766576 Jun 28 05:29:34 PM PDT 24 Jun 28 05:29:35 PM PDT 24 9433397 ps
T765 /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1142612271 Jun 28 05:26:28 PM PDT 24 Jun 28 05:27:02 PM PDT 24 6035836529 ps
T766 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.429914713 Jun 28 05:26:40 PM PDT 24 Jun 28 05:27:02 PM PDT 24 148513999 ps
T110 /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2568787975 Jun 28 05:29:42 PM PDT 24 Jun 28 05:31:16 PM PDT 24 7313777143 ps
T767 /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3451622603 Jun 28 05:26:38 PM PDT 24 Jun 28 05:27:13 PM PDT 24 823371441 ps
T768 /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1469250896 Jun 28 05:28:31 PM PDT 24 Jun 28 05:28:38 PM PDT 24 1396678381 ps
T769 /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1420659087 Jun 28 05:24:49 PM PDT 24 Jun 28 05:24:53 PM PDT 24 23863788 ps
T770 /workspace/coverage/xbar_build_mode/38.xbar_same_source.4243017668 Jun 28 05:28:37 PM PDT 24 Jun 28 05:28:43 PM PDT 24 769438106 ps
T771 /workspace/coverage/xbar_build_mode/8.xbar_same_source.3884550273 Jun 28 05:24:31 PM PDT 24 Jun 28 05:24:36 PM PDT 24 41567260 ps
T772 /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2302156005 Jun 28 05:27:01 PM PDT 24 Jun 28 05:27:13 PM PDT 24 2874354003 ps
T773 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3809242371 Jun 28 05:27:53 PM PDT 24 Jun 28 05:29:58 PM PDT 24 5536739929 ps
T774 /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1920227235 Jun 28 05:29:26 PM PDT 24 Jun 28 05:29:31 PM PDT 24 46165372 ps
T775 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.560351342 Jun 28 05:24:08 PM PDT 24 Jun 28 05:24:32 PM PDT 24 280756815 ps
T776 /workspace/coverage/xbar_build_mode/37.xbar_smoke.3724267881 Jun 28 05:28:32 PM PDT 24 Jun 28 05:28:34 PM PDT 24 9331549 ps
T777 /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3862938735 Jun 28 05:28:09 PM PDT 24 Jun 28 05:29:30 PM PDT 24 5719821434 ps
T778 /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.582982651 Jun 28 05:27:18 PM PDT 24 Jun 28 05:27:23 PM PDT 24 33855726 ps
T779 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2207701585 Jun 28 05:24:05 PM PDT 24 Jun 28 05:24:59 PM PDT 24 296365266 ps
T780 /workspace/coverage/xbar_build_mode/43.xbar_random.1658964909 Jun 28 05:29:16 PM PDT 24 Jun 28 05:29:22 PM PDT 24 616553180 ps
T781 /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3706760827 Jun 28 05:27:18 PM PDT 24 Jun 28 05:27:24 PM PDT 24 757744804 ps
T782 /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2817671 Jun 28 05:25:59 PM PDT 24 Jun 28 05:26:15 PM PDT 24 68784485 ps
T783 /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3052076043 Jun 28 05:29:29 PM PDT 24 Jun 28 05:30:55 PM PDT 24 27333182077 ps
T784 /workspace/coverage/xbar_build_mode/6.xbar_random.1066245847 Jun 28 05:24:04 PM PDT 24 Jun 28 05:24:12 PM PDT 24 87657900 ps
T785 /workspace/coverage/xbar_build_mode/19.xbar_smoke.3307213624 Jun 28 05:26:14 PM PDT 24 Jun 28 05:26:17 PM PDT 24 262787288 ps
T786 /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1138639469 Jun 28 05:29:50 PM PDT 24 Jun 28 05:30:03 PM PDT 24 5773425175 ps
T787 /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3244985676 Jun 28 05:25:34 PM PDT 24 Jun 28 05:26:00 PM PDT 24 7413330482 ps
T788 /workspace/coverage/xbar_build_mode/32.xbar_same_source.3591440059 Jun 28 05:27:53 PM PDT 24 Jun 28 05:27:57 PM PDT 24 331118414 ps
T789 /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4013995823 Jun 28 05:26:29 PM PDT 24 Jun 28 05:26:40 PM PDT 24 3456905531 ps
T790 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.111330866 Jun 28 05:27:31 PM PDT 24 Jun 28 05:27:44 PM PDT 24 3663435608 ps
T791 /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3655174780 Jun 28 05:28:34 PM PDT 24 Jun 28 05:29:29 PM PDT 24 720288051 ps
T792 /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.424342477 Jun 28 05:28:20 PM PDT 24 Jun 28 05:28:28 PM PDT 24 371128521 ps
T793 /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3911150435 Jun 28 05:24:09 PM PDT 24 Jun 28 05:24:22 PM PDT 24 2395920509 ps
T794 /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2694071312 Jun 28 05:27:04 PM PDT 24 Jun 28 05:27:11 PM PDT 24 2585045069 ps
T795 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1630322033 Jun 28 05:28:32 PM PDT 24 Jun 28 05:28:51 PM PDT 24 10360715389 ps
T796 /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3822734664 Jun 28 05:29:48 PM PDT 24 Jun 28 05:29:52 PM PDT 24 57428569 ps
T123 /workspace/coverage/xbar_build_mode/9.xbar_stress_all.166260507 Jun 28 05:24:53 PM PDT 24 Jun 28 05:25:52 PM PDT 24 3242648011 ps
T797 /workspace/coverage/xbar_build_mode/15.xbar_random.1426488671 Jun 28 05:25:36 PM PDT 24 Jun 28 05:25:52 PM PDT 24 1248153676 ps
T798 /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.125304388 Jun 28 05:23:46 PM PDT 24 Jun 28 05:23:48 PM PDT 24 11421461 ps
T799 /workspace/coverage/xbar_build_mode/3.xbar_same_source.1674670123 Jun 28 05:23:41 PM PDT 24 Jun 28 05:23:49 PM PDT 24 1653713244 ps
T800 /workspace/coverage/xbar_build_mode/39.xbar_smoke.2961383906 Jun 28 05:28:43 PM PDT 24 Jun 28 05:28:45 PM PDT 24 9538255 ps
T801 /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2486404293 Jun 28 05:28:48 PM PDT 24 Jun 28 05:29:02 PM PDT 24 2602544157 ps
T802 /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2394587808 Jun 28 05:29:28 PM PDT 24 Jun 28 05:29:30 PM PDT 24 12779908 ps
T803 /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3235844321 Jun 28 05:23:02 PM PDT 24 Jun 28 05:23:14 PM PDT 24 6841173871 ps
T804 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.4120749035 Jun 28 05:29:15 PM PDT 24 Jun 28 05:29:23 PM PDT 24 949865138 ps
T805 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1427617628 Jun 28 05:26:40 PM PDT 24 Jun 28 05:29:02 PM PDT 24 2941461784 ps
T806 /workspace/coverage/xbar_build_mode/4.xbar_smoke.911192977 Jun 28 05:23:48 PM PDT 24 Jun 28 05:23:50 PM PDT 24 12554193 ps
T807 /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2632943054 Jun 28 05:23:15 PM PDT 24 Jun 28 05:23:21 PM PDT 24 60647958 ps
T808 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1968501326 Jun 28 05:27:32 PM PDT 24 Jun 28 05:28:37 PM PDT 24 25699359260 ps
T809 /workspace/coverage/xbar_build_mode/16.xbar_smoke.3349254414 Jun 28 05:25:47 PM PDT 24 Jun 28 05:25:49 PM PDT 24 11241394 ps
T810 /workspace/coverage/xbar_build_mode/10.xbar_random.2114991314 Jun 28 05:24:52 PM PDT 24 Jun 28 05:24:55 PM PDT 24 353531901 ps
T811 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3084521674 Jun 28 05:23:17 PM PDT 24 Jun 28 05:23:21 PM PDT 24 13306116 ps
T812 /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3643264904 Jun 28 05:23:03 PM PDT 24 Jun 28 05:23:05 PM PDT 24 8874368 ps
T813 /workspace/coverage/xbar_build_mode/42.xbar_smoke.2433849883 Jun 28 05:29:14 PM PDT 24 Jun 28 05:29:16 PM PDT 24 9838040 ps
T116 /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.410426180 Jun 28 05:29:14 PM PDT 24 Jun 28 05:30:35 PM PDT 24 23432626041 ps
T814 /workspace/coverage/xbar_build_mode/19.xbar_random.3084544368 Jun 28 05:26:14 PM PDT 24 Jun 28 05:26:31 PM PDT 24 4622573418 ps
T815 /workspace/coverage/xbar_build_mode/25.xbar_stress_all.499475846 Jun 28 05:27:23 PM PDT 24 Jun 28 05:27:47 PM PDT 24 1510219722 ps
T816 /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4277645517 Jun 28 05:28:09 PM PDT 24 Jun 28 05:28:13 PM PDT 24 218992650 ps
T817 /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3976989280 Jun 28 05:26:39 PM PDT 24 Jun 28 05:26:41 PM PDT 24 9121939 ps
T818 /workspace/coverage/xbar_build_mode/25.xbar_error_random.301683856 Jun 28 05:27:19 PM PDT 24 Jun 28 05:27:22 PM PDT 24 42808323 ps
T819 /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2772268701 Jun 28 05:27:30 PM PDT 24 Jun 28 05:27:32 PM PDT 24 14732647 ps
T820 /workspace/coverage/xbar_build_mode/0.xbar_random.3076004581 Jun 28 05:23:05 PM PDT 24 Jun 28 05:23:10 PM PDT 24 39028670 ps
T821 /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3184410700 Jun 28 05:24:17 PM PDT 24 Jun 28 05:24:25 PM PDT 24 2109356080 ps
T822 /workspace/coverage/xbar_build_mode/31.xbar_same_source.2913286134 Jun 28 05:28:00 PM PDT 24 Jun 28 05:28:04 PM PDT 24 115143245 ps
T125 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3090530089 Jun 28 05:27:03 PM PDT 24 Jun 28 05:27:24 PM PDT 24 830060971 ps
T823 /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2030243393 Jun 28 05:26:25 PM PDT 24 Jun 28 05:26:33 PM PDT 24 3424297167 ps
T824 /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2132771778 Jun 28 05:26:14 PM PDT 24 Jun 28 05:26:20 PM PDT 24 2722978645 ps
T825 /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3988584729 Jun 28 05:28:42 PM PDT 24 Jun 28 05:28:49 PM PDT 24 9438907984 ps
T826 /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1457817167 Jun 28 05:25:14 PM PDT 24 Jun 28 05:25:30 PM PDT 24 238478320 ps
T827 /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3340738231 Jun 28 05:29:29 PM PDT 24 Jun 28 05:29:32 PM PDT 24 29936541 ps
T828 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.780386037 Jun 28 05:29:41 PM PDT 24 Jun 28 05:29:49 PM PDT 24 5434155390 ps
T829 /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1036088413 Jun 28 05:25:01 PM PDT 24 Jun 28 05:25:16 PM PDT 24 1086428891 ps
T830 /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2549146255 Jun 28 05:26:26 PM PDT 24 Jun 28 05:26:31 PM PDT 24 746601143 ps
T831 /workspace/coverage/xbar_build_mode/30.xbar_random.427996608 Jun 28 05:27:31 PM PDT 24 Jun 28 05:27:44 PM PDT 24 5145529069 ps
T832 /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.82935267 Jun 28 05:25:46 PM PDT 24 Jun 28 05:26:01 PM PDT 24 1465356748 ps
T833 /workspace/coverage/xbar_build_mode/18.xbar_error_random.1095305813 Jun 28 05:25:58 PM PDT 24 Jun 28 05:26:00 PM PDT 24 79026969 ps
T834 /workspace/coverage/xbar_build_mode/49.xbar_error_random.3785771606 Jun 28 05:29:55 PM PDT 24 Jun 28 05:29:58 PM PDT 24 24960927 ps
T835 /workspace/coverage/xbar_build_mode/23.xbar_error_random.1006096429 Jun 28 05:27:03 PM PDT 24 Jun 28 05:27:07 PM PDT 24 436068441 ps
T836 /workspace/coverage/xbar_build_mode/21.xbar_random.1395581838 Jun 28 05:26:27 PM PDT 24 Jun 28 05:26:37 PM PDT 24 73830095 ps
T837 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2698667880 Jun 28 05:29:51 PM PDT 24 Jun 28 05:31:19 PM PDT 24 2199213384 ps
T838 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3579048078 Jun 28 05:24:50 PM PDT 24 Jun 28 05:24:58 PM PDT 24 1411198166 ps
T839 /workspace/coverage/xbar_build_mode/25.xbar_smoke.198885191 Jun 28 05:27:04 PM PDT 24 Jun 28 05:27:06 PM PDT 24 126266877 ps
T840 /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.233470797 Jun 28 05:23:48 PM PDT 24 Jun 28 05:24:02 PM PDT 24 2735743919 ps
T841 /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1565023017 Jun 28 05:26:56 PM PDT 24 Jun 28 05:27:07 PM PDT 24 2002776930 ps
T842 /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2312028143 Jun 28 05:25:47 PM PDT 24 Jun 28 05:26:29 PM PDT 24 8519090038 ps
T843 /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3692182254 Jun 28 05:25:12 PM PDT 24 Jun 28 05:25:20 PM PDT 24 66770489 ps
T844 /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1491416167 Jun 28 05:28:31 PM PDT 24 Jun 28 05:28:33 PM PDT 24 16368950 ps
T845 /workspace/coverage/xbar_build_mode/41.xbar_same_source.531557531 Jun 28 05:28:57 PM PDT 24 Jun 28 05:29:04 PM PDT 24 94872620 ps
T846 /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.4092600024 Jun 28 05:27:46 PM PDT 24 Jun 28 05:30:19 PM PDT 24 53865452840 ps
T847 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3446761049 Jun 28 05:23:16 PM PDT 24 Jun 28 05:23:28 PM PDT 24 1089745200 ps
T10 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3267518137 Jun 28 05:24:18 PM PDT 24 Jun 28 05:25:58 PM PDT 24 11885441327 ps
T848 /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1171783988 Jun 28 05:26:13 PM PDT 24 Jun 28 05:26:31 PM PDT 24 4950741025 ps
T849 /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4190011384 Jun 28 05:27:46 PM PDT 24 Jun 28 05:29:38 PM PDT 24 42868209276 ps
T850 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2537019151 Jun 28 05:25:46 PM PDT 24 Jun 28 05:25:59 PM PDT 24 126428616 ps
T851 /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1718612869 Jun 28 05:28:43 PM PDT 24 Jun 28 05:28:49 PM PDT 24 1939076322 ps
T852 /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1241217048 Jun 28 05:25:25 PM PDT 24 Jun 28 05:25:35 PM PDT 24 4557069135 ps
T853 /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1600659972 Jun 28 05:29:28 PM PDT 24 Jun 28 05:29:59 PM PDT 24 4132223834 ps
T854 /workspace/coverage/xbar_build_mode/34.xbar_smoke.4177943712 Jun 28 05:28:07 PM PDT 24 Jun 28 05:28:10 PM PDT 24 142294636 ps
T855 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1526204152 Jun 28 05:23:16 PM PDT 24 Jun 28 05:23:26 PM PDT 24 616389885 ps
T5 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3387189668 Jun 28 05:27:29 PM PDT 24 Jun 28 05:28:47 PM PDT 24 5605821656 ps
T856 /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.4275453177 Jun 28 05:25:01 PM PDT 24 Jun 28 05:25:13 PM PDT 24 2300034312 ps
T857 /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3821783851 Jun 28 05:27:18 PM PDT 24 Jun 28 05:27:26 PM PDT 24 3212832443 ps
T858 /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3447308939 Jun 28 05:27:47 PM PDT 24 Jun 28 05:27:51 PM PDT 24 25334044 ps
T859 /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1996003091 Jun 28 05:28:55 PM PDT 24 Jun 28 05:29:04 PM PDT 24 1196110122 ps
T860 /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1622033862 Jun 28 05:24:50 PM PDT 24 Jun 28 05:24:55 PM PDT 24 91466630 ps
T861 /workspace/coverage/xbar_build_mode/44.xbar_stress_all.259652571 Jun 28 05:29:29 PM PDT 24 Jun 28 05:29:53 PM PDT 24 169031017 ps
T862 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3305537217 Jun 28 05:27:18 PM PDT 24 Jun 28 05:27:22 PM PDT 24 18697211 ps
T863 /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.522505540 Jun 28 05:29:27 PM PDT 24 Jun 28 05:30:02 PM PDT 24 17147958085 ps
T864 /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3902807763 Jun 28 05:23:28 PM PDT 24 Jun 28 05:23:30 PM PDT 24 15099320 ps
T98 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.906090574 Jun 28 05:27:54 PM PDT 24 Jun 28 05:32:54 PM PDT 24 115799291319 ps
T865 /workspace/coverage/xbar_build_mode/39.xbar_error_random.3906479610 Jun 28 05:28:45 PM PDT 24 Jun 28 05:28:52 PM PDT 24 64366228 ps
T866 /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4021762439 Jun 28 05:24:04 PM PDT 24 Jun 28 05:26:10 PM PDT 24 26731522839 ps
T867 /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.975959127 Jun 28 05:29:28 PM PDT 24 Jun 28 05:29:37 PM PDT 24 1131549801 ps
T868 /workspace/coverage/xbar_build_mode/40.xbar_random.3108718125 Jun 28 05:28:56 PM PDT 24 Jun 28 05:29:01 PM PDT 24 77734617 ps
T869 /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3364417634 Jun 28 05:27:19 PM PDT 24 Jun 28 05:27:27 PM PDT 24 618199585 ps
T870 /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3084065694 Jun 28 05:29:55 PM PDT 24 Jun 28 05:30:02 PM PDT 24 129604203 ps
T871 /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3167662958 Jun 28 05:24:09 PM PDT 24 Jun 28 05:24:17 PM PDT 24 2329256948 ps
T872 /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3679017725 Jun 28 05:23:28 PM PDT 24 Jun 28 05:23:40 PM PDT 24 1077858391 ps
T873 /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.266290187 Jun 28 05:25:24 PM PDT 24 Jun 28 05:26:19 PM PDT 24 11087797691 ps
T874 /workspace/coverage/xbar_build_mode/34.xbar_error_random.2023866383 Jun 28 05:28:20 PM PDT 24 Jun 28 05:28:36 PM PDT 24 1372464863 ps
T875 /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.4160692462 Jun 28 05:26:28 PM PDT 24 Jun 28 05:26:35 PM PDT 24 58643778 ps
T876 /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2741467625 Jun 28 05:29:38 PM PDT 24 Jun 28 05:29:44 PM PDT 24 3156529676 ps
T877 /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1447990813 Jun 28 05:23:07 PM PDT 24 Jun 28 05:23:20 PM PDT 24 3201612601 ps
T878 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.448747802 Jun 28 05:28:44 PM PDT 24 Jun 28 05:30:55 PM PDT 24 956222835 ps
T879 /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1197594845 Jun 28 05:28:59 PM PDT 24 Jun 28 05:29:59 PM PDT 24 360694334 ps
T99 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2252286483 Jun 28 05:25:46 PM PDT 24 Jun 28 05:28:00 PM PDT 24 4163960207 ps
T880 /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1724770839 Jun 28 05:26:40 PM PDT 24 Jun 28 05:26:47 PM PDT 24 45061168 ps
T881 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4175990023 Jun 28 05:28:08 PM PDT 24 Jun 28 05:32:10 PM PDT 24 38115657131 ps
T882 /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3837585999 Jun 28 05:27:19 PM PDT 24 Jun 28 05:27:21 PM PDT 24 17523084 ps
T883 /workspace/coverage/xbar_build_mode/9.xbar_smoke.732262408 Jun 28 05:24:41 PM PDT 24 Jun 28 05:24:43 PM PDT 24 18241300 ps
T884 /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4135218381 Jun 28 05:27:06 PM PDT 24 Jun 28 05:29:24 PM PDT 24 59231449203 ps
T885 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1083699279 Jun 28 05:26:15 PM PDT 24 Jun 28 05:26:18 PM PDT 24 7170737 ps
T886 /workspace/coverage/xbar_build_mode/49.xbar_same_source.316883795 Jun 28 05:29:51 PM PDT 24 Jun 28 05:30:03 PM PDT 24 2714245758 ps
T887 /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2190351648 Jun 28 05:23:46 PM PDT 24 Jun 28 05:23:58 PM PDT 24 124750783 ps
T888 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1990397087 Jun 28 05:23:29 PM PDT 24 Jun 28 05:23:41 PM PDT 24 75876979 ps
T889 /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3475976264 Jun 28 05:23:18 PM PDT 24 Jun 28 05:23:30 PM PDT 24 2641220702 ps
T890 /workspace/coverage/xbar_build_mode/20.xbar_smoke.6626892 Jun 28 05:26:15 PM PDT 24 Jun 28 05:26:18 PM PDT 24 201220227 ps
T100 /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3178861199 Jun 28 05:25:12 PM PDT 24 Jun 28 05:28:06 PM PDT 24 27143654892 ps
T891 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1262879419 Jun 28 05:23:06 PM PDT 24 Jun 28 05:24:37 PM PDT 24 29462818523 ps
T892 /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.445180391 Jun 28 05:23:48 PM PDT 24 Jun 28 05:23:55 PM PDT 24 1800729336 ps
T893 /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2662330974 Jun 28 05:26:39 PM PDT 24 Jun 28 05:26:47 PM PDT 24 2011283329 ps
T894 /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2878611265 Jun 28 05:28:32 PM PDT 24 Jun 28 05:28:43 PM PDT 24 2872156093 ps
T895 /workspace/coverage/xbar_build_mode/24.xbar_error_random.2306955224 Jun 28 05:27:07 PM PDT 24 Jun 28 05:27:20 PM PDT 24 2253600239 ps
T896 /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2107574970 Jun 28 05:28:41 PM PDT 24 Jun 28 05:28:44 PM PDT 24 98437216 ps
T897 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.206645292 Jun 28 05:27:21 PM PDT 24 Jun 28 05:27:31 PM PDT 24 184393461 ps
T898 /workspace/coverage/xbar_build_mode/30.xbar_same_source.804420395 Jun 28 05:27:34 PM PDT 24 Jun 28 05:27:41 PM PDT 24 793979266 ps
T899 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1191437777 Jun 28 05:25:46 PM PDT 24 Jun 28 05:25:50 PM PDT 24 430257999 ps
T900 /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3145228026 Jun 28 05:29:41 PM PDT 24 Jun 28 05:29:50 PM PDT 24 1744459366 ps

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1828651584
Short name T6
Test name
Test status
Simulation time 5544328390 ps
CPU time 93.18 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:28:53 PM PDT 24
Peak memory 204888 kb
Host smart-b78d3a3c-bc10-46cf-aaeb-b8a92266df7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828651584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1828651584
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.847625256
Short name T80
Test name
Test status
Simulation time 89162465236 ps
CPU time 397.33 seconds
Started Jun 28 05:25:49 PM PDT 24
Finished Jun 28 05:32:26 PM PDT 24
Peak memory 203092 kb
Host smart-8a7a81f0-7cde-4598-ab66-bef4b5eac456
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=847625256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo
w_rsp.847625256
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2522943250
Short name T192
Test name
Test status
Simulation time 98941071184 ps
CPU time 363.26 seconds
Started Jun 28 05:26:28 PM PDT 24
Finished Jun 28 05:32:32 PM PDT 24
Peak memory 203060 kb
Host smart-490e2bf6-1fcc-4bdc-844c-68c1d001201a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2522943250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.2522943250
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.855696305
Short name T187
Test name
Test status
Simulation time 35244176546 ps
CPU time 271.73 seconds
Started Jun 28 05:24:51 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 203060 kb
Host smart-8a0e3197-7456-4d2b-8993-528b81e81deb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=855696305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow
_rsp.855696305
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.4067768411
Short name T186
Test name
Test status
Simulation time 46294638636 ps
CPU time 333.15 seconds
Started Jun 28 05:25:26 PM PDT 24
Finished Jun 28 05:31:00 PM PDT 24
Peak memory 203164 kb
Host smart-296a5169-51fe-4482-b5c3-00c027c86981
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4067768411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.4067768411
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2942049795
Short name T213
Test name
Test status
Simulation time 58121035116 ps
CPU time 127.49 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:31:57 PM PDT 24
Peak memory 202056 kb
Host smart-c0c93db8-c13d-45a6-a292-2d882c656a1b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2942049795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.2942049795
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3781899339
Short name T50
Test name
Test status
Simulation time 14920529133 ps
CPU time 214.48 seconds
Started Jun 28 05:28:32 PM PDT 24
Finished Jun 28 05:32:07 PM PDT 24
Peak memory 205060 kb
Host smart-e965cdab-b2a8-4cb7-b881-41303a7f9504
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3781899339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.3781899339
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.12635662
Short name T63
Test name
Test status
Simulation time 428785648 ps
CPU time 44.07 seconds
Started Jun 28 05:27:46 PM PDT 24
Finished Jun 28 05:28:31 PM PDT 24
Peak memory 204452 kb
Host smart-9aadc855-1419-413e-9609-5c8ddb3d1369
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12635662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rese
t_error.12635662
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.944638862
Short name T51
Test name
Test status
Simulation time 92059799584 ps
CPU time 139.08 seconds
Started Jun 28 05:23:15 PM PDT 24
Finished Jun 28 05:25:35 PM PDT 24
Peak memory 202032 kb
Host smart-50240d0b-12ca-4e45-813e-5941dba07f48
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=944638862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.944638862
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3533354538
Short name T9
Test name
Test status
Simulation time 4108390824 ps
CPU time 154.13 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:32:03 PM PDT 24
Peak memory 207088 kb
Host smart-fc373928-200f-4efd-be0d-0d433d77fd4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3533354538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3533354538
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.400341593
Short name T4
Test name
Test status
Simulation time 461251561 ps
CPU time 81.05 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:29:28 PM PDT 24
Peak memory 204412 kb
Host smart-6e1c7c48-671e-40aa-80b9-cee7e1543554
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=400341593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand
_reset.400341593
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3064724511
Short name T67
Test name
Test status
Simulation time 8897458663 ps
CPU time 26.06 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:28:49 PM PDT 24
Peak memory 202032 kb
Host smart-46774df5-ffe8-492b-bbf5-3d48b6e7a9d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3064724511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3064724511
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1488897668
Short name T19
Test name
Test status
Simulation time 50973362657 ps
CPU time 100.11 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:31:30 PM PDT 24
Peak memory 202000 kb
Host smart-485223da-7faa-4d51-afbd-66491e881dba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1488897668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1488897668
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.330321554
Short name T42
Test name
Test status
Simulation time 320398985 ps
CPU time 26.76 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:30 PM PDT 24
Peak memory 203900 kb
Host smart-b0615f5e-2d94-4716-b5eb-3ec2a71d1953
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=330321554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand
_reset.330321554
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.4233674178
Short name T77
Test name
Test status
Simulation time 7711285928 ps
CPU time 171.36 seconds
Started Jun 28 05:23:16 PM PDT 24
Finished Jun 28 05:26:08 PM PDT 24
Peak memory 206816 kb
Host smart-0e47d956-c8b8-4ff9-867f-d626b9b8afc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4233674178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.4233674178
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.906090574
Short name T98
Test name
Test status
Simulation time 115799291319 ps
CPU time 299.17 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:32:54 PM PDT 24
Peak memory 203128 kb
Host smart-d637ab0e-3379-4f65-a5ba-b34e42efe693
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=906090574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo
w_rsp.906090574
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.4005501041
Short name T89
Test name
Test status
Simulation time 56729765400 ps
CPU time 128.1 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:26:04 PM PDT 24
Peak memory 202884 kb
Host smart-b6646d28-44cb-4404-a60d-e3bf5695c509
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4005501041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.4005501041
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1671833576
Short name T115
Test name
Test status
Simulation time 3484060942 ps
CPU time 98.32 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:31:08 PM PDT 24
Peak memory 204292 kb
Host smart-127f64cc-b7bb-4dd9-8232-3b22c205e2c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1671833576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.1671833576
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.266638867
Short name T220
Test name
Test status
Simulation time 13193366157 ps
CPU time 139.82 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:26:26 PM PDT 24
Peak memory 209080 kb
Host smart-ee61b09a-8b1a-47be-8e09-f1916fdb21c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=266638867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese
t_error.266638867
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.862070866
Short name T35
Test name
Test status
Simulation time 309245351 ps
CPU time 60.82 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:28:30 PM PDT 24
Peak memory 204024 kb
Host smart-e573ba99-6922-4828-9a59-1a28f3f1bc6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862070866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand
_reset.862070866
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1019627297
Short name T177
Test name
Test status
Simulation time 1635242578 ps
CPU time 8.53 seconds
Started Jun 28 05:25:25 PM PDT 24
Finished Jun 28 05:25:34 PM PDT 24
Peak memory 200272 kb
Host smart-7f1862e2-2393-4c40-8dd4-19c37c7f413d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1019627297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1019627297
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3718131137
Short name T160
Test name
Test status
Simulation time 59395738 ps
CPU time 5 seconds
Started Jun 28 05:23:06 PM PDT 24
Finished Jun 28 05:23:12 PM PDT 24
Peak memory 202112 kb
Host smart-0ff0a8f8-7d53-4426-bbbd-c2e0c6a525eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3718131137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3718131137
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.849414007
Short name T540
Test name
Test status
Simulation time 112302600694 ps
CPU time 272.23 seconds
Started Jun 28 05:23:05 PM PDT 24
Finished Jun 28 05:27:38 PM PDT 24
Peak memory 203096 kb
Host smart-fbabc97e-4c6c-45f5-8328-bff876b738dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=849414007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow
_rsp.849414007
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2546198565
Short name T488
Test name
Test status
Simulation time 733078519 ps
CPU time 8.12 seconds
Started Jun 28 05:23:06 PM PDT 24
Finished Jun 28 05:23:15 PM PDT 24
Peak memory 201944 kb
Host smart-215bf0ed-64bd-4e5f-b51b-5f895b582603
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2546198565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2546198565
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.2266396352
Short name T549
Test name
Test status
Simulation time 115272354 ps
CPU time 4.54 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:23:11 PM PDT 24
Peak memory 201916 kb
Host smart-916a277b-f450-45b6-97bc-df2922eae7b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2266396352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2266396352
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3076004581
Short name T820
Test name
Test status
Simulation time 39028670 ps
CPU time 3.38 seconds
Started Jun 28 05:23:05 PM PDT 24
Finished Jun 28 05:23:10 PM PDT 24
Peak memory 201808 kb
Host smart-680efb73-074c-47c4-89e2-094be8f7dbf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3076004581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3076004581
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2885314323
Short name T62
Test name
Test status
Simulation time 37651009747 ps
CPU time 155.4 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:25:41 PM PDT 24
Peak memory 202032 kb
Host smart-b68e89fd-fdbd-4a78-bbc8-ae4f036c2e84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885314323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2885314323
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4215391549
Short name T20
Test name
Test status
Simulation time 14428869680 ps
CPU time 83.48 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 05:24:28 PM PDT 24
Peak memory 202064 kb
Host smart-c0213ca4-6a06-4918-ba64-2ad45799fef9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4215391549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4215391549
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.318947658
Short name T737
Test name
Test status
Simulation time 52549624 ps
CPU time 5.65 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:23:11 PM PDT 24
Peak memory 201904 kb
Host smart-f2ec6353-3c3a-41a8-afcb-f7e9978c6701
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318947658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.318947658
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.2682029573
Short name T57
Test name
Test status
Simulation time 3385200512 ps
CPU time 13.48 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 05:23:18 PM PDT 24
Peak memory 201976 kb
Host smart-5e275e4e-94c3-44ce-b9b3-ed13cf666f02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2682029573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2682029573
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.3766040380
Short name T628
Test name
Test status
Simulation time 11009450 ps
CPU time 1.22 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 05:23:05 PM PDT 24
Peak memory 201904 kb
Host smart-288a3ffa-c25b-4e62-bcb5-f6fc969fe326
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3766040380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3766040380
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2006636797
Short name T535
Test name
Test status
Simulation time 3662888153 ps
CPU time 11.67 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:23:17 PM PDT 24
Peak memory 201948 kb
Host smart-db2f205b-4122-4c17-9a1a-2f752dd3b954
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006636797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2006636797
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2307429751
Short name T433
Test name
Test status
Simulation time 3662535201 ps
CPU time 8.26 seconds
Started Jun 28 05:23:05 PM PDT 24
Finished Jun 28 05:23:15 PM PDT 24
Peak memory 202008 kb
Host smart-cea1f13d-851b-4243-8d28-f73998cabbe3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2307429751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2307429751
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.133297676
Short name T394
Test name
Test status
Simulation time 14016321 ps
CPU time 1.2 seconds
Started Jun 28 05:23:06 PM PDT 24
Finished Jun 28 05:23:08 PM PDT 24
Peak memory 201804 kb
Host smart-228b6527-aa1e-4cf0-9415-a0c8da06bdd3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133297676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.133297676
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3976131568
Short name T91
Test name
Test status
Simulation time 3940830201 ps
CPU time 78.84 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:24:24 PM PDT 24
Peak memory 203000 kb
Host smart-daf7a52b-fbdf-4bd8-b37c-9261a5be5d0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3976131568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3976131568
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1262879419
Short name T891
Test name
Test status
Simulation time 29462818523 ps
CPU time 89.67 seconds
Started Jun 28 05:23:06 PM PDT 24
Finished Jun 28 05:24:37 PM PDT 24
Peak memory 204580 kb
Host smart-802bc4c8-d38e-4292-af62-76409426b662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262879419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1262879419
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2046330512
Short name T169
Test name
Test status
Simulation time 4104152274 ps
CPU time 136 seconds
Started Jun 28 05:23:06 PM PDT 24
Finished Jun 28 05:25:23 PM PDT 24
Peak memory 204564 kb
Host smart-e1b05c2a-990b-49ff-a1cf-3fded769312f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2046330512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.2046330512
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1741052420
Short name T262
Test name
Test status
Simulation time 399139508 ps
CPU time 44.59 seconds
Started Jun 28 05:23:05 PM PDT 24
Finished Jun 28 05:23:51 PM PDT 24
Peak memory 204012 kb
Host smart-cf5bbe16-e221-49dd-8bd6-387398476335
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1741052420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.1741052420
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3067155
Short name T709
Test name
Test status
Simulation time 649496345 ps
CPU time 8.63 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 05:23:12 PM PDT 24
Peak memory 201860 kb
Host smart-c5c5f712-31a6-442e-aed8-3602779c5827
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3067155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3067155
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3446761049
Short name T847
Test name
Test status
Simulation time 1089745200 ps
CPU time 11.54 seconds
Started Jun 28 05:23:16 PM PDT 24
Finished Jun 28 05:23:28 PM PDT 24
Peak memory 201884 kb
Host smart-7967a2fa-890a-4fbe-93e2-60cf7e9ab033
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3446761049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3446761049
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1285241099
Short name T725
Test name
Test status
Simulation time 47554155829 ps
CPU time 63.14 seconds
Started Jun 28 05:23:17 PM PDT 24
Finished Jun 28 05:24:21 PM PDT 24
Peak memory 202072 kb
Host smart-6ed07628-d23c-4456-a0ac-0b3fe471951f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1285241099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1285241099
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2632943054
Short name T807
Test name
Test status
Simulation time 60647958 ps
CPU time 5.03 seconds
Started Jun 28 05:23:15 PM PDT 24
Finished Jun 28 05:23:21 PM PDT 24
Peak memory 201904 kb
Host smart-ad0a0424-4556-4b99-b5d0-70547c50a3e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2632943054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2632943054
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.134189554
Short name T711
Test name
Test status
Simulation time 66699758 ps
CPU time 6.14 seconds
Started Jun 28 05:23:17 PM PDT 24
Finished Jun 28 05:23:24 PM PDT 24
Peak memory 201912 kb
Host smart-55feb6bd-6b54-43e2-b49a-6af2db97f591
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=134189554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.134189554
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.759590304
Short name T490
Test name
Test status
Simulation time 927432424 ps
CPU time 6.56 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:23:12 PM PDT 24
Peak memory 201912 kb
Host smart-00b321af-81cf-4a8c-9be9-4768e9e7d12a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=759590304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.759590304
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2683646009
Short name T415
Test name
Test status
Simulation time 29699573835 ps
CPU time 79.39 seconds
Started Jun 28 05:23:15 PM PDT 24
Finished Jun 28 05:24:35 PM PDT 24
Peak memory 202060 kb
Host smart-49456c30-bf7d-41c1-a8d1-b3c044b89548
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2683646009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2683646009
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.4114804852
Short name T84
Test name
Test status
Simulation time 14336224 ps
CPU time 1.63 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 05:23:06 PM PDT 24
Peak memory 201924 kb
Host smart-eefaea82-79e5-4d48-9e06-17c52f6f89e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114804852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.4114804852
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.417231559
Short name T328
Test name
Test status
Simulation time 12331157 ps
CPU time 1.22 seconds
Started Jun 28 05:23:18 PM PDT 24
Finished Jun 28 05:23:20 PM PDT 24
Peak memory 201812 kb
Host smart-24b61c5f-9030-4a08-8810-787337770bf1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=417231559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.417231559
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.3855816524
Short name T367
Test name
Test status
Simulation time 41735629 ps
CPU time 1.33 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 05:23:07 PM PDT 24
Peak memory 201908 kb
Host smart-4192181c-5e06-48aa-80b9-bf7a4c4128bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3855816524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3855816524
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3235844321
Short name T803
Test name
Test status
Simulation time 6841173871 ps
CPU time 10.7 seconds
Started Jun 28 05:23:02 PM PDT 24
Finished Jun 28 05:23:14 PM PDT 24
Peak memory 201932 kb
Host smart-8d2cd61c-7db4-4dd1-842d-9f0dbe7e4852
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235844321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3235844321
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1447990813
Short name T877
Test name
Test status
Simulation time 3201612601 ps
CPU time 12.74 seconds
Started Jun 28 05:23:07 PM PDT 24
Finished Jun 28 05:23:20 PM PDT 24
Peak memory 202216 kb
Host smart-bb9f3085-25ac-4183-841a-01c2f7baca57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1447990813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1447990813
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3643264904
Short name T812
Test name
Test status
Simulation time 8874368 ps
CPU time 1.17 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 05:23:05 PM PDT 24
Peak memory 201904 kb
Host smart-1eff2724-d289-4977-b955-9a20a0a2a582
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643264904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3643264904
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1450773983
Short name T341
Test name
Test status
Simulation time 239972346 ps
CPU time 26.48 seconds
Started Jun 28 05:23:15 PM PDT 24
Finished Jun 28 05:23:42 PM PDT 24
Peak memory 201912 kb
Host smart-65ee8320-7426-4a5c-a8d6-53bc91c1bf5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1450773983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1450773983
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1526204152
Short name T855
Test name
Test status
Simulation time 616389885 ps
CPU time 9.05 seconds
Started Jun 28 05:23:16 PM PDT 24
Finished Jun 28 05:23:26 PM PDT 24
Peak memory 201896 kb
Host smart-7a2f4fac-9ce0-479d-8f98-8a99b1c5c23c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1526204152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1526204152
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3084521674
Short name T811
Test name
Test status
Simulation time 13306116 ps
CPU time 3.52 seconds
Started Jun 28 05:23:17 PM PDT 24
Finished Jun 28 05:23:21 PM PDT 24
Peak memory 201964 kb
Host smart-ba435fad-4607-42df-94f8-5b9f2d8f3b88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3084521674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.3084521674
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1736372068
Short name T643
Test name
Test status
Simulation time 39488181 ps
CPU time 3.37 seconds
Started Jun 28 05:23:16 PM PDT 24
Finished Jun 28 05:23:20 PM PDT 24
Peak memory 201896 kb
Host smart-49bf6f29-df3c-4941-84b8-4a03c3a82c0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1736372068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1736372068
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1064576752
Short name T45
Test name
Test status
Simulation time 33160047 ps
CPU time 6.78 seconds
Started Jun 28 05:24:50 PM PDT 24
Finished Jun 28 05:24:58 PM PDT 24
Peak memory 201884 kb
Host smart-198d9ed8-b014-47af-82d6-f9f70ef8a7d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064576752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1064576752
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.4147266117
Short name T205
Test name
Test status
Simulation time 14956127527 ps
CPU time 62.43 seconds
Started Jun 28 05:24:59 PM PDT 24
Finished Jun 28 05:26:02 PM PDT 24
Peak memory 202028 kb
Host smart-b809e915-e6bd-489d-97d8-78009cdb1b8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4147266117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.4147266117
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2088032541
Short name T617
Test name
Test status
Simulation time 594393843 ps
CPU time 4.34 seconds
Started Jun 28 05:25:03 PM PDT 24
Finished Jun 28 05:25:08 PM PDT 24
Peak memory 201968 kb
Host smart-faa7359a-ccd0-4f22-85b5-ddd0ccdf3616
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2088032541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2088032541
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.3648670128
Short name T228
Test name
Test status
Simulation time 13891100 ps
CPU time 1.84 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:05 PM PDT 24
Peak memory 201916 kb
Host smart-23c52ce2-7738-4f38-a0a8-efd504dc3a3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3648670128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3648670128
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.2114991314
Short name T810
Test name
Test status
Simulation time 353531901 ps
CPU time 3.21 seconds
Started Jun 28 05:24:52 PM PDT 24
Finished Jun 28 05:24:55 PM PDT 24
Peak memory 201908 kb
Host smart-494d81e3-ef3b-454d-b980-f1ea8b23381c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2114991314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2114991314
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2710914707
Short name T24
Test name
Test status
Simulation time 201596149397 ps
CPU time 154.25 seconds
Started Jun 28 05:24:50 PM PDT 24
Finished Jun 28 05:27:25 PM PDT 24
Peak memory 201992 kb
Host smart-8fb821dc-babf-402e-b45b-8ee22d7a02cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710914707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2710914707
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3822509244
Short name T112
Test name
Test status
Simulation time 53912125807 ps
CPU time 194.59 seconds
Started Jun 28 05:24:52 PM PDT 24
Finished Jun 28 05:28:07 PM PDT 24
Peak memory 202072 kb
Host smart-a134286a-1bdd-42f3-b005-250fa1e04faf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3822509244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3822509244
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1833659595
Short name T372
Test name
Test status
Simulation time 77994200 ps
CPU time 9.72 seconds
Started Jun 28 05:24:51 PM PDT 24
Finished Jun 28 05:25:02 PM PDT 24
Peak memory 201904 kb
Host smart-77368eec-5cd0-4105-ad7e-abfdf59671b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833659595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1833659595
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2106238418
Short name T121
Test name
Test status
Simulation time 5400265640 ps
CPU time 14.85 seconds
Started Jun 28 05:25:05 PM PDT 24
Finished Jun 28 05:25:21 PM PDT 24
Peak memory 202016 kb
Host smart-fedc0de9-fc71-46f4-9769-cc7edaff6583
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2106238418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2106238418
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.3035939743
Short name T246
Test name
Test status
Simulation time 39613611 ps
CPU time 1.28 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:24:51 PM PDT 24
Peak memory 201884 kb
Host smart-c81ade44-24c3-4d54-8e76-e32ea6be265d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3035939743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3035939743
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3579048078
Short name T838
Test name
Test status
Simulation time 1411198166 ps
CPU time 7.17 seconds
Started Jun 28 05:24:50 PM PDT 24
Finished Jun 28 05:24:58 PM PDT 24
Peak memory 201912 kb
Host smart-b9d934d2-4e52-4cf8-a2a4-426ab1758a20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579048078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3579048078
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3916111473
Short name T146
Test name
Test status
Simulation time 1994021014 ps
CPU time 10.63 seconds
Started Jun 28 05:24:51 PM PDT 24
Finished Jun 28 05:25:02 PM PDT 24
Peak memory 201880 kb
Host smart-f4629ce2-173c-44fa-b52c-7b6430353498
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3916111473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3916111473
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3712571823
Short name T730
Test name
Test status
Simulation time 20168105 ps
CPU time 1.14 seconds
Started Jun 28 05:24:48 PM PDT 24
Finished Jun 28 05:24:50 PM PDT 24
Peak memory 201900 kb
Host smart-cd7b2d72-e3c1-422a-ac6a-ab15d7b53dda
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712571823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3712571823
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.769582928
Short name T286
Test name
Test status
Simulation time 1488212576 ps
CPU time 23.2 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:27 PM PDT 24
Peak memory 201916 kb
Host smart-808ac4f9-57ee-4d5c-8222-230ba0e5585b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=769582928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.769582928
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3479125421
Short name T599
Test name
Test status
Simulation time 372009304 ps
CPU time 12.59 seconds
Started Jun 28 05:25:03 PM PDT 24
Finished Jun 28 05:25:17 PM PDT 24
Peak memory 201968 kb
Host smart-f55aed04-9681-403c-b2b0-88ab6ce26d84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3479125421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3479125421
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.4167172294
Short name T223
Test name
Test status
Simulation time 574968950 ps
CPU time 90.87 seconds
Started Jun 28 05:25:04 PM PDT 24
Finished Jun 28 05:26:36 PM PDT 24
Peak memory 206696 kb
Host smart-a083b51b-9aea-42af-aae7-943fdbf9db3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4167172294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.4167172294
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.330868342
Short name T538
Test name
Test status
Simulation time 5500125290 ps
CPU time 164.67 seconds
Started Jun 28 05:25:03 PM PDT 24
Finished Jun 28 05:27:49 PM PDT 24
Peak memory 207252 kb
Host smart-8bde0e55-04c5-48ee-885d-0a95a3923ece
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=330868342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_res
et_error.330868342
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.4275453177
Short name T856
Test name
Test status
Simulation time 2300034312 ps
CPU time 10.6 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:13 PM PDT 24
Peak memory 201972 kb
Host smart-dcb20906-3c1d-4457-b6e2-8afa85245994
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4275453177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4275453177
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.4187020479
Short name T306
Test name
Test status
Simulation time 51939129 ps
CPU time 11.7 seconds
Started Jun 28 05:24:59 PM PDT 24
Finished Jun 28 05:25:11 PM PDT 24
Peak memory 201832 kb
Host smart-4c38b92f-aafc-4c66-b100-a7248ce10ba4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4187020479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.4187020479
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.432409457
Short name T210
Test name
Test status
Simulation time 57841207642 ps
CPU time 119.57 seconds
Started Jun 28 05:25:04 PM PDT 24
Finished Jun 28 05:27:04 PM PDT 24
Peak memory 202056 kb
Host smart-7b4a889c-0deb-46b0-a558-cfb7524a9ac8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=432409457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.432409457
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2869609250
Short name T103
Test name
Test status
Simulation time 365636651 ps
CPU time 5.05 seconds
Started Jun 28 05:25:03 PM PDT 24
Finished Jun 28 05:25:09 PM PDT 24
Peak memory 201968 kb
Host smart-4ac4cffe-a48b-48c7-a539-aed61ea01475
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2869609250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2869609250
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.3658403869
Short name T456
Test name
Test status
Simulation time 337561197 ps
CPU time 6.91 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:11 PM PDT 24
Peak memory 201916 kb
Host smart-76e0214c-7938-417a-a3bf-5207f3786f54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3658403869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3658403869
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.3153541935
Short name T240
Test name
Test status
Simulation time 760458158 ps
CPU time 2.81 seconds
Started Jun 28 05:25:05 PM PDT 24
Finished Jun 28 05:25:09 PM PDT 24
Peak memory 201912 kb
Host smart-02c5fdf7-f7c0-4d6e-8d3a-0eafac69f467
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3153541935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3153541935
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.344967081
Short name T359
Test name
Test status
Simulation time 75108918095 ps
CPU time 166.1 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:27:49 PM PDT 24
Peak memory 202024 kb
Host smart-a9f3a628-4778-4cd9-9f1b-c50778750700
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=344967081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.344967081
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3894537134
Short name T239
Test name
Test status
Simulation time 2503067894 ps
CPU time 17.57 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:20 PM PDT 24
Peak memory 202008 kb
Host smart-6e3b2814-523a-4acc-a14f-fcd1e03c09a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3894537134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3894537134
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2902444618
Short name T233
Test name
Test status
Simulation time 39181144 ps
CPU time 3.34 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:06 PM PDT 24
Peak memory 201816 kb
Host smart-27cf6363-2ce4-47e4-9afa-0007a9728952
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902444618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2902444618
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.1813283519
Short name T368
Test name
Test status
Simulation time 109786032 ps
CPU time 4.15 seconds
Started Jun 28 05:25:00 PM PDT 24
Finished Jun 28 05:25:05 PM PDT 24
Peak memory 201912 kb
Host smart-4559a672-d248-4aa0-848f-2a90d27372d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1813283519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1813283519
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.135101595
Short name T32
Test name
Test status
Simulation time 14610947 ps
CPU time 1.28 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:04 PM PDT 24
Peak memory 201908 kb
Host smart-943a601a-1cdc-4426-a7c6-e55ce433ba0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=135101595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.135101595
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2318997997
Short name T155
Test name
Test status
Simulation time 3738059761 ps
CPU time 10.5 seconds
Started Jun 28 05:25:00 PM PDT 24
Finished Jun 28 05:25:11 PM PDT 24
Peak memory 201972 kb
Host smart-583fa002-6d3f-4fda-ba68-03bd8b89289e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318997997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2318997997
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3565265692
Short name T245
Test name
Test status
Simulation time 844094898 ps
CPU time 6.1 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:09 PM PDT 24
Peak memory 201944 kb
Host smart-6e0f9735-d335-4c01-82d1-c714139143b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3565265692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3565265692
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2051812518
Short name T323
Test name
Test status
Simulation time 8708699 ps
CPU time 1.29 seconds
Started Jun 28 05:25:00 PM PDT 24
Finished Jun 28 05:25:02 PM PDT 24
Peak memory 201904 kb
Host smart-4428a629-50f1-48b2-8154-ef69bc2a6b40
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051812518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2051812518
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3740207236
Short name T94
Test name
Test status
Simulation time 5370899845 ps
CPU time 68.51 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:26:10 PM PDT 24
Peak memory 205268 kb
Host smart-248ea779-847d-44f5-ab3c-7c4bf46cd23d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3740207236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3740207236
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1734819111
Short name T561
Test name
Test status
Simulation time 451455538 ps
CPU time 27.91 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:30 PM PDT 24
Peak memory 201940 kb
Host smart-704ea3ef-696d-4297-b473-b4eb0fbdbfad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1734819111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1734819111
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3307204811
Short name T602
Test name
Test status
Simulation time 3755229283 ps
CPU time 46.81 seconds
Started Jun 28 05:25:04 PM PDT 24
Finished Jun 28 05:25:51 PM PDT 24
Peak memory 203396 kb
Host smart-3857f41e-a00c-42fb-9235-c40453c002b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3307204811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.3307204811
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2165866279
Short name T574
Test name
Test status
Simulation time 46066078 ps
CPU time 3.07 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:04 PM PDT 24
Peak memory 201904 kb
Host smart-e091c10c-42a6-4915-8303-9d8f6bffdf15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2165866279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2165866279
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1036088413
Short name T829
Test name
Test status
Simulation time 1086428891 ps
CPU time 14.38 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:16 PM PDT 24
Peak memory 201916 kb
Host smart-64309fa1-d51a-4a64-aedf-300036e2cba2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1036088413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1036088413
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1312342889
Short name T95
Test name
Test status
Simulation time 57639089237 ps
CPU time 359.47 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:31:02 PM PDT 24
Peak memory 203928 kb
Host smart-26a4c1c6-cf0f-4101-8bbd-06df568d48f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1312342889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.1312342889
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4227719268
Short name T327
Test name
Test status
Simulation time 588863232 ps
CPU time 9.86 seconds
Started Jun 28 05:25:17 PM PDT 24
Finished Jun 28 05:25:27 PM PDT 24
Peak memory 201968 kb
Host smart-760fb0cb-b6a3-426f-96e9-6bcea8372979
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4227719268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4227719268
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.3992907765
Short name T270
Test name
Test status
Simulation time 116769777 ps
CPU time 5.82 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:09 PM PDT 24
Peak memory 201912 kb
Host smart-8dcf6583-a853-4a2c-89d5-b7c5151fb292
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3992907765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3992907765
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.4091702826
Short name T503
Test name
Test status
Simulation time 239451359 ps
CPU time 2.73 seconds
Started Jun 28 05:25:03 PM PDT 24
Finished Jun 28 05:25:07 PM PDT 24
Peak memory 201904 kb
Host smart-9c6da6c0-49b2-4745-8ee5-5ed4033ae272
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4091702826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4091702826
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2175138016
Short name T120
Test name
Test status
Simulation time 53306457489 ps
CPU time 63.36 seconds
Started Jun 28 05:25:03 PM PDT 24
Finished Jun 28 05:26:07 PM PDT 24
Peak memory 202036 kb
Host smart-bcf80f08-b6fa-45df-973f-c58a3df9d26f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175138016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2175138016
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.900244938
Short name T156
Test name
Test status
Simulation time 22563776490 ps
CPU time 92.69 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:26:34 PM PDT 24
Peak memory 202068 kb
Host smart-ceb8c2dc-aa5e-4cce-8d04-13c80e1e3692
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=900244938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.900244938
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.4136656971
Short name T263
Test name
Test status
Simulation time 175817611 ps
CPU time 3.65 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:05 PM PDT 24
Peak memory 201904 kb
Host smart-e90f598a-1c71-4c27-b7dc-1639ce45913c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136656971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4136656971
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1281118748
Short name T566
Test name
Test status
Simulation time 633019798 ps
CPU time 8.47 seconds
Started Jun 28 05:25:04 PM PDT 24
Finished Jun 28 05:25:13 PM PDT 24
Peak memory 201896 kb
Host smart-7e8a15d3-e5ca-42f4-b72b-73d28a954999
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1281118748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1281118748
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.2342419975
Short name T450
Test name
Test status
Simulation time 102769824 ps
CPU time 1.99 seconds
Started Jun 28 05:25:05 PM PDT 24
Finished Jun 28 05:25:07 PM PDT 24
Peak memory 201884 kb
Host smart-c92f0274-ac2b-4948-8c56-9066238bac09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2342419975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2342419975
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3057322063
Short name T530
Test name
Test status
Simulation time 2122489357 ps
CPU time 10.71 seconds
Started Jun 28 05:25:01 PM PDT 24
Finished Jun 28 05:25:13 PM PDT 24
Peak memory 201828 kb
Host smart-7d621e5e-46e5-4274-b9c7-5f1b6d58f3a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057322063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3057322063
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.4114162794
Short name T375
Test name
Test status
Simulation time 584236363 ps
CPU time 4.95 seconds
Started Jun 28 05:25:04 PM PDT 24
Finished Jun 28 05:25:09 PM PDT 24
Peak memory 201872 kb
Host smart-3456c05f-5268-4e89-a8ae-0dfda0f2cb4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4114162794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4114162794
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2042442134
Short name T178
Test name
Test status
Simulation time 12588152 ps
CPU time 1.27 seconds
Started Jun 28 05:25:02 PM PDT 24
Finished Jun 28 05:25:05 PM PDT 24
Peak memory 201904 kb
Host smart-137f0f29-d4c4-4780-ba5e-ea7eb498008c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042442134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2042442134
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2036630871
Short name T745
Test name
Test status
Simulation time 1331055866 ps
CPU time 18.73 seconds
Started Jun 28 05:25:11 PM PDT 24
Finished Jun 28 05:25:31 PM PDT 24
Peak memory 201920 kb
Host smart-96552848-53a0-4037-a96f-7c897edc0e73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2036630871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2036630871
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3040757029
Short name T139
Test name
Test status
Simulation time 1375713395 ps
CPU time 20.06 seconds
Started Jun 28 05:25:14 PM PDT 24
Finished Jun 28 05:25:34 PM PDT 24
Peak memory 201864 kb
Host smart-9b3553dd-c80e-4f8e-a34f-e91b0e663be3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3040757029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3040757029
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3634037976
Short name T92
Test name
Test status
Simulation time 1468342153 ps
CPU time 45.9 seconds
Started Jun 28 05:25:16 PM PDT 24
Finished Jun 28 05:26:03 PM PDT 24
Peak memory 204208 kb
Host smart-dcf92af0-0e48-48db-8dfa-f8cd01a917c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3634037976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.3634037976
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3199779311
Short name T292
Test name
Test status
Simulation time 4057334136 ps
CPU time 109.23 seconds
Started Jun 28 05:25:16 PM PDT 24
Finished Jun 28 05:27:06 PM PDT 24
Peak memory 206984 kb
Host smart-aa3cff8d-55c6-45ac-9b4a-12eca61ebf98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3199779311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3199779311
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3538962528
Short name T111
Test name
Test status
Simulation time 125794568 ps
CPU time 2.86 seconds
Started Jun 28 05:25:04 PM PDT 24
Finished Jun 28 05:25:08 PM PDT 24
Peak memory 201908 kb
Host smart-e76ed995-49b6-402e-ac20-71f933853b05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3538962528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3538962528
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3035328250
Short name T619
Test name
Test status
Simulation time 62446833 ps
CPU time 10.01 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:25:23 PM PDT 24
Peak memory 201912 kb
Host smart-cfeed0dd-d192-4ded-9637-c1303df0e251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3035328250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3035328250
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3381209416
Short name T761
Test name
Test status
Simulation time 51701432128 ps
CPU time 340.85 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:30:54 PM PDT 24
Peak memory 204136 kb
Host smart-eb53cbd5-0cec-4972-b789-43622f50a0f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3381209416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3381209416
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.746223564
Short name T291
Test name
Test status
Simulation time 316671902 ps
CPU time 5.9 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:25:19 PM PDT 24
Peak memory 201960 kb
Host smart-62ac4500-de85-4c32-8a50-7525d637e5f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=746223564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.746223564
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.3596357446
Short name T754
Test name
Test status
Simulation time 90060642 ps
CPU time 5.82 seconds
Started Jun 28 05:25:16 PM PDT 24
Finished Jun 28 05:25:22 PM PDT 24
Peak memory 201920 kb
Host smart-4360c301-b335-42f0-85a1-eee0bf28eb9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3596357446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3596357446
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.533856300
Short name T371
Test name
Test status
Simulation time 194499913 ps
CPU time 6.79 seconds
Started Jun 28 05:25:18 PM PDT 24
Finished Jun 28 05:25:25 PM PDT 24
Peak memory 201876 kb
Host smart-c7d15ccc-42a4-4e32-acd5-6f4441ac6f2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=533856300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.533856300
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2736375013
Short name T483
Test name
Test status
Simulation time 46943056525 ps
CPU time 51.45 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:26:05 PM PDT 24
Peak memory 201940 kb
Host smart-aaab128f-aa4c-4245-8eb7-a902c90636fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736375013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2736375013
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3178861199
Short name T100
Test name
Test status
Simulation time 27143654892 ps
CPU time 173.55 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:28:06 PM PDT 24
Peak memory 202064 kb
Host smart-2cf80347-5af4-4b58-8d7a-d5be72070c81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3178861199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3178861199
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3692182254
Short name T843
Test name
Test status
Simulation time 66770489 ps
CPU time 7.56 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:25:20 PM PDT 24
Peak memory 201900 kb
Host smart-ee531358-e446-45be-a905-f56d46b2fe39
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692182254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3692182254
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.2555371893
Short name T23
Test name
Test status
Simulation time 1488049801 ps
CPU time 8.57 seconds
Started Jun 28 05:25:16 PM PDT 24
Finished Jun 28 05:25:25 PM PDT 24
Peak memory 201848 kb
Host smart-7e218d95-7fb7-4fd2-888b-64950e711b5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555371893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2555371893
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.2517363475
Short name T299
Test name
Test status
Simulation time 89868594 ps
CPU time 1.88 seconds
Started Jun 28 05:25:11 PM PDT 24
Finished Jun 28 05:25:14 PM PDT 24
Peak memory 201904 kb
Host smart-aa25c841-f062-4d9b-bee6-367650870eb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2517363475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2517363475
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.925661445
Short name T58
Test name
Test status
Simulation time 4647370729 ps
CPU time 8.71 seconds
Started Jun 28 05:25:13 PM PDT 24
Finished Jun 28 05:25:22 PM PDT 24
Peak memory 201976 kb
Host smart-017f61da-2bdf-479e-927d-79032e0504a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=925661445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.925661445
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.927273653
Short name T760
Test name
Test status
Simulation time 4092007254 ps
CPU time 11.02 seconds
Started Jun 28 05:25:17 PM PDT 24
Finished Jun 28 05:25:29 PM PDT 24
Peak memory 201976 kb
Host smart-102cc41f-9a60-44f8-be06-13b81946b841
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=927273653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.927273653
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1054268004
Short name T701
Test name
Test status
Simulation time 19833792 ps
CPU time 1.21 seconds
Started Jun 28 05:25:15 PM PDT 24
Finished Jun 28 05:25:16 PM PDT 24
Peak memory 201804 kb
Host smart-adc3f411-548a-47d2-8c8b-788172c0477f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054268004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1054268004
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1457817167
Short name T826
Test name
Test status
Simulation time 238478320 ps
CPU time 15.47 seconds
Started Jun 28 05:25:14 PM PDT 24
Finished Jun 28 05:25:30 PM PDT 24
Peak memory 201820 kb
Host smart-854f4f23-3e97-4ff8-a54e-abd55f766b43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1457817167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1457817167
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2386424487
Short name T65
Test name
Test status
Simulation time 486035171 ps
CPU time 48.37 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:26:02 PM PDT 24
Peak memory 201972 kb
Host smart-1cac7f54-c570-4125-a250-2ee4f3a188a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2386424487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2386424487
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.4191219137
Short name T436
Test name
Test status
Simulation time 114506915 ps
CPU time 21.06 seconds
Started Jun 28 05:25:17 PM PDT 24
Finished Jun 28 05:25:38 PM PDT 24
Peak memory 202988 kb
Host smart-ff4c15f5-5181-40c3-93a9-c0bdde1fcabc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4191219137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.4191219137
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1900614651
Short name T710
Test name
Test status
Simulation time 61352005 ps
CPU time 11.85 seconds
Started Jun 28 05:25:23 PM PDT 24
Finished Jun 28 05:25:36 PM PDT 24
Peak memory 201968 kb
Host smart-317ef329-290c-4002-8863-4bf0e704191e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1900614651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.1900614651
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1742417747
Short name T712
Test name
Test status
Simulation time 39993035 ps
CPU time 2.94 seconds
Started Jun 28 05:25:12 PM PDT 24
Finished Jun 28 05:25:15 PM PDT 24
Peak memory 201908 kb
Host smart-5da51f14-0739-4e76-947f-687f7de4900a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1742417747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1742417747
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2597564216
Short name T316
Test name
Test status
Simulation time 229710668 ps
CPU time 9.97 seconds
Started Jun 28 05:25:25 PM PDT 24
Finished Jun 28 05:25:36 PM PDT 24
Peak memory 201916 kb
Host smart-25066f82-57c5-4648-be5a-f442fc3dec41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2597564216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2597564216
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.73476552
Short name T688
Test name
Test status
Simulation time 48688319 ps
CPU time 4.4 seconds
Started Jun 28 05:25:27 PM PDT 24
Finished Jun 28 05:25:32 PM PDT 24
Peak memory 201960 kb
Host smart-ba31dd36-7c32-4e81-98d8-e1eaf748d901
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73476552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.73476552
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.2420043586
Short name T605
Test name
Test status
Simulation time 81150597 ps
CPU time 6.17 seconds
Started Jun 28 05:25:23 PM PDT 24
Finished Jun 28 05:25:29 PM PDT 24
Peak memory 201916 kb
Host smart-bb096a82-75a4-4ce1-87c6-20c17a5a1cb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2420043586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2420043586
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.76137930
Short name T315
Test name
Test status
Simulation time 28673794444 ps
CPU time 110.67 seconds
Started Jun 28 05:25:22 PM PDT 24
Finished Jun 28 05:27:13 PM PDT 24
Peak memory 202028 kb
Host smart-cebb5112-f504-41d9-9135-6d46b291abfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=76137930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.76137930
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.266290187
Short name T873
Test name
Test status
Simulation time 11087797691 ps
CPU time 54.51 seconds
Started Jun 28 05:25:24 PM PDT 24
Finished Jun 28 05:26:19 PM PDT 24
Peak memory 202068 kb
Host smart-b8097786-f8fb-4f65-8c91-d9c904399a21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=266290187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.266290187
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.27324586
Short name T692
Test name
Test status
Simulation time 244139889 ps
CPU time 6.68 seconds
Started Jun 28 05:25:24 PM PDT 24
Finished Jun 28 05:25:31 PM PDT 24
Peak memory 201900 kb
Host smart-a09b3176-c3e6-46db-90ae-4996642fbdad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.27324586
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1954381656
Short name T108
Test name
Test status
Simulation time 1178901294 ps
CPU time 8.23 seconds
Started Jun 28 05:25:25 PM PDT 24
Finished Jun 28 05:25:34 PM PDT 24
Peak memory 200448 kb
Host smart-0effd83e-2de0-4029-a511-416d38c6d9c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954381656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1954381656
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.3688655356
Short name T130
Test name
Test status
Simulation time 83708133 ps
CPU time 1.58 seconds
Started Jun 28 05:25:25 PM PDT 24
Finished Jun 28 05:25:27 PM PDT 24
Peak memory 201904 kb
Host smart-70cc57f5-3b3f-4c84-bbdd-65f6e93f72f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3688655356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3688655356
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1241217048
Short name T852
Test name
Test status
Simulation time 4557069135 ps
CPU time 8.54 seconds
Started Jun 28 05:25:25 PM PDT 24
Finished Jun 28 05:25:35 PM PDT 24
Peak memory 202028 kb
Host smart-e8832399-06af-4e8c-ab0b-779f91a3a2e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241217048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1241217048
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1786722228
Short name T413
Test name
Test status
Simulation time 2098422327 ps
CPU time 11.66 seconds
Started Jun 28 05:25:32 PM PDT 24
Finished Jun 28 05:25:44 PM PDT 24
Peak memory 201920 kb
Host smart-8931381d-0a81-4935-acf0-9b9ab5bdde91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1786722228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1786722228
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2812922194
Short name T465
Test name
Test status
Simulation time 9159694 ps
CPU time 1.15 seconds
Started Jun 28 05:25:25 PM PDT 24
Finished Jun 28 05:25:27 PM PDT 24
Peak memory 201804 kb
Host smart-ceab51ee-312a-46db-a487-b8dfd9dfc531
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812922194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2812922194
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3207706506
Short name T426
Test name
Test status
Simulation time 2911151321 ps
CPU time 32 seconds
Started Jun 28 05:25:23 PM PDT 24
Finished Jun 28 05:25:56 PM PDT 24
Peak memory 202972 kb
Host smart-17bcb229-7226-4f3e-9f5e-038adb60cd96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3207706506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3207706506
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1326375671
Short name T408
Test name
Test status
Simulation time 19183438551 ps
CPU time 81.52 seconds
Started Jun 28 05:25:29 PM PDT 24
Finished Jun 28 05:26:52 PM PDT 24
Peak memory 202068 kb
Host smart-d4afe71c-37ee-43dd-a756-4688eb593e2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1326375671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1326375671
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1713055731
Short name T616
Test name
Test status
Simulation time 836423028 ps
CPU time 78.21 seconds
Started Jun 28 05:25:23 PM PDT 24
Finished Jun 28 05:26:42 PM PDT 24
Peak memory 204660 kb
Host smart-d5696c74-7473-4edd-9556-b1956ec5f6f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1713055731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.1713055731
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2581233828
Short name T615
Test name
Test status
Simulation time 5835840546 ps
CPU time 73.39 seconds
Started Jun 28 05:25:23 PM PDT 24
Finished Jun 28 05:26:37 PM PDT 24
Peak memory 204644 kb
Host smart-9b72e252-8731-444d-881c-22427084ed40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2581233828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.2581233828
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3292576838
Short name T52
Test name
Test status
Simulation time 45615907 ps
CPU time 1.55 seconds
Started Jun 28 05:25:29 PM PDT 24
Finished Jun 28 05:25:32 PM PDT 24
Peak memory 201884 kb
Host smart-8d1bee60-fae7-4b63-b10d-fb983f0bb9e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3292576838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3292576838
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3553790164
Short name T93
Test name
Test status
Simulation time 754278660 ps
CPU time 16.59 seconds
Started Jun 28 05:25:34 PM PDT 24
Finished Jun 28 05:25:51 PM PDT 24
Peak memory 201836 kb
Host smart-b157897f-4ec0-4b0b-bad9-6e5e441726ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3553790164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3553790164
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1734698421
Short name T751
Test name
Test status
Simulation time 165243281656 ps
CPU time 164.37 seconds
Started Jun 28 05:25:35 PM PDT 24
Finished Jun 28 05:28:20 PM PDT 24
Peak memory 203096 kb
Host smart-fc25316e-5ba8-4edd-a382-7d65e6fbeb02
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1734698421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1734698421
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.126572498
Short name T653
Test name
Test status
Simulation time 191291281 ps
CPU time 2.98 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:25:50 PM PDT 24
Peak memory 201960 kb
Host smart-16d80ba7-82d8-49e8-b5c8-d5fc512127b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=126572498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.126572498
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.125919130
Short name T314
Test name
Test status
Simulation time 77947513 ps
CPU time 1.74 seconds
Started Jun 28 05:25:35 PM PDT 24
Finished Jun 28 05:25:37 PM PDT 24
Peak memory 201920 kb
Host smart-9b2eeabc-6025-4cc5-8779-cec8ccae4599
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125919130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.125919130
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.1426488671
Short name T797
Test name
Test status
Simulation time 1248153676 ps
CPU time 15.02 seconds
Started Jun 28 05:25:36 PM PDT 24
Finished Jun 28 05:25:52 PM PDT 24
Peak memory 201908 kb
Host smart-f3e77af5-c618-4729-81f6-66aeb9a5ed51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1426488671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1426488671
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3244985676
Short name T787
Test name
Test status
Simulation time 7413330482 ps
CPU time 25.01 seconds
Started Jun 28 05:25:34 PM PDT 24
Finished Jun 28 05:26:00 PM PDT 24
Peak memory 202032 kb
Host smart-77695048-05cf-477d-a6a0-fdc4a50f45e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244985676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3244985676
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3591919864
Short name T2
Test name
Test status
Simulation time 72805322086 ps
CPU time 148.35 seconds
Started Jun 28 05:25:34 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 202072 kb
Host smart-28a8200b-8735-493e-a77d-288e72d4a27b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3591919864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3591919864
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.4139152251
Short name T356
Test name
Test status
Simulation time 159568394 ps
CPU time 6.92 seconds
Started Jun 28 05:25:35 PM PDT 24
Finished Jun 28 05:25:43 PM PDT 24
Peak memory 201880 kb
Host smart-2d265d2f-dc6f-4f55-973b-5938df1a5b29
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139152251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.4139152251
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.2819875625
Short name T506
Test name
Test status
Simulation time 1047231029 ps
CPU time 13.71 seconds
Started Jun 28 05:25:36 PM PDT 24
Finished Jun 28 05:25:50 PM PDT 24
Peak memory 201912 kb
Host smart-54258d9b-d5b1-4f5b-9cdd-f50caa265efd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819875625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2819875625
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.4053265097
Short name T180
Test name
Test status
Simulation time 54606720 ps
CPU time 1.67 seconds
Started Jun 28 05:25:22 PM PDT 24
Finished Jun 28 05:25:24 PM PDT 24
Peak memory 201904 kb
Host smart-7e961c82-a530-45e7-9e26-7c0e80e269fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4053265097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4053265097
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1353524274
Short name T129
Test name
Test status
Simulation time 1697746667 ps
CPU time 8.33 seconds
Started Jun 28 05:25:34 PM PDT 24
Finished Jun 28 05:25:43 PM PDT 24
Peak memory 201876 kb
Host smart-cb34b21e-01a6-46e6-b660-d68408fc04c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353524274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1353524274
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.699085283
Short name T278
Test name
Test status
Simulation time 1777451270 ps
CPU time 7.12 seconds
Started Jun 28 05:25:35 PM PDT 24
Finished Jun 28 05:25:43 PM PDT 24
Peak memory 201880 kb
Host smart-058de766-0e40-4fa5-830f-628558166b52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=699085283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.699085283
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1338660732
Short name T434
Test name
Test status
Simulation time 10175272 ps
CPU time 1.01 seconds
Started Jun 28 05:25:29 PM PDT 24
Finished Jun 28 05:25:31 PM PDT 24
Peak memory 201876 kb
Host smart-712f2267-b9f5-406f-b204-8b1efa2f91b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338660732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1338660732
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4004602001
Short name T159
Test name
Test status
Simulation time 304062848 ps
CPU time 29.33 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:26:16 PM PDT 24
Peak memory 202872 kb
Host smart-4ab0c85a-ee48-4f67-b7bf-429d1873bc74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4004602001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4004602001
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2472942444
Short name T128
Test name
Test status
Simulation time 163482719 ps
CPU time 14.98 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:26:01 PM PDT 24
Peak memory 201964 kb
Host smart-64f5bd5e-9e79-427e-bf4b-2f7524e917b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2472942444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2472942444
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2252286483
Short name T99
Test name
Test status
Simulation time 4163960207 ps
CPU time 133.94 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:28:00 PM PDT 24
Peak memory 206708 kb
Host smart-4ed746ad-36a5-45bb-b6df-05486d42b68a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2252286483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.2252286483
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1949591318
Short name T7
Test name
Test status
Simulation time 512053326 ps
CPU time 60.45 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:26:48 PM PDT 24
Peak memory 203628 kb
Host smart-ccc94583-96c4-4071-a677-5c5607c8740c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1949591318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.1949591318
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.869849272
Short name T85
Test name
Test status
Simulation time 107303522 ps
CPU time 2.9 seconds
Started Jun 28 05:25:35 PM PDT 24
Finished Jun 28 05:25:38 PM PDT 24
Peak memory 201912 kb
Host smart-cc237e8c-bb55-4af8-939c-857fd6bcb656
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=869849272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.869849272
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2537019151
Short name T850
Test name
Test status
Simulation time 126428616 ps
CPU time 12.17 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:25:59 PM PDT 24
Peak memory 201912 kb
Host smart-56a1dc40-93a6-49e3-b4b9-90f48c0c36e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2537019151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2537019151
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1191437777
Short name T899
Test name
Test status
Simulation time 430257999 ps
CPU time 3.88 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:25:50 PM PDT 24
Peak memory 201960 kb
Host smart-5ba2633c-6dd4-4cf6-8525-c369807f85a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1191437777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1191437777
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.1223240407
Short name T620
Test name
Test status
Simulation time 242057095 ps
CPU time 4.38 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:25:51 PM PDT 24
Peak memory 201916 kb
Host smart-610fd6b9-0187-42b1-94b8-6c0d42a33f76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1223240407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1223240407
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.47369793
Short name T30
Test name
Test status
Simulation time 2069470322 ps
CPU time 14.25 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:26:02 PM PDT 24
Peak memory 201920 kb
Host smart-8b3ae7f3-8e8b-4bf4-95ea-a534dabcc19a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47369793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.47369793
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2312028143
Short name T842
Test name
Test status
Simulation time 8519090038 ps
CPU time 41.34 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:26:29 PM PDT 24
Peak memory 202012 kb
Host smart-4b31494b-d008-48a0-b58e-28a95450292d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312028143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2312028143
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1589282039
Short name T729
Test name
Test status
Simulation time 8004882731 ps
CPU time 60.29 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:26:48 PM PDT 24
Peak memory 202064 kb
Host smart-0d5abcb8-37c4-4f78-ba77-2d655b9b73c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1589282039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1589282039
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.569454060
Short name T256
Test name
Test status
Simulation time 122485483 ps
CPU time 5.75 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:25:54 PM PDT 24
Peak memory 201904 kb
Host smart-5b555580-b9fd-4ec4-ac63-0ecf6fdeb261
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569454060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.569454060
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.3518778843
Short name T229
Test name
Test status
Simulation time 1248639738 ps
CPU time 14.26 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:26:01 PM PDT 24
Peak memory 201912 kb
Host smart-80bea6a6-e838-45bf-a9ae-d1313afc3061
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3518778843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3518778843
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.3349254414
Short name T809
Test name
Test status
Simulation time 11241394 ps
CPU time 1.18 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:25:49 PM PDT 24
Peak memory 201900 kb
Host smart-81c44926-b904-4f58-8c76-bb3b16449df1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3349254414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3349254414
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3373794924
Short name T3
Test name
Test status
Simulation time 3118708389 ps
CPU time 10.1 seconds
Started Jun 28 05:25:48 PM PDT 24
Finished Jun 28 05:25:59 PM PDT 24
Peak memory 201972 kb
Host smart-0b16f411-a833-4cea-8a5d-d5df43eb783f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373794924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3373794924
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.4122175563
Short name T564
Test name
Test status
Simulation time 3144500576 ps
CPU time 6.75 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:25:55 PM PDT 24
Peak memory 202220 kb
Host smart-4b9cf944-e515-42a5-b877-09e28d3799ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4122175563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4122175563
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1011097293
Short name T601
Test name
Test status
Simulation time 7715299 ps
CPU time 1.17 seconds
Started Jun 28 05:25:50 PM PDT 24
Finished Jun 28 05:25:52 PM PDT 24
Peak memory 201872 kb
Host smart-3c5aec14-9c1a-4cbe-8d5d-7b1e7e399e26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011097293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1011097293
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2282012804
Short name T460
Test name
Test status
Simulation time 2272288602 ps
CPU time 38.64 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:26:27 PM PDT 24
Peak memory 201960 kb
Host smart-261dd1f7-7541-414d-ae74-9853db7cd03c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2282012804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2282012804
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2426763041
Short name T747
Test name
Test status
Simulation time 3810675071 ps
CPU time 47.67 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:26:36 PM PDT 24
Peak memory 201940 kb
Host smart-2cb9553b-1e58-4e5f-ad48-b74d61549d41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2426763041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2426763041
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.569089117
Short name T395
Test name
Test status
Simulation time 1330136761 ps
CPU time 112.22 seconds
Started Jun 28 05:25:48 PM PDT 24
Finished Jun 28 05:27:41 PM PDT 24
Peak memory 204212 kb
Host smart-67c8a773-ee6e-4008-9e93-ae80000a7856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=569089117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand
_reset.569089117
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2890145128
Short name T428
Test name
Test status
Simulation time 194825905 ps
CPU time 13.13 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:26:00 PM PDT 24
Peak memory 201936 kb
Host smart-3afcc5ea-1bb9-4970-b61e-a164364e3f14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2890145128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.2890145128
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.82935267
Short name T832
Test name
Test status
Simulation time 1465356748 ps
CPU time 13.75 seconds
Started Jun 28 05:25:46 PM PDT 24
Finished Jun 28 05:26:01 PM PDT 24
Peak memory 201832 kb
Host smart-d8238473-18c8-4def-8b81-45148565424c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82935267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.82935267
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.829283390
Short name T303
Test name
Test status
Simulation time 206069113 ps
CPU time 3.38 seconds
Started Jun 28 05:26:01 PM PDT 24
Finished Jun 28 05:26:05 PM PDT 24
Peak memory 201860 kb
Host smart-c8eb5fc2-6706-48c8-9e2c-d7294fd7ecb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=829283390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.829283390
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3738539298
Short name T141
Test name
Test status
Simulation time 20684957288 ps
CPU time 131 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:28:11 PM PDT 24
Peak memory 202124 kb
Host smart-1cf39838-1dcd-4ed5-8bdf-e749c80b8999
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3738539298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.3738539298
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1232921206
Short name T332
Test name
Test status
Simulation time 138503184 ps
CPU time 6.55 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:08 PM PDT 24
Peak memory 201968 kb
Host smart-0cd40a1e-2a0a-4177-ae06-cb5815ed5265
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1232921206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1232921206
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.2800096573
Short name T580
Test name
Test status
Simulation time 25357954 ps
CPU time 3.16 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:05 PM PDT 24
Peak memory 201904 kb
Host smart-22b4803a-f678-4fee-b71f-093978ea6937
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2800096573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2800096573
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.4194106654
Short name T512
Test name
Test status
Simulation time 973054697 ps
CPU time 10.1 seconds
Started Jun 28 05:25:58 PM PDT 24
Finished Jun 28 05:26:09 PM PDT 24
Peak memory 201904 kb
Host smart-67215520-0d59-4e3b-843e-5b35d07b01ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4194106654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4194106654
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.728122089
Short name T718
Test name
Test status
Simulation time 72223654158 ps
CPU time 159.11 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 201956 kb
Host smart-c826b8e1-11ff-40aa-90e0-282eee6be8af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=728122089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.728122089
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3119658859
Short name T73
Test name
Test status
Simulation time 25425395518 ps
CPU time 168.73 seconds
Started Jun 28 05:26:01 PM PDT 24
Finished Jun 28 05:28:51 PM PDT 24
Peak memory 202044 kb
Host smart-d6e0428e-6050-48c1-9348-5a61a95b6cb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3119658859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3119658859
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3645112584
Short name T707
Test name
Test status
Simulation time 247447706 ps
CPU time 8.93 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:09 PM PDT 24
Peak memory 201900 kb
Host smart-567bb5f7-cd3a-4898-b824-1e807718a4a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645112584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3645112584
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.667559128
Short name T345
Test name
Test status
Simulation time 4417294854 ps
CPU time 9.03 seconds
Started Jun 28 05:26:01 PM PDT 24
Finished Jun 28 05:26:11 PM PDT 24
Peak memory 202012 kb
Host smart-e1c9054a-e70c-44b4-8dbb-077890f52675
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=667559128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.667559128
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2605979634
Short name T548
Test name
Test status
Simulation time 41131690 ps
CPU time 1.24 seconds
Started Jun 28 05:25:47 PM PDT 24
Finished Jun 28 05:25:49 PM PDT 24
Peak memory 201904 kb
Host smart-2695292c-5ab3-4790-b594-9dc445fbc240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2605979634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2605979634
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1740002244
Short name T727
Test name
Test status
Simulation time 1267213650 ps
CPU time 6.46 seconds
Started Jun 28 05:25:45 PM PDT 24
Finished Jun 28 05:25:52 PM PDT 24
Peak memory 201904 kb
Host smart-56e33dca-71da-43ee-bee9-3b48990f989e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740002244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1740002244
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2757641792
Short name T449
Test name
Test status
Simulation time 3316182563 ps
CPU time 8.25 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:08 PM PDT 24
Peak memory 201988 kb
Host smart-d3415a98-bee1-403e-8505-6415b5e85f92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2757641792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2757641792
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2586758837
Short name T336
Test name
Test status
Simulation time 9938272 ps
CPU time 1.16 seconds
Started Jun 28 05:25:48 PM PDT 24
Finished Jun 28 05:25:50 PM PDT 24
Peak memory 201904 kb
Host smart-858e57fd-4469-4f8c-a978-68ee2ca84a7f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586758837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2586758837
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2545023160
Short name T440
Test name
Test status
Simulation time 2757980609 ps
CPU time 56.84 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:57 PM PDT 24
Peak memory 203500 kb
Host smart-5c20c394-3174-470e-b632-3e804e7cbcf3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2545023160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2545023160
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3881615035
Short name T624
Test name
Test status
Simulation time 12102986648 ps
CPU time 55.2 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:55 PM PDT 24
Peak memory 202092 kb
Host smart-99613213-f5e3-43cc-baec-bce08fa1b909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3881615035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3881615035
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2817671
Short name T782
Test name
Test status
Simulation time 68784485 ps
CPU time 15.28 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:15 PM PDT 24
Peak memory 204016 kb
Host smart-76d335ec-ca79-437f-95d9-5b7c3b2a6b42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2817671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_r
eset.2817671
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3259802809
Short name T743
Test name
Test status
Simulation time 2507830758 ps
CPU time 107.9 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:27:48 PM PDT 24
Peak memory 204480 kb
Host smart-16fef7e4-f54e-4153-bc7a-978a34f0daf6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3259802809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.3259802809
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3340192522
Short name T378
Test name
Test status
Simulation time 185573477 ps
CPU time 3.14 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:03 PM PDT 24
Peak memory 201912 kb
Host smart-71136f3b-6168-4470-8b6c-d30cced947e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3340192522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3340192522
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2929687645
Short name T508
Test name
Test status
Simulation time 916207028 ps
CPU time 15.02 seconds
Started Jun 28 05:26:01 PM PDT 24
Finished Jun 28 05:26:17 PM PDT 24
Peak memory 201900 kb
Host smart-b451b09c-53e9-43be-82e7-18eaf0b2f129
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2929687645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2929687645
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.865969852
Short name T199
Test name
Test status
Simulation time 23566183736 ps
CPU time 121.74 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 202068 kb
Host smart-6ea66b21-ac37-440e-ab41-545eb585d552
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=865969852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo
w_rsp.865969852
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2673563309
Short name T635
Test name
Test status
Simulation time 216063039 ps
CPU time 4.47 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:26:20 PM PDT 24
Peak memory 201936 kb
Host smart-255499ff-ea70-4d94-b8c7-4ef990356878
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2673563309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2673563309
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.1095305813
Short name T833
Test name
Test status
Simulation time 79026969 ps
CPU time 1.2 seconds
Started Jun 28 05:25:58 PM PDT 24
Finished Jun 28 05:26:00 PM PDT 24
Peak memory 201908 kb
Host smart-66207c97-7ea4-472a-896a-e7e8c3e390b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1095305813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1095305813
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.2365756386
Short name T552
Test name
Test status
Simulation time 690019692 ps
CPU time 13.94 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:14 PM PDT 24
Peak memory 201904 kb
Host smart-d30ad900-fcd2-4cc1-af30-6e84ffc17ead
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365756386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2365756386
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.738825960
Short name T238
Test name
Test status
Simulation time 29751890725 ps
CPU time 121.78 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 202036 kb
Host smart-88ba687f-5b73-4dab-8fad-f27c07604d0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=738825960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.738825960
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.202038292
Short name T137
Test name
Test status
Simulation time 8818924185 ps
CPU time 36.11 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:37 PM PDT 24
Peak memory 201984 kb
Host smart-6f965f23-6545-4781-a90f-9d74cfbc19c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=202038292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.202038292
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3236201089
Short name T281
Test name
Test status
Simulation time 62821954 ps
CPU time 2 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:04 PM PDT 24
Peak memory 201904 kb
Host smart-1d10c623-b3e1-4f11-b6ee-efef85fe64f1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236201089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3236201089
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3099755797
Short name T307
Test name
Test status
Simulation time 296726915 ps
CPU time 4.63 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:06 PM PDT 24
Peak memory 201904 kb
Host smart-6bb29f6d-6730-47b7-9d8d-f3ced5eaba17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3099755797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3099755797
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.2200321703
Short name T258
Test name
Test status
Simulation time 150266934 ps
CPU time 1.54 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:03 PM PDT 24
Peak memory 201848 kb
Host smart-ae128699-0a6b-4fec-af2a-c2663b4e0660
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2200321703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2200321703
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2336608106
Short name T343
Test name
Test status
Simulation time 4264782898 ps
CPU time 9.02 seconds
Started Jun 28 05:25:58 PM PDT 24
Finished Jun 28 05:26:08 PM PDT 24
Peak memory 201868 kb
Host smart-3ee8e710-c832-4aaf-b202-a0571385b3e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336608106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2336608106
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1896113966
Short name T324
Test name
Test status
Simulation time 2184533774 ps
CPU time 8.67 seconds
Started Jun 28 05:26:00 PM PDT 24
Finished Jun 28 05:26:10 PM PDT 24
Peak memory 201976 kb
Host smart-2a4f00c2-a6fb-49a2-9896-878e46dfbe12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1896113966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1896113966
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1552529163
Short name T297
Test name
Test status
Simulation time 17594034 ps
CPU time 1.2 seconds
Started Jun 28 05:25:59 PM PDT 24
Finished Jun 28 05:26:02 PM PDT 24
Peak memory 201820 kb
Host smart-aed41ca5-525a-4e19-ba08-cf8bb4b982dc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552529163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1552529163
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.38108986
Short name T405
Test name
Test status
Simulation time 1390972952 ps
CPU time 30.41 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:26:46 PM PDT 24
Peak memory 201920 kb
Host smart-b9e1e514-8f9b-465f-83cd-2499d57d05d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38108986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.38108986
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3609891543
Short name T289
Test name
Test status
Simulation time 765931727 ps
CPU time 29.98 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:45 PM PDT 24
Peak memory 201972 kb
Host smart-8129d527-bf0c-453d-bc60-ef4c630ca322
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3609891543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3609891543
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3890348154
Short name T49
Test name
Test status
Simulation time 3738105488 ps
CPU time 54.52 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:27:09 PM PDT 24
Peak memory 204068 kb
Host smart-94c51bb1-ae84-4dbb-8fd0-e5e6fc884219
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3890348154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.3890348154
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2685903193
Short name T351
Test name
Test status
Simulation time 1288853651 ps
CPU time 42.06 seconds
Started Jun 28 05:26:12 PM PDT 24
Finished Jun 28 05:26:55 PM PDT 24
Peak memory 203764 kb
Host smart-88753760-e4c7-49d3-9bcd-d09c13c1ec0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2685903193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2685903193
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2912386204
Short name T610
Test name
Test status
Simulation time 683292786 ps
CPU time 9.15 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:25 PM PDT 24
Peak memory 201916 kb
Host smart-edeff311-13bf-4f1b-b1b0-decac22ca3af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2912386204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2912386204
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.724209316
Short name T184
Test name
Test status
Simulation time 1238789631 ps
CPU time 26.94 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:43 PM PDT 24
Peak memory 202080 kb
Host smart-869d5c4a-5d01-41b3-82ca-252b7faa2f3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=724209316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.724209316
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2451665663
Short name T188
Test name
Test status
Simulation time 54642614097 ps
CPU time 212.56 seconds
Started Jun 28 05:26:12 PM PDT 24
Finished Jun 28 05:29:45 PM PDT 24
Peak memory 203156 kb
Host smart-6bb51791-ebf9-45ff-a7de-c91490f75ab2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2451665663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.2451665663
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1761802934
Short name T515
Test name
Test status
Simulation time 68156413 ps
CPU time 6.14 seconds
Started Jun 28 05:26:13 PM PDT 24
Finished Jun 28 05:26:20 PM PDT 24
Peak memory 201940 kb
Host smart-96f803cc-736c-4722-9cef-ae677722a78b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1761802934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1761802934
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.4084201951
Short name T585
Test name
Test status
Simulation time 29190964 ps
CPU time 2.6 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:18 PM PDT 24
Peak memory 201888 kb
Host smart-c92ab68c-13c9-4ab9-a0ae-c9b787460f4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4084201951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.4084201951
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.3084544368
Short name T814
Test name
Test status
Simulation time 4622573418 ps
CPU time 15.89 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:26:31 PM PDT 24
Peak memory 202236 kb
Host smart-6e13c64f-46e0-4797-b60a-113af526d7d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3084544368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3084544368
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1079845869
Short name T424
Test name
Test status
Simulation time 26693915310 ps
CPU time 100.58 seconds
Started Jun 28 05:26:12 PM PDT 24
Finished Jun 28 05:27:53 PM PDT 24
Peak memory 202032 kb
Host smart-e1d5af99-01c4-4665-9716-f9e6113e1218
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079845869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1079845869
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1171783988
Short name T848
Test name
Test status
Simulation time 4950741025 ps
CPU time 17.94 seconds
Started Jun 28 05:26:13 PM PDT 24
Finished Jun 28 05:26:31 PM PDT 24
Peak memory 202044 kb
Host smart-d66d139d-c947-4b7d-89a1-5ef142b56b11
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1171783988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1171783988
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.4180132414
Short name T363
Test name
Test status
Simulation time 65862983 ps
CPU time 8.71 seconds
Started Jun 28 05:26:12 PM PDT 24
Finished Jun 28 05:26:22 PM PDT 24
Peak memory 201904 kb
Host smart-aa0add5f-786b-4bfc-8cda-c35cd983c46a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180132414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.4180132414
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3861040125
Short name T753
Test name
Test status
Simulation time 646113518 ps
CPU time 7.51 seconds
Started Jun 28 05:26:13 PM PDT 24
Finished Jun 28 05:26:21 PM PDT 24
Peak memory 201888 kb
Host smart-685166f4-8b59-42f8-829b-60624d4b10ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3861040125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3861040125
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.3307213624
Short name T785
Test name
Test status
Simulation time 262787288 ps
CPU time 1.87 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:26:17 PM PDT 24
Peak memory 202064 kb
Host smart-5c89902f-8fb2-4421-8cde-7c241d22e17d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3307213624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3307213624
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.966513041
Short name T736
Test name
Test status
Simulation time 10212493310 ps
CPU time 7.38 seconds
Started Jun 28 05:26:12 PM PDT 24
Finished Jun 28 05:26:20 PM PDT 24
Peak memory 202008 kb
Host smart-dc21addd-2836-4438-9301-a1debe6560f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=966513041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.966513041
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.466485094
Short name T716
Test name
Test status
Simulation time 1317187181 ps
CPU time 7.35 seconds
Started Jun 28 05:26:13 PM PDT 24
Finished Jun 28 05:26:21 PM PDT 24
Peak memory 201948 kb
Host smart-6831096c-191e-40a6-b9cc-2ef66efa4446
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=466485094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.466485094
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3844628215
Short name T614
Test name
Test status
Simulation time 13501973 ps
CPU time 1.31 seconds
Started Jun 28 05:26:12 PM PDT 24
Finished Jun 28 05:26:14 PM PDT 24
Peak memory 201876 kb
Host smart-0b887980-2524-49f6-95b9-ce27891dbf36
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844628215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3844628215
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1266506254
Short name T470
Test name
Test status
Simulation time 3261413129 ps
CPU time 38.35 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:54 PM PDT 24
Peak memory 201980 kb
Host smart-3e19ece9-3476-433a-85ec-fd20e59b7915
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1266506254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1266506254
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1038362650
Short name T683
Test name
Test status
Simulation time 418080019 ps
CPU time 6.23 seconds
Started Jun 28 05:26:16 PM PDT 24
Finished Jun 28 05:26:22 PM PDT 24
Peak memory 201972 kb
Host smart-e7ff46cc-d533-4a52-b2ca-1dd104a1761b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1038362650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1038362650
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1083699279
Short name T885
Test name
Test status
Simulation time 7170737 ps
CPU time 1.91 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:18 PM PDT 24
Peak memory 201892 kb
Host smart-6f8f6588-d995-41ea-8261-d8f06bc0fb1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1083699279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1083699279
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.256666264
Short name T703
Test name
Test status
Simulation time 515885088 ps
CPU time 30.63 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:46 PM PDT 24
Peak memory 204012 kb
Host smart-4369fc76-6339-4a4c-bccc-31cc5aa56edb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=256666264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res
et_error.256666264
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3947180216
Short name T60
Test name
Test status
Simulation time 1316136942 ps
CPU time 11.05 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:26:26 PM PDT 24
Peak memory 201912 kb
Host smart-6d9a8814-8635-4783-8d72-d2f907866624
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3947180216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3947180216
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.868195825
Short name T650
Test name
Test status
Simulation time 40189247 ps
CPU time 9.7 seconds
Started Jun 28 05:23:28 PM PDT 24
Finished Jun 28 05:23:39 PM PDT 24
Peak memory 201916 kb
Host smart-f13dcd2f-207e-47d3-be0e-9bdb3f702636
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=868195825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.868195825
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1539980638
Short name T197
Test name
Test status
Simulation time 92560421920 ps
CPU time 123.34 seconds
Started Jun 28 05:23:28 PM PDT 24
Finished Jun 28 05:25:32 PM PDT 24
Peak memory 203020 kb
Host smart-844948ca-2560-444d-a9ee-d13af067007f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1539980638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.1539980638
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3781394488
Short name T251
Test name
Test status
Simulation time 33794768 ps
CPU time 1.32 seconds
Started Jun 28 05:23:27 PM PDT 24
Finished Jun 28 05:23:29 PM PDT 24
Peak memory 201960 kb
Host smart-a0e1c646-8096-47ec-b9fc-0fa9a1f9034f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3781394488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3781394488
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.3707986335
Short name T265
Test name
Test status
Simulation time 967810839 ps
CPU time 11.06 seconds
Started Jun 28 05:23:27 PM PDT 24
Finished Jun 28 05:23:38 PM PDT 24
Peak memory 201912 kb
Host smart-97550461-d51d-4558-9860-ae0b7504f26d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3707986335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3707986335
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.1066796145
Short name T154
Test name
Test status
Simulation time 494511537 ps
CPU time 8.68 seconds
Started Jun 28 05:23:17 PM PDT 24
Finished Jun 28 05:23:27 PM PDT 24
Peak memory 201908 kb
Host smart-6e704f2d-567c-445d-af18-90cdbc3aa432
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1066796145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1066796145
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4107451850
Short name T588
Test name
Test status
Simulation time 8248129544 ps
CPU time 18.92 seconds
Started Jun 28 05:23:26 PM PDT 24
Finished Jun 28 05:23:45 PM PDT 24
Peak memory 202028 kb
Host smart-6f569eaa-50d4-4785-b8ed-f17b475c7598
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107451850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4107451850
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2043646584
Short name T425
Test name
Test status
Simulation time 37367344297 ps
CPU time 109.62 seconds
Started Jun 28 05:23:28 PM PDT 24
Finished Jun 28 05:25:18 PM PDT 24
Peak memory 202012 kb
Host smart-052614e5-d806-45a3-8491-eb93df91f5f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2043646584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2043646584
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.4077133620
Short name T544
Test name
Test status
Simulation time 38810180 ps
CPU time 6 seconds
Started Jun 28 05:23:16 PM PDT 24
Finished Jun 28 05:23:23 PM PDT 24
Peak memory 201904 kb
Host smart-c606bf2d-49dd-49c5-94ef-73303d7f4fbf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077133620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4077133620
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.1981867766
Short name T763
Test name
Test status
Simulation time 488846739 ps
CPU time 6.92 seconds
Started Jun 28 05:23:27 PM PDT 24
Finished Jun 28 05:23:34 PM PDT 24
Peak memory 201912 kb
Host smart-8d547938-180c-464b-89dc-7a2e7019a39b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1981867766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1981867766
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.3712227248
Short name T448
Test name
Test status
Simulation time 37822494 ps
CPU time 1.51 seconds
Started Jun 28 05:23:16 PM PDT 24
Finished Jun 28 05:23:18 PM PDT 24
Peak memory 201844 kb
Host smart-d2c21077-48bf-41e1-9e3e-f6a542aa9625
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3712227248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3712227248
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3475976264
Short name T889
Test name
Test status
Simulation time 2641220702 ps
CPU time 10.97 seconds
Started Jun 28 05:23:18 PM PDT 24
Finished Jun 28 05:23:30 PM PDT 24
Peak memory 201856 kb
Host smart-4dc87e48-7188-4aa2-90b1-331de7537ab5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475976264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3475976264
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3177605549
Short name T746
Test name
Test status
Simulation time 2950036079 ps
CPU time 8.9 seconds
Started Jun 28 05:23:17 PM PDT 24
Finished Jun 28 05:23:26 PM PDT 24
Peak memory 201908 kb
Host smart-d5f28a32-02f5-4d60-8942-2f2a2149b56d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3177605549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3177605549
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3471021970
Short name T559
Test name
Test status
Simulation time 16024789 ps
CPU time 1.09 seconds
Started Jun 28 05:23:14 PM PDT 24
Finished Jun 28 05:23:16 PM PDT 24
Peak memory 201872 kb
Host smart-66d63d9f-a4ab-4a88-8fa9-3a466fd334f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471021970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3471021970
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.103198464
Short name T504
Test name
Test status
Simulation time 1218312540 ps
CPU time 31.71 seconds
Started Jun 28 05:23:29 PM PDT 24
Finished Jun 28 05:24:01 PM PDT 24
Peak memory 202940 kb
Host smart-1275d09d-a68e-45a5-b874-3e2abdd0c4a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103198464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.103198464
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.241327938
Short name T680
Test name
Test status
Simulation time 418341957 ps
CPU time 15.11 seconds
Started Jun 28 05:23:27 PM PDT 24
Finished Jun 28 05:23:43 PM PDT 24
Peak memory 201912 kb
Host smart-c059de2e-f63c-4c4f-8ea7-05710602f7c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=241327938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.241327938
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1990397087
Short name T888
Test name
Test status
Simulation time 75876979 ps
CPU time 12.36 seconds
Started Jun 28 05:23:29 PM PDT 24
Finished Jun 28 05:23:41 PM PDT 24
Peak memory 201872 kb
Host smart-a6ab9e09-a668-4dac-bda8-0cf0e3259994
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1990397087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.1990397087
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2027542203
Short name T505
Test name
Test status
Simulation time 638738047 ps
CPU time 46.88 seconds
Started Jun 28 05:23:29 PM PDT 24
Finished Jun 28 05:24:17 PM PDT 24
Peak memory 204104 kb
Host smart-89d969f0-8a34-45c6-adb5-f80f1fcc9d29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2027542203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.2027542203
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3679017725
Short name T872
Test name
Test status
Simulation time 1077858391 ps
CPU time 11.39 seconds
Started Jun 28 05:23:28 PM PDT 24
Finished Jun 28 05:23:40 PM PDT 24
Peak memory 201880 kb
Host smart-81f4e9d4-685a-4f4d-8415-ee10dd3a121e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3679017725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3679017725
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.406729493
Short name T618
Test name
Test status
Simulation time 1369730434 ps
CPU time 5.73 seconds
Started Jun 28 05:26:24 PM PDT 24
Finished Jun 28 05:26:31 PM PDT 24
Peak memory 201912 kb
Host smart-854477d3-3183-4ad8-9d30-5fa4987d94a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=406729493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.406729493
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.4204484551
Short name T140
Test name
Test status
Simulation time 146077913 ps
CPU time 3.63 seconds
Started Jun 28 05:26:23 PM PDT 24
Finished Jun 28 05:26:27 PM PDT 24
Peak memory 201972 kb
Host smart-68339e2f-245a-4f60-828e-cfd5bdd4ba74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4204484551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.4204484551
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.2386463657
Short name T495
Test name
Test status
Simulation time 55231308 ps
CPU time 4.73 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:26:31 PM PDT 24
Peak memory 201900 kb
Host smart-6df0ea90-9592-42df-a456-1e25b3e750b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2386463657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2386463657
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.34733693
Short name T41
Test name
Test status
Simulation time 114341905 ps
CPU time 9.3 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:26:35 PM PDT 24
Peak memory 201848 kb
Host smart-d7dbc5a1-3c71-4dc7-be31-47fb274fec96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34733693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.34733693
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2001133150
Short name T68
Test name
Test status
Simulation time 83500601375 ps
CPU time 66.53 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:27:34 PM PDT 24
Peak memory 202032 kb
Host smart-e54c5ef8-abdd-4c4a-9f1a-649e3c03250e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001133150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2001133150
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1142612271
Short name T765
Test name
Test status
Simulation time 6035836529 ps
CPU time 32.71 seconds
Started Jun 28 05:26:28 PM PDT 24
Finished Jun 28 05:27:02 PM PDT 24
Peak memory 202060 kb
Host smart-05add782-6aa0-472a-bff2-feb28134b1c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1142612271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1142612271
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1215711303
Short name T163
Test name
Test status
Simulation time 49172462 ps
CPU time 4.51 seconds
Started Jun 28 05:26:28 PM PDT 24
Finished Jun 28 05:26:34 PM PDT 24
Peak memory 201900 kb
Host smart-cf7a3d48-fec3-452c-8830-2412b1d75f0e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215711303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1215711303
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.2501762855
Short name T272
Test name
Test status
Simulation time 564461952 ps
CPU time 8.23 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:26:34 PM PDT 24
Peak memory 201916 kb
Host smart-8f8c3f41-69ff-470f-97e3-ecc9a5dd6a76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2501762855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2501762855
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.6626892
Short name T890
Test name
Test status
Simulation time 201220227 ps
CPU time 2.03 seconds
Started Jun 28 05:26:15 PM PDT 24
Finished Jun 28 05:26:18 PM PDT 24
Peak memory 201904 kb
Host smart-a8169495-ec4b-4a4d-a700-ca3deacccf3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6626892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.6626892
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1249572382
Short name T728
Test name
Test status
Simulation time 3505752318 ps
CPU time 9.23 seconds
Started Jun 28 05:26:13 PM PDT 24
Finished Jun 28 05:26:22 PM PDT 24
Peak memory 201968 kb
Host smart-1e89b568-c086-4185-8b40-7a1233615b44
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249572382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1249572382
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2132771778
Short name T824
Test name
Test status
Simulation time 2722978645 ps
CPU time 5.8 seconds
Started Jun 28 05:26:14 PM PDT 24
Finished Jun 28 05:26:20 PM PDT 24
Peak memory 202044 kb
Host smart-867e9bce-ea87-48da-a2bc-5a661872dbaf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2132771778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2132771778
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3963723815
Short name T319
Test name
Test status
Simulation time 10381556 ps
CPU time 1.02 seconds
Started Jun 28 05:26:13 PM PDT 24
Finished Jun 28 05:26:15 PM PDT 24
Peak memory 201816 kb
Host smart-38421bee-2ce1-420d-ac05-be96ec4de51e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963723815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3963723815
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.4003874440
Short name T325
Test name
Test status
Simulation time 154492443 ps
CPU time 11.92 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:26:39 PM PDT 24
Peak memory 201984 kb
Host smart-dd87dcb0-8c6b-4229-aee1-ab494a5c5a8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003874440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4003874440
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3299339994
Short name T406
Test name
Test status
Simulation time 725023644 ps
CPU time 14.2 seconds
Started Jun 28 05:26:28 PM PDT 24
Finished Jun 28 05:26:43 PM PDT 24
Peak memory 201872 kb
Host smart-f52f3afe-d737-485d-bf81-db63ae44175b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3299339994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3299339994
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2481486777
Short name T104
Test name
Test status
Simulation time 3170490523 ps
CPU time 116.71 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:28:22 PM PDT 24
Peak memory 205580 kb
Host smart-235f4966-c524-4786-b7a2-23291c87f47c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2481486777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.2481486777
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.904126435
Short name T64
Test name
Test status
Simulation time 434387846 ps
CPU time 63.79 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:27:31 PM PDT 24
Peak memory 205076 kb
Host smart-3a86ad23-ec38-465c-8e70-9a57ab927d88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=904126435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res
et_error.904126435
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.4275102922
Short name T575
Test name
Test status
Simulation time 439047531 ps
CPU time 9.29 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:26:36 PM PDT 24
Peak memory 201824 kb
Host smart-12e0599e-0e2a-44de-9eec-bee53e765f8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4275102922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4275102922
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2548213257
Short name T541
Test name
Test status
Simulation time 32082706 ps
CPU time 4.43 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:26:32 PM PDT 24
Peak memory 201916 kb
Host smart-dbe1c170-059b-484d-8d4b-4501b4fff6e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2548213257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2548213257
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3256460554
Short name T206
Test name
Test status
Simulation time 45569753254 ps
CPU time 239.82 seconds
Started Jun 28 05:26:27 PM PDT 24
Finished Jun 28 05:30:28 PM PDT 24
Peak memory 202992 kb
Host smart-38989a34-9d9c-4e04-a502-a6b20aac6691
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3256460554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.3256460554
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2173243367
Short name T500
Test name
Test status
Simulation time 2234774036 ps
CPU time 8.93 seconds
Started Jun 28 05:26:29 PM PDT 24
Finished Jun 28 05:26:38 PM PDT 24
Peak memory 202028 kb
Host smart-98f04298-fe51-4b1e-98d6-9b943650c08b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2173243367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2173243367
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.1927765508
Short name T285
Test name
Test status
Simulation time 729657264 ps
CPU time 12.31 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:26:38 PM PDT 24
Peak memory 201892 kb
Host smart-d68954c7-3fde-4106-ae20-0749a6f6e16c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1927765508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1927765508
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.1395581838
Short name T836
Test name
Test status
Simulation time 73830095 ps
CPU time 9.21 seconds
Started Jun 28 05:26:27 PM PDT 24
Finished Jun 28 05:26:37 PM PDT 24
Peak memory 201876 kb
Host smart-139ab2e7-9ad3-4654-902b-1623df79265c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1395581838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1395581838
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2732710216
Short name T171
Test name
Test status
Simulation time 29058824666 ps
CPU time 96.25 seconds
Started Jun 28 05:26:27 PM PDT 24
Finished Jun 28 05:28:04 PM PDT 24
Peak memory 202040 kb
Host smart-af4a695d-7ffc-41ce-a424-4b6235699486
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732710216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2732710216
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1885772603
Short name T744
Test name
Test status
Simulation time 9694981180 ps
CPU time 43.53 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:27:10 PM PDT 24
Peak memory 202068 kb
Host smart-82583ccb-37cb-4ea6-aece-6dff9a673e51
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1885772603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1885772603
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.4160692462
Short name T875
Test name
Test status
Simulation time 58643778 ps
CPU time 6.11 seconds
Started Jun 28 05:26:28 PM PDT 24
Finished Jun 28 05:26:35 PM PDT 24
Peak memory 201900 kb
Host smart-64ba9c63-6d22-40b3-8f07-e9401e32e847
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160692462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4160692462
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.3199566328
Short name T714
Test name
Test status
Simulation time 1044159620 ps
CPU time 11.45 seconds
Started Jun 28 05:26:27 PM PDT 24
Finished Jun 28 05:26:39 PM PDT 24
Peak memory 201884 kb
Host smart-8358cbd9-de60-4389-b4d1-0e6e80194559
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3199566328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3199566328
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1549767701
Short name T493
Test name
Test status
Simulation time 49083104 ps
CPU time 1.44 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:26:27 PM PDT 24
Peak memory 201884 kb
Host smart-6a071687-0108-463e-bc03-edf5eecbb158
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1549767701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1549767701
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4013995823
Short name T789
Test name
Test status
Simulation time 3456905531 ps
CPU time 11.14 seconds
Started Jun 28 05:26:29 PM PDT 24
Finished Jun 28 05:26:40 PM PDT 24
Peak memory 201968 kb
Host smart-d796f83e-d5fc-4c3f-8287-e0cae2df8c0e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013995823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4013995823
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2030243393
Short name T823
Test name
Test status
Simulation time 3424297167 ps
CPU time 6.81 seconds
Started Jun 28 05:26:25 PM PDT 24
Finished Jun 28 05:26:33 PM PDT 24
Peak memory 202004 kb
Host smart-d6c02a50-47a7-4ddc-a981-dd9e2c048cac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2030243393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2030243393
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3357050614
Short name T591
Test name
Test status
Simulation time 9329742 ps
CPU time 1.15 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:26:29 PM PDT 24
Peak memory 201904 kb
Host smart-78dd1e76-b73c-4f31-b5f3-780ba5bf7f4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357050614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3357050614
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.500758526
Short name T370
Test name
Test status
Simulation time 17452643780 ps
CPU time 76.61 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:27:57 PM PDT 24
Peak memory 203024 kb
Host smart-0884ee89-dd19-48b8-9a44-fcddf6eddafd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=500758526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.500758526
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.856242859
Short name T721
Test name
Test status
Simulation time 4619668312 ps
CPU time 80.29 seconds
Started Jun 28 05:26:42 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 203060 kb
Host smart-f5c1db71-6772-4e49-8010-f2e912f6ee1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856242859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.856242859
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.753588960
Short name T634
Test name
Test status
Simulation time 1360702296 ps
CPU time 73.31 seconds
Started Jun 28 05:26:38 PM PDT 24
Finished Jun 28 05:27:52 PM PDT 24
Peak memory 204196 kb
Host smart-99018959-33ee-413b-a082-0af864181f19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=753588960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand
_reset.753588960
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.429914713
Short name T766
Test name
Test status
Simulation time 148513999 ps
CPU time 20.32 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:27:02 PM PDT 24
Peak memory 202988 kb
Host smart-215f7cc9-28fb-4c1d-869d-146d66311222
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=429914713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_res
et_error.429914713
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2549146255
Short name T830
Test name
Test status
Simulation time 746601143 ps
CPU time 3.72 seconds
Started Jun 28 05:26:26 PM PDT 24
Finished Jun 28 05:26:31 PM PDT 24
Peak memory 201908 kb
Host smart-7875e79e-f0f5-47cb-8da7-615ed1a534ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2549146255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2549146255
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2451054914
Short name T447
Test name
Test status
Simulation time 1059389473 ps
CPU time 22.25 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:27:02 PM PDT 24
Peak memory 201916 kb
Host smart-7feb1995-bfe9-4c61-888a-039868f680b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2451054914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2451054914
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.4162316279
Short name T191
Test name
Test status
Simulation time 69328266330 ps
CPU time 260.21 seconds
Started Jun 28 05:26:41 PM PDT 24
Finished Jun 28 05:31:02 PM PDT 24
Peak memory 204116 kb
Host smart-7610e9eb-ecec-429f-88ca-c362d22ba738
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4162316279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.4162316279
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.108083927
Short name T418
Test name
Test status
Simulation time 320982560 ps
CPU time 5.43 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:45 PM PDT 24
Peak memory 201904 kb
Host smart-b4d91dc4-f17d-413d-b3ba-e5180431a0bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108083927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.108083927
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1265729577
Short name T623
Test name
Test status
Simulation time 2306905314 ps
CPU time 13.48 seconds
Started Jun 28 05:26:38 PM PDT 24
Finished Jun 28 05:26:53 PM PDT 24
Peak memory 201944 kb
Host smart-d9d5ebfa-cc3a-416e-86f9-30a0b5adab4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1265729577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1265729577
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.2805699684
Short name T755
Test name
Test status
Simulation time 8924738 ps
CPU time 1.13 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:26:42 PM PDT 24
Peak memory 201808 kb
Host smart-becde85a-beb9-4e19-af74-9c30f8e4492c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2805699684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2805699684
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3207202281
Short name T165
Test name
Test status
Simulation time 23335021611 ps
CPU time 76.12 seconds
Started Jun 28 05:26:41 PM PDT 24
Finished Jun 28 05:27:58 PM PDT 24
Peak memory 202032 kb
Host smart-adec423b-0220-4ea8-b6f6-f11c9279617a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207202281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3207202281
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1937278497
Short name T453
Test name
Test status
Simulation time 29859009260 ps
CPU time 164.19 seconds
Started Jun 28 05:26:38 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 202068 kb
Host smart-8ebda560-7c40-4a81-93d3-1cb9a5bc0082
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1937278497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1937278497
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1583511096
Short name T416
Test name
Test status
Simulation time 272411399 ps
CPU time 4.66 seconds
Started Jun 28 05:26:38 PM PDT 24
Finished Jun 28 05:26:43 PM PDT 24
Peak memory 201872 kb
Host smart-ff8d9628-3a9d-41b9-a6b8-c46f486970c2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583511096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1583511096
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.2821157280
Short name T659
Test name
Test status
Simulation time 198079464 ps
CPU time 3.17 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:43 PM PDT 24
Peak memory 201836 kb
Host smart-b4b227d2-193b-4a3d-9180-a2a8a5c0b962
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2821157280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2821157280
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.5580881
Short name T698
Test name
Test status
Simulation time 179687966 ps
CPU time 1.39 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:41 PM PDT 24
Peak memory 201812 kb
Host smart-2696c7dd-2dc2-42ab-94be-e10d416bc7e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5580881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.5580881
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1565023017
Short name T841
Test name
Test status
Simulation time 2002776930 ps
CPU time 10.27 seconds
Started Jun 28 05:26:56 PM PDT 24
Finished Jun 28 05:27:07 PM PDT 24
Peak memory 201908 kb
Host smart-36878a5e-307d-4d03-8425-365c1b8a6544
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565023017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1565023017
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1939244192
Short name T322
Test name
Test status
Simulation time 1435578537 ps
CPU time 8.15 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:48 PM PDT 24
Peak memory 202120 kb
Host smart-1d69f292-816b-4210-b3b8-2091f441ff25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1939244192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1939244192
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3976989280
Short name T817
Test name
Test status
Simulation time 9121939 ps
CPU time 1.16 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:41 PM PDT 24
Peak memory 201904 kb
Host smart-b0fb114a-24b7-41c6-a88e-c7128f5888fd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976989280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3976989280
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3451622603
Short name T767
Test name
Test status
Simulation time 823371441 ps
CPU time 34.44 seconds
Started Jun 28 05:26:38 PM PDT 24
Finished Jun 28 05:27:13 PM PDT 24
Peak memory 201916 kb
Host smart-f16f6c34-b54d-4c3c-a873-628af2b11298
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3451622603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3451622603
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3986655322
Short name T360
Test name
Test status
Simulation time 3395198383 ps
CPU time 38.5 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:27:20 PM PDT 24
Peak memory 202036 kb
Host smart-66e26ebf-51f9-4efe-a30c-bfe257cf5203
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3986655322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3986655322
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1427617628
Short name T805
Test name
Test status
Simulation time 2941461784 ps
CPU time 141.99 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:29:02 PM PDT 24
Peak memory 204668 kb
Host smart-4d620700-7186-43ad-b52e-4b6d23c6d340
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1427617628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.1427617628
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2288088278
Short name T451
Test name
Test status
Simulation time 49156300 ps
CPU time 2.2 seconds
Started Jun 28 05:26:41 PM PDT 24
Finished Jun 28 05:26:44 PM PDT 24
Peak memory 201964 kb
Host smart-52a7abd9-35b5-495f-8bdb-c7b70ce2eea0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2288088278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.2288088278
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.373062283
Short name T388
Test name
Test status
Simulation time 102307995 ps
CPU time 4.62 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:26:45 PM PDT 24
Peak memory 202116 kb
Host smart-2d6d4d6a-0446-4781-b348-3e703c0e6fb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373062283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.373062283
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3090530089
Short name T125
Test name
Test status
Simulation time 830060971 ps
CPU time 19.85 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:24 PM PDT 24
Peak memory 201916 kb
Host smart-c2cd9d87-1e39-4d40-afda-b6827f613566
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3090530089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3090530089
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4106958391
Short name T204
Test name
Test status
Simulation time 18518830366 ps
CPU time 114.41 seconds
Started Jun 28 05:27:06 PM PDT 24
Finished Jun 28 05:29:02 PM PDT 24
Peak memory 203092 kb
Host smart-e9051444-0320-4141-bc5b-5bd5fe88f2c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4106958391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.4106958391
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3107310035
Short name T625
Test name
Test status
Simulation time 884607060 ps
CPU time 8.88 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:16 PM PDT 24
Peak memory 201872 kb
Host smart-b736951f-c972-469d-abec-f93f62e91171
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3107310035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3107310035
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.1006096429
Short name T835
Test name
Test status
Simulation time 436068441 ps
CPU time 3.13 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:07 PM PDT 24
Peak memory 201916 kb
Host smart-35182505-2a8b-4d0b-90ea-a0ee3f0ff554
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1006096429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1006096429
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.3283688295
Short name T498
Test name
Test status
Simulation time 188537432 ps
CPU time 2.9 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:43 PM PDT 24
Peak memory 201820 kb
Host smart-cb94f891-d98d-4963-9cb9-fde1b6e13516
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3283688295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3283688295
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.409616106
Short name T520
Test name
Test status
Simulation time 122197691747 ps
CPU time 102.75 seconds
Started Jun 28 05:27:02 PM PDT 24
Finished Jun 28 05:28:45 PM PDT 24
Peak memory 201956 kb
Host smart-f8214881-a1f3-45e3-a168-e46d114d5afd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=409616106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.409616106
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2083636860
Short name T174
Test name
Test status
Simulation time 9072325560 ps
CPU time 40.18 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 202056 kb
Host smart-cd75b6ca-d2d5-4cb1-bd49-dca504da021b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2083636860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2083636860
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1724770839
Short name T880
Test name
Test status
Simulation time 45061168 ps
CPU time 6.95 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:26:47 PM PDT 24
Peak memory 201904 kb
Host smart-750c2ede-e61e-4a01-9194-ef9581bbaddb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724770839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1724770839
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.1242296410
Short name T534
Test name
Test status
Simulation time 20814446 ps
CPU time 1.74 seconds
Started Jun 28 05:27:02 PM PDT 24
Finished Jun 28 05:27:05 PM PDT 24
Peak memory 201816 kb
Host smart-1e8b3607-bc10-4889-a77a-c0b48edb1905
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1242296410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1242296410
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2670612179
Short name T333
Test name
Test status
Simulation time 12360815 ps
CPU time 1.24 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:26:42 PM PDT 24
Peak memory 201800 kb
Host smart-9d6bd988-4b16-4e24-9c3d-03b55a08a49b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2670612179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2670612179
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2662330974
Short name T893
Test name
Test status
Simulation time 2011283329 ps
CPU time 7.62 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:47 PM PDT 24
Peak memory 201888 kb
Host smart-0f182226-79d6-42e8-aa24-8c27c58f58df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662330974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2662330974
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.795017222
Short name T175
Test name
Test status
Simulation time 1628843554 ps
CPU time 6.56 seconds
Started Jun 28 05:26:40 PM PDT 24
Finished Jun 28 05:26:48 PM PDT 24
Peak memory 201944 kb
Host smart-99e484d5-e2c5-4656-af40-61e27e040ba4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=795017222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.795017222
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1634232714
Short name T691
Test name
Test status
Simulation time 15362577 ps
CPU time 1.19 seconds
Started Jun 28 05:26:39 PM PDT 24
Finished Jun 28 05:26:40 PM PDT 24
Peak memory 201904 kb
Host smart-968ec38e-b421-4274-96d7-e0814827c210
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634232714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1634232714
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2996636437
Short name T438
Test name
Test status
Simulation time 665053858 ps
CPU time 20.56 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:26 PM PDT 24
Peak memory 201860 kb
Host smart-d90dd591-c7a9-4463-887c-7cce6bf334f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2996636437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2996636437
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2637116085
Short name T475
Test name
Test status
Simulation time 383577728 ps
CPU time 35.33 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:41 PM PDT 24
Peak memory 201972 kb
Host smart-ff86da74-dbdf-4e2f-8ef4-e2bdfddff1ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2637116085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2637116085
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2183824880
Short name T182
Test name
Test status
Simulation time 454898416 ps
CPU time 48.31 seconds
Started Jun 28 05:27:06 PM PDT 24
Finished Jun 28 05:27:55 PM PDT 24
Peak memory 204216 kb
Host smart-69335404-e999-4c55-9eea-bb3f7598b013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2183824880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2183824880
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3105839939
Short name T519
Test name
Test status
Simulation time 343066667 ps
CPU time 17.67 seconds
Started Jun 28 05:27:07 PM PDT 24
Finished Jun 28 05:27:25 PM PDT 24
Peak memory 202988 kb
Host smart-b53839aa-93a8-4d8c-b6f2-9206bcf12882
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3105839939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3105839939
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.645702425
Short name T463
Test name
Test status
Simulation time 160076594 ps
CPU time 4.31 seconds
Started Jun 28 05:27:01 PM PDT 24
Finished Jun 28 05:27:06 PM PDT 24
Peak memory 201904 kb
Host smart-e07e743f-96a2-462e-ba3f-01c7bb296295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=645702425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.645702425
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2593224284
Short name T501
Test name
Test status
Simulation time 1383113890 ps
CPU time 13.65 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:20 PM PDT 24
Peak memory 201828 kb
Host smart-fd891bf9-6b93-4f37-b124-5375622b97e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2593224284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2593224284
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1423589357
Short name T689
Test name
Test status
Simulation time 47598539406 ps
CPU time 318.7 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:32:23 PM PDT 24
Peak memory 203092 kb
Host smart-2b109dcf-b4f6-4de5-bdaf-287fc4ffa183
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1423589357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.1423589357
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2694071312
Short name T794
Test name
Test status
Simulation time 2585045069 ps
CPU time 6.38 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:11 PM PDT 24
Peak memory 202024 kb
Host smart-f87e6e3a-34a5-4560-9c6b-f68c3531979a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2694071312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2694071312
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.2306955224
Short name T895
Test name
Test status
Simulation time 2253600239 ps
CPU time 12.45 seconds
Started Jun 28 05:27:07 PM PDT 24
Finished Jun 28 05:27:20 PM PDT 24
Peak memory 201976 kb
Host smart-a16fb9c2-6c70-43f4-bda0-bd1ca46b6608
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2306955224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2306955224
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.1885003911
Short name T612
Test name
Test status
Simulation time 5358939163 ps
CPU time 14.78 seconds
Started Jun 28 05:27:02 PM PDT 24
Finished Jun 28 05:27:18 PM PDT 24
Peak memory 202028 kb
Host smart-7d86bb40-e865-447a-94ef-0ea4ba3e043a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1885003911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1885003911
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4135218381
Short name T884
Test name
Test status
Simulation time 59231449203 ps
CPU time 136.99 seconds
Started Jun 28 05:27:06 PM PDT 24
Finished Jun 28 05:29:24 PM PDT 24
Peak memory 201956 kb
Host smart-7ef01c2d-38c2-4108-af09-7cbaf248a872
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135218381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4135218381
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3438207082
Short name T551
Test name
Test status
Simulation time 40670329169 ps
CPU time 139.73 seconds
Started Jun 28 05:27:02 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 202068 kb
Host smart-fca56709-f7cc-45aa-9000-6887bc8605b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3438207082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3438207082
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1506397382
Short name T578
Test name
Test status
Simulation time 166654980 ps
CPU time 6.75 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:13 PM PDT 24
Peak memory 201816 kb
Host smart-aed5ff4f-332e-4783-8e89-dca263d37849
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506397382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1506397382
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.743800183
Short name T594
Test name
Test status
Simulation time 17794742 ps
CPU time 1.51 seconds
Started Jun 28 05:27:07 PM PDT 24
Finished Jun 28 05:27:09 PM PDT 24
Peak memory 201912 kb
Host smart-b2474f64-52d4-42e2-95e8-656010a09980
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=743800183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.743800183
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.3519109208
Short name T338
Test name
Test status
Simulation time 44003638 ps
CPU time 1.48 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:06 PM PDT 24
Peak memory 201904 kb
Host smart-1c722415-04a4-4f1b-a92c-9895d8c74b7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3519109208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3519109208
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.195143374
Short name T54
Test name
Test status
Simulation time 1812872214 ps
CPU time 7.34 seconds
Started Jun 28 05:27:02 PM PDT 24
Finished Jun 28 05:27:10 PM PDT 24
Peak memory 201876 kb
Host smart-22476d1c-c832-4b1c-bb17-273034fee6bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=195143374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.195143374
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1466394632
Short name T385
Test name
Test status
Simulation time 2511590205 ps
CPU time 9.92 seconds
Started Jun 28 05:27:06 PM PDT 24
Finished Jun 28 05:27:17 PM PDT 24
Peak memory 201988 kb
Host smart-3e0c932e-962c-492f-a364-760961e74973
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1466394632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1466394632
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2257105781
Short name T598
Test name
Test status
Simulation time 14044852 ps
CPU time 1.39 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:07 PM PDT 24
Peak memory 201872 kb
Host smart-509c06e0-cc3b-4ee2-8c4f-8eae759afde5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257105781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2257105781
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2609450009
Short name T179
Test name
Test status
Simulation time 7369509731 ps
CPU time 31.46 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:36 PM PDT 24
Peak memory 203032 kb
Host smart-d2107339-f859-461b-8a3f-396e69fa79b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2609450009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2609450009
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.964863333
Short name T203
Test name
Test status
Simulation time 3329354640 ps
CPU time 56.36 seconds
Started Jun 28 05:27:06 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 201900 kb
Host smart-31e1a336-d969-4fa0-9cee-3b738db39a64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964863333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.964863333
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2442181120
Short name T523
Test name
Test status
Simulation time 73103700 ps
CPU time 6.31 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:13 PM PDT 24
Peak memory 201884 kb
Host smart-f78928ba-c3c8-4b5a-8d7a-2d3a8159b694
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2442181120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.2442181120
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4178541389
Short name T595
Test name
Test status
Simulation time 96874293 ps
CPU time 3.24 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:08 PM PDT 24
Peak memory 201960 kb
Host smart-ce916265-0213-4f8a-b924-9ca925f3691c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178541389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.4178541389
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2302156005
Short name T772
Test name
Test status
Simulation time 2874354003 ps
CPU time 11.24 seconds
Started Jun 28 05:27:01 PM PDT 24
Finished Jun 28 05:27:13 PM PDT 24
Peak memory 202136 kb
Host smart-ed1531e3-3516-464d-a85d-f121e72b31a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2302156005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2302156005
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1493581636
Short name T273
Test name
Test status
Simulation time 1983509499 ps
CPU time 13.36 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:17 PM PDT 24
Peak memory 201912 kb
Host smart-98aba1ae-b844-4d07-92db-49a899d3d47e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1493581636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1493581636
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3718733262
Short name T202
Test name
Test status
Simulation time 77305322135 ps
CPU time 184.73 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:30:11 PM PDT 24
Peak memory 203088 kb
Host smart-de3f7c50-f5a9-4748-a2d6-e07eae355ada
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3718733262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.3718733262
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3790730086
Short name T702
Test name
Test status
Simulation time 91101265 ps
CPU time 5.73 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:27:28 PM PDT 24
Peak memory 201880 kb
Host smart-9cd2ab72-e5de-4777-aad0-1db46edcb334
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3790730086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3790730086
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.301683856
Short name T818
Test name
Test status
Simulation time 42808323 ps
CPU time 2.2 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:22 PM PDT 24
Peak memory 201872 kb
Host smart-1d91269f-97c7-4067-845a-d886a58a9af6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=301683856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.301683856
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.3344468665
Short name T124
Test name
Test status
Simulation time 740476290 ps
CPU time 12.12 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:16 PM PDT 24
Peak memory 201884 kb
Host smart-efbc826e-23ac-4c2f-96af-4d27834e9a8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3344468665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3344468665
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3809037584
Short name T1
Test name
Test status
Simulation time 239729485225 ps
CPU time 178.55 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:30:03 PM PDT 24
Peak memory 202036 kb
Host smart-fb7c0abc-d84c-4c69-8b61-af3a85edbec7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809037584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3809037584
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1429209274
Short name T421
Test name
Test status
Simulation time 10606887774 ps
CPU time 43.95 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:50 PM PDT 24
Peak memory 201996 kb
Host smart-cd760b89-0752-4d61-b485-53583be64edd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1429209274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1429209274
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3586579092
Short name T401
Test name
Test status
Simulation time 43392418 ps
CPU time 6.98 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:14 PM PDT 24
Peak memory 201872 kb
Host smart-1500f2ed-675f-4199-8a1e-a08c2ec343d2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586579092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3586579092
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.3468163471
Short name T419
Test name
Test status
Simulation time 75782812 ps
CPU time 6.31 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:11 PM PDT 24
Peak memory 201912 kb
Host smart-38e38aaa-4979-4255-a3b0-4c56c13ff65f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3468163471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3468163471
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.198885191
Short name T839
Test name
Test status
Simulation time 126266877 ps
CPU time 1.43 seconds
Started Jun 28 05:27:04 PM PDT 24
Finished Jun 28 05:27:06 PM PDT 24
Peak memory 201912 kb
Host smart-c6bfd63e-eadc-4855-ba04-6a9031eced86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=198885191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.198885191
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1640138844
Short name T61
Test name
Test status
Simulation time 2531219993 ps
CPU time 8.43 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:15 PM PDT 24
Peak memory 201952 kb
Host smart-9d01d1ad-3dd8-4c93-bfa6-8f8f79f39799
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640138844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1640138844
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3507452116
Short name T442
Test name
Test status
Simulation time 2440263331 ps
CPU time 10.89 seconds
Started Jun 28 05:27:03 PM PDT 24
Finished Jun 28 05:27:15 PM PDT 24
Peak memory 202004 kb
Host smart-de0e1671-f436-4095-969d-a29913f83c35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3507452116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3507452116
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1355220451
Short name T340
Test name
Test status
Simulation time 15687029 ps
CPU time 1.22 seconds
Started Jun 28 05:27:05 PM PDT 24
Finished Jun 28 05:27:08 PM PDT 24
Peak memory 201804 kb
Host smart-b2ee4347-a0b4-4027-9758-9a4982389b0d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355220451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1355220451
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.499475846
Short name T815
Test name
Test status
Simulation time 1510219722 ps
CPU time 23.87 seconds
Started Jun 28 05:27:23 PM PDT 24
Finished Jun 28 05:27:47 PM PDT 24
Peak memory 201960 kb
Host smart-7b4d6150-02b9-429a-ae55-62ba471e654d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=499475846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.499475846
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.744118631
Short name T674
Test name
Test status
Simulation time 7029378528 ps
CPU time 100.76 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:29:00 PM PDT 24
Peak memory 203132 kb
Host smart-23f80721-02d2-43e2-beb0-129a2381fa10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=744118631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.744118631
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3414194391
Short name T740
Test name
Test status
Simulation time 744656354 ps
CPU time 108.58 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:29:11 PM PDT 24
Peak memory 206428 kb
Host smart-06fd76a9-61c0-4b9f-a388-7561597d8a2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3414194391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3414194391
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2329130403
Short name T473
Test name
Test status
Simulation time 1012150376 ps
CPU time 135.56 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 205964 kb
Host smart-b9a767e6-a6c6-42e8-b608-5b70d9a18aa8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2329130403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.2329130403
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1476267693
Short name T637
Test name
Test status
Simulation time 158066140 ps
CPU time 5.28 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:26 PM PDT 24
Peak memory 201864 kb
Host smart-fd24a518-0991-45fa-bd10-86880693ab4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1476267693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1476267693
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.206645292
Short name T897
Test name
Test status
Simulation time 184393461 ps
CPU time 8.87 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:27:31 PM PDT 24
Peak memory 201888 kb
Host smart-dd660872-dc93-466e-9e76-ecc060307d9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=206645292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.206645292
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.333102736
Short name T86
Test name
Test status
Simulation time 62898097839 ps
CPU time 81.88 seconds
Started Jun 28 05:27:17 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 202192 kb
Host smart-f2d76dda-d172-4153-aa01-3d1e416a5add
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=333102736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo
w_rsp.333102736
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3364417634
Short name T869
Test name
Test status
Simulation time 618199585 ps
CPU time 6.48 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:27 PM PDT 24
Peak memory 201968 kb
Host smart-7d67ffc4-147a-40b4-ac48-f6cd9de8d1c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364417634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3364417634
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2054492601
Short name T693
Test name
Test status
Simulation time 1227282903 ps
CPU time 9.94 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:31 PM PDT 24
Peak memory 201840 kb
Host smart-7579bec7-52cc-4326-b5cc-93d64079657a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2054492601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2054492601
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3777975308
Short name T236
Test name
Test status
Simulation time 1024466986 ps
CPU time 15.73 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:34 PM PDT 24
Peak memory 201804 kb
Host smart-adb6cab3-7132-4d24-ba4f-74371fe53e79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3777975308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3777975308
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.2262623903
Short name T190
Test name
Test status
Simulation time 27363073152 ps
CPU time 109.5 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:29:12 PM PDT 24
Peak memory 202004 kb
Host smart-b345125d-27d8-4744-a7a1-05abc87de62e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262623903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2262623903
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2820443394
Short name T694
Test name
Test status
Simulation time 14335722954 ps
CPU time 23.54 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:42 PM PDT 24
Peak memory 202048 kb
Host smart-c057a77a-59df-4339-b0fb-9c7d651d739c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2820443394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2820443394
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3305537217
Short name T862
Test name
Test status
Simulation time 18697211 ps
CPU time 2.47 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:22 PM PDT 24
Peak memory 201868 kb
Host smart-9707c9e6-d67f-4c6e-95c7-8402645f6065
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305537217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3305537217
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.948940903
Short name T235
Test name
Test status
Simulation time 645125272 ps
CPU time 10.04 seconds
Started Jun 28 05:27:23 PM PDT 24
Finished Jun 28 05:27:34 PM PDT 24
Peak memory 201916 kb
Host smart-b783b5fd-07e8-4fce-b3d6-835e53b18bd3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=948940903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.948940903
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.1997874631
Short name T583
Test name
Test status
Simulation time 54373987 ps
CPU time 1.49 seconds
Started Jun 28 05:27:17 PM PDT 24
Finished Jun 28 05:27:19 PM PDT 24
Peak memory 201900 kb
Host smart-ab919003-82be-4d60-ade8-b8995f69c458
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1997874631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1997874631
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1121392728
Short name T337
Test name
Test status
Simulation time 3956090796 ps
CPU time 11.07 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:33 PM PDT 24
Peak memory 201888 kb
Host smart-d8e42f18-518f-4b7f-823b-0df7979fb7c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121392728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1121392728
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3706760827
Short name T781
Test name
Test status
Simulation time 757744804 ps
CPU time 5.07 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:24 PM PDT 24
Peak memory 201944 kb
Host smart-01a6deb4-0cbb-4595-b314-7bcb92df0928
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3706760827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3706760827
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3837585999
Short name T882
Test name
Test status
Simulation time 17523084 ps
CPU time 1.15 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:21 PM PDT 24
Peak memory 201904 kb
Host smart-7de423cf-e23d-46cd-88ae-3078b654452b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837585999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3837585999
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2007672240
Short name T414
Test name
Test status
Simulation time 430742701 ps
CPU time 50.52 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:28:12 PM PDT 24
Peak memory 202940 kb
Host smart-5fb38090-2c66-4880-a8da-49a3128fc08e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2007672240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2007672240
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3727746302
Short name T392
Test name
Test status
Simulation time 4752343328 ps
CPU time 44.03 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 202028 kb
Host smart-eaad4d39-d900-4493-ad1b-e07fd344c549
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3727746302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3727746302
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.59938887
Short name T224
Test name
Test status
Simulation time 510372782 ps
CPU time 38.13 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:28:00 PM PDT 24
Peak memory 203984 kb
Host smart-d436b174-1143-4ec8-b8c6-2d3caf42b017
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59938887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rese
t_error.59938887
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.414492072
Short name T509
Test name
Test status
Simulation time 49174677 ps
CPU time 1.85 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:23 PM PDT 24
Peak memory 201832 kb
Host smart-58883d6e-6a04-44c7-b234-07d7edaa6dc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=414492072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.414492072
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2267375569
Short name T88
Test name
Test status
Simulation time 845572041 ps
CPU time 20.91 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:42 PM PDT 24
Peak memory 201920 kb
Host smart-85f9c41c-b577-43ca-b215-46c0985a328a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2267375569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2267375569
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2322336924
Short name T209
Test name
Test status
Simulation time 20623231103 ps
CPU time 146.37 seconds
Started Jun 28 05:27:23 PM PDT 24
Finished Jun 28 05:29:49 PM PDT 24
Peak memory 203096 kb
Host smart-5cb64f19-abe5-4a38-8754-cc20c4006df3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2322336924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.2322336924
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.582982651
Short name T778
Test name
Test status
Simulation time 33855726 ps
CPU time 3.83 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:23 PM PDT 24
Peak memory 201944 kb
Host smart-1c4e3620-1679-40ca-ab3f-0e5bbc9eb774
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=582982651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.582982651
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.2577734242
Short name T308
Test name
Test status
Simulation time 374398752 ps
CPU time 5.22 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:27 PM PDT 24
Peak memory 201888 kb
Host smart-d60c088a-0534-4da7-bdd5-dba9d9046f30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2577734242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2577734242
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.2953167406
Short name T622
Test name
Test status
Simulation time 67300991 ps
CPU time 7.72 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:28 PM PDT 24
Peak memory 201852 kb
Host smart-ab603b13-b3e7-4610-bfd0-7236102f82c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2953167406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2953167406
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3511167275
Short name T101
Test name
Test status
Simulation time 33096448108 ps
CPU time 149.53 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:29:51 PM PDT 24
Peak memory 201940 kb
Host smart-931cbdc1-2552-4f6f-b194-12fe50486682
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511167275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3511167275
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4143728295
Short name T361
Test name
Test status
Simulation time 16334718722 ps
CPU time 82.31 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:28:41 PM PDT 24
Peak memory 202064 kb
Host smart-71703d4c-afc5-498f-86fc-13b3711ab608
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4143728295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4143728295
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.272108100
Short name T244
Test name
Test status
Simulation time 68287498 ps
CPU time 9.75 seconds
Started Jun 28 05:27:23 PM PDT 24
Finished Jun 28 05:27:33 PM PDT 24
Peak memory 201876 kb
Host smart-861349c3-37f4-49a7-b994-0930a2b28b14
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272108100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.272108100
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.1960641636
Short name T287
Test name
Test status
Simulation time 49566435 ps
CPU time 2.92 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:23 PM PDT 24
Peak memory 201880 kb
Host smart-d58bc1b1-fd97-4165-a043-27c0a786c754
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960641636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1960641636
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.3575556099
Short name T254
Test name
Test status
Simulation time 47380917 ps
CPU time 1.48 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:23 PM PDT 24
Peak memory 201900 kb
Host smart-acd7b32a-9030-4056-95ad-7a2cff082e57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575556099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3575556099
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1266059602
Short name T167
Test name
Test status
Simulation time 4550064962 ps
CPU time 9.69 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:32 PM PDT 24
Peak memory 202032 kb
Host smart-6f7c5cc2-8c5a-48f2-b6f1-c89e88a74d2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266059602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1266059602
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3966880814
Short name T295
Test name
Test status
Simulation time 4892271948 ps
CPU time 7.05 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:27 PM PDT 24
Peak memory 202276 kb
Host smart-024806c6-13b4-4a6e-87fd-fd8658258d02
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3966880814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3966880814
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3560877153
Short name T353
Test name
Test status
Simulation time 10248274 ps
CPU time 1.1 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:21 PM PDT 24
Peak memory 201900 kb
Host smart-35b9db61-e97f-4277-b6b3-d4670dcd2c17
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560877153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3560877153
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4151172554
Short name T247
Test name
Test status
Simulation time 251591911 ps
CPU time 28.52 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:47 PM PDT 24
Peak memory 202932 kb
Host smart-074cc399-c14c-4bd6-9032-0856504b40d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151172554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4151172554
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.21990841
Short name T420
Test name
Test status
Simulation time 1583726290 ps
CPU time 26.79 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:48 PM PDT 24
Peak memory 201912 kb
Host smart-c4b81e56-2540-4f04-aa1b-2c6ad219e7f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21990841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.21990841
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.382114558
Short name T525
Test name
Test status
Simulation time 304627408 ps
CPU time 62.8 seconds
Started Jun 28 05:27:22 PM PDT 24
Finished Jun 28 05:28:26 PM PDT 24
Peak memory 204248 kb
Host smart-7b5b4a87-191a-4326-a367-21874a092473
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=382114558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.382114558
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.4156626664
Short name T144
Test name
Test status
Simulation time 4145103541 ps
CPU time 38.1 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:59 PM PDT 24
Peak memory 203040 kb
Host smart-23d0f3ef-7fa7-4182-b0a6-842c173c5074
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4156626664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.4156626664
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3817395690
Short name T310
Test name
Test status
Simulation time 1169087449 ps
CPU time 7.44 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:27:30 PM PDT 24
Peak memory 201912 kb
Host smart-2fe3ae70-100d-435f-84c8-d83f3c4e4d95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3817395690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3817395690
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3147304520
Short name T467
Test name
Test status
Simulation time 51020553 ps
CPU time 4.93 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:27:35 PM PDT 24
Peak memory 201908 kb
Host smart-df9bfdd8-75a7-4cf0-8264-5abc8f013ee7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3147304520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3147304520
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2864936574
Short name T196
Test name
Test status
Simulation time 139998745096 ps
CPU time 281.92 seconds
Started Jun 28 05:27:46 PM PDT 24
Finished Jun 28 05:32:29 PM PDT 24
Peak memory 203072 kb
Host smart-606755f5-d2a8-4632-897f-d0bb091d6613
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2864936574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2864936574
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3554828914
Short name T735
Test name
Test status
Simulation time 28332567 ps
CPU time 2.64 seconds
Started Jun 28 05:27:28 PM PDT 24
Finished Jun 28 05:27:32 PM PDT 24
Peak memory 201972 kb
Host smart-efa78658-f5df-4c4e-977c-b3ffac6f3a34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3554828914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3554828914
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.4137363690
Short name T172
Test name
Test status
Simulation time 995249307 ps
CPU time 13.87 seconds
Started Jun 28 05:27:32 PM PDT 24
Finished Jun 28 05:27:47 PM PDT 24
Peak memory 201820 kb
Host smart-196343df-7fbe-4ec9-b8e2-ea8acbef2e51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4137363690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4137363690
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.2193110442
Short name T300
Test name
Test status
Simulation time 1725045407 ps
CPU time 4.61 seconds
Started Jun 28 05:27:17 PM PDT 24
Finished Jun 28 05:27:22 PM PDT 24
Peak memory 201908 kb
Host smart-2adcac74-a397-4a3b-8647-ebd13518f923
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193110442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2193110442
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.578423728
Short name T320
Test name
Test status
Simulation time 46229615401 ps
CPU time 60.35 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:28:32 PM PDT 24
Peak memory 201976 kb
Host smart-0ecac490-35f9-46a9-9c0d-bf71e095efa1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=578423728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.578423728
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4068736950
Short name T219
Test name
Test status
Simulation time 19057195293 ps
CPU time 107.27 seconds
Started Jun 28 05:27:31 PM PDT 24
Finished Jun 28 05:29:20 PM PDT 24
Peak memory 202068 kb
Host smart-7c964067-9d4c-46ea-8a3c-c9386c3c24f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4068736950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4068736950
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2864960995
Short name T243
Test name
Test status
Simulation time 148541358 ps
CPU time 3.14 seconds
Started Jun 28 05:27:32 PM PDT 24
Finished Jun 28 05:27:36 PM PDT 24
Peak memory 201800 kb
Host smart-0b9e5bf3-f081-43cb-948a-52ca10f76ce1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864960995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2864960995
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.2769075880
Short name T514
Test name
Test status
Simulation time 75285465 ps
CPU time 1.64 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:27:49 PM PDT 24
Peak memory 201896 kb
Host smart-532f961f-f9f9-4f28-8594-ae2c46704d3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2769075880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2769075880
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.3632177127
Short name T17
Test name
Test status
Simulation time 22814129 ps
CPU time 1.28 seconds
Started Jun 28 05:27:19 PM PDT 24
Finished Jun 28 05:27:22 PM PDT 24
Peak memory 201804 kb
Host smart-d006ed20-5b8b-41d7-9cd3-855cf4a23f25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3632177127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3632177127
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3821783851
Short name T857
Test name
Test status
Simulation time 3212832443 ps
CPU time 7.9 seconds
Started Jun 28 05:27:18 PM PDT 24
Finished Jun 28 05:27:26 PM PDT 24
Peak memory 201920 kb
Host smart-d6117315-2a87-47f0-9b7e-313842ca0427
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821783851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3821783851
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1051392687
Short name T431
Test name
Test status
Simulation time 1516172993 ps
CPU time 6.79 seconds
Started Jun 28 05:27:20 PM PDT 24
Finished Jun 28 05:27:28 PM PDT 24
Peak memory 201876 kb
Host smart-a401db55-b0b2-4c39-b066-95ee5317c9a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1051392687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1051392687
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1088821675
Short name T682
Test name
Test status
Simulation time 10013311 ps
CPU time 1.11 seconds
Started Jun 28 05:27:21 PM PDT 24
Finished Jun 28 05:27:23 PM PDT 24
Peak memory 201900 kb
Host smart-dfe0cb12-2f8a-4581-bb77-58f58f745a58
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088821675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1088821675
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3364738602
Short name T733
Test name
Test status
Simulation time 272627881 ps
CPU time 19.04 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:27:49 PM PDT 24
Peak memory 201912 kb
Host smart-2fcc0caa-bfcc-4dfc-bb50-c3f0cc325644
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364738602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3364738602
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3387189668
Short name T5
Test name
Test status
Simulation time 5605821656 ps
CPU time 77.23 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:28:47 PM PDT 24
Peak memory 203112 kb
Host smart-c66b32b3-6073-4d21-8be6-13addc3e9ab6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3387189668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3387189668
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3127459423
Short name T565
Test name
Test status
Simulation time 705461589 ps
CPU time 66.17 seconds
Started Jun 28 05:27:31 PM PDT 24
Finished Jun 28 05:28:38 PM PDT 24
Peak memory 204332 kb
Host smart-a1aea26f-f08a-40fc-885f-e560505fb1fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3127459423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.3127459423
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3087059050
Short name T472
Test name
Test status
Simulation time 60288195 ps
CPU time 7.7 seconds
Started Jun 28 05:27:28 PM PDT 24
Finished Jun 28 05:27:37 PM PDT 24
Peak memory 201908 kb
Host smart-df339fd1-0fa3-4949-9b9a-a1005976ecef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087059050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3087059050
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.111330866
Short name T790
Test name
Test status
Simulation time 3663435608 ps
CPU time 12.31 seconds
Started Jun 28 05:27:31 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 201892 kb
Host smart-eb63d037-53ee-4d39-9cac-37e2fba0b0ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111330866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.111330866
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3438944964
Short name T215
Test name
Test status
Simulation time 118902809242 ps
CPU time 215.64 seconds
Started Jun 28 05:27:27 PM PDT 24
Finished Jun 28 05:31:03 PM PDT 24
Peak memory 203016 kb
Host smart-10c9040a-1b22-40d6-b3d2-0b57f92b5b5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3438944964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.3438944964
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.542691083
Short name T446
Test name
Test status
Simulation time 222269213 ps
CPU time 5.02 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:27:36 PM PDT 24
Peak memory 201960 kb
Host smart-54f16929-969e-4c92-bb03-37eda3c7a898
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=542691083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.542691083
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.4158661906
Short name T749
Test name
Test status
Simulation time 115209934 ps
CPU time 8.74 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:27:39 PM PDT 24
Peak memory 201900 kb
Host smart-fd89df35-62f0-4bf5-8dac-74d156470b52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4158661906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4158661906
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.56626402
Short name T290
Test name
Test status
Simulation time 161140257 ps
CPU time 3.03 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:27:50 PM PDT 24
Peak memory 201900 kb
Host smart-f90040e9-77b6-44f7-a642-78f50105df3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56626402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.56626402
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3550226796
Short name T294
Test name
Test status
Simulation time 4244928493 ps
CPU time 12.47 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:27:43 PM PDT 24
Peak memory 201976 kb
Host smart-1b4edb2a-119e-4836-ae4e-c5b38754e970
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550226796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3550226796
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2007080537
Short name T396
Test name
Test status
Simulation time 7233792162 ps
CPU time 51.86 seconds
Started Jun 28 05:27:28 PM PDT 24
Finished Jun 28 05:28:21 PM PDT 24
Peak memory 202048 kb
Host smart-a91e22ae-ba59-44ef-86c4-1fc15d153820
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2007080537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2007080537
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2490920137
Short name T556
Test name
Test status
Simulation time 147631209 ps
CPU time 10.18 seconds
Started Jun 28 05:27:33 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 201804 kb
Host smart-06a6d91c-deac-4d93-9ab5-22ba7d4c8934
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490920137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2490920137
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1567708635
Short name T304
Test name
Test status
Simulation time 589360149 ps
CPU time 7.49 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:27:37 PM PDT 24
Peak memory 201896 kb
Host smart-8c217f5a-62fd-462d-9b21-a3b5224f6c6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1567708635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1567708635
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.4259826123
Short name T131
Test name
Test status
Simulation time 75593048 ps
CPU time 1.9 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:27:32 PM PDT 24
Peak memory 201904 kb
Host smart-d6cc2f49-e74c-40c1-8f25-3d8b70a6b58f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4259826123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4259826123
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3113226507
Short name T527
Test name
Test status
Simulation time 1516550628 ps
CPU time 7.7 seconds
Started Jun 28 05:27:29 PM PDT 24
Finished Jun 28 05:27:38 PM PDT 24
Peak memory 201816 kb
Host smart-405f2a4f-22b4-4913-afca-e8966b57c5cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113226507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3113226507
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2949351197
Short name T231
Test name
Test status
Simulation time 2039090033 ps
CPU time 11.18 seconds
Started Jun 28 05:27:32 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 201852 kb
Host smart-029ae277-5f10-4c16-9073-a90f83b31bb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2949351197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2949351197
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2772268701
Short name T819
Test name
Test status
Simulation time 14732647 ps
CPU time 1.14 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:27:32 PM PDT 24
Peak memory 201900 kb
Host smart-2d51b83c-ad1f-4e47-8417-fbdb91d2351e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772268701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2772268701
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.710428222
Short name T695
Test name
Test status
Simulation time 1009191705 ps
CPU time 19.92 seconds
Started Jun 28 05:27:32 PM PDT 24
Finished Jun 28 05:27:53 PM PDT 24
Peak memory 201900 kb
Host smart-5befaf5f-945a-4e0a-bbb0-fe315b7bdd60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=710428222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.710428222
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1968501326
Short name T808
Test name
Test status
Simulation time 25699359260 ps
CPU time 63.9 seconds
Started Jun 28 05:27:32 PM PDT 24
Finished Jun 28 05:28:37 PM PDT 24
Peak memory 202976 kb
Host smart-95cd3534-31ac-435e-b9ff-2f1481eb707e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1968501326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1968501326
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1329423567
Short name T713
Test name
Test status
Simulation time 1403271038 ps
CPU time 106.76 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:29:17 PM PDT 24
Peak memory 204680 kb
Host smart-61f0d52d-5a5b-48c2-8336-6df4240f216c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1329423567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1329423567
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.404723361
Short name T573
Test name
Test status
Simulation time 60027514 ps
CPU time 5.78 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:27:37 PM PDT 24
Peak memory 202116 kb
Host smart-90dfd64a-afc4-4549-9af6-8b4810cf76c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=404723361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.404723361
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2003688279
Short name T466
Test name
Test status
Simulation time 120365050 ps
CPU time 9.43 seconds
Started Jun 28 05:23:42 PM PDT 24
Finished Jun 28 05:23:52 PM PDT 24
Peak memory 201912 kb
Host smart-d69b9cfe-2412-426a-af23-4fc8926d025b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2003688279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2003688279
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3323224794
Short name T218
Test name
Test status
Simulation time 29739055558 ps
CPU time 233.08 seconds
Started Jun 28 05:24:00 PM PDT 24
Finished Jun 28 05:27:54 PM PDT 24
Peak memory 203072 kb
Host smart-7878bdf9-712a-4047-b118-2a178973b86b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3323224794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.3323224794
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.735003909
Short name T660
Test name
Test status
Simulation time 79482407 ps
CPU time 4.73 seconds
Started Jun 28 05:23:47 PM PDT 24
Finished Jun 28 05:23:52 PM PDT 24
Peak memory 201896 kb
Host smart-f49a36a3-7470-43f3-a42f-9871c933cff6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=735003909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.735003909
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.2874802918
Short name T647
Test name
Test status
Simulation time 1091698567 ps
CPU time 14.94 seconds
Started Jun 28 05:23:41 PM PDT 24
Finished Jun 28 05:23:57 PM PDT 24
Peak memory 201920 kb
Host smart-61e09624-8ba0-4166-b013-91ad55550806
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2874802918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2874802918
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.2047367650
Short name T596
Test name
Test status
Simulation time 3204061345 ps
CPU time 7.82 seconds
Started Jun 28 05:23:50 PM PDT 24
Finished Jun 28 05:23:58 PM PDT 24
Peak memory 201944 kb
Host smart-1f425234-9b26-4f9e-ad44-eb2f05677204
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2047367650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2047367650
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1214985754
Short name T252
Test name
Test status
Simulation time 11599370440 ps
CPU time 32.38 seconds
Started Jun 28 05:23:48 PM PDT 24
Finished Jun 28 05:24:21 PM PDT 24
Peak memory 202012 kb
Host smart-474beff8-0ae3-426e-a027-938e5d0ae3f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214985754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1214985754
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2007079278
Short name T579
Test name
Test status
Simulation time 8912080695 ps
CPU time 50.24 seconds
Started Jun 28 05:23:39 PM PDT 24
Finished Jun 28 05:24:30 PM PDT 24
Peak memory 202068 kb
Host smart-ea6d21f6-27c4-429f-b200-a1389bd9e2eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2007079278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2007079278
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1894089392
Short name T655
Test name
Test status
Simulation time 68350328 ps
CPU time 6.36 seconds
Started Jun 28 05:23:48 PM PDT 24
Finished Jun 28 05:23:55 PM PDT 24
Peak memory 201808 kb
Host smart-2c58b41b-d268-474e-aea2-be70c8eaae67
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894089392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1894089392
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.1674670123
Short name T799
Test name
Test status
Simulation time 1653713244 ps
CPU time 7.58 seconds
Started Jun 28 05:23:41 PM PDT 24
Finished Jun 28 05:23:49 PM PDT 24
Peak memory 201916 kb
Host smart-2153f091-dfb1-4ec9-982b-d1e4c0650700
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1674670123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1674670123
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.212018578
Short name T471
Test name
Test status
Simulation time 101491267 ps
CPU time 1.68 seconds
Started Jun 28 05:23:29 PM PDT 24
Finished Jun 28 05:23:31 PM PDT 24
Peak memory 201824 kb
Host smart-9931f683-e5cd-423e-9f69-c79d1f13b240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=212018578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.212018578
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.722584361
Short name T271
Test name
Test status
Simulation time 2132899071 ps
CPU time 6.77 seconds
Started Jun 28 05:23:40 PM PDT 24
Finished Jun 28 05:23:47 PM PDT 24
Peak memory 201876 kb
Host smart-540b362e-88e1-4269-bbba-a0a46b5f7769
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=722584361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.722584361
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.445180391
Short name T892
Test name
Test status
Simulation time 1800729336 ps
CPU time 6.84 seconds
Started Jun 28 05:23:48 PM PDT 24
Finished Jun 28 05:23:55 PM PDT 24
Peak memory 201944 kb
Host smart-92875818-0fbd-4158-8af5-b745a24f9e34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=445180391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.445180391
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3902807763
Short name T864
Test name
Test status
Simulation time 15099320 ps
CPU time 1.43 seconds
Started Jun 28 05:23:28 PM PDT 24
Finished Jun 28 05:23:30 PM PDT 24
Peak memory 201864 kb
Host smart-98b0b4cf-544c-4f1a-951a-ed7d05a5e736
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902807763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3902807763
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.32906907
Short name T487
Test name
Test status
Simulation time 752506790 ps
CPU time 12.31 seconds
Started Jun 28 05:23:50 PM PDT 24
Finished Jun 28 05:24:02 PM PDT 24
Peak memory 201884 kb
Host smart-b8d977f5-5ea6-48ed-b0f7-8a145e8c8bb0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32906907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.32906907
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1356010010
Short name T317
Test name
Test status
Simulation time 6932895320 ps
CPU time 54.65 seconds
Started Jun 28 05:23:40 PM PDT 24
Finished Jun 28 05:24:35 PM PDT 24
Peak memory 203092 kb
Host smart-8a5ac33f-3c1b-40a6-9619-d3548b6c4fe0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1356010010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1356010010
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3326236025
Short name T69
Test name
Test status
Simulation time 6512589463 ps
CPU time 141.47 seconds
Started Jun 28 05:23:40 PM PDT 24
Finished Jun 28 05:26:03 PM PDT 24
Peak memory 206264 kb
Host smart-85016fdd-2976-497d-9011-af0b8797b6fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3326236025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.3326236025
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4233388143
Short name T639
Test name
Test status
Simulation time 2698746783 ps
CPU time 131.65 seconds
Started Jun 28 05:23:40 PM PDT 24
Finished Jun 28 05:25:52 PM PDT 24
Peak memory 207232 kb
Host smart-0fe56785-6702-4424-a54c-fcd1cad84b8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4233388143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.4233388143
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.838529827
Short name T626
Test name
Test status
Simulation time 395414417 ps
CPU time 8.7 seconds
Started Jun 28 05:23:47 PM PDT 24
Finished Jun 28 05:23:56 PM PDT 24
Peak memory 201912 kb
Host smart-5fa9182b-162a-4c5e-b337-e0528a0f30e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=838529827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.838529827
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2075378938
Short name T309
Test name
Test status
Simulation time 51040397 ps
CPU time 7.44 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:27:54 PM PDT 24
Peak memory 201896 kb
Host smart-efaad822-fea3-4045-a029-67c012d0af59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2075378938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2075378938
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.798403534
Short name T208
Test name
Test status
Simulation time 353396934161 ps
CPU time 401.35 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:34:28 PM PDT 24
Peak memory 204944 kb
Host smart-11106ddd-8b19-4ee6-8230-f557bfdff5b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=798403534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo
w_rsp.798403534
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.4048315271
Short name T445
Test name
Test status
Simulation time 54729018 ps
CPU time 2.15 seconds
Started Jun 28 05:27:43 PM PDT 24
Finished Jun 28 05:27:46 PM PDT 24
Peak memory 201952 kb
Host smart-82befae0-9e58-4964-8366-656e51a63b66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048315271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.4048315271
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.2610022402
Short name T318
Test name
Test status
Simulation time 323721912 ps
CPU time 4.96 seconds
Started Jun 28 05:27:43 PM PDT 24
Finished Jun 28 05:27:49 PM PDT 24
Peak memory 201892 kb
Host smart-53330f7b-69a2-4d00-bdb7-aa87adc9e644
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2610022402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2610022402
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.427996608
Short name T831
Test name
Test status
Simulation time 5145529069 ps
CPU time 11.75 seconds
Started Jun 28 05:27:31 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 202036 kb
Host smart-d7c19753-0112-4139-8518-f97db082b916
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=427996608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.427996608
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3429600937
Short name T507
Test name
Test status
Simulation time 195889111375 ps
CPU time 157.13 seconds
Started Jun 28 05:27:32 PM PDT 24
Finished Jun 28 05:30:10 PM PDT 24
Peak memory 202032 kb
Host smart-79135cf3-bba1-47fb-8861-50c351aa62b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429600937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3429600937
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1271171238
Short name T113
Test name
Test status
Simulation time 14992255392 ps
CPU time 49.67 seconds
Started Jun 28 05:27:28 PM PDT 24
Finished Jun 28 05:28:19 PM PDT 24
Peak memory 202068 kb
Host smart-67af6f01-512c-4c37-bae1-73e6789836a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1271171238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1271171238
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1570256153
Short name T47
Test name
Test status
Simulation time 48683621 ps
CPU time 5.6 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:27:52 PM PDT 24
Peak memory 201884 kb
Host smart-4d99d949-a32d-4ad5-9a24-1f585e9b30d3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570256153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1570256153
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.804420395
Short name T898
Test name
Test status
Simulation time 793979266 ps
CPU time 6.8 seconds
Started Jun 28 05:27:34 PM PDT 24
Finished Jun 28 05:27:41 PM PDT 24
Peak memory 201888 kb
Host smart-ac7d00e0-e19a-4d72-a18f-e6b4c5d205c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=804420395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.804420395
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.1799137852
Short name T18
Test name
Test status
Simulation time 14946457 ps
CPU time 1.51 seconds
Started Jun 28 05:27:30 PM PDT 24
Finished Jun 28 05:27:32 PM PDT 24
Peak memory 202064 kb
Host smart-83ce3eb7-f296-4974-b2cf-a1773c5448e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799137852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1799137852
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.4179381803
Short name T550
Test name
Test status
Simulation time 3272935720 ps
CPU time 9.58 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:27:56 PM PDT 24
Peak memory 201944 kb
Host smart-5737b14e-bb95-4e8a-9c27-64ec1b395e22
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179381803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4179381803
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3011940206
Short name T521
Test name
Test status
Simulation time 1290660191 ps
CPU time 6.79 seconds
Started Jun 28 05:27:31 PM PDT 24
Finished Jun 28 05:27:38 PM PDT 24
Peak memory 201944 kb
Host smart-7f797b82-a56e-4da7-9acf-863c21f8fa57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3011940206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3011940206
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2690717175
Short name T607
Test name
Test status
Simulation time 9342447 ps
CPU time 1.14 seconds
Started Jun 28 05:27:45 PM PDT 24
Finished Jun 28 05:27:48 PM PDT 24
Peak memory 201884 kb
Host smart-b46d81e8-c02c-4632-92bc-295dd6f16fe6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690717175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2690717175
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1623816036
Short name T398
Test name
Test status
Simulation time 2618087657 ps
CPU time 52.13 seconds
Started Jun 28 05:27:41 PM PDT 24
Finished Jun 28 05:28:34 PM PDT 24
Peak memory 203220 kb
Host smart-0ec63443-6a2f-4f1f-b570-b38aaf234a5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1623816036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1623816036
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3473936490
Short name T759
Test name
Test status
Simulation time 3693563333 ps
CPU time 53.62 seconds
Started Jun 28 05:27:46 PM PDT 24
Finished Jun 28 05:28:41 PM PDT 24
Peak memory 202032 kb
Host smart-2bb0d1aa-ebd0-4da1-984f-e10e230eb4d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3473936490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3473936490
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1189196550
Short name T71
Test name
Test status
Simulation time 167476746 ps
CPU time 18.21 seconds
Started Jun 28 05:27:40 PM PDT 24
Finished Jun 28 05:27:59 PM PDT 24
Peak memory 202988 kb
Host smart-939b7dda-f68e-4de4-9454-96d00f7e254d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1189196550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.1189196550
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2687323782
Short name T697
Test name
Test status
Simulation time 326604301 ps
CPU time 35.4 seconds
Started Jun 28 05:27:41 PM PDT 24
Finished Jun 28 05:28:17 PM PDT 24
Peak memory 203980 kb
Host smart-eca18298-6d4d-492c-97fc-6284ac6707b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2687323782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.2687323782
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2655938803
Short name T391
Test name
Test status
Simulation time 74428336 ps
CPU time 2.6 seconds
Started Jun 28 05:27:41 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 201908 kb
Host smart-04b28c6a-9e01-4749-97c0-42bbfc7f2715
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2655938803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2655938803
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3738036667
Short name T651
Test name
Test status
Simulation time 20190503 ps
CPU time 1.3 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:27:57 PM PDT 24
Peak memory 201896 kb
Host smart-03123381-ac90-4a05-8e43-1289857731c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3738036667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3738036667
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3034103238
Short name T207
Test name
Test status
Simulation time 70770475189 ps
CPU time 347.6 seconds
Started Jun 28 05:27:55 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 204108 kb
Host smart-5d8ad742-2c85-4fbe-989a-b7aebda761f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3034103238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.3034103238
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1826768973
Short name T621
Test name
Test status
Simulation time 164306234 ps
CPU time 3.53 seconds
Started Jun 28 05:27:53 PM PDT 24
Finished Jun 28 05:27:58 PM PDT 24
Peak memory 201968 kb
Host smart-601bc77b-1998-4b70-8c6d-71dd8ef25a54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1826768973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1826768973
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.3555448943
Short name T241
Test name
Test status
Simulation time 614073078 ps
CPU time 6.47 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:28:01 PM PDT 24
Peak memory 201916 kb
Host smart-ee3cc987-e2d6-46a2-8d55-1ac412aa22b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3555448943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3555448943
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.873474555
Short name T33
Test name
Test status
Simulation time 422321659 ps
CPU time 7.67 seconds
Started Jun 28 05:27:41 PM PDT 24
Finished Jun 28 05:27:49 PM PDT 24
Peak memory 201908 kb
Host smart-532dcf3b-3a7b-4f6e-b653-bd8be4370e8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873474555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.873474555
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.4092600024
Short name T846
Test name
Test status
Simulation time 53865452840 ps
CPU time 151.19 seconds
Started Jun 28 05:27:46 PM PDT 24
Finished Jun 28 05:30:19 PM PDT 24
Peak memory 202040 kb
Host smart-797c6d5a-a2e9-4762-9bdc-ff0696a33c5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092600024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4092600024
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4190011384
Short name T849
Test name
Test status
Simulation time 42868209276 ps
CPU time 110.84 seconds
Started Jun 28 05:27:46 PM PDT 24
Finished Jun 28 05:29:38 PM PDT 24
Peak memory 202068 kb
Host smart-ce0cf6e0-8575-4bf4-bd02-0b2b5cd904d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4190011384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.4190011384
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3447308939
Short name T858
Test name
Test status
Simulation time 25334044 ps
CPU time 2.99 seconds
Started Jun 28 05:27:47 PM PDT 24
Finished Jun 28 05:27:51 PM PDT 24
Peak memory 201900 kb
Host smart-0f22bcb4-16a7-411e-9542-b81483b0042d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447308939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3447308939
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.2913286134
Short name T822
Test name
Test status
Simulation time 115143245 ps
CPU time 3.66 seconds
Started Jun 28 05:28:00 PM PDT 24
Finished Jun 28 05:28:04 PM PDT 24
Peak memory 201896 kb
Host smart-0bd6f413-8c48-464e-802e-680385c7df80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2913286134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2913286134
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.1884585593
Short name T344
Test name
Test status
Simulation time 31185027 ps
CPU time 1.21 seconds
Started Jun 28 05:27:42 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 201900 kb
Host smart-b8c5bd13-c36d-43f6-a81d-e202733cff2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1884585593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1884585593
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1986087062
Short name T355
Test name
Test status
Simulation time 13586049252 ps
CPU time 12.65 seconds
Started Jun 28 05:27:46 PM PDT 24
Finished Jun 28 05:28:00 PM PDT 24
Peak memory 202032 kb
Host smart-f666bbff-5845-4d2e-ad3f-8e73ddf1f569
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986087062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1986087062
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.858869396
Short name T260
Test name
Test status
Simulation time 930687299 ps
CPU time 6.18 seconds
Started Jun 28 05:27:41 PM PDT 24
Finished Jun 28 05:27:48 PM PDT 24
Peak memory 201852 kb
Host smart-ab21bc4b-8919-4baf-88f0-895149506e24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=858869396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.858869396
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3523488810
Short name T48
Test name
Test status
Simulation time 8448681 ps
CPU time 1.11 seconds
Started Jun 28 05:27:42 PM PDT 24
Finished Jun 28 05:27:44 PM PDT 24
Peak memory 201888 kb
Host smart-0e2ddd99-f11e-4be9-a262-86bcbba0fbed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523488810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3523488810
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1419765082
Short name T46
Test name
Test status
Simulation time 193402621 ps
CPU time 15.89 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:28:11 PM PDT 24
Peak memory 201920 kb
Host smart-423cd705-7ac1-4bfe-b7e8-3c35ae9228c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1419765082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1419765082
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2516544956
Short name T330
Test name
Test status
Simulation time 229212113 ps
CPU time 25.94 seconds
Started Jun 28 05:27:53 PM PDT 24
Finished Jun 28 05:28:20 PM PDT 24
Peak memory 201956 kb
Host smart-1d0c8a17-30c3-4efc-aac9-30b4712a5231
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2516544956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2516544956
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3809242371
Short name T773
Test name
Test status
Simulation time 5536739929 ps
CPU time 123.17 seconds
Started Jun 28 05:27:53 PM PDT 24
Finished Jun 28 05:29:58 PM PDT 24
Peak memory 205732 kb
Host smart-40fdd77d-8fa1-45a9-8cb4-bd667a13df47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3809242371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.3809242371
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4020121133
Short name T276
Test name
Test status
Simulation time 12247823981 ps
CPU time 205.79 seconds
Started Jun 28 05:27:55 PM PDT 24
Finished Jun 28 05:31:22 PM PDT 24
Peak memory 208356 kb
Host smart-395327a9-4d32-4bf0-a2bd-c287b660a8e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4020121133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.4020121133
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3214045059
Short name T441
Test name
Test status
Simulation time 8053190 ps
CPU time 1.06 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:27:56 PM PDT 24
Peak memory 201904 kb
Host smart-6e4b89f6-bb1d-4e4b-bba8-d7fd8f0cf4cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3214045059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3214045059
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1969927626
Short name T510
Test name
Test status
Simulation time 58261184 ps
CPU time 16.04 seconds
Started Jun 28 05:27:55 PM PDT 24
Finished Jun 28 05:28:12 PM PDT 24
Peak memory 201916 kb
Host smart-75fad84d-037a-45fa-8f35-5715cc570a24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969927626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1969927626
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2764096236
Short name T248
Test name
Test status
Simulation time 268949643 ps
CPU time 2.34 seconds
Started Jun 28 05:27:55 PM PDT 24
Finished Jun 28 05:27:58 PM PDT 24
Peak memory 201868 kb
Host smart-a7de2d9d-a343-4cc0-ac0e-156b8e37b2db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2764096236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2764096236
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.519454923
Short name T81
Test name
Test status
Simulation time 48070528 ps
CPU time 2.8 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:27:58 PM PDT 24
Peak memory 201916 kb
Host smart-41ede7a8-641b-46f6-b37e-6650074bd511
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=519454923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.519454923
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.1013247922
Short name T374
Test name
Test status
Simulation time 1117628312 ps
CPU time 10.94 seconds
Started Jun 28 05:27:56 PM PDT 24
Finished Jun 28 05:28:07 PM PDT 24
Peak memory 201904 kb
Host smart-22396afe-5450-4165-99cc-c45c8e8b3f66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1013247922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1013247922
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1406931957
Short name T678
Test name
Test status
Simulation time 30602186612 ps
CPU time 146.78 seconds
Started Jun 28 05:27:52 PM PDT 24
Finished Jun 28 05:30:19 PM PDT 24
Peak memory 202036 kb
Host smart-fef9d1e8-3141-4931-a674-aac65329b19a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406931957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1406931957
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1310969858
Short name T738
Test name
Test status
Simulation time 13372093985 ps
CPU time 65.26 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:29:00 PM PDT 24
Peak memory 202056 kb
Host smart-17635fb4-1fb1-4b7d-868e-903a3e59b79a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1310969858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1310969858
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4029057483
Short name T554
Test name
Test status
Simulation time 97905140 ps
CPU time 7.59 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 202080 kb
Host smart-ce28b705-113a-4f25-9cc2-b215206b22ea
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029057483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4029057483
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.3591440059
Short name T788
Test name
Test status
Simulation time 331118414 ps
CPU time 3.3 seconds
Started Jun 28 05:27:53 PM PDT 24
Finished Jun 28 05:27:57 PM PDT 24
Peak memory 201820 kb
Host smart-8c9b0b36-7f7d-4b94-981d-d01dfb8390cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3591440059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3591440059
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.3455933034
Short name T373
Test name
Test status
Simulation time 67017455 ps
CPU time 1.26 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:27:57 PM PDT 24
Peak memory 201884 kb
Host smart-2d505239-4065-4387-abe3-91c0528b904d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3455933034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3455933034
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1850359294
Short name T352
Test name
Test status
Simulation time 5757424123 ps
CPU time 10.37 seconds
Started Jun 28 05:27:57 PM PDT 24
Finished Jun 28 05:28:07 PM PDT 24
Peak memory 202024 kb
Host smart-a3c8e2e3-c232-431c-8a6d-fb1759674a61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850359294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1850359294
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3335386647
Short name T230
Test name
Test status
Simulation time 987723098 ps
CPU time 7.65 seconds
Started Jun 28 05:27:55 PM PDT 24
Finished Jun 28 05:28:04 PM PDT 24
Peak memory 201948 kb
Host smart-554f3687-021a-4548-a516-3169d33727fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3335386647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3335386647
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.776255129
Short name T335
Test name
Test status
Simulation time 8936556 ps
CPU time 1.2 seconds
Started Jun 28 05:27:53 PM PDT 24
Finished Jun 28 05:27:55 PM PDT 24
Peak memory 201904 kb
Host smart-59a7428b-020f-4890-ab90-e8fc11bbd587
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776255129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.776255129
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3862938735
Short name T777
Test name
Test status
Simulation time 5719821434 ps
CPU time 79.96 seconds
Started Jun 28 05:28:09 PM PDT 24
Finished Jun 28 05:29:30 PM PDT 24
Peak memory 203416 kb
Host smart-4a95175c-101a-4076-a80d-295cb43c91e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3862938735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3862938735
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1489889755
Short name T195
Test name
Test status
Simulation time 14134584121 ps
CPU time 95.77 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:29:43 PM PDT 24
Peak memory 204508 kb
Host smart-d884d371-7c38-43bd-887b-604bf270896d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1489889755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1489889755
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2378290802
Short name T302
Test name
Test status
Simulation time 9661247796 ps
CPU time 195.26 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:31:24 PM PDT 24
Peak memory 207088 kb
Host smart-3195db4e-7798-4092-8be1-8e9540f290dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2378290802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2378290802
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.158384885
Short name T70
Test name
Test status
Simulation time 533107287 ps
CPU time 7.76 seconds
Started Jun 28 05:27:54 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 201884 kb
Host smart-98083787-7502-4f3c-aae1-029836ae9de7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=158384885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.158384885
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.483298724
Short name T284
Test name
Test status
Simulation time 486169340 ps
CPU time 11.26 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:28:20 PM PDT 24
Peak memory 201856 kb
Host smart-54d9b9b0-162a-4ad8-b8b5-284672db4551
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=483298724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.483298724
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1901104057
Short name T198
Test name
Test status
Simulation time 5140791863 ps
CPU time 33.97 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:42 PM PDT 24
Peak memory 201972 kb
Host smart-99e2cb06-89a5-4f81-83ab-b68a753ed316
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1901104057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.1901104057
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.17537547
Short name T232
Test name
Test status
Simulation time 256490533 ps
CPU time 4.32 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:28:13 PM PDT 24
Peak memory 201808 kb
Host smart-d466d803-dea7-433c-a3ca-3efbfeebba0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17537547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.17537547
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.3484180787
Short name T261
Test name
Test status
Simulation time 216143880 ps
CPU time 4.37 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:13 PM PDT 24
Peak memory 201872 kb
Host smart-ff925fd2-f4f9-4171-a2c5-9b83543fc9f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3484180787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3484180787
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.2692262297
Short name T264
Test name
Test status
Simulation time 460590297 ps
CPU time 4.16 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:12 PM PDT 24
Peak memory 201908 kb
Host smart-7df421b9-cd0c-4104-82a1-3fc8fdbf7a4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2692262297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2692262297
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.4272761191
Short name T726
Test name
Test status
Simulation time 6532278319 ps
CPU time 27.5 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:35 PM PDT 24
Peak memory 202032 kb
Host smart-f544467e-4cd3-4cd9-8e55-e180acbebaf5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272761191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4272761191
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2528864575
Short name T758
Test name
Test status
Simulation time 22915277960 ps
CPU time 162.73 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:30:51 PM PDT 24
Peak memory 202004 kb
Host smart-4ae112f1-b1c0-4e17-b1da-95751e9fd925
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2528864575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2528864575
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2031108731
Short name T681
Test name
Test status
Simulation time 32343951 ps
CPU time 3.02 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:09 PM PDT 24
Peak memory 201808 kb
Host smart-640df8fd-2de6-4a9c-9455-7ea596985bc3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031108731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2031108731
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1378821453
Short name T382
Test name
Test status
Simulation time 135505242 ps
CPU time 2.29 seconds
Started Jun 28 05:28:05 PM PDT 24
Finished Jun 28 05:28:08 PM PDT 24
Peak memory 201816 kb
Host smart-55742d02-0503-4554-be72-9c43c4e20674
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1378821453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1378821453
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.3699915331
Short name T499
Test name
Test status
Simulation time 13053483 ps
CPU time 1.05 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:28:10 PM PDT 24
Peak memory 201776 kb
Host smart-a289f836-2376-484f-a8a2-e267ebfdc5ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3699915331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3699915331
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4007603279
Short name T427
Test name
Test status
Simulation time 2179140482 ps
CPU time 8.49 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:16 PM PDT 24
Peak memory 201968 kb
Host smart-f306710c-c3f3-45ef-92db-d27653d3b6c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007603279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4007603279
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2975409176
Short name T636
Test name
Test status
Simulation time 1420738835 ps
CPU time 9.46 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:17 PM PDT 24
Peak memory 201900 kb
Host smart-4fa9948b-ad7a-4b0d-b3ad-d7353479ddd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2975409176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2975409176
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3603056053
Short name T357
Test name
Test status
Simulation time 12226045 ps
CPU time 1.16 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:28:10 PM PDT 24
Peak memory 202124 kb
Host smart-d85df1b8-b3eb-452d-84d3-401bcdb31fe4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603056053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3603056053
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.580532961
Short name T377
Test name
Test status
Simulation time 556635790 ps
CPU time 15.94 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:23 PM PDT 24
Peak memory 201840 kb
Host smart-8e13fa76-d7c5-4c55-990b-9a72ee4d3e90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=580532961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.580532961
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.4094824200
Short name T162
Test name
Test status
Simulation time 7750143007 ps
CPU time 85.6 seconds
Started Jun 28 05:28:05 PM PDT 24
Finished Jun 28 05:29:31 PM PDT 24
Peak memory 203116 kb
Host smart-ed97875c-21cd-4b8e-9d31-7b9556f42954
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4094824200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4094824200
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1096832326
Short name T586
Test name
Test status
Simulation time 1193004131 ps
CPU time 142.73 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 206800 kb
Host smart-87fe7574-8b80-49d5-90bf-cfb8232c87b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1096832326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1096832326
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2460264778
Short name T529
Test name
Test status
Simulation time 1495885531 ps
CPU time 128.2 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:30:14 PM PDT 24
Peak memory 207924 kb
Host smart-df655a6a-50b7-42a4-aec4-f96618b420cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2460264778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.2460264778
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4277645517
Short name T816
Test name
Test status
Simulation time 218992650 ps
CPU time 3.66 seconds
Started Jun 28 05:28:09 PM PDT 24
Finished Jun 28 05:28:13 PM PDT 24
Peak memory 201880 kb
Host smart-7c5e7716-8a21-47a4-9412-1feba9d506d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4277645517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4277645517
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1021149560
Short name T142
Test name
Test status
Simulation time 2066525446 ps
CPU time 14.53 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:28:23 PM PDT 24
Peak memory 201860 kb
Host smart-de908667-2488-41a6-8d30-00fccbdca5b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1021149560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1021149560
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4175990023
Short name T881
Test name
Test status
Simulation time 38115657131 ps
CPU time 240.94 seconds
Started Jun 28 05:28:08 PM PDT 24
Finished Jun 28 05:32:10 PM PDT 24
Peak memory 203096 kb
Host smart-3ef1efaf-f6c1-4f57-a43c-a2151ecd03aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4175990023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.4175990023
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.424342477
Short name T792
Test name
Test status
Simulation time 371128521 ps
CPU time 6.51 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:28 PM PDT 24
Peak memory 201964 kb
Host smart-1fddeb75-ffbc-4492-97d9-c3c58067cf49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=424342477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.424342477
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.2023866383
Short name T874
Test name
Test status
Simulation time 1372464863 ps
CPU time 14.33 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:36 PM PDT 24
Peak memory 201912 kb
Host smart-112b8046-745e-493d-9c32-9e7250a699be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2023866383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2023866383
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.4088456305
Short name T485
Test name
Test status
Simulation time 868023465 ps
CPU time 6.47 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:14 PM PDT 24
Peak memory 201888 kb
Host smart-9b26e196-44f4-416c-b80e-b64d45094347
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4088456305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.4088456305
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1120064030
Short name T55
Test name
Test status
Simulation time 196625664360 ps
CPU time 120.71 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:30:07 PM PDT 24
Peak memory 202032 kb
Host smart-454b3101-63f4-43cc-9fa2-2ff1fd5c94e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120064030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1120064030
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.205057702
Short name T75
Test name
Test status
Simulation time 19611107230 ps
CPU time 95.44 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:29:43 PM PDT 24
Peak memory 202060 kb
Host smart-80236e70-a360-44cd-926f-1263ef174099
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=205057702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.205057702
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.812949289
Short name T542
Test name
Test status
Simulation time 77107211 ps
CPU time 10.71 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:18 PM PDT 24
Peak memory 201900 kb
Host smart-e492c81f-af77-4d92-a801-772c8b916766
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812949289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.812949289
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.2501879474
Short name T253
Test name
Test status
Simulation time 756229046 ps
CPU time 8.41 seconds
Started Jun 28 05:28:06 PM PDT 24
Finished Jun 28 05:28:15 PM PDT 24
Peak memory 201908 kb
Host smart-ab631b9f-4d16-4894-bb12-996fac415905
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2501879474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2501879474
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.4177943712
Short name T854
Test name
Test status
Simulation time 142294636 ps
CPU time 1.57 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:10 PM PDT 24
Peak memory 201904 kb
Host smart-139eb996-0e1e-4df5-b104-eea34454c644
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4177943712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4177943712
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1157664498
Short name T404
Test name
Test status
Simulation time 7367752889 ps
CPU time 8.76 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:17 PM PDT 24
Peak memory 201996 kb
Host smart-6a8f8898-62a5-4708-a148-d83d3c25d6d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157664498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1157664498
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1557814702
Short name T536
Test name
Test status
Simulation time 1071740620 ps
CPU time 7.78 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:16 PM PDT 24
Peak memory 201864 kb
Host smart-30321992-d462-4bee-a1b9-46d74614b034
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1557814702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1557814702
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2968127107
Short name T717
Test name
Test status
Simulation time 13601322 ps
CPU time 1.2 seconds
Started Jun 28 05:28:07 PM PDT 24
Finished Jun 28 05:28:10 PM PDT 24
Peak memory 201884 kb
Host smart-3522457b-1835-4ee5-a054-d671f2326422
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968127107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2968127107
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1464494667
Short name T661
Test name
Test status
Simulation time 7789572155 ps
CPU time 85.58 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:29:46 PM PDT 24
Peak memory 203520 kb
Host smart-28932b12-a95b-4feb-9032-18d654652c41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1464494667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1464494667
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1486370307
Short name T211
Test name
Test status
Simulation time 11403569194 ps
CPU time 39.64 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:29:01 PM PDT 24
Peak memory 201992 kb
Host smart-717c19ab-d5c2-410d-8c44-8a931dce4bdd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486370307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1486370307
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1937671990
Short name T136
Test name
Test status
Simulation time 251007222 ps
CPU time 45.02 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:29:06 PM PDT 24
Peak memory 204012 kb
Host smart-4c231a85-888d-4afe-ba4d-8fc073dc5304
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937671990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.1937671990
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1632486888
Short name T439
Test name
Test status
Simulation time 1605500375 ps
CPU time 49.23 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:29:12 PM PDT 24
Peak memory 203996 kb
Host smart-81609d2e-4a99-4bc8-87cc-e7e44132e75d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1632486888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.1632486888
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.523961844
Short name T696
Test name
Test status
Simulation time 64115001 ps
CPU time 5.13 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:26 PM PDT 24
Peak memory 201884 kb
Host smart-6d6785d8-9792-494e-9839-28a82ea1fdde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=523961844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.523961844
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2769238419
Short name T135
Test name
Test status
Simulation time 230092475 ps
CPU time 5.33 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:28:28 PM PDT 24
Peak memory 201912 kb
Host smart-6dfdebcc-7a5c-4f89-a0d4-a9cad340104c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2769238419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2769238419
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3427358751
Short name T189
Test name
Test status
Simulation time 13868914333 ps
CPU time 89.08 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:29:50 PM PDT 24
Peak memory 202072 kb
Host smart-0be21bc5-db98-401c-9889-25a4d6fe9a3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3427358751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.3427358751
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4053638910
Short name T627
Test name
Test status
Simulation time 62443462 ps
CPU time 3.68 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:28:24 PM PDT 24
Peak memory 201964 kb
Host smart-058a3f68-a646-4e7f-819f-5af510de7888
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4053638910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4053638910
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.1176491042
Short name T671
Test name
Test status
Simulation time 952866763 ps
CPU time 12.32 seconds
Started Jun 28 05:28:21 PM PDT 24
Finished Jun 28 05:28:34 PM PDT 24
Peak memory 201920 kb
Host smart-d58b1c45-ad59-4878-b27b-199306837f61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1176491042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1176491042
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.2406674455
Short name T249
Test name
Test status
Simulation time 614416012 ps
CPU time 11.27 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:28:31 PM PDT 24
Peak memory 201808 kb
Host smart-6cccabdc-d491-42ac-9282-a5eeb3e1273a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2406674455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2406674455
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3214324058
Short name T149
Test name
Test status
Simulation time 12335001045 ps
CPU time 32.69 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:28:52 PM PDT 24
Peak memory 202016 kb
Host smart-2315aa54-e8d2-474c-ae44-a51d2f9591c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214324058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3214324058
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3210004599
Short name T642
Test name
Test status
Simulation time 8432205870 ps
CPU time 26.15 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:28:49 PM PDT 24
Peak memory 202280 kb
Host smart-ee3eb150-b635-4c7d-add4-184be3607784
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3210004599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3210004599
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1092401593
Short name T630
Test name
Test status
Simulation time 111296016 ps
CPU time 6.33 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:28:29 PM PDT 24
Peak memory 202124 kb
Host smart-649a2106-849d-4617-b588-046e67985110
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092401593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1092401593
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.2745589622
Short name T633
Test name
Test status
Simulation time 1074269374 ps
CPU time 13.35 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:34 PM PDT 24
Peak memory 201916 kb
Host smart-04d14703-e18c-4b24-a262-12c9516988da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2745589622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2745589622
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.1910787969
Short name T606
Test name
Test status
Simulation time 116953535 ps
CPU time 1.46 seconds
Started Jun 28 05:28:21 PM PDT 24
Finished Jun 28 05:28:24 PM PDT 24
Peak memory 201884 kb
Host smart-353d0543-0ed8-4072-ab86-3b94b5a64bd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1910787969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1910787969
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2164928921
Short name T459
Test name
Test status
Simulation time 2123250684 ps
CPU time 8.37 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:28:29 PM PDT 24
Peak memory 202048 kb
Host smart-d83754c8-4048-4bdb-9b63-ab8419bc4fc9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164928921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2164928921
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1368130261
Short name T685
Test name
Test status
Simulation time 937917736 ps
CPU time 6.82 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:28 PM PDT 24
Peak memory 201852 kb
Host smart-93043f45-1880-4513-914a-ea43a7051b5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1368130261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1368130261
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4145492456
Short name T458
Test name
Test status
Simulation time 9290145 ps
CPU time 1.31 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:28:21 PM PDT 24
Peak memory 201872 kb
Host smart-96d752f0-259e-4190-ab91-14e890ef10c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145492456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4145492456
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1439460348
Short name T280
Test name
Test status
Simulation time 1231017678 ps
CPU time 40.86 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:29:02 PM PDT 24
Peak memory 202936 kb
Host smart-8e49a609-7671-4a8c-8120-74816ac4f942
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1439460348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1439460348
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.418519645
Short name T584
Test name
Test status
Simulation time 668353141 ps
CPU time 13.26 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:34 PM PDT 24
Peak memory 201920 kb
Host smart-ccccd8ce-b190-4d20-9908-184be7c5099d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=418519645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.418519645
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2601976534
Short name T365
Test name
Test status
Simulation time 521528696 ps
CPU time 87.83 seconds
Started Jun 28 05:28:21 PM PDT 24
Finished Jun 28 05:29:50 PM PDT 24
Peak memory 204452 kb
Host smart-b7b5bc99-aff8-470a-8c67-44289efbaa74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2601976534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.2601976534
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.4244412647
Short name T422
Test name
Test status
Simulation time 12614701366 ps
CPU time 169.43 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:31:09 PM PDT 24
Peak memory 207740 kb
Host smart-189dcdbf-04d9-42d3-98a7-780abfa327fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4244412647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.4244412647
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2600418203
Short name T675
Test name
Test status
Simulation time 120764462 ps
CPU time 7.48 seconds
Started Jun 28 05:28:18 PM PDT 24
Finished Jun 28 05:28:26 PM PDT 24
Peak memory 201908 kb
Host smart-18263ede-26a7-43ee-b19d-98ad6bfe1b5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2600418203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2600418203
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3344008951
Short name T194
Test name
Test status
Simulation time 21008856116 ps
CPU time 162.44 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:31:06 PM PDT 24
Peak memory 203284 kb
Host smart-85b4d39a-561b-429a-b15b-6c8595d08d21
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3344008951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.3344008951
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2207266472
Short name T14
Test name
Test status
Simulation time 50742391 ps
CPU time 5.12 seconds
Started Jun 28 05:28:33 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 201944 kb
Host smart-df3aa5de-055b-4990-9df6-98e8fba169c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2207266472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2207266472
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.3061447427
Short name T567
Test name
Test status
Simulation time 726183267 ps
CPU time 15.16 seconds
Started Jun 28 05:28:23 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 201916 kb
Host smart-ebede4e4-e67b-4bfa-b9f8-847e4bab28aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3061447427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3061447427
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.1405968221
Short name T127
Test name
Test status
Simulation time 69124434 ps
CPU time 6.09 seconds
Started Jun 28 05:28:23 PM PDT 24
Finished Jun 28 05:28:30 PM PDT 24
Peak memory 201904 kb
Host smart-0df6d667-4c7a-42c8-8ac4-b78f33b76d48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1405968221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1405968221
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2594740212
Short name T283
Test name
Test status
Simulation time 22800852296 ps
CPU time 47.14 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:29:08 PM PDT 24
Peak memory 202032 kb
Host smart-64695509-1660-4b04-a57f-e7e38a328119
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594740212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2594740212
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.4278160409
Short name T102
Test name
Test status
Simulation time 9452000923 ps
CPU time 44.26 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:29:07 PM PDT 24
Peak memory 202068 kb
Host smart-a8ff0d6c-86d1-469c-a738-639abbae620f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4278160409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4278160409
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.275803829
Short name T376
Test name
Test status
Simulation time 221881363 ps
CPU time 7.48 seconds
Started Jun 28 05:28:21 PM PDT 24
Finished Jun 28 05:28:30 PM PDT 24
Peak memory 201880 kb
Host smart-7ed67117-7ff5-47bd-a4d3-27393c57ba05
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275803829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.275803829
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.2772228080
Short name T53
Test name
Test status
Simulation time 925415129 ps
CPU time 6.48 seconds
Started Jun 28 05:28:18 PM PDT 24
Finished Jun 28 05:28:25 PM PDT 24
Peak memory 201916 kb
Host smart-8871d325-4307-4a78-a677-d2930d9fdb7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2772228080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2772228080
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.3526903931
Short name T321
Test name
Test status
Simulation time 45769667 ps
CPU time 1.4 seconds
Started Jun 28 05:28:22 PM PDT 24
Finished Jun 28 05:28:25 PM PDT 24
Peak memory 201896 kb
Host smart-b17cf87d-ac20-4460-9d14-edc4e4f5b7d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3526903931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3526903931
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2103518172
Short name T739
Test name
Test status
Simulation time 2376047733 ps
CPU time 8.97 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:30 PM PDT 24
Peak memory 201872 kb
Host smart-21fa81aa-928d-400c-a473-40efcc4cb78d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103518172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2103518172
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1751656272
Short name T669
Test name
Test status
Simulation time 5070001916 ps
CPU time 7.58 seconds
Started Jun 28 05:28:19 PM PDT 24
Finished Jun 28 05:28:27 PM PDT 24
Peak memory 202064 kb
Host smart-e0abae5c-b16c-4aca-b4fc-c2790854f200
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1751656272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1751656272
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2730312676
Short name T21
Test name
Test status
Simulation time 15658162 ps
CPU time 1.26 seconds
Started Jun 28 05:28:20 PM PDT 24
Finished Jun 28 05:28:22 PM PDT 24
Peak memory 201876 kb
Host smart-8731a2ec-7a57-495d-9725-824d1786de90
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730312676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2730312676
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2634524490
Short name T331
Test name
Test status
Simulation time 407366453 ps
CPU time 5.76 seconds
Started Jun 28 05:28:34 PM PDT 24
Finished Jun 28 05:28:41 PM PDT 24
Peak memory 201912 kb
Host smart-17f8b663-088e-46e4-836f-96b61c54fcdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2634524490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2634524490
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1408834114
Short name T13
Test name
Test status
Simulation time 369354438 ps
CPU time 24.56 seconds
Started Jun 28 05:28:33 PM PDT 24
Finished Jun 28 05:28:59 PM PDT 24
Peak memory 201960 kb
Host smart-7dd18e0b-e5af-4dd3-9365-eb7f1766d591
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1408834114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1408834114
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1022572927
Short name T134
Test name
Test status
Simulation time 54081869 ps
CPU time 8.38 seconds
Started Jun 28 05:28:32 PM PDT 24
Finished Jun 28 05:28:41 PM PDT 24
Peak memory 201960 kb
Host smart-e6a2b4e7-4d78-43d1-809a-4fa7f3f546fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1022572927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.1022572927
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.347384786
Short name T393
Test name
Test status
Simulation time 966713643 ps
CPU time 12.03 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:28:44 PM PDT 24
Peak memory 201916 kb
Host smart-5cf72e04-1253-419b-b0b3-e9a40567c072
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=347384786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.347384786
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1243996283
Short name T593
Test name
Test status
Simulation time 107235743 ps
CPU time 2.62 seconds
Started Jun 28 05:28:36 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 201916 kb
Host smart-0198cfa8-cbc5-4918-9292-1f98f6311f93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1243996283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1243996283
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.223978498
Short name T216
Test name
Test status
Simulation time 36073944605 ps
CPU time 268.87 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 203012 kb
Host smart-a70f682a-2ee4-4fd2-a128-8aa942aac217
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=223978498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo
w_rsp.223978498
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.298569897
Short name T526
Test name
Test status
Simulation time 76829943 ps
CPU time 5.31 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:28:40 PM PDT 24
Peak memory 201960 kb
Host smart-bf5678bc-2607-413e-a10a-eb4c7caebfff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=298569897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.298569897
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.2938045394
Short name T282
Test name
Test status
Simulation time 400986961 ps
CPU time 7.52 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:28:44 PM PDT 24
Peak memory 201836 kb
Host smart-7877b725-7a3f-406a-87d7-e3cc398802f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2938045394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2938045394
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.1772604243
Short name T117
Test name
Test status
Simulation time 924372692 ps
CPU time 18.63 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:28:51 PM PDT 24
Peak memory 201884 kb
Host smart-51959239-682f-42af-86e0-fe20093037e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1772604243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1772604243
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1072533659
Short name T293
Test name
Test status
Simulation time 13805620216 ps
CPU time 55.5 seconds
Started Jun 28 05:28:33 PM PDT 24
Finished Jun 28 05:29:30 PM PDT 24
Peak memory 201996 kb
Host smart-ddc6dfd4-5651-4391-a4be-f51dec9b750e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072533659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1072533659
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.385585020
Short name T533
Test name
Test status
Simulation time 4170211461 ps
CPU time 29.32 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:29:01 PM PDT 24
Peak memory 201940 kb
Host smart-15fd16c2-c5ee-4f37-98d6-30a3d978784f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=385585020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.385585020
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2168230480
Short name T257
Test name
Test status
Simulation time 56625957 ps
CPU time 5.18 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:28:40 PM PDT 24
Peak memory 201892 kb
Host smart-1706e382-e9d4-46f0-bcdc-5ebc4b7b8006
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168230480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2168230480
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.494159974
Short name T492
Test name
Test status
Simulation time 118570310 ps
CPU time 3.65 seconds
Started Jun 28 05:28:33 PM PDT 24
Finished Jun 28 05:28:37 PM PDT 24
Peak memory 201916 kb
Host smart-fa76453d-b3d3-4e6b-b641-9827c75f8099
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=494159974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.494159974
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.3724267881
Short name T776
Test name
Test status
Simulation time 9331549 ps
CPU time 1.18 seconds
Started Jun 28 05:28:32 PM PDT 24
Finished Jun 28 05:28:34 PM PDT 24
Peak memory 201800 kb
Host smart-e8ef8801-7aa9-41e7-9a84-4a26221d3e41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3724267881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3724267881
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1450030646
Short name T454
Test name
Test status
Simulation time 2722810620 ps
CPU time 12.84 seconds
Started Jun 28 05:28:37 PM PDT 24
Finished Jun 28 05:28:50 PM PDT 24
Peak memory 201972 kb
Host smart-6d6e7aaa-96ef-4ff0-ab82-8fbf28247b2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450030646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1450030646
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1469250896
Short name T768
Test name
Test status
Simulation time 1396678381 ps
CPU time 6.76 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:28:38 PM PDT 24
Peak memory 201944 kb
Host smart-a522c234-3f9c-4abe-83b4-8246d43a3fc8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1469250896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1469250896
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1491416167
Short name T844
Test name
Test status
Simulation time 16368950 ps
CPU time 1.02 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:28:33 PM PDT 24
Peak memory 201884 kb
Host smart-6d79558d-9df0-45ae-9a1c-afbff64c9da7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491416167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1491416167
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3655174780
Short name T791
Test name
Test status
Simulation time 720288051 ps
CPU time 54.14 seconds
Started Jun 28 05:28:34 PM PDT 24
Finished Jun 28 05:29:29 PM PDT 24
Peak memory 203116 kb
Host smart-2f4e06c6-e775-47a6-a303-3b3afd82bc6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3655174780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3655174780
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2893644509
Short name T732
Test name
Test status
Simulation time 4905325263 ps
CPU time 82.7 seconds
Started Jun 28 05:28:31 PM PDT 24
Finished Jun 28 05:29:54 PM PDT 24
Peak memory 202096 kb
Host smart-8dcf13d5-ea84-4d6a-8a41-1e32b351805a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2893644509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2893644509
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1301341660
Short name T170
Test name
Test status
Simulation time 1472511583 ps
CPU time 78.75 seconds
Started Jun 28 05:28:36 PM PDT 24
Finished Jun 28 05:29:55 PM PDT 24
Peak memory 204788 kb
Host smart-9743b5f8-bb44-4d64-af95-3396280831ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1301341660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.1301341660
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1883995828
Short name T452
Test name
Test status
Simulation time 70496650 ps
CPU time 4.13 seconds
Started Jun 28 05:28:34 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 201960 kb
Host smart-e0a231a9-acc9-4e1a-90b1-74753d87f3be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1883995828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.1883995828
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.460005872
Short name T43
Test name
Test status
Simulation time 386425427 ps
CPU time 9 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:28:45 PM PDT 24
Peak memory 201900 kb
Host smart-8ca49595-02ba-4359-8748-2f3debfb5938
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=460005872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.460005872
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2667243934
Short name T553
Test name
Test status
Simulation time 897731732 ps
CPU time 8.53 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:28:44 PM PDT 24
Peak memory 201904 kb
Host smart-d8aca3cd-5bb4-48d0-9d02-5b841fa21a46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2667243934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2667243934
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1630322033
Short name T795
Test name
Test status
Simulation time 10360715389 ps
CPU time 18.47 seconds
Started Jun 28 05:28:32 PM PDT 24
Finished Jun 28 05:28:51 PM PDT 24
Peak memory 201972 kb
Host smart-9e8b0003-1633-4a50-8ea4-ab10e993be48
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1630322033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.1630322033
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2286068072
Short name T369
Test name
Test status
Simulation time 835559095 ps
CPU time 10.12 seconds
Started Jun 28 05:28:45 PM PDT 24
Finished Jun 28 05:28:56 PM PDT 24
Peak memory 201968 kb
Host smart-59c8f336-47d3-4308-b23c-b2c917616ad9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2286068072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2286068072
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.637505840
Short name T342
Test name
Test status
Simulation time 488509405 ps
CPU time 3.75 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:28:47 PM PDT 24
Peak memory 201920 kb
Host smart-0b7c9f5b-a65c-42fe-91fd-e9413a088a3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=637505840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.637505840
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.4061464933
Short name T348
Test name
Test status
Simulation time 28030413 ps
CPU time 1.48 seconds
Started Jun 28 05:28:32 PM PDT 24
Finished Jun 28 05:28:34 PM PDT 24
Peak memory 201900 kb
Host smart-851769f6-0a78-45d4-8fca-b52223b5a16a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4061464933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.4061464933
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1134864417
Short name T176
Test name
Test status
Simulation time 67772090963 ps
CPU time 166.11 seconds
Started Jun 28 05:28:37 PM PDT 24
Finished Jun 28 05:31:23 PM PDT 24
Peak memory 202036 kb
Host smart-42f77e29-3775-4581-b0e3-4b7d0bbed94d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134864417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1134864417
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1366246838
Short name T26
Test name
Test status
Simulation time 13551033721 ps
CPU time 83.27 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:29:59 PM PDT 24
Peak memory 201980 kb
Host smart-5d928197-71e3-46b3-b9fa-68a4853a3fda
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1366246838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1366246838
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1207897377
Short name T476
Test name
Test status
Simulation time 45268954 ps
CPU time 3.73 seconds
Started Jun 28 05:28:33 PM PDT 24
Finished Jun 28 05:28:38 PM PDT 24
Peak memory 201880 kb
Host smart-0f5ab2b3-e246-410a-a7f2-e9cfea172938
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207897377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1207897377
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.4243017668
Short name T770
Test name
Test status
Simulation time 769438106 ps
CPU time 5.93 seconds
Started Jun 28 05:28:37 PM PDT 24
Finished Jun 28 05:28:43 PM PDT 24
Peak memory 201916 kb
Host smart-98d1bf28-d527-4765-aa4b-989522968666
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4243017668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4243017668
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.3287475025
Short name T670
Test name
Test status
Simulation time 80084565 ps
CPU time 1.78 seconds
Started Jun 28 05:28:34 PM PDT 24
Finished Jun 28 05:28:36 PM PDT 24
Peak memory 201880 kb
Host smart-5a991b58-826b-4ae6-bd26-fad5e19c7398
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3287475025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3287475025
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2878611265
Short name T894
Test name
Test status
Simulation time 2872156093 ps
CPU time 10.47 seconds
Started Jun 28 05:28:32 PM PDT 24
Finished Jun 28 05:28:43 PM PDT 24
Peak memory 201876 kb
Host smart-d9b48e92-fb19-492d-8969-dc664675fd82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878611265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2878611265
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1377018824
Short name T600
Test name
Test status
Simulation time 3771794581 ps
CPU time 13.8 seconds
Started Jun 28 05:28:35 PM PDT 24
Finished Jun 28 05:28:50 PM PDT 24
Peak memory 201920 kb
Host smart-ba083ac0-9789-4016-a034-df9aa1468c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1377018824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1377018824
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.4175518899
Short name T631
Test name
Test status
Simulation time 10073871 ps
CPU time 1.19 seconds
Started Jun 28 05:28:33 PM PDT 24
Finished Jun 28 05:28:36 PM PDT 24
Peak memory 201884 kb
Host smart-4f3efccb-be4a-4d61-bd63-242a0d0a804a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175518899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.4175518899
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2400097584
Short name T511
Test name
Test status
Simulation time 284275283 ps
CPU time 36.64 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:29:22 PM PDT 24
Peak memory 203028 kb
Host smart-bc8a0989-6f7c-44f6-97be-6064fbde29cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2400097584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2400097584
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1783435845
Short name T311
Test name
Test status
Simulation time 132289167 ps
CPU time 19.28 seconds
Started Jun 28 05:28:42 PM PDT 24
Finished Jun 28 05:29:03 PM PDT 24
Peak memory 202136 kb
Host smart-4add794c-8f6d-4a9c-8ef2-f53584849f74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783435845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1783435845
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.4080262620
Short name T275
Test name
Test status
Simulation time 431324862 ps
CPU time 60.9 seconds
Started Jun 28 05:28:49 PM PDT 24
Finished Jun 28 05:29:50 PM PDT 24
Peak memory 204108 kb
Host smart-bcdbeb8c-afbb-4409-ae30-338f3ba90781
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4080262620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.4080262620
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.807466333
Short name T679
Test name
Test status
Simulation time 145388139 ps
CPU time 11.85 seconds
Started Jun 28 05:28:45 PM PDT 24
Finished Jun 28 05:28:57 PM PDT 24
Peak memory 201968 kb
Host smart-b95e34dd-7850-4577-aed3-8e6c7442cb76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=807466333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res
et_error.807466333
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1605381002
Short name T59
Test name
Test status
Simulation time 467045689 ps
CPU time 4.59 seconds
Started Jun 28 05:28:42 PM PDT 24
Finished Jun 28 05:28:47 PM PDT 24
Peak memory 201880 kb
Host smart-614d50bd-2386-4b47-9cdd-841122f48db3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1605381002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1605381002
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2317449147
Short name T432
Test name
Test status
Simulation time 40958653 ps
CPU time 2.65 seconds
Started Jun 28 05:28:45 PM PDT 24
Finished Jun 28 05:28:49 PM PDT 24
Peak memory 201912 kb
Host smart-fe26072c-b4eb-4ecd-95de-544a81b00551
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2317449147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2317449147
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.204928289
Short name T96
Test name
Test status
Simulation time 17090145858 ps
CPU time 83.97 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:30:09 PM PDT 24
Peak memory 202072 kb
Host smart-62dc68c3-5e4e-430c-bddb-f03bf752cfd8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=204928289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo
w_rsp.204928289
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1154784206
Short name T649
Test name
Test status
Simulation time 708930394 ps
CPU time 11.28 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:28:55 PM PDT 24
Peak memory 201968 kb
Host smart-dbfad4d1-bc7d-4c79-9664-724bf11d93d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1154784206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1154784206
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.3906479610
Short name T865
Test name
Test status
Simulation time 64366228 ps
CPU time 6.91 seconds
Started Jun 28 05:28:45 PM PDT 24
Finished Jun 28 05:28:52 PM PDT 24
Peak memory 201912 kb
Host smart-38411598-b4a9-4c3e-bd0d-a8d4e385cdac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906479610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3906479610
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.590442805
Short name T474
Test name
Test status
Simulation time 1411886520 ps
CPU time 13.05 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:28:58 PM PDT 24
Peak memory 201896 kb
Host smart-91998d21-0c67-4e82-b315-d7aeb2b1d9f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=590442805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.590442805
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2987128340
Short name T400
Test name
Test status
Simulation time 35898701695 ps
CPU time 64.47 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:29:50 PM PDT 24
Peak memory 202016 kb
Host smart-98ccd250-478c-4904-8de8-f3e10d987409
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987128340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2987128340
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2486404293
Short name T801
Test name
Test status
Simulation time 2602544157 ps
CPU time 12.86 seconds
Started Jun 28 05:28:48 PM PDT 24
Finished Jun 28 05:29:02 PM PDT 24
Peak memory 202008 kb
Host smart-ec85efb3-dcca-42f1-a791-81b63e60cbbb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2486404293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2486404293
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2085661767
Short name T126
Test name
Test status
Simulation time 47813298 ps
CPU time 1.82 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:28:46 PM PDT 24
Peak memory 201800 kb
Host smart-eb290edb-3c29-444b-9b5a-ac849b104650
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085661767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2085661767
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.2783989254
Short name T658
Test name
Test status
Simulation time 30514287 ps
CPU time 2.47 seconds
Started Jun 28 05:28:42 PM PDT 24
Finished Jun 28 05:28:46 PM PDT 24
Peak memory 201912 kb
Host smart-13a850ea-14a4-4947-be5e-9399e4d1f45f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2783989254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2783989254
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.2961383906
Short name T800
Test name
Test status
Simulation time 9538255 ps
CPU time 1.17 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:28:45 PM PDT 24
Peak memory 201904 kb
Host smart-50ec5d6c-790b-405c-ad04-207d62488ba1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2961383906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2961383906
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3988584729
Short name T825
Test name
Test status
Simulation time 9438907984 ps
CPU time 5.74 seconds
Started Jun 28 05:28:42 PM PDT 24
Finished Jun 28 05:28:49 PM PDT 24
Peak memory 202000 kb
Host smart-60276cba-f7de-40dd-a4f4-8895f4059ead
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988584729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3988584729
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1718612869
Short name T851
Test name
Test status
Simulation time 1939076322 ps
CPU time 5.76 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:28:49 PM PDT 24
Peak memory 201944 kb
Host smart-3b27a8ec-4b29-49a8-98ee-8fe88049535e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1718612869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1718612869
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3351075302
Short name T312
Test name
Test status
Simulation time 9999581 ps
CPU time 1.35 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:28:46 PM PDT 24
Peak memory 201864 kb
Host smart-6ab3c094-0ce8-469c-be23-19ef4c5ac45b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351075302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3351075302
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.253049452
Short name T581
Test name
Test status
Simulation time 1363894823 ps
CPU time 61.96 seconds
Started Jun 28 05:28:42 PM PDT 24
Finished Jun 28 05:29:45 PM PDT 24
Peak memory 205176 kb
Host smart-cc717a1c-a95f-4f07-a723-95e61c370bcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=253049452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.253049452
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2962867075
Short name T379
Test name
Test status
Simulation time 154796139 ps
CPU time 1.91 seconds
Started Jun 28 05:28:49 PM PDT 24
Finished Jun 28 05:28:51 PM PDT 24
Peak memory 201968 kb
Host smart-fec3e7bb-0ad9-492a-b381-0845fc0e62d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2962867075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2962867075
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1890854791
Short name T645
Test name
Test status
Simulation time 4633375685 ps
CPU time 96.22 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:30:20 PM PDT 24
Peak memory 204636 kb
Host smart-d9e1014e-da17-499c-b2b9-9b6128019d19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1890854791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.1890854791
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.448747802
Short name T878
Test name
Test status
Simulation time 956222835 ps
CPU time 130.07 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:30:55 PM PDT 24
Peak memory 204340 kb
Host smart-4b995886-50e8-4c8b-af25-d4d674529521
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=448747802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.448747802
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2107574970
Short name T896
Test name
Test status
Simulation time 98437216 ps
CPU time 1.91 seconds
Started Jun 28 05:28:41 PM PDT 24
Finished Jun 28 05:28:44 PM PDT 24
Peak memory 201904 kb
Host smart-cb27f9ab-0d95-4aaf-b10d-827d99b770d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2107574970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2107574970
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.20849231
Short name T350
Test name
Test status
Simulation time 2440873272 ps
CPU time 27.88 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:24:23 PM PDT 24
Peak memory 201980 kb
Host smart-cc11bdb8-21ab-4b62-9771-fe2feac68eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20849231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.20849231
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.731840056
Short name T143
Test name
Test status
Simulation time 39912966159 ps
CPU time 97.9 seconds
Started Jun 28 05:23:54 PM PDT 24
Finished Jun 28 05:25:32 PM PDT 24
Peak memory 202040 kb
Host smart-ef01a073-e5b5-483f-884d-644c5d1496ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=731840056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow
_rsp.731840056
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.977920181
Short name T403
Test name
Test status
Simulation time 1080780528 ps
CPU time 8.57 seconds
Started Jun 28 05:23:53 PM PDT 24
Finished Jun 28 05:24:02 PM PDT 24
Peak memory 201960 kb
Host smart-9779dba8-9875-4c41-bf9a-0d726414dc51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=977920181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.977920181
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3074208848
Short name T277
Test name
Test status
Simulation time 44780787 ps
CPU time 1.28 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:23:57 PM PDT 24
Peak memory 201916 kb
Host smart-09a5cd63-8e74-40d2-b2b7-a65b031e5104
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3074208848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3074208848
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2314168374
Short name T173
Test name
Test status
Simulation time 81993162 ps
CPU time 4.28 seconds
Started Jun 28 05:23:46 PM PDT 24
Finished Jun 28 05:23:51 PM PDT 24
Peak memory 201880 kb
Host smart-c8ade51c-5d94-40d5-8692-97eba72df6c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2314168374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2314168374
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.207689334
Short name T684
Test name
Test status
Simulation time 39198790145 ps
CPU time 141.11 seconds
Started Jun 28 05:23:41 PM PDT 24
Finished Jun 28 05:26:02 PM PDT 24
Peak memory 201944 kb
Host smart-aa9e93a2-6734-44de-b06b-fb212f3899e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=207689334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.207689334
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.100332517
Short name T34
Test name
Test status
Simulation time 52948350051 ps
CPU time 60.07 seconds
Started Jun 28 05:23:41 PM PDT 24
Finished Jun 28 05:24:42 PM PDT 24
Peak memory 202068 kb
Host smart-d79d21a9-00ed-4f28-9ad1-8b92f409ef97
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=100332517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.100332517
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2190351648
Short name T887
Test name
Test status
Simulation time 124750783 ps
CPU time 11.84 seconds
Started Jun 28 05:23:46 PM PDT 24
Finished Jun 28 05:23:58 PM PDT 24
Peak memory 201896 kb
Host smart-9184cd37-37a4-4bc3-b047-d53d9dd20f68
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190351648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2190351648
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.1658367687
Short name T274
Test name
Test status
Simulation time 1582264846 ps
CPU time 9.36 seconds
Started Jun 28 05:23:52 PM PDT 24
Finished Jun 28 05:24:02 PM PDT 24
Peak memory 201860 kb
Host smart-deab9ed7-b969-4d71-a4bd-b2a2ca63e67f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658367687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1658367687
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.911192977
Short name T806
Test name
Test status
Simulation time 12554193 ps
CPU time 1.11 seconds
Started Jun 28 05:23:48 PM PDT 24
Finished Jun 28 05:23:50 PM PDT 24
Peak memory 201820 kb
Host smart-cdacb059-712e-4f55-8a3b-92e23ee65489
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=911192977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.911192977
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3217379187
Short name T346
Test name
Test status
Simulation time 2825763549 ps
CPU time 9.7 seconds
Started Jun 28 05:23:48 PM PDT 24
Finished Jun 28 05:23:58 PM PDT 24
Peak memory 201944 kb
Host smart-60598340-b08c-42b3-b1ae-fc4b69d08d79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217379187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3217379187
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.233470797
Short name T840
Test name
Test status
Simulation time 2735743919 ps
CPU time 13.75 seconds
Started Jun 28 05:23:48 PM PDT 24
Finished Jun 28 05:24:02 PM PDT 24
Peak memory 201976 kb
Host smart-84a74306-eab8-4f48-88b8-ee845513b572
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=233470797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.233470797
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.125304388
Short name T798
Test name
Test status
Simulation time 11421461 ps
CPU time 1.36 seconds
Started Jun 28 05:23:46 PM PDT 24
Finished Jun 28 05:23:48 PM PDT 24
Peak memory 201900 kb
Host smart-15d70b53-7715-4cbb-8e65-8c8dcfe502d6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125304388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.125304388
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3413607545
Short name T83
Test name
Test status
Simulation time 400959139 ps
CPU time 45.57 seconds
Started Jun 28 05:23:52 PM PDT 24
Finished Jun 28 05:24:38 PM PDT 24
Peak memory 202936 kb
Host smart-1e25a76e-cd93-4daa-aab9-946eee0cc97f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3413607545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3413607545
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3782995252
Short name T158
Test name
Test status
Simulation time 527485286 ps
CPU time 23.45 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:24:19 PM PDT 24
Peak memory 201920 kb
Host smart-c4b2c9d2-717e-4b69-8f11-bac6390fa63a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3782995252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3782995252
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1475650740
Short name T641
Test name
Test status
Simulation time 652613964 ps
CPU time 101.76 seconds
Started Jun 28 05:23:54 PM PDT 24
Finished Jun 28 05:25:36 PM PDT 24
Peak memory 204660 kb
Host smart-a7bc56eb-5253-47f3-a231-3c0abb16c9e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1475650740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.1475650740
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3572526834
Short name T528
Test name
Test status
Simulation time 3568186206 ps
CPU time 46.51 seconds
Started Jun 28 05:23:53 PM PDT 24
Finished Jun 28 05:24:40 PM PDT 24
Peak memory 203800 kb
Host smart-94605b00-a0d3-401e-af06-f6159d7241f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3572526834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.3572526834
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1947231828
Short name T313
Test name
Test status
Simulation time 512956736 ps
CPU time 7.96 seconds
Started Jun 28 05:23:53 PM PDT 24
Finished Jun 28 05:24:02 PM PDT 24
Peak memory 201832 kb
Host smart-41dae3f5-1e3d-4438-9758-3605325976cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1947231828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1947231828
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3765370358
Short name T305
Test name
Test status
Simulation time 208106112 ps
CPU time 14.73 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:13 PM PDT 24
Peak memory 201916 kb
Host smart-5656f956-03d3-470e-9aaa-574927151406
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3765370358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3765370358
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.975291509
Short name T122
Test name
Test status
Simulation time 12160349802 ps
CPU time 97.28 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:30:36 PM PDT 24
Peak memory 202044 kb
Host smart-d6239498-8648-46ae-aa5d-95e9f604186a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=975291509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.975291509
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.112176444
Short name T699
Test name
Test status
Simulation time 357141954 ps
CPU time 7.56 seconds
Started Jun 28 05:28:58 PM PDT 24
Finished Jun 28 05:29:07 PM PDT 24
Peak memory 201944 kb
Host smart-4a488443-5ceb-4bfb-8f7c-55710e49315e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112176444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.112176444
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.1615428744
Short name T301
Test name
Test status
Simulation time 14850818 ps
CPU time 1.11 seconds
Started Jun 28 05:28:56 PM PDT 24
Finished Jun 28 05:28:57 PM PDT 24
Peak memory 201916 kb
Host smart-093ea9b9-bba5-44c2-a9db-bacc1c25d22f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1615428744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1615428744
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.3108718125
Short name T868
Test name
Test status
Simulation time 77734617 ps
CPU time 4.48 seconds
Started Jun 28 05:28:56 PM PDT 24
Finished Jun 28 05:29:01 PM PDT 24
Peak memory 201856 kb
Host smart-02e98be3-aa97-4bc2-85d7-7e240df29204
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3108718125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3108718125
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2541799103
Short name T74
Test name
Test status
Simulation time 42805647423 ps
CPU time 102.49 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 202012 kb
Host smart-fa33e5e1-070a-41de-9f55-c158298d2aa3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541799103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2541799103
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.807307203
Short name T668
Test name
Test status
Simulation time 7738410558 ps
CPU time 28.52 seconds
Started Jun 28 05:28:56 PM PDT 24
Finished Jun 28 05:29:25 PM PDT 24
Peak memory 202068 kb
Host smart-1b3d5b10-4d39-4f7d-88f9-8168ed4fb6f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=807307203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.807307203
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3854106301
Short name T576
Test name
Test status
Simulation time 82061837 ps
CPU time 5.63 seconds
Started Jun 28 05:28:54 PM PDT 24
Finished Jun 28 05:29:01 PM PDT 24
Peak memory 201880 kb
Host smart-faeff0d4-6bfb-4c51-b93a-1d039abbf9d3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854106301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3854106301
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.3379188940
Short name T464
Test name
Test status
Simulation time 132208360 ps
CPU time 6.19 seconds
Started Jun 28 05:28:56 PM PDT 24
Finished Jun 28 05:29:03 PM PDT 24
Peak memory 202116 kb
Host smart-c40ffbf1-6809-4808-8605-286383b915f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379188940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3379188940
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.848231845
Short name T25
Test name
Test status
Simulation time 50051830 ps
CPU time 1.28 seconds
Started Jun 28 05:28:44 PM PDT 24
Finished Jun 28 05:28:46 PM PDT 24
Peak memory 201900 kb
Host smart-22599b55-fb7e-474a-bafb-9ed57b13eaa7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=848231845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.848231845
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.106338429
Short name T147
Test name
Test status
Simulation time 1916463630 ps
CPU time 9.56 seconds
Started Jun 28 05:28:59 PM PDT 24
Finished Jun 28 05:29:09 PM PDT 24
Peak memory 201856 kb
Host smart-da0317e4-7947-452a-8550-8fade0a0117d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=106338429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.106338429
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3693355689
Short name T358
Test name
Test status
Simulation time 3831040279 ps
CPU time 9.71 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:29:05 PM PDT 24
Peak memory 202008 kb
Host smart-11be7cdc-49e8-438f-930d-27f8d2a42e1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3693355689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3693355689
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1377547961
Short name T734
Test name
Test status
Simulation time 13526014 ps
CPU time 1.16 seconds
Started Jun 28 05:28:43 PM PDT 24
Finished Jun 28 05:28:45 PM PDT 24
Peak memory 201836 kb
Host smart-798f9d93-453d-4600-83d0-424ded49263c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377547961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1377547961
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3070379489
Short name T646
Test name
Test status
Simulation time 626550869 ps
CPU time 6.81 seconds
Started Jun 28 05:28:56 PM PDT 24
Finished Jun 28 05:29:03 PM PDT 24
Peak memory 201868 kb
Host smart-c4b89fa1-eac7-403d-9fe3-7d724bc0ffa9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3070379489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3070379489
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3073503114
Short name T168
Test name
Test status
Simulation time 315346523 ps
CPU time 23.12 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:29:19 PM PDT 24
Peak memory 201964 kb
Host smart-9d22c0ac-0515-4aee-9ab1-c0ad58b1ea82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3073503114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3073503114
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.4052013528
Short name T222
Test name
Test status
Simulation time 697594453 ps
CPU time 51.9 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:29:47 PM PDT 24
Peak memory 204496 kb
Host smart-1e6aab7b-ff53-48b8-a31f-e8cfa0f87cdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4052013528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.4052013528
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1475720975
Short name T225
Test name
Test status
Simulation time 335194648 ps
CPU time 42.12 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:40 PM PDT 24
Peak memory 203180 kb
Host smart-eb57b051-36d9-4bff-8c6e-e98e95788e5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1475720975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.1475720975
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3321449456
Short name T597
Test name
Test status
Simulation time 70411883 ps
CPU time 9.41 seconds
Started Jun 28 05:28:54 PM PDT 24
Finished Jun 28 05:29:04 PM PDT 24
Peak memory 201820 kb
Host smart-7d910d9a-f8f6-4140-942d-1177a946d3f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3321449456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3321449456
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3684042964
Short name T457
Test name
Test status
Simulation time 4182166249 ps
CPU time 14.9 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:29:10 PM PDT 24
Peak memory 201952 kb
Host smart-e2113da1-f0c1-4ed0-b905-038db952884a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3684042964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3684042964
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.526965346
Short name T148
Test name
Test status
Simulation time 16691620125 ps
CPU time 105.8 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 202076 kb
Host smart-f75c76cd-ebef-4860-9272-188da675505a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=526965346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.526965346
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4246009587
Short name T107
Test name
Test status
Simulation time 86540233 ps
CPU time 2.18 seconds
Started Jun 28 05:28:53 PM PDT 24
Finished Jun 28 05:28:56 PM PDT 24
Peak memory 201872 kb
Host smart-2aaf9dd8-fda7-43e4-baf8-4d68dca1a8cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4246009587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4246009587
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.716275113
Short name T266
Test name
Test status
Simulation time 945870605 ps
CPU time 12.21 seconds
Started Jun 28 05:28:58 PM PDT 24
Finished Jun 28 05:29:11 PM PDT 24
Peak memory 201912 kb
Host smart-7cd0d343-207a-4c2a-a204-de54dd34b1f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=716275113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.716275113
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.1068433531
Short name T40
Test name
Test status
Simulation time 8631156 ps
CPU time 1.23 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:28:57 PM PDT 24
Peak memory 201904 kb
Host smart-1a0d8b6c-a7ea-4609-99e2-e9f875340dbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1068433531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1068433531
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.88884522
Short name T731
Test name
Test status
Simulation time 35081436386 ps
CPU time 146.79 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:31:22 PM PDT 24
Peak memory 202004 kb
Host smart-9c642b0a-92c0-4167-b7b2-fd1a8ebe8483
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=88884522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.88884522
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1496034679
Short name T87
Test name
Test status
Simulation time 1206690892 ps
CPU time 9.94 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:29:06 PM PDT 24
Peak memory 201864 kb
Host smart-1619c6e7-ec37-412a-b170-b204ff91c4fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1496034679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1496034679
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1432600999
Short name T704
Test name
Test status
Simulation time 52821403 ps
CPU time 5.16 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:03 PM PDT 24
Peak memory 201864 kb
Host smart-d5bb4f2b-256a-4007-bcc8-87fbde72d9df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432600999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1432600999
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.531557531
Short name T845
Test name
Test status
Simulation time 94872620 ps
CPU time 5.83 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:04 PM PDT 24
Peak memory 201896 kb
Host smart-03ce88ff-3428-4ec6-823d-70adb3110a05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=531557531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.531557531
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1227731483
Short name T518
Test name
Test status
Simulation time 173993920 ps
CPU time 1.66 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:00 PM PDT 24
Peak memory 201900 kb
Host smart-da122ff7-4d28-441e-9d44-8a99fdb808c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1227731483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1227731483
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2941894356
Short name T648
Test name
Test status
Simulation time 11259888135 ps
CPU time 9.24 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:07 PM PDT 24
Peak memory 202028 kb
Host smart-630b44d8-a6c4-451f-882b-69a50fb0b8a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941894356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2941894356
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1996003091
Short name T859
Test name
Test status
Simulation time 1196110122 ps
CPU time 8.32 seconds
Started Jun 28 05:28:55 PM PDT 24
Finished Jun 28 05:29:04 PM PDT 24
Peak memory 201948 kb
Host smart-f3e05f29-9c64-4ec4-802c-e48e998eb47c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1996003091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1996003091
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2553725134
Short name T153
Test name
Test status
Simulation time 34826187 ps
CPU time 1.27 seconds
Started Jun 28 05:28:59 PM PDT 24
Finished Jun 28 05:29:01 PM PDT 24
Peak memory 201904 kb
Host smart-800841e9-18cb-4acf-9cc5-0120205a30af
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553725134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2553725134
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1197594845
Short name T879
Test name
Test status
Simulation time 360694334 ps
CPU time 60.28 seconds
Started Jun 28 05:28:59 PM PDT 24
Finished Jun 28 05:29:59 PM PDT 24
Peak memory 201980 kb
Host smart-087e9df6-b470-43d7-83ce-406503193b76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1197594845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1197594845
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4228052446
Short name T722
Test name
Test status
Simulation time 31844569372 ps
CPU time 59.4 seconds
Started Jun 28 05:28:58 PM PDT 24
Finished Jun 28 05:29:58 PM PDT 24
Peak memory 202076 kb
Host smart-50290ae6-8a95-48e2-a2fd-c0a9a9f1ab2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4228052446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4228052446
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3493760702
Short name T364
Test name
Test status
Simulation time 324967232 ps
CPU time 36.84 seconds
Started Jun 28 05:28:53 PM PDT 24
Finished Jun 28 05:29:31 PM PDT 24
Peak memory 204112 kb
Host smart-d7bb76ee-82d5-4c57-b855-eba9b22bd4eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3493760702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3493760702
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2460903636
Short name T226
Test name
Test status
Simulation time 668533189 ps
CPU time 83.88 seconds
Started Jun 28 05:29:13 PM PDT 24
Finished Jun 28 05:30:37 PM PDT 24
Peak memory 205852 kb
Host smart-9166edcb-9e88-4add-86b4-75a9fdef91fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2460903636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2460903636
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1144279484
Short name T589
Test name
Test status
Simulation time 1467335920 ps
CPU time 8.06 seconds
Started Jun 28 05:28:57 PM PDT 24
Finished Jun 28 05:29:06 PM PDT 24
Peak memory 201872 kb
Host smart-d8771e44-6dd7-4e8f-b8b8-752ec9ea8878
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1144279484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1144279484
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2270757491
Short name T78
Test name
Test status
Simulation time 1449548940 ps
CPU time 20.03 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:29:35 PM PDT 24
Peak memory 201896 kb
Host smart-2e56063c-36d8-4653-9eb1-bb2a21e6d2a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2270757491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2270757491
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1592698179
Short name T114
Test name
Test status
Simulation time 16566485062 ps
CPU time 88.96 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:30:45 PM PDT 24
Peak memory 202072 kb
Host smart-76c79a30-44c4-4423-9d2b-a72f5787c58b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1592698179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.1592698179
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2219152329
Short name T664
Test name
Test status
Simulation time 52644441 ps
CPU time 6 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:29:21 PM PDT 24
Peak memory 201868 kb
Host smart-86eb867a-6383-43b2-97a9-958c14cc6825
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219152329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2219152329
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.4072435418
Short name T654
Test name
Test status
Simulation time 98872073 ps
CPU time 3.92 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:29:19 PM PDT 24
Peak memory 201900 kb
Host smart-eb8b5e3e-62b3-447f-8dfc-0b5f6c835ad6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4072435418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4072435418
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.1799692631
Short name T412
Test name
Test status
Simulation time 424122210 ps
CPU time 6.9 seconds
Started Jun 28 05:29:13 PM PDT 24
Finished Jun 28 05:29:20 PM PDT 24
Peak memory 201904 kb
Host smart-feed32d6-bfb5-4a10-9a11-387fe67cb9f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799692631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1799692631
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.410426180
Short name T116
Test name
Test status
Simulation time 23432626041 ps
CPU time 79.05 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:30:35 PM PDT 24
Peak memory 202036 kb
Host smart-077d1e17-ee0e-4bd4-8eac-d9fac135583f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=410426180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.410426180
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.4085878625
Short name T389
Test name
Test status
Simulation time 20490309359 ps
CPU time 81.05 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:30:36 PM PDT 24
Peak memory 202060 kb
Host smart-65af0b06-3451-40fb-b29d-04f1663324e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4085878625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4085878625
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3062914899
Short name T298
Test name
Test status
Simulation time 142601544 ps
CPU time 7.75 seconds
Started Jun 28 05:29:13 PM PDT 24
Finished Jun 28 05:29:22 PM PDT 24
Peak memory 201900 kb
Host smart-e53919c0-9698-4dcb-bc12-cd9045536596
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062914899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3062914899
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3696868652
Short name T443
Test name
Test status
Simulation time 34551717 ps
CPU time 2.02 seconds
Started Jun 28 05:29:16 PM PDT 24
Finished Jun 28 05:29:18 PM PDT 24
Peak memory 201888 kb
Host smart-4aea5965-a514-4cf7-a939-534e30ea6093
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3696868652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3696868652
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.2433849883
Short name T813
Test name
Test status
Simulation time 9838040 ps
CPU time 1.23 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:29:16 PM PDT 24
Peak memory 201904 kb
Host smart-a2ee90d4-23ec-4efc-8ef6-abec70aeebeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2433849883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2433849883
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1041127218
Short name T259
Test name
Test status
Simulation time 5293183316 ps
CPU time 8.86 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 202164 kb
Host smart-a2059a60-d9e9-45d7-890a-513ad9dbfb6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041127218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1041127218
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1744853672
Short name T22
Test name
Test status
Simulation time 1117394973 ps
CPU time 7.73 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 201948 kb
Host smart-9412280e-6e62-474e-8e08-ae7ffca157ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1744853672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1744853672
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2751763109
Short name T608
Test name
Test status
Simulation time 10553177 ps
CPU time 1.27 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:29:17 PM PDT 24
Peak memory 202120 kb
Host smart-0acc6c7a-60a9-4fe3-8d56-3029c5dd74d2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751763109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2751763109
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.757631562
Short name T381
Test name
Test status
Simulation time 364224271 ps
CPU time 51.1 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:30:07 PM PDT 24
Peak memory 203996 kb
Host smart-0c638771-cc64-43b4-bc21-0565d4cbf1cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=757631562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.757631562
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4161041467
Short name T354
Test name
Test status
Simulation time 3014363562 ps
CPU time 50.95 seconds
Started Jun 28 05:29:13 PM PDT 24
Finished Jun 28 05:30:05 PM PDT 24
Peak memory 202036 kb
Host smart-569253e3-0892-4943-a1c9-318c62c64b2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4161041467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4161041467
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2436864247
Short name T326
Test name
Test status
Simulation time 2922419103 ps
CPU time 146.53 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 207852 kb
Host smart-5c844edf-78d1-4aa0-8293-fc6e36641bd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2436864247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.2436864247
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2052192274
Short name T486
Test name
Test status
Simulation time 4896884365 ps
CPU time 126.74 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:31:22 PM PDT 24
Peak memory 206388 kb
Host smart-7d31fad6-2e51-4492-a307-b4b25c10e081
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2052192274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2052192274
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1434794940
Short name T491
Test name
Test status
Simulation time 591597525 ps
CPU time 7.93 seconds
Started Jun 28 05:29:13 PM PDT 24
Finished Jun 28 05:29:22 PM PDT 24
Peak memory 201884 kb
Host smart-697f6564-7ab1-4099-865c-ac99db85a957
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1434794940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1434794940
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.4081254721
Short name T537
Test name
Test status
Simulation time 2696140322 ps
CPU time 15.39 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:45 PM PDT 24
Peak memory 201880 kb
Host smart-7e6bcf96-398e-4993-88e7-5b84fb76f93e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4081254721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4081254721
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.146230776
Short name T212
Test name
Test status
Simulation time 278044024577 ps
CPU time 293.68 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:34:21 PM PDT 24
Peak memory 203092 kb
Host smart-f3eee8f6-0f54-4606-ab7c-5d7ed2cbde8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=146230776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo
w_rsp.146230776
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1920227235
Short name T774
Test name
Test status
Simulation time 46165372 ps
CPU time 4.01 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:29:31 PM PDT 24
Peak memory 201968 kb
Host smart-341662c6-3527-4995-831a-0cac88ae6588
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1920227235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1920227235
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.76471592
Short name T133
Test name
Test status
Simulation time 49506322 ps
CPU time 3.9 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:32 PM PDT 24
Peak memory 201892 kb
Host smart-a0d73530-2e2b-40be-ab5e-bd66c9e2b84a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76471592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.76471592
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1658964909
Short name T780
Test name
Test status
Simulation time 616553180 ps
CPU time 5.98 seconds
Started Jun 28 05:29:16 PM PDT 24
Finished Jun 28 05:29:22 PM PDT 24
Peak memory 201884 kb
Host smart-d58d100f-85be-4786-836b-eaefd9cf99f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658964909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1658964909
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.522505540
Short name T863
Test name
Test status
Simulation time 17147958085 ps
CPU time 34.86 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:30:02 PM PDT 24
Peak memory 202032 kb
Host smart-6dd0c793-a1a8-4051-bb99-2ad96a3ba768
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=522505540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.522505540
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3829893746
Short name T28
Test name
Test status
Simulation time 10781146653 ps
CPU time 76.97 seconds
Started Jun 28 05:29:32 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 201964 kb
Host smart-9712e1fd-c057-4ec2-b079-a43ebee1ec42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3829893746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3829893746
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1963705323
Short name T662
Test name
Test status
Simulation time 40471928 ps
CPU time 3.01 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:31 PM PDT 24
Peak memory 201904 kb
Host smart-647da296-6fff-4b17-9600-079dddb9fbf6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963705323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1963705323
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.394419762
Short name T750
Test name
Test status
Simulation time 898519843 ps
CPU time 11.33 seconds
Started Jun 28 05:29:34 PM PDT 24
Finished Jun 28 05:29:46 PM PDT 24
Peak memory 201916 kb
Host smart-6f52a214-27bf-49a5-8ec3-f081c369adf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=394419762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.394419762
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.1407348638
Short name T334
Test name
Test status
Simulation time 11088545 ps
CPU time 1.17 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:29:17 PM PDT 24
Peak memory 201828 kb
Host smart-7091567b-447a-4c56-8cfe-54a90cc367dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1407348638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1407348638
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1564883437
Short name T502
Test name
Test status
Simulation time 4512393721 ps
CPU time 8.13 seconds
Started Jun 28 05:29:14 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 201932 kb
Host smart-2c6c2132-96fc-41bb-a8c2-d8a71904a960
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564883437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1564883437
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.4120749035
Short name T804
Test name
Test status
Simulation time 949865138 ps
CPU time 7.21 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:29:23 PM PDT 24
Peak memory 201940 kb
Host smart-cb94b280-fd37-46c8-9f0c-f29f94c7db73
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4120749035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.4120749035
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3992484123
Short name T513
Test name
Test status
Simulation time 11781342 ps
CPU time 1.29 seconds
Started Jun 28 05:29:15 PM PDT 24
Finished Jun 28 05:29:17 PM PDT 24
Peak memory 201888 kb
Host smart-a3f0f43a-dbd0-4eef-8645-3b64df017bd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992484123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3992484123
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3108839235
Short name T288
Test name
Test status
Simulation time 419599799 ps
CPU time 5.29 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:29:32 PM PDT 24
Peak memory 201880 kb
Host smart-305c11a0-c13f-462b-87f8-a312fd757bbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3108839235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3108839235
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.879407661
Short name T604
Test name
Test status
Simulation time 8837006955 ps
CPU time 45.05 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:30:13 PM PDT 24
Peak memory 202040 kb
Host smart-8ae1f8ce-d7ca-4823-8a7a-87f9fe588f1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=879407661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.879407661
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.99604006
Short name T672
Test name
Test status
Simulation time 113264280 ps
CPU time 30.74 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:30:08 PM PDT 24
Peak memory 202848 kb
Host smart-e0f6850b-e7ae-4174-8126-bacd8676b5e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99604006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_
reset.99604006
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2540561865
Short name T387
Test name
Test status
Simulation time 1166801408 ps
CPU time 132.57 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 205768 kb
Host smart-0e65daeb-9e4d-439a-9503-4ce0f4d5877f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2540561865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.2540561865
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1547606017
Short name T757
Test name
Test status
Simulation time 1298655617 ps
CPU time 5.61 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:34 PM PDT 24
Peak memory 201816 kb
Host smart-598516be-81fc-4236-b355-ed36d6dcb12b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1547606017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1547606017
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2760686125
Short name T109
Test name
Test status
Simulation time 4347882895 ps
CPU time 17.85 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:29:44 PM PDT 24
Peak memory 202036 kb
Host smart-f622a8a7-1c78-444e-9876-cf5356d4c526
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2760686125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2760686125
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1071355296
Short name T185
Test name
Test status
Simulation time 54952903959 ps
CPU time 176.46 seconds
Started Jun 28 05:29:32 PM PDT 24
Finished Jun 28 05:32:29 PM PDT 24
Peak memory 202992 kb
Host smart-458467b9-a61f-4089-a19f-2dd546e34f79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1071355296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.1071355296
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1572740236
Short name T613
Test name
Test status
Simulation time 17769547 ps
CPU time 1.82 seconds
Started Jun 28 05:29:36 PM PDT 24
Finished Jun 28 05:29:38 PM PDT 24
Peak memory 201948 kb
Host smart-a6ea1994-062d-4e5d-89c7-34eb01a8138b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1572740236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1572740236
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.562468641
Short name T237
Test name
Test status
Simulation time 1121917712 ps
CPU time 8.81 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:29:39 PM PDT 24
Peak memory 201908 kb
Host smart-6664f31a-bb34-4cfa-9191-b3a73e139873
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=562468641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.562468641
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.1205388653
Short name T469
Test name
Test status
Simulation time 234511031 ps
CPU time 9.61 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:39 PM PDT 24
Peak memory 201836 kb
Host smart-962e9e18-e394-4fb6-b325-2cb94e87e514
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1205388653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1205388653
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.734674397
Short name T562
Test name
Test status
Simulation time 15997174693 ps
CPU time 62.31 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:30:33 PM PDT 24
Peak memory 201976 kb
Host smart-c4a7ebb9-35df-4c31-8392-7248f9dc6642
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=734674397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.734674397
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3953878298
Short name T329
Test name
Test status
Simulation time 1341301451 ps
CPU time 10.15 seconds
Started Jun 28 05:29:31 PM PDT 24
Finished Jun 28 05:29:42 PM PDT 24
Peak memory 201936 kb
Host smart-73ea9637-d9d8-4661-b788-4b50fe2f5cf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3953878298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3953878298
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2394587808
Short name T802
Test name
Test status
Simulation time 12779908 ps
CPU time 1.04 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:30 PM PDT 24
Peak memory 201820 kb
Host smart-7c264b0d-4632-4753-880e-999d87dbea61
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394587808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2394587808
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.2733561765
Short name T411
Test name
Test status
Simulation time 89627019 ps
CPU time 5.46 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:34 PM PDT 24
Peak memory 201836 kb
Host smart-cb3d5a28-01d0-4323-aa75-225838f63b08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2733561765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2733561765
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.322132031
Short name T752
Test name
Test status
Simulation time 11825248 ps
CPU time 1.13 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:29 PM PDT 24
Peak memory 202112 kb
Host smart-ec50c671-c421-4918-bae0-4ece816b003d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=322132031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.322132031
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.162225415
Short name T570
Test name
Test status
Simulation time 2039987966 ps
CPU time 8.78 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 201876 kb
Host smart-cffb7fee-618f-434c-9141-d2d4f0c344e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=162225415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.162225415
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2904361979
Short name T380
Test name
Test status
Simulation time 934712868 ps
CPU time 6.59 seconds
Started Jun 28 05:29:30 PM PDT 24
Finished Jun 28 05:29:37 PM PDT 24
Peak memory 201944 kb
Host smart-5b14d717-bc10-4a48-a3e9-d964fd717952
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2904361979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2904361979
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.584574165
Short name T587
Test name
Test status
Simulation time 11765237 ps
CPU time 1.44 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:30 PM PDT 24
Peak memory 201900 kb
Host smart-c821d7d6-7e4c-4299-a4e7-9c15dd4e88ca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584574165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.584574165
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.259652571
Short name T861
Test name
Test status
Simulation time 169031017 ps
CPU time 22.96 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:29:53 PM PDT 24
Peak memory 201840 kb
Host smart-125cc0af-7d50-4b19-84d0-c3ff7329e477
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=259652571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.259652571
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3720993969
Short name T468
Test name
Test status
Simulation time 6920820062 ps
CPU time 111.13 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:31:20 PM PDT 24
Peak memory 203116 kb
Host smart-0a09a585-7532-45cf-8441-91bafb63565f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3720993969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3720993969
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1641078662
Short name T481
Test name
Test status
Simulation time 18713840 ps
CPU time 1.88 seconds
Started Jun 28 05:29:25 PM PDT 24
Finished Jun 28 05:29:27 PM PDT 24
Peak memory 201884 kb
Host smart-9c97e6d1-fb52-42ae-b771-7cfdb84f83cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1641078662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1641078662
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1384892362
Short name T516
Test name
Test status
Simulation time 278046631 ps
CPU time 6.46 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 201912 kb
Host smart-742d7e54-7dd5-4bfd-9f2f-d9a5eb8800b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1384892362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1384892362
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.4224386580
Short name T399
Test name
Test status
Simulation time 56758639774 ps
CPU time 94.85 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:31:04 PM PDT 24
Peak memory 202076 kb
Host smart-8e1405fb-5571-464e-98d6-8fb034adbb8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4224386580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.4224386580
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2854498404
Short name T66
Test name
Test status
Simulation time 805825170 ps
CPU time 11.7 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:29:39 PM PDT 24
Peak memory 201968 kb
Host smart-e8ea08f7-0ed0-4425-9858-85786d24d3f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2854498404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2854498404
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2066732564
Short name T152
Test name
Test status
Simulation time 34240007 ps
CPU time 2.79 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:29:40 PM PDT 24
Peak memory 201820 kb
Host smart-d16fea13-3482-4eef-b1be-9970b3c94f1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2066732564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2066732564
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.4167092101
Short name T676
Test name
Test status
Simulation time 68464528 ps
CPU time 8.64 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:29:47 PM PDT 24
Peak memory 201888 kb
Host smart-751d5d57-85c5-4144-a85a-ed207b92cf8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4167092101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.4167092101
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2474386264
Short name T132
Test name
Test status
Simulation time 12670622314 ps
CPU time 31.94 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:30:00 PM PDT 24
Peak memory 202036 kb
Host smart-66c681ba-3f99-4ef6-874b-a7b05405fc07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474386264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2474386264
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.390577847
Short name T29
Test name
Test status
Simulation time 31000472554 ps
CPU time 54.45 seconds
Started Jun 28 05:29:30 PM PDT 24
Finished Jun 28 05:30:25 PM PDT 24
Peak memory 202060 kb
Host smart-5f4dc7b7-fb48-4a90-900b-9526b7448b17
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=390577847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.390577847
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1935968367
Short name T15
Test name
Test status
Simulation time 156032463 ps
CPU time 4.79 seconds
Started Jun 28 05:29:25 PM PDT 24
Finished Jun 28 05:29:30 PM PDT 24
Peak memory 201892 kb
Host smart-8d48c2a9-384d-4204-81c4-ab606a7b2616
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935968367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1935968367
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.1214137251
Short name T539
Test name
Test status
Simulation time 86908311 ps
CPU time 3.02 seconds
Started Jun 28 05:29:30 PM PDT 24
Finished Jun 28 05:29:34 PM PDT 24
Peak memory 201916 kb
Host smart-d2803f92-f366-4973-bada-721ee9b699ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1214137251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1214137251
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.2201766576
Short name T764
Test name
Test status
Simulation time 9433397 ps
CPU time 1.17 seconds
Started Jun 28 05:29:34 PM PDT 24
Finished Jun 28 05:29:35 PM PDT 24
Peak memory 201900 kb
Host smart-a5631b57-729d-4292-a5ba-0f98a2da611d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2201766576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2201766576
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4145601952
Short name T708
Test name
Test status
Simulation time 3402977951 ps
CPU time 8.46 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:37 PM PDT 24
Peak memory 201884 kb
Host smart-816c1587-33ed-4f19-898b-bd061b48fb87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145601952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4145601952
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1328901942
Short name T362
Test name
Test status
Simulation time 1254310972 ps
CPU time 7.8 seconds
Started Jun 28 05:29:32 PM PDT 24
Finished Jun 28 05:29:40 PM PDT 24
Peak memory 201848 kb
Host smart-7714d573-6880-4806-8358-60ce86045fec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1328901942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1328901942
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.4229668896
Short name T632
Test name
Test status
Simulation time 13920979 ps
CPU time 1.12 seconds
Started Jun 28 05:29:33 PM PDT 24
Finished Jun 28 05:29:35 PM PDT 24
Peak memory 201900 kb
Host smart-2d38f530-a9dd-4699-9067-10328812f4e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229668896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.4229668896
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.4195878754
Short name T105
Test name
Test status
Simulation time 83119318 ps
CPU time 10.38 seconds
Started Jun 28 05:29:30 PM PDT 24
Finished Jun 28 05:29:41 PM PDT 24
Peak memory 201856 kb
Host smart-d662163a-a971-48df-9c7d-49f981b0b29c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4195878754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4195878754
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2199855720
Short name T652
Test name
Test status
Simulation time 493555500 ps
CPU time 45.34 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:30:12 PM PDT 24
Peak memory 204148 kb
Host smart-82bb7d34-c262-48d3-9867-444425a1b9ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2199855720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2199855720
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2314967493
Short name T221
Test name
Test status
Simulation time 1645082603 ps
CPU time 113.67 seconds
Started Jun 28 05:29:27 PM PDT 24
Finished Jun 28 05:31:21 PM PDT 24
Peak memory 204252 kb
Host smart-79e5bd80-e900-4bfb-a862-f46ca895a489
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2314967493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.2314967493
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1272442679
Short name T227
Test name
Test status
Simulation time 553132678 ps
CPU time 56.26 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:30:26 PM PDT 24
Peak memory 203680 kb
Host smart-3bb2a7db-b02a-4fe0-af01-188bf7d3ffb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1272442679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1272442679
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2424628136
Short name T164
Test name
Test status
Simulation time 47997463 ps
CPU time 5.54 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:35 PM PDT 24
Peak memory 201912 kb
Host smart-4aeecd2a-a7a8-46b6-b6ae-45b2cf0da093
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2424628136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2424628136
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3747394615
Short name T97
Test name
Test status
Simulation time 681509670 ps
CPU time 8.93 seconds
Started Jun 28 05:29:33 PM PDT 24
Finished Jun 28 05:29:42 PM PDT 24
Peak memory 201912 kb
Host smart-33c7a3b4-ef97-40f7-838e-8607af06a730
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3747394615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3747394615
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.685237813
Short name T193
Test name
Test status
Simulation time 33653858024 ps
CPU time 207.97 seconds
Started Jun 28 05:29:34 PM PDT 24
Finished Jun 28 05:33:02 PM PDT 24
Peak memory 203096 kb
Host smart-a0e29376-d1b1-49b2-9633-49d145dcb9e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=685237813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo
w_rsp.685237813
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1932100376
Short name T430
Test name
Test status
Simulation time 30958739 ps
CPU time 2.34 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:29:40 PM PDT 24
Peak memory 201952 kb
Host smart-bff8fe2a-a896-4ef4-98b7-01cb9bf47bac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1932100376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1932100376
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.1728386738
Short name T166
Test name
Test status
Simulation time 192934377 ps
CPU time 4.19 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:29:42 PM PDT 24
Peak memory 201920 kb
Host smart-65ede33b-8679-46b0-8f0f-29bfc16433c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1728386738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1728386738
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.654594179
Short name T455
Test name
Test status
Simulation time 302450563 ps
CPU time 3.88 seconds
Started Jun 28 05:29:30 PM PDT 24
Finished Jun 28 05:29:35 PM PDT 24
Peak memory 201916 kb
Host smart-82e65e49-73ce-425e-9525-6658ff7d0565
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=654594179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.654594179
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3052076043
Short name T783
Test name
Test status
Simulation time 27333182077 ps
CPU time 84.97 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:30:55 PM PDT 24
Peak memory 201980 kb
Host smart-b484a86f-0aa6-4cab-b9fc-caef607a60fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052076043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3052076043
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1600659972
Short name T853
Test name
Test status
Simulation time 4132223834 ps
CPU time 29.53 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:59 PM PDT 24
Peak memory 202008 kb
Host smart-65f96e01-e4fd-4251-b492-86f8fe79ba2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1600659972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1600659972
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2770494444
Short name T494
Test name
Test status
Simulation time 31714039 ps
CPU time 2.54 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:32 PM PDT 24
Peak memory 201884 kb
Host smart-0db79e7f-c18f-4a44-9598-c5175e7c465d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770494444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2770494444
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.1104852770
Short name T715
Test name
Test status
Simulation time 665051118 ps
CPU time 9.04 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:29:47 PM PDT 24
Peak memory 201888 kb
Host smart-0e9e19ae-6480-45fc-b0e5-9a0057eb95cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1104852770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1104852770
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1783890964
Short name T705
Test name
Test status
Simulation time 9810457 ps
CPU time 1.13 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:29:28 PM PDT 24
Peak memory 201904 kb
Host smart-99713b9d-e184-4cd3-9ca0-fafe7b940d03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783890964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1783890964
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1227682702
Short name T545
Test name
Test status
Simulation time 2245212313 ps
CPU time 9.24 seconds
Started Jun 28 05:29:26 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 201904 kb
Host smart-db4c5425-3ff4-4ffa-9e18-cc175a2d75ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227682702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1227682702
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.975959127
Short name T867
Test name
Test status
Simulation time 1131549801 ps
CPU time 8.19 seconds
Started Jun 28 05:29:28 PM PDT 24
Finished Jun 28 05:29:37 PM PDT 24
Peak memory 201944 kb
Host smart-3a835745-b71b-4e55-9bc8-42dc0a740ea4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=975959127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.975959127
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3340738231
Short name T827
Test name
Test status
Simulation time 29936541 ps
CPU time 1.27 seconds
Started Jun 28 05:29:29 PM PDT 24
Finished Jun 28 05:29:32 PM PDT 24
Peak memory 201896 kb
Host smart-a31b3cbc-5e12-4c69-a72f-9915d54ee652
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340738231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3340738231
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1343862019
Short name T656
Test name
Test status
Simulation time 228808420 ps
CPU time 30.81 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:30:10 PM PDT 24
Peak memory 201916 kb
Host smart-6629dd83-0958-4ec1-abfa-3b2d594955d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1343862019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1343862019
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2576328730
Short name T577
Test name
Test status
Simulation time 2853222477 ps
CPU time 48.94 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:30:29 PM PDT 24
Peak memory 202012 kb
Host smart-fe5411d9-b44f-4ff5-a1b1-9a9e67540d2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2576328730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2576328730
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.167919768
Short name T700
Test name
Test status
Simulation time 853752236 ps
CPU time 104.45 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:31:23 PM PDT 24
Peak memory 204556 kb
Host smart-c516ff08-0414-4f6e-b136-384e27559cbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=167919768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand
_reset.167919768
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2256958499
Short name T138
Test name
Test status
Simulation time 550268128 ps
CPU time 42.7 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:30:21 PM PDT 24
Peak memory 204012 kb
Host smart-af185641-a994-47fe-9f31-b800194e8375
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2256958499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.2256958499
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2534885735
Short name T36
Test name
Test status
Simulation time 15041854 ps
CPU time 1.08 seconds
Started Jun 28 05:29:42 PM PDT 24
Finished Jun 28 05:29:43 PM PDT 24
Peak memory 201888 kb
Host smart-619b0f3e-9b64-4183-b1cb-5d13f06be8be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2534885735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2534885735
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1949349198
Short name T366
Test name
Test status
Simulation time 36933490 ps
CPU time 6.43 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:29:46 PM PDT 24
Peak memory 201912 kb
Host smart-a264d86c-ec48-4a6a-ada5-ebc4fb3bdd2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1949349198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1949349198
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3817830111
Short name T118
Test name
Test status
Simulation time 83120951011 ps
CPU time 116.31 seconds
Started Jun 28 05:29:41 PM PDT 24
Finished Jun 28 05:31:38 PM PDT 24
Peak memory 201696 kb
Host smart-15da5c48-bb8b-476a-8a16-c87ec185ba77
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3817830111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.3817830111
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2677402773
Short name T543
Test name
Test status
Simulation time 232513931 ps
CPU time 3.62 seconds
Started Jun 28 05:29:40 PM PDT 24
Finished Jun 28 05:29:44 PM PDT 24
Peak memory 201968 kb
Host smart-d9ea18fb-fe8e-4e32-9b0b-6230a925af04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2677402773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2677402773
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.567682473
Short name T557
Test name
Test status
Simulation time 339453584 ps
CPU time 2.99 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:29:43 PM PDT 24
Peak memory 201916 kb
Host smart-25e3269e-c651-4e82-bcec-b256915ac34b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=567682473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.567682473
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.3722680996
Short name T106
Test name
Test status
Simulation time 55523979 ps
CPU time 7.16 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:29:45 PM PDT 24
Peak memory 201896 kb
Host smart-da753440-2379-40c6-aeaf-9621ba7a096e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3722680996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3722680996
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3261833137
Short name T657
Test name
Test status
Simulation time 59511103795 ps
CPU time 49.08 seconds
Started Jun 28 05:29:40 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 202032 kb
Host smart-46366aa9-0b92-467b-800d-920ec66f10a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261833137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3261833137
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3031726286
Short name T150
Test name
Test status
Simulation time 32451309111 ps
CPU time 160.55 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:32:20 PM PDT 24
Peak memory 202064 kb
Host smart-b5e461fa-6d93-451b-9f5f-67f12517ac4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3031726286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3031726286
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2417952246
Short name T723
Test name
Test status
Simulation time 23975501 ps
CPU time 3.99 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:29:43 PM PDT 24
Peak memory 201896 kb
Host smart-dc8a9884-8b36-4fd5-bda8-0762e2831006
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417952246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2417952246
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.2717573752
Short name T665
Test name
Test status
Simulation time 95241556 ps
CPU time 3.22 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:29:44 PM PDT 24
Peak memory 201916 kb
Host smart-aad6d16e-4e16-4373-9a34-45c87457e3b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2717573752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2717573752
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.1467801920
Short name T558
Test name
Test status
Simulation time 11439022 ps
CPU time 1.16 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:29:40 PM PDT 24
Peak memory 201896 kb
Host smart-c47321aa-e04b-45e5-9ae6-0dcad50919f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1467801920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1467801920
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1593640912
Short name T555
Test name
Test status
Simulation time 1655830644 ps
CPU time 8.44 seconds
Started Jun 28 05:29:40 PM PDT 24
Finished Jun 28 05:29:49 PM PDT 24
Peak memory 201808 kb
Host smart-7b3ecbbe-495b-4f6e-87bc-504d689e3017
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593640912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1593640912
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2741467625
Short name T876
Test name
Test status
Simulation time 3156529676 ps
CPU time 5.17 seconds
Started Jun 28 05:29:38 PM PDT 24
Finished Jun 28 05:29:44 PM PDT 24
Peak memory 201988 kb
Host smart-86f19cb2-fda0-4b11-a73b-743b0321ff8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2741467625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2741467625
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2169250116
Short name T242
Test name
Test status
Simulation time 18211807 ps
CPU time 0.97 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:29:40 PM PDT 24
Peak memory 201904 kb
Host smart-ef48064e-ab84-4a57-b469-b32f0def27d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169250116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2169250116
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2568787975
Short name T110
Test name
Test status
Simulation time 7313777143 ps
CPU time 93.18 seconds
Started Jun 28 05:29:42 PM PDT 24
Finished Jun 28 05:31:16 PM PDT 24
Peak memory 204060 kb
Host smart-b582bead-e39c-457d-8f1a-d05ad217e4ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2568787975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2568787975
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2556954295
Short name T410
Test name
Test status
Simulation time 129887761 ps
CPU time 13.83 seconds
Started Jun 28 05:29:41 PM PDT 24
Finished Jun 28 05:29:56 PM PDT 24
Peak memory 201972 kb
Host smart-31b7d476-d460-4952-8c1d-3d86a381d1cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2556954295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2556954295
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.103027329
Short name T8
Test name
Test status
Simulation time 6288458888 ps
CPU time 82.12 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:31:00 PM PDT 24
Peak memory 205212 kb
Host smart-d49792ff-bc3e-4151-a1b6-3912696466cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103027329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand
_reset.103027329
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.945658679
Short name T477
Test name
Test status
Simulation time 31519604 ps
CPU time 3.76 seconds
Started Jun 28 05:29:37 PM PDT 24
Finished Jun 28 05:29:42 PM PDT 24
Peak memory 201964 kb
Host smart-dff5ecc4-3393-4c5a-a2ce-29afb3d64567
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=945658679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_res
et_error.945658679
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3341935938
Short name T517
Test name
Test status
Simulation time 1203238090 ps
CPU time 9.05 seconds
Started Jun 28 05:29:41 PM PDT 24
Finished Jun 28 05:29:51 PM PDT 24
Peak memory 201892 kb
Host smart-880a83f8-8870-4957-bddf-35cea7b04b96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3341935938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3341935938
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3311769538
Short name T79
Test name
Test status
Simulation time 1418396884 ps
CPU time 15.72 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:30:05 PM PDT 24
Peak memory 201820 kb
Host smart-72b837c9-d699-46ac-b515-d35b16fb2665
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3311769538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3311769538
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4155406817
Short name T90
Test name
Test status
Simulation time 35246596007 ps
CPU time 206.11 seconds
Started Jun 28 05:29:50 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 203096 kb
Host smart-64092ff6-34ef-4794-a451-b28a44b0b89d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4155406817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.4155406817
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3084065694
Short name T870
Test name
Test status
Simulation time 129604203 ps
CPU time 7.08 seconds
Started Jun 28 05:29:55 PM PDT 24
Finished Jun 28 05:30:02 PM PDT 24
Peak memory 201968 kb
Host smart-e01af6ae-5f00-41a0-ad54-fc879f795863
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3084065694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3084065694
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.2057359177
Short name T339
Test name
Test status
Simulation time 196648972 ps
CPU time 3.18 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:29:52 PM PDT 24
Peak memory 201920 kb
Host smart-e2126141-2d36-4c6f-9f51-404bc4215823
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2057359177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2057359177
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.3656159548
Short name T437
Test name
Test status
Simulation time 299552325 ps
CPU time 4.93 seconds
Started Jun 28 05:29:41 PM PDT 24
Finished Jun 28 05:29:47 PM PDT 24
Peak memory 201888 kb
Host smart-eaa3de93-b1ee-4829-bb26-e926dc94bb86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656159548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3656159548
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3913106887
Short name T234
Test name
Test status
Simulation time 12598667880 ps
CPU time 43.69 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:30:24 PM PDT 24
Peak memory 202032 kb
Host smart-1f5d2b39-738d-45af-bd7f-856e361c15f1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913106887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3913106887
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1257862137
Short name T16
Test name
Test status
Simulation time 56913767 ps
CPU time 2.96 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:29:43 PM PDT 24
Peak memory 201800 kb
Host smart-689582a3-e70d-4ce8-bde6-2c1fe606e4fd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257862137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1257862137
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.3246781971
Short name T489
Test name
Test status
Simulation time 527849652 ps
CPU time 7.48 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:29:58 PM PDT 24
Peak memory 201912 kb
Host smart-d13bf16f-f2a0-46f0-b2e1-134a10c72170
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3246781971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3246781971
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.1700574120
Short name T347
Test name
Test status
Simulation time 34524113 ps
CPU time 1.44 seconds
Started Jun 28 05:29:36 PM PDT 24
Finished Jun 28 05:29:38 PM PDT 24
Peak memory 201900 kb
Host smart-18d1249f-a67d-45d9-bd81-e41cf5283c79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1700574120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1700574120
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.780386037
Short name T828
Test name
Test status
Simulation time 5434155390 ps
CPU time 7.02 seconds
Started Jun 28 05:29:41 PM PDT 24
Finished Jun 28 05:29:49 PM PDT 24
Peak memory 201644 kb
Host smart-6c9ef04b-b7db-4263-974b-4b624e26c1aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=780386037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.780386037
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3145228026
Short name T900
Test name
Test status
Simulation time 1744459366 ps
CPU time 8.2 seconds
Started Jun 28 05:29:41 PM PDT 24
Finished Jun 28 05:29:50 PM PDT 24
Peak memory 201944 kb
Host smart-ac35307c-24f7-48d3-bb74-acbcbb9276af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3145228026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3145228026
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2185699903
Short name T690
Test name
Test status
Simulation time 9611316 ps
CPU time 1.19 seconds
Started Jun 28 05:29:39 PM PDT 24
Finished Jun 28 05:29:41 PM PDT 24
Peak memory 201896 kb
Host smart-395a128d-9672-4a84-9858-0d79012cdee2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185699903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2185699903
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1320137366
Short name T384
Test name
Test status
Simulation time 1127819573 ps
CPU time 24.86 seconds
Started Jun 28 05:29:52 PM PDT 24
Finished Jun 28 05:30:18 PM PDT 24
Peak memory 202932 kb
Host smart-173c8e29-6705-499f-bd59-02fa99d271d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1320137366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1320137366
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3805977197
Short name T706
Test name
Test status
Simulation time 657962100 ps
CPU time 29.69 seconds
Started Jun 28 05:29:50 PM PDT 24
Finished Jun 28 05:30:21 PM PDT 24
Peak memory 201932 kb
Host smart-01091f4a-e2ee-45ae-8f07-c82c20e02382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3805977197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3805977197
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1723592649
Short name T478
Test name
Test status
Simulation time 2206790062 ps
CPU time 145.41 seconds
Started Jun 28 05:29:52 PM PDT 24
Finished Jun 28 05:32:18 PM PDT 24
Peak memory 205580 kb
Host smart-3fb52b9d-bd4f-45b0-ae2d-486fb33198b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1723592649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.1723592649
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3746918751
Short name T582
Test name
Test status
Simulation time 900865828 ps
CPU time 101.03 seconds
Started Jun 28 05:29:54 PM PDT 24
Finished Jun 28 05:31:36 PM PDT 24
Peak memory 205816 kb
Host smart-24815a3d-6108-4d33-a25e-0427cba36302
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746918751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.3746918751
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1165874677
Short name T480
Test name
Test status
Simulation time 53551756 ps
CPU time 3.03 seconds
Started Jun 28 05:29:51 PM PDT 24
Finished Jun 28 05:29:54 PM PDT 24
Peak memory 201808 kb
Host smart-7911b612-4618-4293-904b-8e3c178077f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1165874677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1165874677
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2490658303
Short name T44
Test name
Test status
Simulation time 256173262 ps
CPU time 11.43 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 201916 kb
Host smart-c72b713e-7f82-44cd-8ee2-c28f03ad1af9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2490658303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2490658303
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4156400336
Short name T547
Test name
Test status
Simulation time 399485201 ps
CPU time 3.51 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:29:54 PM PDT 24
Peak memory 202172 kb
Host smart-f6e5c448-7d48-4b44-a240-368ae8c3792b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4156400336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.4156400336
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.3785771606
Short name T834
Test name
Test status
Simulation time 24960927 ps
CPU time 2.19 seconds
Started Jun 28 05:29:55 PM PDT 24
Finished Jun 28 05:29:58 PM PDT 24
Peak memory 201916 kb
Host smart-fda5263a-d8c3-4ee3-8555-11ee5c19ce82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3785771606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3785771606
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.3622665553
Short name T268
Test name
Test status
Simulation time 19112899 ps
CPU time 2.04 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:29:51 PM PDT 24
Peak memory 201884 kb
Host smart-365caee1-4b8a-45ff-831d-2ec599a964a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3622665553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3622665553
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3010163959
Short name T72
Test name
Test status
Simulation time 31808385629 ps
CPU time 128.24 seconds
Started Jun 28 05:29:53 PM PDT 24
Finished Jun 28 05:32:02 PM PDT 24
Peak memory 202016 kb
Host smart-9eeb0fb6-0674-48c9-af64-28035f85c82a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010163959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3010163959
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3306111219
Short name T497
Test name
Test status
Simulation time 7351395298 ps
CPU time 26.09 seconds
Started Jun 28 05:29:52 PM PDT 24
Finished Jun 28 05:30:19 PM PDT 24
Peak memory 202064 kb
Host smart-664b18ac-1dde-44b8-867f-4fdfd747f358
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3306111219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3306111219
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.3822734664
Short name T796
Test name
Test status
Simulation time 57428569 ps
CPU time 3.06 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:29:52 PM PDT 24
Peak memory 201904 kb
Host smart-648b8b1d-3285-4efc-ae1c-54c643f91122
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822734664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3822734664
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.316883795
Short name T886
Test name
Test status
Simulation time 2714245758 ps
CPU time 12.07 seconds
Started Jun 28 05:29:51 PM PDT 24
Finished Jun 28 05:30:03 PM PDT 24
Peak memory 201976 kb
Host smart-25039f5b-e4c1-4441-979a-e4e0b1b92497
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=316883795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.316883795
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.376426916
Short name T151
Test name
Test status
Simulation time 8510969 ps
CPU time 1.15 seconds
Started Jun 28 05:29:50 PM PDT 24
Finished Jun 28 05:29:52 PM PDT 24
Peak memory 201860 kb
Host smart-74347702-44ae-4370-9139-5d855d966c23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=376426916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.376426916
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1148401981
Short name T592
Test name
Test status
Simulation time 1352549600 ps
CPU time 7.2 seconds
Started Jun 28 05:29:50 PM PDT 24
Finished Jun 28 05:29:58 PM PDT 24
Peak memory 201912 kb
Host smart-136ae9c6-0941-47aa-a2de-3a4b32bb0a94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148401981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1148401981
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1138639469
Short name T786
Test name
Test status
Simulation time 5773425175 ps
CPU time 12.5 seconds
Started Jun 28 05:29:50 PM PDT 24
Finished Jun 28 05:30:03 PM PDT 24
Peak memory 201980 kb
Host smart-9a47fa4b-2041-48a4-b8ba-0d01b85f6356
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1138639469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1138639469
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1088754279
Short name T250
Test name
Test status
Simulation time 9732552 ps
CPU time 1.25 seconds
Started Jun 28 05:29:54 PM PDT 24
Finished Jun 28 05:29:56 PM PDT 24
Peak memory 201884 kb
Host smart-28ddcd3d-f9a8-4f42-b424-0f70e10380ff
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088754279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1088754279
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3661076442
Short name T201
Test name
Test status
Simulation time 8034645893 ps
CPU time 79.27 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:31:08 PM PDT 24
Peak memory 203212 kb
Host smart-5e75be55-1afb-40f6-943c-986933cb08d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3661076442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3661076442
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.445375072
Short name T402
Test name
Test status
Simulation time 4869700813 ps
CPU time 72.79 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:31:02 PM PDT 24
Peak memory 201948 kb
Host smart-7e5b2019-e9f8-444f-80fb-9b4a497e28d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=445375072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.445375072
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1272509254
Short name T37
Test name
Test status
Simulation time 6729187197 ps
CPU time 112.6 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 205340 kb
Host smart-8599a46b-334c-4152-a026-96f57788eadd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1272509254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1272509254
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2698667880
Short name T837
Test name
Test status
Simulation time 2199213384 ps
CPU time 87.5 seconds
Started Jun 28 05:29:51 PM PDT 24
Finished Jun 28 05:31:19 PM PDT 24
Peak memory 204548 kb
Host smart-201eaae7-9ace-42b4-ba7a-c0a425840e9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2698667880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.2698667880
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3655954458
Short name T687
Test name
Test status
Simulation time 14492952 ps
CPU time 1.98 seconds
Started Jun 28 05:29:47 PM PDT 24
Finished Jun 28 05:29:50 PM PDT 24
Peak memory 201912 kb
Host smart-4ed6e886-d266-4ac3-8cbf-267876846e38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3655954458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3655954458
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3281588049
Short name T397
Test name
Test status
Simulation time 50969732 ps
CPU time 8.97 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:24:05 PM PDT 24
Peak memory 201916 kb
Host smart-b5680e4d-7f4b-4698-9000-5eb06a24276e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281588049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3281588049
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2973600860
Short name T479
Test name
Test status
Simulation time 60386521 ps
CPU time 7.34 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:24:02 PM PDT 24
Peak memory 201964 kb
Host smart-634816ab-9aa1-4d6a-b384-8158e3c64af8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2973600860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2973600860
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.1982236495
Short name T762
Test name
Test status
Simulation time 391981114 ps
CPU time 5.92 seconds
Started Jun 28 05:23:59 PM PDT 24
Finished Jun 28 05:24:05 PM PDT 24
Peak memory 201896 kb
Host smart-658dc29e-04e9-4ea8-9817-06e41961618a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1982236495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1982236495
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.1605162912
Short name T462
Test name
Test status
Simulation time 94184214 ps
CPU time 7.63 seconds
Started Jun 28 05:23:56 PM PDT 24
Finished Jun 28 05:24:04 PM PDT 24
Peak memory 201904 kb
Host smart-359100fe-8493-4d16-9a8f-c0ee15d394fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1605162912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1605162912
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3023932164
Short name T756
Test name
Test status
Simulation time 20714761635 ps
CPU time 93.45 seconds
Started Jun 28 05:23:53 PM PDT 24
Finished Jun 28 05:25:27 PM PDT 24
Peak memory 202044 kb
Host smart-686b1646-2955-47a0-8a84-290647d916c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023932164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3023932164
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2919318080
Short name T296
Test name
Test status
Simulation time 30865135388 ps
CPU time 134.96 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:26:11 PM PDT 24
Peak memory 201964 kb
Host smart-30eb1515-82d4-479f-8e11-615c814974eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2919318080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2919318080
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1184953562
Short name T161
Test name
Test status
Simulation time 49907374 ps
CPU time 6.25 seconds
Started Jun 28 05:23:53 PM PDT 24
Finished Jun 28 05:24:00 PM PDT 24
Peak memory 201900 kb
Host smart-52457926-b4cf-40e1-b4e3-c3cab2df3c3f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184953562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1184953562
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.1577965465
Short name T673
Test name
Test status
Simulation time 291915348 ps
CPU time 4.65 seconds
Started Jun 28 05:23:54 PM PDT 24
Finished Jun 28 05:23:59 PM PDT 24
Peak memory 201916 kb
Host smart-c887d7ef-0593-4cfc-9cd6-4cf4e013fdc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1577965465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1577965465
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1398642583
Short name T609
Test name
Test status
Simulation time 9983647 ps
CPU time 1.2 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:23:56 PM PDT 24
Peak memory 201908 kb
Host smart-d27a52bf-ee9c-4ecb-8417-a8a2defad90b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1398642583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1398642583
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2274535833
Short name T569
Test name
Test status
Simulation time 2469753069 ps
CPU time 8.86 seconds
Started Jun 28 05:23:54 PM PDT 24
Finished Jun 28 05:24:03 PM PDT 24
Peak memory 201952 kb
Host smart-fcf90590-3310-41f8-b612-68b6d822b41a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274535833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2274535833
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.917007997
Short name T429
Test name
Test status
Simulation time 1274944489 ps
CPU time 6.19 seconds
Started Jun 28 05:23:54 PM PDT 24
Finished Jun 28 05:24:01 PM PDT 24
Peak memory 201908 kb
Host smart-3a208642-4739-40bf-abb3-3444a67b066d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=917007997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.917007997
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4190738168
Short name T444
Test name
Test status
Simulation time 8677931 ps
CPU time 1.06 seconds
Started Jun 28 05:23:54 PM PDT 24
Finished Jun 28 05:23:55 PM PDT 24
Peak memory 201904 kb
Host smart-7b4f4f93-3c93-4e0d-9125-a7b4880f8f71
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190738168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4190738168
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3830047186
Short name T686
Test name
Test status
Simulation time 239356554 ps
CPU time 34.32 seconds
Started Jun 28 05:24:06 PM PDT 24
Finished Jun 28 05:24:41 PM PDT 24
Peak memory 203076 kb
Host smart-752f82d2-dca0-4c16-a400-51823c01baf1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3830047186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3830047186
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2958483514
Short name T267
Test name
Test status
Simulation time 3201630491 ps
CPU time 58.9 seconds
Started Jun 28 05:24:04 PM PDT 24
Finished Jun 28 05:25:04 PM PDT 24
Peak memory 202252 kb
Host smart-06ca3a81-3bee-4a15-a768-67fa60f52d7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2958483514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2958483514
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3579217247
Short name T663
Test name
Test status
Simulation time 5525363905 ps
CPU time 74.34 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:25:21 PM PDT 24
Peak memory 204816 kb
Host smart-b2630383-2593-4dad-a09b-847d647f250b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3579217247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3579217247
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.612320571
Short name T27
Test name
Test status
Simulation time 804318224 ps
CPU time 11.86 seconds
Started Jun 28 05:23:55 PM PDT 24
Finished Jun 28 05:24:08 PM PDT 24
Peak memory 201816 kb
Host smart-4384ac4a-9746-4fad-b939-7abc928a118b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=612320571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.612320571
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2819929511
Short name T522
Test name
Test status
Simulation time 657032683 ps
CPU time 15.08 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:24:21 PM PDT 24
Peak memory 201916 kb
Host smart-95b71ca8-edb1-4754-b23e-cfb056296357
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819929511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2819929511
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1034622072
Short name T119
Test name
Test status
Simulation time 66068371976 ps
CPU time 207.34 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:27:33 PM PDT 24
Peak memory 203284 kb
Host smart-bc01a639-f40e-43b3-aac8-5d763720b966
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1034622072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.1034622072
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.199891728
Short name T38
Test name
Test status
Simulation time 2893773477 ps
CPU time 8.88 seconds
Started Jun 28 05:24:06 PM PDT 24
Finished Jun 28 05:24:15 PM PDT 24
Peak memory 202020 kb
Host smart-0fc23cd2-9af5-4295-9a0b-03cc17081d80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=199891728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.199891728
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.688115819
Short name T560
Test name
Test status
Simulation time 1774769688 ps
CPU time 13.09 seconds
Started Jun 28 05:24:06 PM PDT 24
Finished Jun 28 05:24:20 PM PDT 24
Peak memory 201912 kb
Host smart-e7b05e6a-cdf4-47e9-8361-a16ee71b5117
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=688115819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.688115819
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.1066245847
Short name T784
Test name
Test status
Simulation time 87657900 ps
CPU time 8.43 seconds
Started Jun 28 05:24:04 PM PDT 24
Finished Jun 28 05:24:12 PM PDT 24
Peak memory 201844 kb
Host smart-ca58df2e-7c40-4a1b-9465-25d22f0e38fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1066245847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1066245847
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4021762439
Short name T866
Test name
Test status
Simulation time 26731522839 ps
CPU time 125.52 seconds
Started Jun 28 05:24:04 PM PDT 24
Finished Jun 28 05:26:10 PM PDT 24
Peak memory 202036 kb
Host smart-034e9721-2172-4f45-84bd-878244410e9d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021762439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4021762439
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3126554517
Short name T748
Test name
Test status
Simulation time 21218872634 ps
CPU time 74.4 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:25:21 PM PDT 24
Peak memory 202068 kb
Host smart-6757a90f-d100-46c4-a94a-9dc8d763349f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3126554517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3126554517
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2740916573
Short name T386
Test name
Test status
Simulation time 65981325 ps
CPU time 5.09 seconds
Started Jun 28 05:24:07 PM PDT 24
Finished Jun 28 05:24:12 PM PDT 24
Peak memory 201904 kb
Host smart-be1c314b-8d11-4af7-80d0-5ad7ccc9d912
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740916573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2740916573
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.2246142993
Short name T546
Test name
Test status
Simulation time 63974199 ps
CPU time 4.14 seconds
Started Jun 28 05:24:09 PM PDT 24
Finished Jun 28 05:24:14 PM PDT 24
Peak memory 201916 kb
Host smart-3c507841-1446-4d8e-8bc4-a1c7edfbaf64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2246142993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2246142993
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.3220140151
Short name T532
Test name
Test status
Simulation time 45269758 ps
CPU time 1.27 seconds
Started Jun 28 05:24:08 PM PDT 24
Finished Jun 28 05:24:11 PM PDT 24
Peak memory 201892 kb
Host smart-324f6eb7-e688-4952-bd58-e812eaec3ae5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3220140151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3220140151
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.616570372
Short name T568
Test name
Test status
Simulation time 2407110536 ps
CPU time 11.32 seconds
Started Jun 28 05:24:03 PM PDT 24
Finished Jun 28 05:24:15 PM PDT 24
Peak memory 201936 kb
Host smart-a39dc960-6146-4326-9c14-e319ac0a5432
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=616570372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.616570372
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3911150435
Short name T793
Test name
Test status
Simulation time 2395920509 ps
CPU time 12.49 seconds
Started Jun 28 05:24:09 PM PDT 24
Finished Jun 28 05:24:22 PM PDT 24
Peak memory 202004 kb
Host smart-7f97fd58-02f7-43fb-95d7-924c8f68d9df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3911150435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3911150435
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2365004614
Short name T409
Test name
Test status
Simulation time 8823015 ps
CPU time 1.4 seconds
Started Jun 28 05:24:06 PM PDT 24
Finished Jun 28 05:24:08 PM PDT 24
Peak memory 201904 kb
Host smart-a02be4a1-7337-460b-9a6b-ed47910def97
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365004614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2365004614
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4205203455
Short name T724
Test name
Test status
Simulation time 3348975972 ps
CPU time 47.06 seconds
Started Jun 28 05:24:03 PM PDT 24
Finished Jun 28 05:24:51 PM PDT 24
Peak memory 202920 kb
Host smart-667a466b-c595-46ac-a55d-8f9fbceedbb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4205203455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4205203455
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.560351342
Short name T775
Test name
Test status
Simulation time 280756815 ps
CPU time 23.55 seconds
Started Jun 28 05:24:08 PM PDT 24
Finished Jun 28 05:24:32 PM PDT 24
Peak memory 201892 kb
Host smart-7b242f68-c6ee-4c89-ad2b-26927b75ec48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=560351342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.560351342
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2207701585
Short name T779
Test name
Test status
Simulation time 296365266 ps
CPU time 53.61 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:24:59 PM PDT 24
Peak memory 204220 kb
Host smart-8e9b5ed4-fc84-4054-958b-20c0c7327292
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2207701585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.2207701585
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.306701419
Short name T200
Test name
Test status
Simulation time 14279331582 ps
CPU time 208.95 seconds
Started Jun 28 05:24:04 PM PDT 24
Finished Jun 28 05:27:34 PM PDT 24
Peak memory 208092 kb
Host smart-13ed9038-7de7-492d-a2cf-22f784d35192
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=306701419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese
t_error.306701419
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.456835880
Short name T590
Test name
Test status
Simulation time 274987193 ps
CPU time 5.92 seconds
Started Jun 28 05:24:08 PM PDT 24
Finished Jun 28 05:24:15 PM PDT 24
Peak memory 201896 kb
Host smart-56780da8-844f-4855-8d08-870558944e62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=456835880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.456835880
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3256773464
Short name T217
Test name
Test status
Simulation time 170063276 ps
CPU time 1.56 seconds
Started Jun 28 05:24:20 PM PDT 24
Finished Jun 28 05:24:22 PM PDT 24
Peak memory 201912 kb
Host smart-ba4de38b-47c0-4cad-8e9f-0e57a7984514
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3256773464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3256773464
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1122697015
Short name T214
Test name
Test status
Simulation time 14932551486 ps
CPU time 91.42 seconds
Started Jun 28 05:24:16 PM PDT 24
Finished Jun 28 05:25:47 PM PDT 24
Peak memory 202040 kb
Host smart-b37f4c97-fded-4462-a351-ea053d48514c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1122697015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.1122697015
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1545989706
Short name T720
Test name
Test status
Simulation time 197648590 ps
CPU time 4.26 seconds
Started Jun 28 05:24:17 PM PDT 24
Finished Jun 28 05:24:22 PM PDT 24
Peak memory 201912 kb
Host smart-707c5c5f-5a78-4406-8441-268bed846e73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1545989706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1545989706
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3643975075
Short name T482
Test name
Test status
Simulation time 68734524 ps
CPU time 4.15 seconds
Started Jun 28 05:24:17 PM PDT 24
Finished Jun 28 05:24:22 PM PDT 24
Peak memory 201920 kb
Host smart-4156f846-cd0e-4b70-aaab-1ea690c39f99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3643975075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3643975075
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.3243130954
Short name T571
Test name
Test status
Simulation time 283702629 ps
CPU time 10.45 seconds
Started Jun 28 05:24:07 PM PDT 24
Finished Jun 28 05:24:18 PM PDT 24
Peak memory 201908 kb
Host smart-0ffbeb69-936b-4fe6-a39d-b63478da10f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3243130954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3243130954
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.889020712
Short name T640
Test name
Test status
Simulation time 45443698010 ps
CPU time 159.96 seconds
Started Jun 28 05:24:19 PM PDT 24
Finished Jun 28 05:26:59 PM PDT 24
Peak memory 202040 kb
Host smart-6f1690e4-a224-4d37-a404-c5dfa398a047
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=889020712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.889020712
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4033951734
Short name T638
Test name
Test status
Simulation time 29294433858 ps
CPU time 175.73 seconds
Started Jun 28 05:24:17 PM PDT 24
Finished Jun 28 05:27:13 PM PDT 24
Peak memory 202068 kb
Host smart-36065222-0d93-4f79-b1dd-4d972097b41d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4033951734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4033951734
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.418121345
Short name T741
Test name
Test status
Simulation time 248540269 ps
CPU time 6.15 seconds
Started Jun 28 05:24:18 PM PDT 24
Finished Jun 28 05:24:25 PM PDT 24
Peak memory 201860 kb
Host smart-635e3c6c-7725-415c-aa2b-ba0edde31202
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418121345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.418121345
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.4177226103
Short name T531
Test name
Test status
Simulation time 127868409 ps
CPU time 2.23 seconds
Started Jun 28 05:24:19 PM PDT 24
Finished Jun 28 05:24:21 PM PDT 24
Peak memory 201836 kb
Host smart-ecb84cd1-9740-47c6-803d-23b90f5261d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4177226103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4177226103
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.486640661
Short name T603
Test name
Test status
Simulation time 56628485 ps
CPU time 1.56 seconds
Started Jun 28 05:24:05 PM PDT 24
Finished Jun 28 05:24:07 PM PDT 24
Peak memory 201908 kb
Host smart-be1f1e8d-9c2c-4340-9c03-72ecce7780b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=486640661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.486640661
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3167662958
Short name T871
Test name
Test status
Simulation time 2329256948 ps
CPU time 7.51 seconds
Started Jun 28 05:24:09 PM PDT 24
Finished Jun 28 05:24:17 PM PDT 24
Peak memory 201956 kb
Host smart-acb3f62a-06a3-4ddd-b883-02c90dc74491
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167662958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3167662958
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.519928419
Short name T572
Test name
Test status
Simulation time 840065564 ps
CPU time 4.17 seconds
Started Jun 28 05:24:04 PM PDT 24
Finished Jun 28 05:24:09 PM PDT 24
Peak memory 201888 kb
Host smart-bc7da2de-dca8-4e33-87b5-d8983cb763d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=519928419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.519928419
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3368333547
Short name T349
Test name
Test status
Simulation time 12902306 ps
CPU time 1.21 seconds
Started Jun 28 05:24:09 PM PDT 24
Finished Jun 28 05:24:11 PM PDT 24
Peak memory 201904 kb
Host smart-df44ae2a-75a4-46d1-a2a5-fa66e5e10ff2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368333547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3368333547
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.4020004791
Short name T484
Test name
Test status
Simulation time 11237115016 ps
CPU time 67.14 seconds
Started Jun 28 05:24:20 PM PDT 24
Finished Jun 28 05:25:28 PM PDT 24
Peak memory 205492 kb
Host smart-0bf87b7e-9c07-414d-93ee-acc2aa6d94f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4020004791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4020004791
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1211775939
Short name T145
Test name
Test status
Simulation time 499931418 ps
CPU time 42.44 seconds
Started Jun 28 05:24:17 PM PDT 24
Finished Jun 28 05:25:01 PM PDT 24
Peak memory 201920 kb
Host smart-3a0ce254-5fab-497f-af60-9493a024995f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1211775939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1211775939
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1847162547
Short name T435
Test name
Test status
Simulation time 1216097989 ps
CPU time 149.44 seconds
Started Jun 28 05:24:18 PM PDT 24
Finished Jun 28 05:26:48 PM PDT 24
Peak memory 205392 kb
Host smart-fb360aa3-4c91-400a-a1c4-bc689cef269b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1847162547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.1847162547
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3267518137
Short name T10
Test name
Test status
Simulation time 11885441327 ps
CPU time 100.01 seconds
Started Jun 28 05:24:18 PM PDT 24
Finished Jun 28 05:25:58 PM PDT 24
Peak memory 205536 kb
Host smart-7bc48ffc-1f08-442f-a2a1-f272abfcd3bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3267518137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.3267518137
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1333075308
Short name T255
Test name
Test status
Simulation time 223780568 ps
CPU time 4.27 seconds
Started Jun 28 05:24:19 PM PDT 24
Finished Jun 28 05:24:24 PM PDT 24
Peak memory 201916 kb
Host smart-f215b9c0-0a0a-4e4b-8f40-081764ab8d3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1333075308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1333075308
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3352249307
Short name T677
Test name
Test status
Simulation time 61298145 ps
CPU time 9.01 seconds
Started Jun 28 05:24:30 PM PDT 24
Finished Jun 28 05:24:39 PM PDT 24
Peak memory 201916 kb
Host smart-be6410b2-6540-4dcf-9d10-be96528cfd6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3352249307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3352249307
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1107164130
Short name T76
Test name
Test status
Simulation time 30378970831 ps
CPU time 44.59 seconds
Started Jun 28 05:24:41 PM PDT 24
Finished Jun 28 05:25:26 PM PDT 24
Peak memory 202068 kb
Host smart-174dd7d6-a198-450a-9b5f-1228bf97dd0a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1107164130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.1107164130
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2617039866
Short name T611
Test name
Test status
Simulation time 13443814 ps
CPU time 1.37 seconds
Started Jun 28 05:24:42 PM PDT 24
Finished Jun 28 05:24:44 PM PDT 24
Peak memory 201960 kb
Host smart-08f63956-0753-4878-8968-37a7c4727fb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2617039866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2617039866
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.3011164466
Short name T742
Test name
Test status
Simulation time 48483619 ps
CPU time 2.17 seconds
Started Jun 28 05:24:40 PM PDT 24
Finished Jun 28 05:24:43 PM PDT 24
Peak memory 201916 kb
Host smart-d748a694-93ce-4ef9-a8d8-c85d9a9e5e75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3011164466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3011164466
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.2423203631
Short name T666
Test name
Test status
Simulation time 1655491917 ps
CPU time 8.17 seconds
Started Jun 28 05:24:30 PM PDT 24
Finished Jun 28 05:24:38 PM PDT 24
Peak memory 201904 kb
Host smart-dbb25af7-363f-47eb-8c08-d7feedfe0c75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2423203631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2423203631
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1406193932
Short name T157
Test name
Test status
Simulation time 154956952673 ps
CPU time 132.03 seconds
Started Jun 28 05:24:40 PM PDT 24
Finished Jun 28 05:26:53 PM PDT 24
Peak memory 202036 kb
Host smart-9d00bc32-3f32-4e65-aeb3-68bcfdcc05bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406193932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1406193932
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.4215836787
Short name T417
Test name
Test status
Simulation time 11815836102 ps
CPU time 50.6 seconds
Started Jun 28 05:24:40 PM PDT 24
Finished Jun 28 05:25:31 PM PDT 24
Peak memory 202040 kb
Host smart-e1ff75da-da78-48ff-93a9-96d60d2105cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4215836787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4215836787
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.355013054
Short name T524
Test name
Test status
Simulation time 30151672 ps
CPU time 5.14 seconds
Started Jun 28 05:24:42 PM PDT 24
Finished Jun 28 05:24:48 PM PDT 24
Peak memory 201904 kb
Host smart-7d492837-4d85-4374-91d2-16edb47ba3fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355013054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.355013054
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.3884550273
Short name T771
Test name
Test status
Simulation time 41567260 ps
CPU time 4.8 seconds
Started Jun 28 05:24:31 PM PDT 24
Finished Jun 28 05:24:36 PM PDT 24
Peak memory 201816 kb
Host smart-6b138571-b1d2-43d0-8f03-f3ef7a529301
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3884550273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3884550273
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.1648978342
Short name T667
Test name
Test status
Simulation time 16289054 ps
CPU time 1.26 seconds
Started Jun 28 05:24:18 PM PDT 24
Finished Jun 28 05:24:20 PM PDT 24
Peak memory 201808 kb
Host smart-b2c3def4-d0de-4723-bf9b-653e0ce34dfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1648978342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1648978342
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2260612165
Short name T82
Test name
Test status
Simulation time 2776491103 ps
CPU time 9.42 seconds
Started Jun 28 05:24:18 PM PDT 24
Finished Jun 28 05:24:28 PM PDT 24
Peak memory 201952 kb
Host smart-14fa7f93-3f0f-4a89-b3d1-bbc0f188bbf8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260612165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2260612165
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3184410700
Short name T821
Test name
Test status
Simulation time 2109356080 ps
CPU time 6.7 seconds
Started Jun 28 05:24:17 PM PDT 24
Finished Jun 28 05:24:25 PM PDT 24
Peak memory 201948 kb
Host smart-a1689fa3-a00b-45f4-b460-4a789d9740f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3184410700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3184410700
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2552486823
Short name T423
Test name
Test status
Simulation time 9862173 ps
CPU time 1.47 seconds
Started Jun 28 05:24:17 PM PDT 24
Finished Jun 28 05:24:19 PM PDT 24
Peak memory 201872 kb
Host smart-45955e6d-2d62-44dd-9d85-20e5c8261639
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552486823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2552486823
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1922391835
Short name T496
Test name
Test status
Simulation time 16605692811 ps
CPU time 65.16 seconds
Started Jun 28 05:24:39 PM PDT 24
Finished Jun 28 05:25:45 PM PDT 24
Peak memory 205644 kb
Host smart-c9b18e52-8e93-4e65-af9e-3ae4bd3ca819
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1922391835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1922391835
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3655571588
Short name T279
Test name
Test status
Simulation time 260803036 ps
CPU time 30.84 seconds
Started Jun 28 05:24:40 PM PDT 24
Finished Jun 28 05:25:12 PM PDT 24
Peak memory 201904 kb
Host smart-f77f61cf-c0f4-4f1f-a319-d7ed9240b270
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3655571588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3655571588
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3784639454
Short name T390
Test name
Test status
Simulation time 2589991421 ps
CPU time 75.99 seconds
Started Jun 28 05:24:42 PM PDT 24
Finished Jun 28 05:25:58 PM PDT 24
Peak memory 205524 kb
Host smart-ac0a4b69-e3dc-404d-aa8a-2b06fe78d35c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3784639454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.3784639454
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.153025693
Short name T11
Test name
Test status
Simulation time 3477302211 ps
CPU time 114.68 seconds
Started Jun 28 05:24:39 PM PDT 24
Finished Jun 28 05:26:35 PM PDT 24
Peak memory 206836 kb
Host smart-46acf670-0d99-4671-8f67-9d73dc7c4f62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=153025693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese
t_error.153025693
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2499438501
Short name T269
Test name
Test status
Simulation time 893775900 ps
CPU time 12.44 seconds
Started Jun 28 05:24:41 PM PDT 24
Finished Jun 28 05:24:54 PM PDT 24
Peak memory 201832 kb
Host smart-c4b11639-d82f-4d7c-8771-1e25859ff1b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2499438501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2499438501
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1954832837
Short name T31
Test name
Test status
Simulation time 1480762458 ps
CPU time 7.81 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:24:58 PM PDT 24
Peak memory 201908 kb
Host smart-4efbdc61-a6bd-4a9e-81c7-15ee5991064b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954832837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1954832837
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.480242078
Short name T183
Test name
Test status
Simulation time 87239302 ps
CPU time 2.32 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:24:52 PM PDT 24
Peak memory 201928 kb
Host smart-17f3ad11-6afb-44de-b278-0a7934297e2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=480242078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.480242078
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.158313653
Short name T383
Test name
Test status
Simulation time 646544500 ps
CPU time 8.2 seconds
Started Jun 28 05:24:50 PM PDT 24
Finished Jun 28 05:24:59 PM PDT 24
Peak memory 201912 kb
Host smart-0bc029e8-80e9-4f1d-a4fd-a8ff6e78b106
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=158313653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.158313653
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.545748990
Short name T563
Test name
Test status
Simulation time 49111344 ps
CPU time 7.37 seconds
Started Jun 28 05:24:51 PM PDT 24
Finished Jun 28 05:24:59 PM PDT 24
Peak memory 201916 kb
Host smart-d405fcef-22ef-4686-99b2-bcc989e3bd20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=545748990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.545748990
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1017021623
Short name T644
Test name
Test status
Simulation time 2122841676 ps
CPU time 7.57 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:24:57 PM PDT 24
Peak memory 201916 kb
Host smart-87e67056-81d8-49b7-9367-2c209ef35c9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017021623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1017021623
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.602502473
Short name T407
Test name
Test status
Simulation time 49919185264 ps
CPU time 72.18 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:26:02 PM PDT 24
Peak memory 202008 kb
Host smart-e99f1c4b-9b38-4084-91ee-bf38bd24bcfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=602502473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.602502473
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1420659087
Short name T769
Test name
Test status
Simulation time 23863788 ps
CPU time 3.04 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:24:53 PM PDT 24
Peak memory 201904 kb
Host smart-3cd58c4c-c6da-423e-911c-df0fd8ee11e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420659087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1420659087
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3254203253
Short name T181
Test name
Test status
Simulation time 857473831 ps
CPU time 10.83 seconds
Started Jun 28 05:24:50 PM PDT 24
Finished Jun 28 05:25:02 PM PDT 24
Peak memory 201908 kb
Host smart-d8af7a69-eae3-4986-936c-e21cc1220171
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3254203253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3254203253
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.732262408
Short name T883
Test name
Test status
Simulation time 18241300 ps
CPU time 1.1 seconds
Started Jun 28 05:24:41 PM PDT 24
Finished Jun 28 05:24:43 PM PDT 24
Peak memory 201824 kb
Host smart-49c6c28e-b3c2-4a1e-9b1d-2920041654da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=732262408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.732262408
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1441593005
Short name T461
Test name
Test status
Simulation time 2739805563 ps
CPU time 8.38 seconds
Started Jun 28 05:24:41 PM PDT 24
Finished Jun 28 05:24:50 PM PDT 24
Peak memory 201956 kb
Host smart-722c17db-80e3-42bb-9169-17601825911f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441593005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1441593005
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3784805976
Short name T56
Test name
Test status
Simulation time 864575526 ps
CPU time 5.52 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:24:55 PM PDT 24
Peak memory 201848 kb
Host smart-37bc6890-767b-4d1d-a38a-894351518aca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3784805976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3784805976
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.186724041
Short name T39
Test name
Test status
Simulation time 12651400 ps
CPU time 1.32 seconds
Started Jun 28 05:24:32 PM PDT 24
Finished Jun 28 05:24:33 PM PDT 24
Peak memory 201904 kb
Host smart-88a31b37-63c8-4bc8-a050-f3aae93f3d18
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186724041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.186724041
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.166260507
Short name T123
Test name
Test status
Simulation time 3242648011 ps
CPU time 58.95 seconds
Started Jun 28 05:24:53 PM PDT 24
Finished Jun 28 05:25:52 PM PDT 24
Peak memory 201980 kb
Host smart-f6e82703-6aab-4b6b-8696-8d6ba1a4445d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=166260507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.166260507
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2412933419
Short name T629
Test name
Test status
Simulation time 203425778 ps
CPU time 17.89 seconds
Started Jun 28 05:24:48 PM PDT 24
Finished Jun 28 05:25:06 PM PDT 24
Peak memory 201916 kb
Host smart-8bbe3430-302d-4157-866b-9d27ed781310
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2412933419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2412933419
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.485910248
Short name T719
Test name
Test status
Simulation time 507050340 ps
CPU time 40.85 seconds
Started Jun 28 05:24:48 PM PDT 24
Finished Jun 28 05:25:29 PM PDT 24
Peak memory 204168 kb
Host smart-5b538de9-96e7-4787-b9c6-6f0378b11df0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=485910248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_
reset.485910248
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.955246861
Short name T12
Test name
Test status
Simulation time 4434490943 ps
CPU time 84.7 seconds
Started Jun 28 05:24:49 PM PDT 24
Finished Jun 28 05:26:15 PM PDT 24
Peak memory 204328 kb
Host smart-88822b9c-b565-4d32-8dea-8a7e5fd12279
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=955246861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese
t_error.955246861
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1622033862
Short name T860
Test name
Test status
Simulation time 91466630 ps
CPU time 3.95 seconds
Started Jun 28 05:24:50 PM PDT 24
Finished Jun 28 05:24:55 PM PDT 24
Peak memory 201848 kb
Host smart-c6cca6e3-0619-4b4d-b56f-646fceef19d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1622033862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1622033862
Directory /workspace/9.xbar_unmapped_addr/latest
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