Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 403 1 T3 1 T63 4 T6 6
all_values[1] 444 1 T3 4 T13 2 T14 1
all_values[2] 410 1 T3 1 T14 1 T63 1
all_values[3] 424 1 T1 1 T3 1 T13 1
all_values[4] 415 1 T3 4 T13 1 T63 1
all_values[5] 427 1 T3 2 T13 2 T14 1
all_values[6] 426 1 T3 1 T14 1 T63 1
all_values[7] 406 1 T3 2 T16 1 T13 1
all_values[8] 394 1 T1 1 T3 5 T14 1
all_values[9] 397 1 T1 1 T3 4 T13 3
all_values[10] 420 1 T3 2 T13 1 T22 1
all_values[11] 425 1 T1 1 T3 7 T13 3
all_values[12] 365 1 T3 2 T16 1 T13 2
all_values[13] 405 1 T3 5 T63 1 T6 4
all_values[14] 426 1 T3 3 T16 1 T13 2
all_values[15] 445 1 T3 7 T13 1 T6 2
all_values[16] 419 1 T1 1 T3 3 T16 1
all_values[17] 388 1 T3 1 T14 1 T63 1
all_values[18] 432 1 T3 5 T13 1 T63 1
all_values[19] 429 1 T3 3 T14 1 T63 2
all_values[20] 420 1 T3 3 T13 2 T14 1
all_values[21] 451 1 T1 1 T3 5 T13 1
all_values[22] 429 1 T3 1 T13 3 T14 1
all_values[23] 411 1 T1 1 T3 4 T16 1
all_values[24] 414 1 T3 6 T14 1 T22 1
all_values[25] 391 1 T3 2 T16 1 T13 2
all_values[26] 411 1 T3 2 T13 3 T14 1

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