Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 427 1 T4 1 T16 1 T17 1
all_values[1] 464 1 T4 2 T17 1 T23 1
all_values[2] 430 1 T23 1 T47 3 T80 6
all_values[3] 448 1 T4 2 T43 1 T44 1
all_values[4] 487 1 T3 2 T17 1 T44 1
all_values[5] 471 1 T4 3 T43 1 T274 1
all_values[6] 474 1 T4 1 T17 3 T20 1
all_values[7] 516 1 T17 1 T47 2 T80 1
all_values[8] 467 1 T17 1 T23 1 T59 1
all_values[9] 468 1 T4 2 T16 1 T17 2
all_values[10] 484 1 T4 2 T44 1 T274 1
all_values[11] 479 1 T17 1 T23 1 T44 1
all_values[12] 494 1 T17 1 T20 1 T23 1
all_values[13] 466 1 T4 1 T17 3 T47 1
all_values[14] 447 1 T16 1 T17 1 T43 1
all_values[15] 460 1 T4 1 T16 1 T17 3
all_values[16] 444 1 T4 1 T17 3 T20 1
all_values[17] 509 1 T3 1 T4 2 T17 5
all_values[18] 470 1 T17 4 T274 1 T78 1
all_values[19] 454 1 T4 2 T16 1 T17 1
all_values[20] 461 1 T4 1 T17 2 T23 1
all_values[21] 478 1 T4 1 T17 1 T44 2
all_values[22] 513 1 T3 2 T17 2 T43 2
all_values[23] 450 1 T16 1 T17 1 T23 1
all_values[24] 469 1 T17 1 T23 1 T43 1
all_values[25] 487 1 T3 1 T4 1 T59 1
all_values[26] 507 1 T16 1 T17 1 T59 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%