Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	496	1			T19	1		T25	1		T21	3
all_values[1]	437	1			T25	1		T27	6		T31	9
all_values[2]	463	1			T1	2		T16	1		T19	2
all_values[3]	491	1			T16	2		T21	2		T27	2
all_values[4]	490	1			T1	2		T21	2		T27	6
all_values[5]	487	1			T1	1		T21	2		T27	7
all_values[6]	468	1			T1	1		T25	1		T21	1
all_values[7]	462	1			T16	1		T27	5		T31	4
all_values[8]	473	1			T21	1		T27	7		T31	4
all_values[9]	466	1			T16	1		T19	1		T21	1
all_values[10]	496	1			T1	1		T16	1		T19	1
all_values[11]	464	1			T25	3		T21	1		T27	5
all_values[12]	469	1			T27	3		T31	4		T71	4
all_values[13]	477	1			T16	1		T21	2		T27	7
all_values[14]	477	1			T19	2		T27	6		T31	7
all_values[15]	468	1			T1	2		T21	1		T27	8
all_values[16]	491	1			T1	1		T19	2		T25	1
all_values[17]	439	1			T19	1		T27	7		T31	5
all_values[18]	496	1			T16	1		T25	1		T21	3
all_values[19]	479	1			T25	1		T27	4		T31	6
all_values[20]	448	1			T1	1		T16	1		T27	2
all_values[21]	455	1			T16	1		T19	1		T25	1
all_values[22]	469	1			T1	1		T16	1		T19	2
all_values[23]	448	1			T25	1		T21	1		T27	4
all_values[24]	470	1			T1	1		T25	1		T27	2
all_values[25]	501	1			T1	2		T16	1		T21	1
all_values[26]	462	1			T27	6		T31	6		T71	6