Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 441 1 T3 4 T5 9 T19 2
all_values[1] 408 1 T3 1 T5 4 T19 6
all_values[2] 447 1 T3 3 T5 8 T19 5
all_values[3] 414 1 T3 8 T5 6 T19 6
all_values[4] 475 1 T3 3 T5 6 T19 6
all_values[5] 475 1 T3 7 T5 7 T19 4
all_values[6] 445 1 T3 4 T5 5 T19 9
all_values[7] 443 1 T3 3 T5 4 T19 3
all_values[8] 468 1 T3 5 T5 3 T19 2
all_values[9] 420 1 T3 5 T5 5 T19 2
all_values[10] 442 1 T5 8 T19 5 T54 2
all_values[11] 471 1 T3 6 T5 9 T19 3
all_values[12] 444 1 T3 3 T5 1 T19 1
all_values[13] 428 1 T3 1 T5 7 T19 3
all_values[14] 469 1 T3 6 T5 7 T19 1
all_values[15] 419 1 T3 3 T5 6 T19 5
all_values[16] 471 1 T3 2 T5 6 T19 8
all_values[17] 455 1 T3 10 T5 3 T19 5
all_values[18] 448 1 T3 2 T5 5 T19 5
all_values[19] 439 1 T3 7 T5 8 T19 4
all_values[20] 455 1 T3 3 T5 4 T19 3
all_values[21] 462 1 T3 8 T5 10 T19 8
all_values[22] 466 1 T3 2 T5 6 T19 3
all_values[23] 441 1 T3 6 T5 3 T19 5
all_values[24] 432 1 T3 4 T5 7 T19 4
all_values[25] 446 1 T3 5 T5 5 T19 3
all_values[26] 441 1 T3 3 T5 6 T19 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%