Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.33 100.00 95.99 100.00 100.00 100.00 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T764 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3736908261 Jul 07 05:56:52 PM PDT 24 Jul 07 05:57:09 PM PDT 24 5110031449 ps
T765 /workspace/coverage/xbar_build_mode/28.xbar_random.4010545676 Jul 07 05:58:10 PM PDT 24 Jul 07 05:58:17 PM PDT 24 71039359 ps
T766 /workspace/coverage/xbar_build_mode/39.xbar_smoke.3314357058 Jul 07 05:58:47 PM PDT 24 Jul 07 05:58:49 PM PDT 24 17870364 ps
T767 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.845726607 Jul 07 05:57:23 PM PDT 24 Jul 07 05:57:33 PM PDT 24 73713613 ps
T768 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3810698320 Jul 07 05:58:46 PM PDT 24 Jul 07 06:00:55 PM PDT 24 893794481 ps
T769 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2609945307 Jul 07 05:56:55 PM PDT 24 Jul 07 05:57:38 PM PDT 24 2050752394 ps
T770 /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1836110460 Jul 07 05:57:28 PM PDT 24 Jul 07 05:57:39 PM PDT 24 3691709597 ps
T771 /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1767932766 Jul 07 05:57:30 PM PDT 24 Jul 07 05:57:38 PM PDT 24 3607413642 ps
T772 /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3752507352 Jul 07 05:56:58 PM PDT 24 Jul 07 05:59:02 PM PDT 24 18768182100 ps
T773 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2241499219 Jul 07 05:58:11 PM PDT 24 Jul 07 06:02:34 PM PDT 24 102549345539 ps
T774 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.701645845 Jul 07 05:57:31 PM PDT 24 Jul 07 05:58:21 PM PDT 24 3930170705 ps
T775 /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3150468139 Jul 07 05:57:26 PM PDT 24 Jul 07 05:57:32 PM PDT 24 76268783 ps
T776 /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3212528711 Jul 07 05:56:45 PM PDT 24 Jul 07 05:56:53 PM PDT 24 3320681915 ps
T777 /workspace/coverage/xbar_build_mode/23.xbar_smoke.3112783540 Jul 07 05:57:47 PM PDT 24 Jul 07 05:57:49 PM PDT 24 101921768 ps
T120 /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.287475631 Jul 07 05:57:31 PM PDT 24 Jul 07 06:00:34 PM PDT 24 242539014136 ps
T778 /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1020453427 Jul 07 05:59:00 PM PDT 24 Jul 07 05:59:11 PM PDT 24 20100224783 ps
T779 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3326369998 Jul 07 05:56:48 PM PDT 24 Jul 07 05:58:33 PM PDT 24 3545157655 ps
T780 /workspace/coverage/xbar_build_mode/29.xbar_same_source.1913135865 Jul 07 05:58:15 PM PDT 24 Jul 07 05:58:18 PM PDT 24 28255409 ps
T781 /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2153454565 Jul 07 05:58:45 PM PDT 24 Jul 07 05:58:51 PM PDT 24 93568926 ps
T782 /workspace/coverage/xbar_build_mode/32.xbar_same_source.1481352772 Jul 07 05:58:21 PM PDT 24 Jul 07 05:58:32 PM PDT 24 2307366289 ps
T783 /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2189089711 Jul 07 05:57:06 PM PDT 24 Jul 07 05:57:08 PM PDT 24 11551121 ps
T784 /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2887830817 Jul 07 05:59:26 PM PDT 24 Jul 07 05:59:28 PM PDT 24 8745911 ps
T785 /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3554482810 Jul 07 05:58:15 PM PDT 24 Jul 07 05:58:25 PM PDT 24 1060178565 ps
T786 /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.791610851 Jul 07 05:58:11 PM PDT 24 Jul 07 05:58:16 PM PDT 24 41959408 ps
T787 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.557726397 Jul 07 05:58:32 PM PDT 24 Jul 07 06:00:18 PM PDT 24 418690465 ps
T788 /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2091293349 Jul 07 05:57:51 PM PDT 24 Jul 07 05:59:16 PM PDT 24 11121204670 ps
T193 /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4184997891 Jul 07 05:57:07 PM PDT 24 Jul 07 06:02:23 PM PDT 24 138312997444 ps
T789 /workspace/coverage/xbar_build_mode/10.xbar_error_random.3922637674 Jul 07 05:56:53 PM PDT 24 Jul 07 05:56:57 PM PDT 24 68865178 ps
T790 /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1623183902 Jul 07 05:56:26 PM PDT 24 Jul 07 05:56:28 PM PDT 24 13669711 ps
T791 /workspace/coverage/xbar_build_mode/16.xbar_stress_all.765933322 Jul 07 05:57:23 PM PDT 24 Jul 07 05:57:54 PM PDT 24 759348833 ps
T792 /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3265586589 Jul 07 05:58:58 PM PDT 24 Jul 07 05:59:09 PM PDT 24 1499043527 ps
T793 /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3626688820 Jul 07 05:57:26 PM PDT 24 Jul 07 05:57:27 PM PDT 24 8893805 ps
T794 /workspace/coverage/xbar_build_mode/1.xbar_error_random.4152277147 Jul 07 05:56:26 PM PDT 24 Jul 07 05:56:31 PM PDT 24 598101701 ps
T795 /workspace/coverage/xbar_build_mode/16.xbar_error_random.3029479019 Jul 07 05:57:20 PM PDT 24 Jul 07 05:57:31 PM PDT 24 178862533 ps
T796 /workspace/coverage/xbar_build_mode/12.xbar_error_random.1091155965 Jul 07 05:57:03 PM PDT 24 Jul 07 05:57:16 PM PDT 24 780317240 ps
T797 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3767322775 Jul 07 05:58:32 PM PDT 24 Jul 07 06:01:48 PM PDT 24 30449735031 ps
T798 /workspace/coverage/xbar_build_mode/2.xbar_same_source.551068885 Jul 07 05:56:33 PM PDT 24 Jul 07 05:56:36 PM PDT 24 164700650 ps
T799 /workspace/coverage/xbar_build_mode/19.xbar_error_random.3789056617 Jul 07 05:57:34 PM PDT 24 Jul 07 05:57:38 PM PDT 24 73525919 ps
T37 /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1541557297 Jul 07 05:57:54 PM PDT 24 Jul 07 05:59:53 PM PDT 24 19394064100 ps
T800 /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1039060904 Jul 07 05:57:27 PM PDT 24 Jul 07 05:57:40 PM PDT 24 72300995 ps
T801 /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2079405636 Jul 07 05:58:56 PM PDT 24 Jul 07 05:59:12 PM PDT 24 11995412859 ps
T802 /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3773068306 Jul 07 05:58:21 PM PDT 24 Jul 07 05:58:33 PM PDT 24 1385207198 ps
T803 /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1595161902 Jul 07 05:58:11 PM PDT 24 Jul 07 05:58:14 PM PDT 24 152671536 ps
T804 /workspace/coverage/xbar_build_mode/13.xbar_random.1180344986 Jul 07 05:57:12 PM PDT 24 Jul 07 05:57:23 PM PDT 24 831701752 ps
T805 /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2543980971 Jul 07 05:59:14 PM PDT 24 Jul 07 05:59:23 PM PDT 24 5765723830 ps
T806 /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1152348441 Jul 07 05:59:26 PM PDT 24 Jul 07 05:59:34 PM PDT 24 59250391 ps
T807 /workspace/coverage/xbar_build_mode/43.xbar_random.1720668666 Jul 07 05:59:03 PM PDT 24 Jul 07 05:59:05 PM PDT 24 18842113 ps
T808 /workspace/coverage/xbar_build_mode/31.xbar_same_source.2257357888 Jul 07 05:58:15 PM PDT 24 Jul 07 05:58:23 PM PDT 24 573873891 ps
T194 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3109414742 Jul 07 05:56:54 PM PDT 24 Jul 07 06:03:08 PM PDT 24 258266005940 ps
T809 /workspace/coverage/xbar_build_mode/3.xbar_stress_all.195004587 Jul 07 05:56:31 PM PDT 24 Jul 07 05:56:45 PM PDT 24 113374792 ps
T810 /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.967893380 Jul 07 05:56:34 PM PDT 24 Jul 07 05:56:43 PM PDT 24 594727280 ps
T811 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1038461523 Jul 07 05:59:16 PM PDT 24 Jul 07 05:59:26 PM PDT 24 134460758 ps
T812 /workspace/coverage/xbar_build_mode/8.xbar_smoke.1488759817 Jul 07 05:56:49 PM PDT 24 Jul 07 05:56:50 PM PDT 24 9491780 ps
T813 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1459271846 Jul 07 05:58:30 PM PDT 24 Jul 07 05:59:19 PM PDT 24 250780571 ps
T814 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2273569217 Jul 07 05:58:14 PM PDT 24 Jul 07 06:02:42 PM PDT 24 34208328089 ps
T815 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2129719516 Jul 07 05:58:28 PM PDT 24 Jul 07 05:59:41 PM PDT 24 1484442803 ps
T816 /workspace/coverage/xbar_build_mode/39.xbar_stress_all.4030534180 Jul 07 05:58:49 PM PDT 24 Jul 07 06:00:34 PM PDT 24 12669340516 ps
T817 /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1427692189 Jul 07 05:59:05 PM PDT 24 Jul 07 05:59:12 PM PDT 24 99269514 ps
T818 /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.740921904 Jul 07 05:58:42 PM PDT 24 Jul 07 05:59:09 PM PDT 24 14313212128 ps
T146 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2644364985 Jul 07 05:58:45 PM PDT 24 Jul 07 05:59:41 PM PDT 24 16143549703 ps
T819 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1110411953 Jul 07 05:59:28 PM PDT 24 Jul 07 05:59:32 PM PDT 24 41999291 ps
T820 /workspace/coverage/xbar_build_mode/3.xbar_same_source.1362324675 Jul 07 05:56:36 PM PDT 24 Jul 07 05:56:47 PM PDT 24 765593944 ps
T821 /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3293811078 Jul 07 05:59:16 PM PDT 24 Jul 07 05:59:20 PM PDT 24 434754453 ps
T822 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1299715410 Jul 07 05:59:10 PM PDT 24 Jul 07 06:04:10 PM PDT 24 86573443018 ps
T823 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3145514358 Jul 07 05:56:53 PM PDT 24 Jul 07 05:58:28 PM PDT 24 12158703457 ps
T824 /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1992810453 Jul 07 05:56:25 PM PDT 24 Jul 07 05:56:38 PM PDT 24 3082201511 ps
T825 /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1670089274 Jul 07 05:58:56 PM PDT 24 Jul 07 06:01:51 PM PDT 24 58286103769 ps
T826 /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4069186575 Jul 07 05:56:43 PM PDT 24 Jul 07 05:56:48 PM PDT 24 69272841 ps
T827 /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1680866023 Jul 07 05:56:53 PM PDT 24 Jul 07 05:56:57 PM PDT 24 46747547 ps
T828 /workspace/coverage/xbar_build_mode/15.xbar_error_random.4005693110 Jul 07 05:57:29 PM PDT 24 Jul 07 05:57:37 PM PDT 24 255625904 ps
T829 /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1547464805 Jul 07 05:59:02 PM PDT 24 Jul 07 05:59:10 PM PDT 24 89273748 ps
T830 /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2921770711 Jul 07 05:56:47 PM PDT 24 Jul 07 05:57:14 PM PDT 24 5748084110 ps
T831 /workspace/coverage/xbar_build_mode/33.xbar_same_source.3081418456 Jul 07 05:58:29 PM PDT 24 Jul 07 05:58:31 PM PDT 24 118445316 ps
T832 /workspace/coverage/xbar_build_mode/29.xbar_stress_all.986156420 Jul 07 05:58:15 PM PDT 24 Jul 07 05:58:23 PM PDT 24 469400731 ps
T833 /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2652093888 Jul 07 05:56:28 PM PDT 24 Jul 07 05:57:22 PM PDT 24 6215950762 ps
T834 /workspace/coverage/xbar_build_mode/12.xbar_smoke.1040922947 Jul 07 05:57:00 PM PDT 24 Jul 07 05:57:02 PM PDT 24 9217845 ps
T835 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.4242236374 Jul 07 05:57:11 PM PDT 24 Jul 07 05:57:59 PM PDT 24 7163732934 ps
T836 /workspace/coverage/xbar_build_mode/27.xbar_smoke.1922688596 Jul 07 05:58:08 PM PDT 24 Jul 07 05:58:10 PM PDT 24 48807347 ps
T109 /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2091927396 Jul 07 05:57:31 PM PDT 24 Jul 07 06:00:13 PM PDT 24 141897185452 ps
T837 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2018154262 Jul 07 05:56:29 PM PDT 24 Jul 07 05:58:14 PM PDT 24 15639513337 ps
T198 /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3353237944 Jul 07 05:57:12 PM PDT 24 Jul 07 06:02:04 PM PDT 24 55287593136 ps
T838 /workspace/coverage/xbar_build_mode/0.xbar_error_random.4230756616 Jul 07 05:56:22 PM PDT 24 Jul 07 05:56:29 PM PDT 24 439269162 ps
T110 /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2039138781 Jul 07 05:57:13 PM PDT 24 Jul 07 05:57:20 PM PDT 24 586443825 ps
T839 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2778167504 Jul 07 05:56:45 PM PDT 24 Jul 07 05:57:02 PM PDT 24 199050003 ps
T840 /workspace/coverage/xbar_build_mode/24.xbar_error_random.3462516070 Jul 07 05:57:56 PM PDT 24 Jul 07 05:58:08 PM PDT 24 869889947 ps
T841 /workspace/coverage/xbar_build_mode/7.xbar_same_source.2542339820 Jul 07 05:56:46 PM PDT 24 Jul 07 05:56:56 PM PDT 24 1485645782 ps
T842 /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.644090347 Jul 07 05:56:27 PM PDT 24 Jul 07 05:56:35 PM PDT 24 4613273595 ps
T843 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3943311312 Jul 07 05:58:17 PM PDT 24 Jul 07 05:58:32 PM PDT 24 110861935 ps
T844 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1487550477 Jul 07 05:58:56 PM PDT 24 Jul 07 06:01:31 PM PDT 24 24284738523 ps
T845 /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.715989283 Jul 07 05:56:47 PM PDT 24 Jul 07 05:56:52 PM PDT 24 255035636 ps
T846 /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2581228163 Jul 07 05:57:23 PM PDT 24 Jul 07 05:57:28 PM PDT 24 861229761 ps
T111 /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.52094289 Jul 07 05:58:18 PM PDT 24 Jul 07 06:01:17 PM PDT 24 66749764192 ps
T847 /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1632598536 Jul 07 05:57:30 PM PDT 24 Jul 07 05:59:49 PM PDT 24 29094460043 ps
T848 /workspace/coverage/xbar_build_mode/5.xbar_random.1928317339 Jul 07 05:56:40 PM PDT 24 Jul 07 05:56:46 PM PDT 24 239442086 ps
T849 /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1137949491 Jul 07 05:59:20 PM PDT 24 Jul 07 06:00:58 PM PDT 24 533078789 ps
T850 /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1556196175 Jul 07 05:57:27 PM PDT 24 Jul 07 05:57:29 PM PDT 24 38786908 ps
T851 /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.474545232 Jul 07 05:57:56 PM PDT 24 Jul 07 05:58:25 PM PDT 24 8959698938 ps
T852 /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.347470514 Jul 07 05:57:02 PM PDT 24 Jul 07 05:57:06 PM PDT 24 25507725 ps
T853 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3241980857 Jul 07 05:57:53 PM PDT 24 Jul 07 05:57:59 PM PDT 24 28972327 ps
T854 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3793493860 Jul 07 05:56:50 PM PDT 24 Jul 07 06:00:41 PM PDT 24 53756191703 ps
T855 /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2836703356 Jul 07 05:56:39 PM PDT 24 Jul 07 05:56:46 PM PDT 24 256130646 ps
T856 /workspace/coverage/xbar_build_mode/0.xbar_smoke.918973733 Jul 07 05:56:27 PM PDT 24 Jul 07 05:56:28 PM PDT 24 69789164 ps
T857 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.129552211 Jul 07 05:58:56 PM PDT 24 Jul 07 05:59:01 PM PDT 24 432246293 ps
T858 /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3626726505 Jul 07 05:56:35 PM PDT 24 Jul 07 05:56:42 PM PDT 24 1014054772 ps
T859 /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3785079113 Jul 07 05:58:30 PM PDT 24 Jul 07 05:59:41 PM PDT 24 40587694600 ps
T161 /workspace/coverage/xbar_build_mode/19.xbar_random.194549612 Jul 07 05:57:28 PM PDT 24 Jul 07 05:57:40 PM PDT 24 1677977777 ps
T860 /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.909945422 Jul 07 05:59:03 PM PDT 24 Jul 07 05:59:13 PM PDT 24 5855927275 ps
T861 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4198337683 Jul 07 05:59:23 PM PDT 24 Jul 07 05:59:44 PM PDT 24 240172488 ps
T862 /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3548020080 Jul 07 05:56:37 PM PDT 24 Jul 07 05:56:41 PM PDT 24 281637473 ps
T863 /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1147742637 Jul 07 05:58:41 PM PDT 24 Jul 07 05:58:49 PM PDT 24 2212549880 ps
T864 /workspace/coverage/xbar_build_mode/20.xbar_smoke.171097781 Jul 07 05:57:32 PM PDT 24 Jul 07 05:57:34 PM PDT 24 23739312 ps
T865 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2766241167 Jul 07 05:57:57 PM PDT 24 Jul 07 05:58:02 PM PDT 24 53167339 ps
T866 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.244909786 Jul 07 05:58:33 PM PDT 24 Jul 07 05:58:41 PM PDT 24 301082807 ps
T867 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1786613546 Jul 07 05:56:36 PM PDT 24 Jul 07 05:56:51 PM PDT 24 234975639 ps
T159 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.164780533 Jul 07 05:57:48 PM PDT 24 Jul 07 05:59:32 PM PDT 24 7554942400 ps
T868 /workspace/coverage/xbar_build_mode/38.xbar_same_source.276688140 Jul 07 05:58:50 PM PDT 24 Jul 07 05:58:51 PM PDT 24 17050234 ps
T147 /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.339868556 Jul 07 05:58:08 PM PDT 24 Jul 07 06:00:34 PM PDT 24 137022679750 ps
T869 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4002384225 Jul 07 05:58:56 PM PDT 24 Jul 07 06:01:25 PM PDT 24 24971768386 ps
T870 /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1350396146 Jul 07 05:58:20 PM PDT 24 Jul 07 05:58:28 PM PDT 24 3500567928 ps
T871 /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.639432809 Jul 07 05:58:53 PM PDT 24 Jul 07 05:59:29 PM PDT 24 11077198335 ps
T872 /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1895223815 Jul 07 05:58:42 PM PDT 24 Jul 07 05:58:45 PM PDT 24 134995873 ps
T873 /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2227400371 Jul 07 05:57:02 PM PDT 24 Jul 07 05:57:04 PM PDT 24 8770942 ps
T112 /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.905577147 Jul 07 05:59:24 PM PDT 24 Jul 07 06:03:36 PM PDT 24 193254155942 ps
T874 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.790624701 Jul 07 05:58:59 PM PDT 24 Jul 07 06:01:54 PM PDT 24 1512336518 ps
T875 /workspace/coverage/xbar_build_mode/1.xbar_same_source.2040315328 Jul 07 05:56:25 PM PDT 24 Jul 07 05:56:34 PM PDT 24 963432332 ps
T876 /workspace/coverage/xbar_build_mode/40.xbar_same_source.2640496084 Jul 07 05:58:55 PM PDT 24 Jul 07 05:59:00 PM PDT 24 40140882 ps
T877 /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2193048946 Jul 07 05:56:46 PM PDT 24 Jul 07 05:57:54 PM PDT 24 10787634386 ps
T878 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1718455791 Jul 07 05:59:28 PM PDT 24 Jul 07 06:00:15 PM PDT 24 2772804356 ps
T879 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3443231980 Jul 07 05:58:35 PM PDT 24 Jul 07 05:59:21 PM PDT 24 4793296799 ps
T880 /workspace/coverage/xbar_build_mode/48.xbar_same_source.221633478 Jul 07 05:59:21 PM PDT 24 Jul 07 05:59:27 PM PDT 24 453232847 ps
T881 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.59842762 Jul 07 05:58:07 PM PDT 24 Jul 07 05:58:15 PM PDT 24 109454605 ps
T882 /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3685528911 Jul 07 05:57:58 PM PDT 24 Jul 07 05:58:16 PM PDT 24 116708802 ps
T883 /workspace/coverage/xbar_build_mode/22.xbar_same_source.294856807 Jul 07 05:57:45 PM PDT 24 Jul 07 05:57:47 PM PDT 24 72781210 ps
T884 /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2944358343 Jul 07 05:56:51 PM PDT 24 Jul 07 05:58:28 PM PDT 24 45311110639 ps
T885 /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.320336911 Jul 07 05:56:22 PM PDT 24 Jul 07 05:56:30 PM PDT 24 154327236 ps
T886 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1849428990 Jul 07 05:57:52 PM PDT 24 Jul 07 06:00:22 PM PDT 24 30301693472 ps
T887 /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1769281235 Jul 07 05:59:28 PM PDT 24 Jul 07 06:00:42 PM PDT 24 31362113015 ps
T888 /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.994466002 Jul 07 05:56:36 PM PDT 24 Jul 07 05:56:38 PM PDT 24 9329650 ps
T889 /workspace/coverage/xbar_build_mode/18.xbar_random.995960555 Jul 07 05:57:24 PM PDT 24 Jul 07 05:57:26 PM PDT 24 61834101 ps
T890 /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2697620429 Jul 07 05:59:27 PM PDT 24 Jul 07 05:59:29 PM PDT 24 80340237 ps
T891 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2322161522 Jul 07 05:58:52 PM PDT 24 Jul 07 05:59:01 PM PDT 24 1959683682 ps
T892 /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2808642135 Jul 07 05:58:33 PM PDT 24 Jul 07 05:58:34 PM PDT 24 8610973 ps
T893 /workspace/coverage/xbar_build_mode/35.xbar_same_source.4121631097 Jul 07 05:58:35 PM PDT 24 Jul 07 05:58:40 PM PDT 24 56018576 ps
T894 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.335317111 Jul 07 05:58:51 PM PDT 24 Jul 07 05:58:55 PM PDT 24 197778246 ps
T895 /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3143719432 Jul 07 05:58:35 PM PDT 24 Jul 07 05:59:43 PM PDT 24 4661181561 ps
T896 /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3134697324 Jul 07 05:57:51 PM PDT 24 Jul 07 05:57:57 PM PDT 24 87831222 ps
T897 /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3622884692 Jul 07 05:58:42 PM PDT 24 Jul 07 06:04:42 PM PDT 24 48639371726 ps
T898 /workspace/coverage/xbar_build_mode/42.xbar_same_source.3179318404 Jul 07 05:58:55 PM PDT 24 Jul 07 05:58:59 PM PDT 24 67761321 ps
T899 /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1936046973 Jul 07 05:59:16 PM PDT 24 Jul 07 05:59:25 PM PDT 24 1836128059 ps
T900 /workspace/coverage/xbar_build_mode/2.xbar_smoke.2993886907 Jul 07 05:56:26 PM PDT 24 Jul 07 05:56:27 PM PDT 24 37813441 ps

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1213966442
Short name T19
Test name
Test status
Simulation time 8728977265 ps
CPU time 170.49 seconds
Started Jul 07 05:56:38 PM PDT 24
Finished Jul 07 05:59:29 PM PDT 24
Peak memory 206536 kb
Host smart-ff5b844b-a384-4373-97b2-ba50a6a40f84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1213966442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.1213966442
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2399724269
Short name T94
Test name
Test status
Simulation time 56623884499 ps
CPU time 296.99 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 06:01:59 PM PDT 24
Peak memory 203116 kb
Host smart-d2ac94f1-ce6f-4727-8269-75140e537e6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2399724269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.2399724269
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.931840020
Short name T98
Test name
Test status
Simulation time 192233958260 ps
CPU time 343.44 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 06:04:46 PM PDT 24
Peak memory 205196 kb
Host smart-1d93d243-cad1-4498-a9df-9e4bb164f55d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=931840020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo
w_rsp.931840020
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2446537080
Short name T192
Test name
Test status
Simulation time 60170909978 ps
CPU time 228.96 seconds
Started Jul 07 05:57:52 PM PDT 24
Finished Jul 07 06:01:41 PM PDT 24
Peak memory 203096 kb
Host smart-ceca145b-ef80-4c21-9aab-a7708cfae0ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2446537080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.2446537080
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3147324798
Short name T113
Test name
Test status
Simulation time 8266584262 ps
CPU time 59.55 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:59:47 PM PDT 24
Peak memory 202100 kb
Host smart-576481dc-a496-4901-9f7f-5ac7ab2d32bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3147324798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3147324798
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.4028063447
Short name T26
Test name
Test status
Simulation time 78327032315 ps
CPU time 377.34 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 06:03:45 PM PDT 24
Peak memory 205252 kb
Host smart-15d8058d-4ccb-4100-8419-6288ed9934cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4028063447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.4028063447
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2422444199
Short name T191
Test name
Test status
Simulation time 62806879597 ps
CPU time 299.7 seconds
Started Jul 07 05:56:38 PM PDT 24
Finished Jul 07 06:01:39 PM PDT 24
Peak memory 203012 kb
Host smart-0f0c12fa-58be-46f8-b823-15fae04a1198
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2422444199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.2422444199
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3264058238
Short name T5
Test name
Test status
Simulation time 555941087 ps
CPU time 125.47 seconds
Started Jul 07 05:58:57 PM PDT 24
Finished Jul 07 06:01:03 PM PDT 24
Peak memory 204560 kb
Host smart-756516a8-1d4d-46e3-933b-cd7e6795b83a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3264058238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3264058238
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3322225224
Short name T99
Test name
Test status
Simulation time 44172255357 ps
CPU time 275.27 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 06:03:37 PM PDT 24
Peak memory 203100 kb
Host smart-eb49f588-5d27-4f68-908a-7a49cd569e93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3322225224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.3322225224
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3919285294
Short name T22
Test name
Test status
Simulation time 261447870414 ps
CPU time 133.48 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 06:01:24 PM PDT 24
Peak memory 202016 kb
Host smart-6284018d-5d32-4b75-9e7b-77cb76339a65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919285294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3919285294
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.526924278
Short name T6
Test name
Test status
Simulation time 731049918 ps
CPU time 66.3 seconds
Started Jul 07 05:57:03 PM PDT 24
Finished Jul 07 05:58:10 PM PDT 24
Peak memory 205152 kb
Host smart-930dbdce-70d8-4c72-9322-fb1ac1ac4a4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=526924278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand
_reset.526924278
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1465015270
Short name T11
Test name
Test status
Simulation time 13722212613 ps
CPU time 166.14 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 06:01:51 PM PDT 24
Peak memory 206284 kb
Host smart-53d3128a-9f8e-40cf-90e1-9c9df0efac99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465015270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.1465015270
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.905577147
Short name T112
Test name
Test status
Simulation time 193254155942 ps
CPU time 252.24 seconds
Started Jul 07 05:59:24 PM PDT 24
Finished Jul 07 06:03:36 PM PDT 24
Peak memory 203076 kb
Host smart-4949bd85-ac34-430e-ade6-3ee365790572
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=905577147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo
w_rsp.905577147
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3128530554
Short name T14
Test name
Test status
Simulation time 3952044917 ps
CPU time 125.35 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:58:39 PM PDT 24
Peak memory 205244 kb
Host smart-fc2c1635-54a8-4ba8-ba52-b42f100893f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3128530554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.3128530554
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2068514583
Short name T13
Test name
Test status
Simulation time 432912434 ps
CPU time 47.35 seconds
Started Jul 07 05:57:29 PM PDT 24
Finished Jul 07 05:58:17 PM PDT 24
Peak memory 203592 kb
Host smart-89f2216c-0a39-4652-a8e2-c2d91ceff9e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2068514583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.2068514583
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1857363122
Short name T10
Test name
Test status
Simulation time 13800460273 ps
CPU time 331.02 seconds
Started Jul 07 05:59:24 PM PDT 24
Finished Jul 07 06:04:56 PM PDT 24
Peak memory 210276 kb
Host smart-9965fe5f-1500-44bd-8d83-9d8be9104a81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1857363122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.1857363122
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2182864880
Short name T12
Test name
Test status
Simulation time 1094941999 ps
CPU time 51.09 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 203860 kb
Host smart-aa154b6e-7675-49d5-828e-49e37ac97743
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2182864880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.2182864880
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3353237944
Short name T198
Test name
Test status
Simulation time 55287593136 ps
CPU time 291.53 seconds
Started Jul 07 05:57:12 PM PDT 24
Finished Jul 07 06:02:04 PM PDT 24
Peak memory 203072 kb
Host smart-c14001bb-f377-4255-b921-ba25862e85e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3353237944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.3353237944
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3269162016
Short name T67
Test name
Test status
Simulation time 8152324259 ps
CPU time 203.46 seconds
Started Jul 07 05:56:28 PM PDT 24
Finished Jul 07 05:59:52 PM PDT 24
Peak memory 208720 kb
Host smart-e2e7dc27-cda4-4808-b459-cff686027c15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3269162016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.3269162016
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.722650131
Short name T100
Test name
Test status
Simulation time 26472677896 ps
CPU time 203.41 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:59:59 PM PDT 24
Peak memory 203068 kb
Host smart-67f5e895-73ef-4978-85ea-f3b88d2d6384
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=722650131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow
_rsp.722650131
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.178932103
Short name T371
Test name
Test status
Simulation time 1428691191 ps
CPU time 124.31 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:58:31 PM PDT 24
Peak memory 207132 kb
Host smart-cf1e4e91-f691-41c3-9e46-cef0294141f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=178932103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese
t_error.178932103
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1717822014
Short name T59
Test name
Test status
Simulation time 397028805 ps
CPU time 45.62 seconds
Started Jul 07 05:56:24 PM PDT 24
Finished Jul 07 05:57:10 PM PDT 24
Peak memory 204080 kb
Host smart-0f2e8f46-2ad4-42b9-b4f2-64b79d1c0753
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1717822014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.1717822014
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.622202905
Short name T411
Test name
Test status
Simulation time 58930967 ps
CPU time 5.33 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:27 PM PDT 24
Peak memory 201892 kb
Host smart-b96713de-46c2-4077-acc6-512387286766
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=622202905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.622202905
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1575039589
Short name T470
Test name
Test status
Simulation time 21889050434 ps
CPU time 109.35 seconds
Started Jul 07 05:56:24 PM PDT 24
Finished Jul 07 05:58:13 PM PDT 24
Peak memory 203076 kb
Host smart-975cb9eb-17cf-4651-82ea-cef62c71ae1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1575039589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.1575039589
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.781908063
Short name T617
Test name
Test status
Simulation time 259325668 ps
CPU time 4.3 seconds
Started Jul 07 05:56:24 PM PDT 24
Finished Jul 07 05:56:29 PM PDT 24
Peak memory 201884 kb
Host smart-6b827c68-8a81-4552-aa1d-0abc4fecdb69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=781908063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.781908063
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.4230756616
Short name T838
Test name
Test status
Simulation time 439269162 ps
CPU time 6.79 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:56:29 PM PDT 24
Peak memory 201856 kb
Host smart-028a6661-4c28-4a04-808c-b309ffeb2cea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4230756616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4230756616
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.1567766551
Short name T274
Test name
Test status
Simulation time 1200759008 ps
CPU time 6.94 seconds
Started Jul 07 05:56:25 PM PDT 24
Finished Jul 07 05:56:32 PM PDT 24
Peak memory 201924 kb
Host smart-be8f923a-fb7d-4ba3-94d0-90678aabc567
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1567766551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1567766551
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3231549718
Short name T441
Test name
Test status
Simulation time 35807386131 ps
CPU time 121.8 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 202048 kb
Host smart-647f9253-2a5a-4eda-bbe8-00234a5c6c84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231549718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3231549718
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1879844168
Short name T722
Test name
Test status
Simulation time 139078651825 ps
CPU time 118.81 seconds
Started Jul 07 05:56:27 PM PDT 24
Finished Jul 07 05:58:26 PM PDT 24
Peak memory 202028 kb
Host smart-8a49767d-c076-4287-a1a8-0a62c3983d41
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1879844168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1879844168
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.320336911
Short name T885
Test name
Test status
Simulation time 154327236 ps
CPU time 7.55 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:56:30 PM PDT 24
Peak memory 201916 kb
Host smart-ca8d8bf1-a176-467b-96c3-dab7e7df7ca6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320336911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.320336911
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1513211555
Short name T260
Test name
Test status
Simulation time 687672898 ps
CPU time 4.98 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:31 PM PDT 24
Peak memory 201924 kb
Host smart-5b595bb2-d7af-407c-a355-e218d3e83914
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513211555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1513211555
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.918973733
Short name T856
Test name
Test status
Simulation time 69789164 ps
CPU time 1.23 seconds
Started Jul 07 05:56:27 PM PDT 24
Finished Jul 07 05:56:28 PM PDT 24
Peak memory 201888 kb
Host smart-49d6a122-2414-4120-b525-74e40af3541c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=918973733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.918973733
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.644090347
Short name T842
Test name
Test status
Simulation time 4613273595 ps
CPU time 7.2 seconds
Started Jul 07 05:56:27 PM PDT 24
Finished Jul 07 05:56:35 PM PDT 24
Peak memory 201984 kb
Host smart-302b5e69-e874-4a15-b9c5-9b7e5a90b67d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=644090347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.644090347
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.4262076857
Short name T340
Test name
Test status
Simulation time 936483566 ps
CPU time 8.07 seconds
Started Jul 07 05:56:27 PM PDT 24
Finished Jul 07 05:56:35 PM PDT 24
Peak memory 201928 kb
Host smart-5e04641d-c902-4477-825f-f02f1d77321f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4262076857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.4262076857
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.4110661981
Short name T84
Test name
Test status
Simulation time 15116553 ps
CPU time 1.43 seconds
Started Jul 07 05:56:23 PM PDT 24
Finished Jul 07 05:56:25 PM PDT 24
Peak memory 201872 kb
Host smart-31a4f9e3-7b83-451c-a71f-02fcc855c3c2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110661981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.4110661981
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2477034120
Short name T8
Test name
Test status
Simulation time 7905432275 ps
CPU time 68.14 seconds
Started Jul 07 05:56:23 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 203976 kb
Host smart-fa597027-f240-4727-b055-58fc61c8b56b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2477034120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2477034120
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1705145403
Short name T85
Test name
Test status
Simulation time 13115148753 ps
CPU time 84.18 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201924 kb
Host smart-338efec6-16ed-4aa2-8280-bc3eaa3fd9ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1705145403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1705145403
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.163716457
Short name T213
Test name
Test status
Simulation time 536076544 ps
CPU time 74.32 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:57:36 PM PDT 24
Peak memory 206456 kb
Host smart-e3e697e9-ea28-4c6a-b4d8-d48d43d906be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=163716457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese
t_error.163716457
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2165007090
Short name T752
Test name
Test status
Simulation time 51661799 ps
CPU time 5.33 seconds
Started Jul 07 05:56:23 PM PDT 24
Finished Jul 07 05:56:29 PM PDT 24
Peak memory 201900 kb
Host smart-753e3799-1ca5-401a-8eba-9909048828b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2165007090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2165007090
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2463187640
Short name T326
Test name
Test status
Simulation time 438474703 ps
CPU time 3.31 seconds
Started Jul 07 05:56:31 PM PDT 24
Finished Jul 07 05:56:34 PM PDT 24
Peak memory 201900 kb
Host smart-5d332eda-8a32-4b1d-8d45-4017b82b5a22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2463187640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2463187640
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3100705156
Short name T203
Test name
Test status
Simulation time 9761380095 ps
CPU time 45.44 seconds
Started Jul 07 05:56:25 PM PDT 24
Finished Jul 07 05:57:11 PM PDT 24
Peak memory 202052 kb
Host smart-a92544bf-1713-4a8f-9d75-c3526945e901
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3100705156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.3100705156
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2991640033
Short name T130
Test name
Test status
Simulation time 64466830 ps
CPU time 5.29 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:32 PM PDT 24
Peak memory 202244 kb
Host smart-3f4be533-1aa7-410b-82d0-0bf3fccaf228
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2991640033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2991640033
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.4152277147
Short name T794
Test name
Test status
Simulation time 598101701 ps
CPU time 4.67 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:31 PM PDT 24
Peak memory 201900 kb
Host smart-263223e6-f13e-405d-8680-9596d5d41e13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4152277147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.4152277147
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.2370815326
Short name T425
Test name
Test status
Simulation time 483048001 ps
CPU time 9.67 seconds
Started Jul 07 05:56:25 PM PDT 24
Finished Jul 07 05:56:36 PM PDT 24
Peak memory 201884 kb
Host smart-55a6cfdc-b240-4886-87d5-65cf5446c76d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2370815326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2370815326
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1850374564
Short name T136
Test name
Test status
Simulation time 23419632369 ps
CPU time 99.88 seconds
Started Jul 07 05:56:24 PM PDT 24
Finished Jul 07 05:58:05 PM PDT 24
Peak memory 202044 kb
Host smart-642ef6e0-3052-4e9b-be0d-47ae0ec6df85
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850374564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1850374564
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2018154262
Short name T837
Test name
Test status
Simulation time 15639513337 ps
CPU time 103.96 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 202076 kb
Host smart-41cee884-bcd6-4f92-9567-e88da051fa3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2018154262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2018154262
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2255723607
Short name T40
Test name
Test status
Simulation time 54909642 ps
CPU time 6.98 seconds
Started Jul 07 05:56:30 PM PDT 24
Finished Jul 07 05:56:37 PM PDT 24
Peak memory 201724 kb
Host smart-5701dd45-bd13-4632-a645-88bf34ca8584
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255723607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2255723607
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.2040315328
Short name T875
Test name
Test status
Simulation time 963432332 ps
CPU time 8.28 seconds
Started Jul 07 05:56:25 PM PDT 24
Finished Jul 07 05:56:34 PM PDT 24
Peak memory 201912 kb
Host smart-50c2fb64-8633-481d-b4fa-6d5e1bece448
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2040315328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2040315328
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.1759165726
Short name T432
Test name
Test status
Simulation time 11047084 ps
CPU time 1.32 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:23 PM PDT 24
Peak memory 201916 kb
Host smart-771ae030-dd1e-4dce-b5c6-4161b2eb046d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759165726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1759165726
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2172867565
Short name T486
Test name
Test status
Simulation time 2255034353 ps
CPU time 7.69 seconds
Started Jul 07 05:56:24 PM PDT 24
Finished Jul 07 05:56:32 PM PDT 24
Peak memory 201956 kb
Host smart-27edce10-0d9b-4e25-bad5-ecf77aaffd19
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172867565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2172867565
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1529049985
Short name T392
Test name
Test status
Simulation time 1133976178 ps
CPU time 7.45 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:34 PM PDT 24
Peak memory 201952 kb
Host smart-5054a459-5e9b-4f18-b3f7-65508c136053
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1529049985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1529049985
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2626124780
Short name T721
Test name
Test status
Simulation time 9851697 ps
CPU time 1.03 seconds
Started Jul 07 05:56:25 PM PDT 24
Finished Jul 07 05:56:26 PM PDT 24
Peak memory 201876 kb
Host smart-d4ef3b3c-dcab-41e8-ac6e-c6668fe5c77e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626124780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2626124780
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2652093888
Short name T833
Test name
Test status
Simulation time 6215950762 ps
CPU time 53.17 seconds
Started Jul 07 05:56:28 PM PDT 24
Finished Jul 07 05:57:22 PM PDT 24
Peak memory 203040 kb
Host smart-272c6b58-459d-4475-8382-74d886882847
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2652093888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2652093888
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2213506379
Short name T499
Test name
Test status
Simulation time 273087028 ps
CPU time 20.77 seconds
Started Jul 07 05:56:27 PM PDT 24
Finished Jul 07 05:56:48 PM PDT 24
Peak memory 201900 kb
Host smart-bc5113fe-beec-416d-b95d-798703e25359
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2213506379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2213506379
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1511215191
Short name T356
Test name
Test status
Simulation time 333184957 ps
CPU time 41.44 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 204012 kb
Host smart-df07d32e-935d-485e-be46-53e00ae88200
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1511215191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.1511215191
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1623183902
Short name T790
Test name
Test status
Simulation time 13669711 ps
CPU time 1.59 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:28 PM PDT 24
Peak memory 201916 kb
Host smart-2b825911-7c8f-46f7-ac47-950d209dfa18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1623183902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1623183902
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.4112165117
Short name T376
Test name
Test status
Simulation time 468110362 ps
CPU time 12.34 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 05:57:06 PM PDT 24
Peak memory 201920 kb
Host smart-d4d02e73-2932-4f08-8ac7-e498f40523f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4112165117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.4112165117
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3109414742
Short name T194
Test name
Test status
Simulation time 258266005940 ps
CPU time 373.71 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 06:03:08 PM PDT 24
Peak memory 203672 kb
Host smart-5bb515ca-9782-4186-9010-15e376138dbf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3109414742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.3109414742
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3979851829
Short name T412
Test name
Test status
Simulation time 275988886 ps
CPU time 6.21 seconds
Started Jul 07 05:56:59 PM PDT 24
Finished Jul 07 05:57:06 PM PDT 24
Peak memory 201976 kb
Host smart-7fe5f45c-c287-42f4-b78c-989a628251e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3979851829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3979851829
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.3922637674
Short name T789
Test name
Test status
Simulation time 68865178 ps
CPU time 3.9 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:56:57 PM PDT 24
Peak memory 201920 kb
Host smart-b7a84f44-907b-4cec-b0e8-d5bc866d8937
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3922637674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3922637674
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.1763532164
Short name T463
Test name
Test status
Simulation time 92959880 ps
CPU time 6.2 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:57:00 PM PDT 24
Peak memory 201916 kb
Host smart-6ca0d9b3-be17-4fc0-b5db-74fd40fa486c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1763532164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1763532164
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2897237541
Short name T324
Test name
Test status
Simulation time 172535629644 ps
CPU time 153.34 seconds
Started Jul 07 05:56:52 PM PDT 24
Finished Jul 07 05:59:26 PM PDT 24
Peak memory 202020 kb
Host smart-66ffa176-09ff-43a7-a5bd-354532e35f46
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897237541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2897237541
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.429328080
Short name T495
Test name
Test status
Simulation time 90631591856 ps
CPU time 173.46 seconds
Started Jul 07 05:56:57 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 202068 kb
Host smart-867a87b3-a850-4d46-9c69-4f49411754e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=429328080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.429328080
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3115484067
Short name T233
Test name
Test status
Simulation time 15966143 ps
CPU time 1.85 seconds
Started Jul 07 05:56:58 PM PDT 24
Finished Jul 07 05:57:00 PM PDT 24
Peak memory 201896 kb
Host smart-b57399ad-4a6f-48d1-bd09-052871673a2c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115484067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3115484067
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2473582098
Short name T66
Test name
Test status
Simulation time 343918687 ps
CPU time 3.72 seconds
Started Jul 07 05:56:57 PM PDT 24
Finished Jul 07 05:57:01 PM PDT 24
Peak memory 201868 kb
Host smart-39cf961b-f98a-4114-9f07-0c6ed7df525a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2473582098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2473582098
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.2389539956
Short name T546
Test name
Test status
Simulation time 8053192 ps
CPU time 1.15 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:57:04 PM PDT 24
Peak memory 201880 kb
Host smart-31185494-0829-42da-8e9c-46ff2d151ad6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2389539956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2389539956
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.85756836
Short name T454
Test name
Test status
Simulation time 3387747428 ps
CPU time 10.58 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:57:04 PM PDT 24
Peak memory 201956 kb
Host smart-874b8c73-8e1e-4d5d-a6b0-9a9ff31e8d61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=85756836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.85756836
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.196674904
Short name T598
Test name
Test status
Simulation time 1601611446 ps
CPU time 7.77 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 05:57:02 PM PDT 24
Peak memory 202240 kb
Host smart-b0e96907-915a-4c5f-8038-65b900315f4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=196674904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.196674904
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.530096692
Short name T647
Test name
Test status
Simulation time 10367858 ps
CPU time 1.14 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 05:56:55 PM PDT 24
Peak memory 201908 kb
Host smart-84320308-ad98-459d-bb4a-4b2722a4da23
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530096692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.530096692
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2174471489
Short name T396
Test name
Test status
Simulation time 248582290 ps
CPU time 27.13 seconds
Started Jul 07 05:56:55 PM PDT 24
Finished Jul 07 05:57:22 PM PDT 24
Peak memory 202944 kb
Host smart-950a8ecb-b6a2-4dc9-bf63-54b5d78df4dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2174471489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2174471489
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3736908261
Short name T764
Test name
Test status
Simulation time 5110031449 ps
CPU time 16.81 seconds
Started Jul 07 05:56:52 PM PDT 24
Finished Jul 07 05:57:09 PM PDT 24
Peak memory 202100 kb
Host smart-3b57417a-09cf-4f86-b2c1-718acfaa79e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3736908261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3736908261
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1036648554
Short name T478
Test name
Test status
Simulation time 726862914 ps
CPU time 89.33 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:58:32 PM PDT 24
Peak memory 206624 kb
Host smart-f24484b6-f3ec-457f-a85f-1e9715345268
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1036648554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.1036648554
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2609945307
Short name T769
Test name
Test status
Simulation time 2050752394 ps
CPU time 42.66 seconds
Started Jul 07 05:56:55 PM PDT 24
Finished Jul 07 05:57:38 PM PDT 24
Peak memory 202960 kb
Host smart-061b1a44-d0c4-4178-a224-2be413f67237
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2609945307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.2609945307
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.497064740
Short name T25
Test name
Test status
Simulation time 1099861849 ps
CPU time 5.72 seconds
Started Jul 07 05:56:59 PM PDT 24
Finished Jul 07 05:57:05 PM PDT 24
Peak memory 201920 kb
Host smart-1f20636d-a979-43e8-99b0-77717c8327dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=497064740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.497064740
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3892546686
Short name T39
Test name
Test status
Simulation time 2718766326 ps
CPU time 16.63 seconds
Started Jul 07 05:56:59 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 201892 kb
Host smart-7d8e2bc5-16e3-441f-9817-289ea453c7c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3892546686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3892546686
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.898186403
Short name T424
Test name
Test status
Simulation time 226512818 ps
CPU time 3.67 seconds
Started Jul 07 05:57:01 PM PDT 24
Finished Jul 07 05:57:05 PM PDT 24
Peak memory 201788 kb
Host smart-76e324bf-9853-4ded-8ded-1a0b4e200592
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=898186403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.898186403
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.3614833798
Short name T327
Test name
Test status
Simulation time 345097984 ps
CPU time 5.41 seconds
Started Jul 07 05:56:56 PM PDT 24
Finished Jul 07 05:57:01 PM PDT 24
Peak memory 201920 kb
Host smart-c74e40c7-ed61-4c8c-a6b6-1072959298fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3614833798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3614833798
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.4173179893
Short name T35
Test name
Test status
Simulation time 340359622 ps
CPU time 3.58 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:56:57 PM PDT 24
Peak memory 201892 kb
Host smart-17f10fe4-1aa5-4227-b793-27cefe8f7c2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4173179893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.4173179893
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.515391209
Short name T562
Test name
Test status
Simulation time 22777627353 ps
CPU time 74.57 seconds
Started Jul 07 05:57:01 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 202036 kb
Host smart-f6035612-582a-4f68-b636-187684508522
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=515391209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.515391209
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3752507352
Short name T772
Test name
Test status
Simulation time 18768182100 ps
CPU time 123.5 seconds
Started Jul 07 05:56:58 PM PDT 24
Finished Jul 07 05:59:02 PM PDT 24
Peak memory 202040 kb
Host smart-3be3bea3-36be-44ff-803b-6bba4d2aaa9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3752507352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3752507352
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.506093623
Short name T704
Test name
Test status
Simulation time 9033712 ps
CPU time 1.15 seconds
Started Jul 07 05:56:59 PM PDT 24
Finished Jul 07 05:57:00 PM PDT 24
Peak memory 201904 kb
Host smart-4e8d4f4d-fcba-4d24-ac7f-9113eb27023b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506093623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.506093623
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.1424404003
Short name T707
Test name
Test status
Simulation time 30244867 ps
CPU time 2.68 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:57:05 PM PDT 24
Peak memory 201736 kb
Host smart-35c58b58-9552-4136-bef8-317c182c4142
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1424404003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1424404003
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.3630244571
Short name T686
Test name
Test status
Simulation time 7862420 ps
CPU time 1.02 seconds
Started Jul 07 05:57:00 PM PDT 24
Finished Jul 07 05:57:01 PM PDT 24
Peak memory 201908 kb
Host smart-8182ad55-ceda-4810-8233-c67acc3f3663
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3630244571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3630244571
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3824688793
Short name T740
Test name
Test status
Simulation time 1210768776 ps
CPU time 6.41 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:57:00 PM PDT 24
Peak memory 201916 kb
Host smart-8179ee54-552e-4cc8-b7a1-e0bbc0f0826f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824688793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3824688793
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.842439952
Short name T16
Test name
Test status
Simulation time 983592893 ps
CPU time 6.11 seconds
Started Jul 07 05:56:59 PM PDT 24
Finished Jul 07 05:57:05 PM PDT 24
Peak memory 201952 kb
Host smart-b2da71ca-f4f8-46b6-a80c-2b98a5c62c8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=842439952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.842439952
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2227400371
Short name T873
Test name
Test status
Simulation time 8770942 ps
CPU time 1.16 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:57:04 PM PDT 24
Peak memory 201880 kb
Host smart-bbc110a7-d07e-4dc8-9e08-e8d850f97e52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227400371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2227400371
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.875166814
Short name T444
Test name
Test status
Simulation time 576209895 ps
CPU time 5.5 seconds
Started Jul 07 05:57:01 PM PDT 24
Finished Jul 07 05:57:07 PM PDT 24
Peak memory 201908 kb
Host smart-738cee4c-acd4-4e12-9680-70c06003e1a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=875166814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.875166814
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.954787253
Short name T537
Test name
Test status
Simulation time 1100494019 ps
CPU time 51.09 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:57:54 PM PDT 24
Peak memory 201940 kb
Host smart-11f277db-054b-424a-a2ae-49e37205ba31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=954787253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.954787253
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.330376532
Short name T386
Test name
Test status
Simulation time 204113186 ps
CPU time 17.2 seconds
Started Jul 07 05:56:59 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 202948 kb
Host smart-ae694be3-233f-4b3d-8858-8fccc5d4afcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=330376532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand
_reset.330376532
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.551256990
Short name T221
Test name
Test status
Simulation time 464931946 ps
CPU time 62.46 seconds
Started Jul 07 05:57:03 PM PDT 24
Finished Jul 07 05:58:06 PM PDT 24
Peak memory 204988 kb
Host smart-760a6228-c575-46f8-ad93-a8d968449387
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551256990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res
et_error.551256990
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.652181041
Short name T479
Test name
Test status
Simulation time 98436690 ps
CPU time 6.78 seconds
Started Jul 07 05:56:56 PM PDT 24
Finished Jul 07 05:57:03 PM PDT 24
Peak memory 201884 kb
Host smart-e3bd6a14-3dff-4584-b259-505d9b6cb75b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=652181041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.652181041
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3687013978
Short name T102
Test name
Test status
Simulation time 1704606870 ps
CPU time 11.31 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:57:18 PM PDT 24
Peak memory 201936 kb
Host smart-dc546def-ae04-4a30-ac9f-10aae0394f3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3687013978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3687013978
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.61645307
Short name T189
Test name
Test status
Simulation time 34293068580 ps
CPU time 141.58 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:59:28 PM PDT 24
Peak memory 203100 kb
Host smart-71573d48-ee93-49da-94a5-4bc5798ee9da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=61645307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow
_rsp.61645307
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3387708068
Short name T405
Test name
Test status
Simulation time 602458495 ps
CPU time 1.96 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 201976 kb
Host smart-67a7fc41-ff8b-49c9-abd3-923f37a3385a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3387708068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3387708068
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1091155965
Short name T796
Test name
Test status
Simulation time 780317240 ps
CPU time 12.96 seconds
Started Jul 07 05:57:03 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 202204 kb
Host smart-1e8f461f-c01d-4178-a262-2bab6e05b84d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1091155965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1091155965
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.822407526
Short name T296
Test name
Test status
Simulation time 39310823 ps
CPU time 3.78 seconds
Started Jul 07 05:57:04 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 201916 kb
Host smart-e7710bfa-2ae7-41bc-a767-e1939ec28905
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=822407526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.822407526
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1624120846
Short name T119
Test name
Test status
Simulation time 117025710268 ps
CPU time 97.77 seconds
Started Jul 07 05:57:00 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 202020 kb
Host smart-b33baf3d-62b1-4587-bf9f-b7bee3a2584a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624120846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1624120846
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.684793280
Short name T541
Test name
Test status
Simulation time 11340698332 ps
CPU time 85.2 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 202076 kb
Host smart-14858b85-869e-4fe6-9beb-6d9468988322
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=684793280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.684793280
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.4012962845
Short name T595
Test name
Test status
Simulation time 22236199 ps
CPU time 3.32 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:57:06 PM PDT 24
Peak memory 202192 kb
Host smart-78811fb2-ed89-4784-b896-5a0720808260
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012962845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4012962845
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1288680105
Short name T657
Test name
Test status
Simulation time 21584307 ps
CPU time 2.02 seconds
Started Jul 07 05:57:07 PM PDT 24
Finished Jul 07 05:57:09 PM PDT 24
Peak memory 201920 kb
Host smart-e55314d6-64ee-4f97-8cfa-307a1bacfe96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1288680105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1288680105
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.1040922947
Short name T834
Test name
Test status
Simulation time 9217845 ps
CPU time 1.49 seconds
Started Jul 07 05:57:00 PM PDT 24
Finished Jul 07 05:57:02 PM PDT 24
Peak memory 201928 kb
Host smart-3bf8867f-c0a9-4f81-916e-c82721a137f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1040922947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1040922947
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2168846782
Short name T739
Test name
Test status
Simulation time 5424762238 ps
CPU time 7.69 seconds
Started Jul 07 05:57:01 PM PDT 24
Finished Jul 07 05:57:09 PM PDT 24
Peak memory 202032 kb
Host smart-8316dedc-d74d-4276-b624-7d671a3591e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168846782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2168846782
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1233801681
Short name T700
Test name
Test status
Simulation time 6390472075 ps
CPU time 8.41 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:57:15 PM PDT 24
Peak memory 202068 kb
Host smart-842acdd9-5c2e-48f2-b1d7-1386575ca8ad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1233801681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1233801681
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2189089711
Short name T783
Test name
Test status
Simulation time 11551121 ps
CPU time 1.26 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 201904 kb
Host smart-4e14f2a9-b5cf-4402-a429-ced13a8c523a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189089711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2189089711
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2998712247
Short name T735
Test name
Test status
Simulation time 194605737 ps
CPU time 20.46 seconds
Started Jul 07 05:57:04 PM PDT 24
Finished Jul 07 05:57:25 PM PDT 24
Peak memory 201916 kb
Host smart-c14fe6ec-ab0d-4158-9100-2f50c2394b46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2998712247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2998712247
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.4039904201
Short name T438
Test name
Test status
Simulation time 4478730316 ps
CPU time 72.56 seconds
Started Jul 07 05:57:04 PM PDT 24
Finished Jul 07 05:58:17 PM PDT 24
Peak memory 204368 kb
Host smart-8754c2b9-8ee0-4e2a-8ae5-542d520c37f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4039904201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4039904201
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2190860036
Short name T520
Test name
Test status
Simulation time 27930901 ps
CPU time 6.17 seconds
Started Jul 07 05:57:10 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 201904 kb
Host smart-0d451a89-15dd-4225-b19f-78a46b10eb13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2190860036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.2190860036
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3296031478
Short name T465
Test name
Test status
Simulation time 135699086 ps
CPU time 2.45 seconds
Started Jul 07 05:57:04 PM PDT 24
Finished Jul 07 05:57:07 PM PDT 24
Peak memory 201884 kb
Host smart-05e4a58c-277e-459a-bd72-0a7c70705aad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296031478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3296031478
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3443989875
Short name T240
Test name
Test status
Simulation time 48067686 ps
CPU time 7.06 seconds
Started Jul 07 05:57:07 PM PDT 24
Finished Jul 07 05:57:14 PM PDT 24
Peak memory 202200 kb
Host smart-7dce3c23-b9f6-4563-91fa-f1c189a82d28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3443989875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3443989875
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4184997891
Short name T193
Test name
Test status
Simulation time 138312997444 ps
CPU time 316.64 seconds
Started Jul 07 05:57:07 PM PDT 24
Finished Jul 07 06:02:23 PM PDT 24
Peak memory 203072 kb
Host smart-70627373-8888-4a18-a226-2e7d5cf5081a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4184997891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.4184997891
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2315481672
Short name T620
Test name
Test status
Simulation time 831509878 ps
CPU time 6.19 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:23 PM PDT 24
Peak memory 201940 kb
Host smart-4f9b0d86-8b20-40d3-8b31-673aee5e7a11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2315481672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2315481672
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.384346513
Short name T717
Test name
Test status
Simulation time 271721684 ps
CPU time 6.35 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:57:12 PM PDT 24
Peak memory 201920 kb
Host smart-f0781764-c9a4-4e4f-b6cd-9e5b0de72cdd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=384346513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.384346513
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.1180344986
Short name T804
Test name
Test status
Simulation time 831701752 ps
CPU time 11.26 seconds
Started Jul 07 05:57:12 PM PDT 24
Finished Jul 07 05:57:23 PM PDT 24
Peak memory 201904 kb
Host smart-2bf6cacb-b261-4491-8e06-ecef23dbfe64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1180344986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1180344986
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3518983033
Short name T436
Test name
Test status
Simulation time 21016478831 ps
CPU time 55.68 seconds
Started Jul 07 05:57:07 PM PDT 24
Finished Jul 07 05:58:03 PM PDT 24
Peak memory 202036 kb
Host smart-663647a9-d16b-4c48-ba17-a7d28b2a66f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518983033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3518983033
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2131459374
Short name T125
Test name
Test status
Simulation time 32669496333 ps
CPU time 77.2 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:58:35 PM PDT 24
Peak memory 202044 kb
Host smart-19fafc99-6c60-4f60-bb7a-d8f74608ee60
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2131459374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2131459374
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.4070921329
Short name T511
Test name
Test status
Simulation time 31238790 ps
CPU time 3.91 seconds
Started Jul 07 05:57:10 PM PDT 24
Finished Jul 07 05:57:14 PM PDT 24
Peak memory 201904 kb
Host smart-f643cdfe-2e2e-4dfd-b51d-315ed7429b1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070921329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.4070921329
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.1954477986
Short name T619
Test name
Test status
Simulation time 151511223 ps
CPU time 2.22 seconds
Started Jul 07 05:57:13 PM PDT 24
Finished Jul 07 05:57:15 PM PDT 24
Peak memory 201924 kb
Host smart-9da201a2-d809-4ace-964e-64ca27cb58f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954477986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1954477986
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.804545116
Short name T429
Test name
Test status
Simulation time 112240722 ps
CPU time 1.39 seconds
Started Jul 07 05:57:09 PM PDT 24
Finished Jul 07 05:57:11 PM PDT 24
Peak memory 201840 kb
Host smart-e0577beb-6f91-4e16-9b13-376ec19ec520
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=804545116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.804545116
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.566580669
Short name T96
Test name
Test status
Simulation time 1622300485 ps
CPU time 7.12 seconds
Started Jul 07 05:57:13 PM PDT 24
Finished Jul 07 05:57:20 PM PDT 24
Peak memory 201904 kb
Host smart-105003f5-4836-41f0-8359-c14c9bccdc6b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=566580669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.566580669
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.27725115
Short name T230
Test name
Test status
Simulation time 2897497124 ps
CPU time 4.88 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:23 PM PDT 24
Peak memory 201984 kb
Host smart-551ca624-f424-46f1-8d25-54d9a4f5eeaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=27725115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.27725115
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1405372453
Short name T369
Test name
Test status
Simulation time 10404816 ps
CPU time 1.24 seconds
Started Jul 07 05:57:06 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 201912 kb
Host smart-3cd0b985-ea87-445c-8634-af23a6d52149
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405372453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1405372453
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2894083494
Short name T24
Test name
Test status
Simulation time 4853978512 ps
CPU time 33.85 seconds
Started Jul 07 05:57:13 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 203048 kb
Host smart-b8493a84-3a8f-46d2-a93a-c14e3c54d324
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2894083494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2894083494
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3063532201
Short name T736
Test name
Test status
Simulation time 302779185 ps
CPU time 9.6 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:27 PM PDT 24
Peak memory 201948 kb
Host smart-2c7d5e9c-c03f-44f1-9477-2b9070a31218
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3063532201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3063532201
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.4242236374
Short name T835
Test name
Test status
Simulation time 7163732934 ps
CPU time 47.82 seconds
Started Jul 07 05:57:11 PM PDT 24
Finished Jul 07 05:57:59 PM PDT 24
Peak memory 205620 kb
Host smart-65fe4190-a82f-4985-a431-0bf3087829ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4242236374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.4242236374
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4197140074
Short name T319
Test name
Test status
Simulation time 269431950 ps
CPU time 35.31 seconds
Started Jul 07 05:57:14 PM PDT 24
Finished Jul 07 05:57:50 PM PDT 24
Peak memory 203836 kb
Host smart-318cc6f5-d253-4f9d-9b5f-61bbc9423f84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197140074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.4197140074
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3404988654
Short name T625
Test name
Test status
Simulation time 761143177 ps
CPU time 7.92 seconds
Started Jul 07 05:57:07 PM PDT 24
Finished Jul 07 05:57:15 PM PDT 24
Peak memory 201908 kb
Host smart-797b8f68-0667-4edb-a266-78c5cb22bc1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3404988654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3404988654
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2039138781
Short name T110
Test name
Test status
Simulation time 586443825 ps
CPU time 7.11 seconds
Started Jul 07 05:57:13 PM PDT 24
Finished Jul 07 05:57:20 PM PDT 24
Peak memory 201896 kb
Host smart-62a97de4-6d3c-493d-acca-22b8c0ef1ecf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2039138781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2039138781
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.700812933
Short name T698
Test name
Test status
Simulation time 963646682 ps
CPU time 9.45 seconds
Started Jul 07 05:57:13 PM PDT 24
Finished Jul 07 05:57:23 PM PDT 24
Peak memory 201980 kb
Host smart-12980a16-b57f-4125-89dd-a62144716582
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=700812933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.700812933
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.239911713
Short name T661
Test name
Test status
Simulation time 152562385 ps
CPU time 2.08 seconds
Started Jul 07 05:57:12 PM PDT 24
Finished Jul 07 05:57:15 PM PDT 24
Peak memory 201900 kb
Host smart-3a401d08-ba7e-45b1-9b1d-57d494490135
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=239911713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.239911713
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.2005841540
Short name T72
Test name
Test status
Simulation time 1464949746 ps
CPU time 8.47 seconds
Started Jul 07 05:57:10 PM PDT 24
Finished Jul 07 05:57:19 PM PDT 24
Peak memory 201884 kb
Host smart-1b76910c-1ba0-4da6-aff4-fd84e8ed8240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2005841540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2005841540
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.837755878
Short name T257
Test name
Test status
Simulation time 138642167247 ps
CPU time 152.35 seconds
Started Jul 07 05:57:14 PM PDT 24
Finished Jul 07 05:59:47 PM PDT 24
Peak memory 202008 kb
Host smart-b46039df-2442-4cea-9503-13b8d4391a0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=837755878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.837755878
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2800161308
Short name T62
Test name
Test status
Simulation time 11720854265 ps
CPU time 65.4 seconds
Started Jul 07 05:57:12 PM PDT 24
Finished Jul 07 05:58:17 PM PDT 24
Peak memory 202068 kb
Host smart-523d815b-bb45-4cfa-911c-2f06da9d5366
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2800161308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2800161308
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.4008831246
Short name T246
Test name
Test status
Simulation time 66989284 ps
CPU time 8.02 seconds
Started Jul 07 05:57:14 PM PDT 24
Finished Jul 07 05:57:22 PM PDT 24
Peak memory 201904 kb
Host smart-c7aacc49-f3fe-4d4f-8229-1119ae10ff27
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008831246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.4008831246
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.3052509859
Short name T497
Test name
Test status
Simulation time 41217082 ps
CPU time 3.63 seconds
Started Jul 07 05:57:12 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 201944 kb
Host smart-fa212cb9-21f2-4e43-b446-9d9069819168
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3052509859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3052509859
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.2538663502
Short name T502
Test name
Test status
Simulation time 158364921 ps
CPU time 1.25 seconds
Started Jul 07 05:57:09 PM PDT 24
Finished Jul 07 05:57:11 PM PDT 24
Peak memory 201876 kb
Host smart-57651e8a-819a-40ac-a219-97070b563e10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2538663502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2538663502
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3370154451
Short name T226
Test name
Test status
Simulation time 6338155983 ps
CPU time 9.62 seconds
Started Jul 07 05:57:12 PM PDT 24
Finished Jul 07 05:57:21 PM PDT 24
Peak memory 202036 kb
Host smart-4a4f3230-bf8f-4585-9e1f-0082aad5fd77
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370154451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3370154451
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2766448761
Short name T456
Test name
Test status
Simulation time 3229290169 ps
CPU time 12.05 seconds
Started Jul 07 05:57:14 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 202012 kb
Host smart-88f8cea0-6390-4e3a-83b6-0cd18d8ff60f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2766448761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2766448761
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1377042625
Short name T286
Test name
Test status
Simulation time 11070967 ps
CPU time 1.34 seconds
Started Jul 07 05:57:11 PM PDT 24
Finished Jul 07 05:57:12 PM PDT 24
Peak memory 201904 kb
Host smart-f90587da-edb3-4c3b-95bb-82c167685d62
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377042625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1377042625
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2182009838
Short name T178
Test name
Test status
Simulation time 11867527285 ps
CPU time 54 seconds
Started Jul 07 05:57:14 PM PDT 24
Finished Jul 07 05:58:08 PM PDT 24
Peak memory 203068 kb
Host smart-598fdbc4-a5d6-4b54-9849-9b29f5a3d8d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2182009838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2182009838
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3594997476
Short name T516
Test name
Test status
Simulation time 22113897 ps
CPU time 2.21 seconds
Started Jul 07 05:57:15 PM PDT 24
Finished Jul 07 05:57:18 PM PDT 24
Peak memory 201968 kb
Host smart-c182c81f-f44c-47dc-a7d9-61de02b0d4b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3594997476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3594997476
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3170253099
Short name T222
Test name
Test status
Simulation time 149086962 ps
CPU time 13.48 seconds
Started Jul 07 05:57:16 PM PDT 24
Finished Jul 07 05:57:30 PM PDT 24
Peak memory 202996 kb
Host smart-0c207f71-f853-4094-9759-fb75b0f31aed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3170253099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3170253099
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.947881584
Short name T487
Test name
Test status
Simulation time 149102800 ps
CPU time 18.37 seconds
Started Jul 07 05:57:21 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 202992 kb
Host smart-be51c307-45c2-4466-8c23-945fc7473558
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=947881584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res
et_error.947881584
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2431743844
Short name T471
Test name
Test status
Simulation time 72283459 ps
CPU time 5.97 seconds
Started Jul 07 05:57:13 PM PDT 24
Finished Jul 07 05:57:19 PM PDT 24
Peak memory 201892 kb
Host smart-d0bea289-671f-480c-9c2d-c430dfac1269
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2431743844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2431743844
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2953618986
Short name T45
Test name
Test status
Simulation time 184461462 ps
CPU time 4.37 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:33 PM PDT 24
Peak memory 201904 kb
Host smart-73f54957-9230-4341-9b81-dacf43e1b0a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2953618986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2953618986
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.4103738892
Short name T202
Test name
Test status
Simulation time 36940107105 ps
CPU time 222.08 seconds
Started Jul 07 05:57:19 PM PDT 24
Finished Jul 07 06:01:01 PM PDT 24
Peak memory 203300 kb
Host smart-8480375b-b717-42b2-bf92-66661517c61b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4103738892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.4103738892
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.352018607
Short name T129
Test name
Test status
Simulation time 404086811 ps
CPU time 6.63 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:24 PM PDT 24
Peak memory 201848 kb
Host smart-20499c2a-5a2d-4a81-9123-d6d3b5e1b0a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=352018607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.352018607
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.4005693110
Short name T828
Test name
Test status
Simulation time 255625904 ps
CPU time 6.46 seconds
Started Jul 07 05:57:29 PM PDT 24
Finished Jul 07 05:57:37 PM PDT 24
Peak memory 201900 kb
Host smart-133e0d09-4e06-48b8-a95b-91213a214979
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005693110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4005693110
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.3888924173
Short name T291
Test name
Test status
Simulation time 60704118 ps
CPU time 3.81 seconds
Started Jul 07 05:57:18 PM PDT 24
Finished Jul 07 05:57:22 PM PDT 24
Peak memory 201916 kb
Host smart-8e631c4a-a2df-4532-8941-11e7c5bfc9e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3888924173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3888924173
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2962356696
Short name T763
Test name
Test status
Simulation time 66968870805 ps
CPU time 193.3 seconds
Started Jul 07 05:57:18 PM PDT 24
Finished Jul 07 06:00:31 PM PDT 24
Peak memory 202048 kb
Host smart-8d494ef5-2cca-465b-b46c-6fc168144ffa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962356696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2962356696
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2093594458
Short name T145
Test name
Test status
Simulation time 5492341608 ps
CPU time 35.46 seconds
Started Jul 07 05:57:22 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 202096 kb
Host smart-0ea1fb23-f44a-42a2-a859-ca3f14021d8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2093594458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2093594458
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1987477919
Short name T271
Test name
Test status
Simulation time 61668799 ps
CPU time 8.17 seconds
Started Jul 07 05:57:22 PM PDT 24
Finished Jul 07 05:57:31 PM PDT 24
Peak memory 201724 kb
Host smart-3cfb9958-54b3-4cb6-b7ac-2336fb26ad83
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987477919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1987477919
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.4075625976
Short name T86
Test name
Test status
Simulation time 10091883 ps
CPU time 1.3 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:29 PM PDT 24
Peak memory 201900 kb
Host smart-9c6fbd15-1834-4b40-97e2-72c3b5182960
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4075625976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4075625976
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3639863532
Short name T500
Test name
Test status
Simulation time 11754023 ps
CPU time 1.21 seconds
Started Jul 07 05:57:15 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 201908 kb
Host smart-a17578d3-e4f1-4079-ac39-0babb6df6670
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3639863532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3639863532
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2530171777
Short name T138
Test name
Test status
Simulation time 15948376999 ps
CPU time 10.52 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:28 PM PDT 24
Peak memory 202012 kb
Host smart-9ad166e3-9291-40fa-8157-8863572a1e9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530171777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2530171777
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2901275196
Short name T430
Test name
Test status
Simulation time 1167708561 ps
CPU time 8.51 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 201932 kb
Host smart-65acbaa5-452b-4afe-98a1-8ecc0fb067ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2901275196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2901275196
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1105128766
Short name T677
Test name
Test status
Simulation time 19714537 ps
CPU time 1.25 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:18 PM PDT 24
Peak memory 201908 kb
Host smart-658c8434-37d0-499b-a84a-1c8be32701a3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105128766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1105128766
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2698338901
Short name T82
Test name
Test status
Simulation time 8375202024 ps
CPU time 37.38 seconds
Started Jul 07 05:57:15 PM PDT 24
Finished Jul 07 05:57:53 PM PDT 24
Peak memory 203072 kb
Host smart-b6df688b-b73d-4865-818b-f47f8b730282
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2698338901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2698338901
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1029840726
Short name T332
Test name
Test status
Simulation time 14934003182 ps
CPU time 42.41 seconds
Started Jul 07 05:57:22 PM PDT 24
Finished Jul 07 05:58:05 PM PDT 24
Peak memory 201916 kb
Host smart-aeea9354-f0a6-4b67-a93b-cb6c96e0a62f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1029840726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1029840726
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.730711964
Short name T379
Test name
Test status
Simulation time 3787422562 ps
CPU time 100.79 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:59:09 PM PDT 24
Peak memory 205128 kb
Host smart-906d3936-7710-4676-a33b-e1502c23c67f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=730711964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand
_reset.730711964
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.280404056
Short name T355
Test name
Test status
Simulation time 7665184507 ps
CPU time 51.35 seconds
Started Jul 07 05:57:19 PM PDT 24
Finished Jul 07 05:58:10 PM PDT 24
Peak memory 204140 kb
Host smart-9b51c55f-4566-4396-be59-cceb0c7ec48a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=280404056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res
et_error.280404056
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1556196175
Short name T850
Test name
Test status
Simulation time 38786908 ps
CPU time 1.19 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:57:29 PM PDT 24
Peak memory 201900 kb
Host smart-3c481dbb-4733-46c3-83a6-c0564df84c33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1556196175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1556196175
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3221441264
Short name T115
Test name
Test status
Simulation time 806949248 ps
CPU time 10.4 seconds
Started Jul 07 05:57:24 PM PDT 24
Finished Jul 07 05:57:35 PM PDT 24
Peak memory 201864 kb
Host smart-5cbbf309-9a60-4121-ab05-50f7affd103a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3221441264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3221441264
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1882813091
Short name T196
Test name
Test status
Simulation time 115955201783 ps
CPU time 341.17 seconds
Started Jul 07 05:57:19 PM PDT 24
Finished Jul 07 06:03:01 PM PDT 24
Peak memory 203752 kb
Host smart-7bf3e656-3dd8-40bf-bfef-467a1751a383
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1882813091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.1882813091
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2701865042
Short name T745
Test name
Test status
Simulation time 663445773 ps
CPU time 2.57 seconds
Started Jul 07 05:57:21 PM PDT 24
Finished Jul 07 05:57:24 PM PDT 24
Peak memory 201980 kb
Host smart-073b9f52-d5d2-467b-8998-0b310c191357
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2701865042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2701865042
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.3029479019
Short name T795
Test name
Test status
Simulation time 178862533 ps
CPU time 10.11 seconds
Started Jul 07 05:57:20 PM PDT 24
Finished Jul 07 05:57:31 PM PDT 24
Peak memory 201896 kb
Host smart-59c2bbf1-9154-4fd8-b4d5-14776e2b2aa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3029479019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3029479019
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.2906518677
Short name T2
Test name
Test status
Simulation time 104661740 ps
CPU time 9.33 seconds
Started Jul 07 05:57:16 PM PDT 24
Finished Jul 07 05:57:25 PM PDT 24
Peak memory 201904 kb
Host smart-270d948c-ca66-4b34-afba-09b7ca48dc21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2906518677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2906518677
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3376184894
Short name T667
Test name
Test status
Simulation time 10301165208 ps
CPU time 39.03 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:58:02 PM PDT 24
Peak memory 202040 kb
Host smart-101c6ed3-7ca5-4b69-8f6b-debed2aba703
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376184894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3376184894
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3202924537
Short name T28
Test name
Test status
Simulation time 10454466919 ps
CPU time 47.75 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 202048 kb
Host smart-59064c07-4b09-4c2f-bfb6-8a06962c6ce0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3202924537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3202924537
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.1581192078
Short name T87
Test name
Test status
Simulation time 42255709 ps
CPU time 2.3 seconds
Started Jul 07 05:57:24 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 201888 kb
Host smart-71e10049-e798-46b0-8b53-5ba36b5b2a7a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581192078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1581192078
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.793427692
Short name T408
Test name
Test status
Simulation time 108718572 ps
CPU time 5.95 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201828 kb
Host smart-e2b06bc4-974e-451b-8fbb-f0c9dc031896
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=793427692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.793427692
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.1408741499
Short name T697
Test name
Test status
Simulation time 7967085 ps
CPU time 1.04 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:18 PM PDT 24
Peak memory 201908 kb
Host smart-afea6f82-ea24-4ffc-a9cd-a4b8b6bc3369
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1408741499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1408741499
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1836110460
Short name T770
Test name
Test status
Simulation time 3691709597 ps
CPU time 10.86 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:39 PM PDT 24
Peak memory 201956 kb
Host smart-3fb02184-e546-4823-9dcb-d7abc57b8f3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836110460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1836110460
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3744292376
Short name T733
Test name
Test status
Simulation time 4551488796 ps
CPU time 5.12 seconds
Started Jul 07 05:57:17 PM PDT 24
Finished Jul 07 05:57:22 PM PDT 24
Peak memory 202076 kb
Host smart-68b68190-7ce2-4225-877e-85d62d4bb89f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3744292376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3744292376
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1322319114
Short name T399
Test name
Test status
Simulation time 9581243 ps
CPU time 1.12 seconds
Started Jul 07 05:57:20 PM PDT 24
Finished Jul 07 05:57:21 PM PDT 24
Peak memory 201904 kb
Host smart-6aa4c0b8-9295-476a-96f4-e27f178525f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322319114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1322319114
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.765933322
Short name T791
Test name
Test status
Simulation time 759348833 ps
CPU time 31.27 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:57:54 PM PDT 24
Peak memory 201860 kb
Host smart-309af7f2-4140-4163-8f2d-ba4b04fef6a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=765933322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.765933322
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1310426979
Short name T348
Test name
Test status
Simulation time 175621299 ps
CPU time 12.03 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:57:35 PM PDT 24
Peak memory 201904 kb
Host smart-cdf71ce9-cee6-4bb5-bae2-1bcda1c39550
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1310426979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1310426979
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3111695505
Short name T507
Test name
Test status
Simulation time 437714842 ps
CPU time 48.72 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:58:15 PM PDT 24
Peak memory 204228 kb
Host smart-2e71220e-302b-4a8c-851e-86dc3b51cdac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3111695505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.3111695505
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.845726607
Short name T767
Test name
Test status
Simulation time 73713613 ps
CPU time 9.71 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:57:33 PM PDT 24
Peak memory 201904 kb
Host smart-fefcda42-6728-4771-9360-7bc9f3f76d42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=845726607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res
et_error.845726607
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2731463029
Short name T34
Test name
Test status
Simulation time 963727531 ps
CPU time 10.21 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:57:34 PM PDT 24
Peak memory 201828 kb
Host smart-d2ef3347-7af6-4923-8dd1-8cec9fa6c879
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2731463029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2731463029
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2622148402
Short name T569
Test name
Test status
Simulation time 707293280 ps
CPU time 10.28 seconds
Started Jul 07 05:57:24 PM PDT 24
Finished Jul 07 05:57:35 PM PDT 24
Peak memory 201856 kb
Host smart-93fb5c5f-ffdd-41ae-ad9b-47a707dbb895
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622148402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2622148402
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3150468139
Short name T775
Test name
Test status
Simulation time 76268783 ps
CPU time 5.54 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201876 kb
Host smart-222234a0-e972-48b8-a1a9-2ac0defdbe06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3150468139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3150468139
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.2958022854
Short name T267
Test name
Test status
Simulation time 60230888 ps
CPU time 2.28 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 201896 kb
Host smart-82b5f82f-17c7-4c68-9b05-73c07c7604b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2958022854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2958022854
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.2087362672
Short name T236
Test name
Test status
Simulation time 8634837 ps
CPU time 1.08 seconds
Started Jul 07 05:57:19 PM PDT 24
Finished Jul 07 05:57:21 PM PDT 24
Peak memory 201888 kb
Host smart-6858c50b-da2b-40b9-b59b-7642eb294cd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2087362672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2087362672
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.706660705
Short name T561
Test name
Test status
Simulation time 30157142383 ps
CPU time 74.35 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:58:41 PM PDT 24
Peak memory 202008 kb
Host smart-3323687d-d47c-4925-9bfd-601f861e1079
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=706660705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.706660705
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1854841133
Short name T663
Test name
Test status
Simulation time 7295199629 ps
CPU time 26.19 seconds
Started Jul 07 05:57:22 PM PDT 24
Finished Jul 07 05:57:49 PM PDT 24
Peak memory 202004 kb
Host smart-a73bf904-aec9-4c62-8116-222cdfd38946
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1854841133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1854841133
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.184412947
Short name T660
Test name
Test status
Simulation time 50871524 ps
CPU time 2.05 seconds
Started Jul 07 05:57:24 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 201904 kb
Host smart-0e52eda6-abf0-4f44-865f-a64b80e3ea52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184412947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.184412947
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.3367634981
Short name T248
Test name
Test status
Simulation time 353001094 ps
CPU time 2.58 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:57:29 PM PDT 24
Peak memory 201912 kb
Host smart-b7c31add-1976-4dea-88ae-b86b1c4f036a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3367634981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3367634981
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2202151997
Short name T55
Test name
Test status
Simulation time 68111726 ps
CPU time 1.34 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:57:27 PM PDT 24
Peak memory 201920 kb
Host smart-9e7fe7d8-e4cd-4fa8-9d33-f55b292c5e93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2202151997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2202151997
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3889836555
Short name T665
Test name
Test status
Simulation time 2108310296 ps
CPU time 9.21 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:57:34 PM PDT 24
Peak memory 201856 kb
Host smart-3a9955ba-a065-4e32-9d6a-213110e4dfe4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889836555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3889836555
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2581228163
Short name T846
Test name
Test status
Simulation time 861229761 ps
CPU time 4.45 seconds
Started Jul 07 05:57:23 PM PDT 24
Finished Jul 07 05:57:28 PM PDT 24
Peak memory 201952 kb
Host smart-d328844d-99b6-4f38-a68b-f595d91bd591
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2581228163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2581228163
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.226422956
Short name T464
Test name
Test status
Simulation time 9055327 ps
CPU time 1.31 seconds
Started Jul 07 05:57:29 PM PDT 24
Finished Jul 07 05:57:31 PM PDT 24
Peak memory 201888 kb
Host smart-39dc50f6-0e34-413d-88a2-fc6158cfbc8f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226422956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.226422956
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.1018483856
Short name T281
Test name
Test status
Simulation time 785469059 ps
CPU time 9.04 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:57:36 PM PDT 24
Peak memory 201940 kb
Host smart-c01ab279-7cef-4d64-b075-43df2117b627
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1018483856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1018483856
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3117780221
Short name T556
Test name
Test status
Simulation time 148017918 ps
CPU time 11.61 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:57:38 PM PDT 24
Peak memory 201888 kb
Host smart-5f067f26-583d-414f-a625-d1414171a5c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3117780221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3117780221
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3531912467
Short name T107
Test name
Test status
Simulation time 2612252478 ps
CPU time 37.7 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:58:05 PM PDT 24
Peak memory 204092 kb
Host smart-fcaf7f0c-d5e6-42d9-90df-a202b06dcd30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3531912467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.3531912467
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.120890889
Short name T610
Test name
Test status
Simulation time 2995170257 ps
CPU time 71.5 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:58:36 PM PDT 24
Peak memory 204104 kb
Host smart-47a64ae3-1d17-4fcd-b5ad-cc62abc4d6e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=120890889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res
et_error.120890889
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.3312240204
Short name T283
Test name
Test status
Simulation time 334216706 ps
CPU time 3.61 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201916 kb
Host smart-a3f1b2b8-e339-4e2d-86df-226dc46df3be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3312240204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3312240204
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3779689333
Short name T558
Test name
Test status
Simulation time 1417664775 ps
CPU time 20.03 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:48 PM PDT 24
Peak memory 201916 kb
Host smart-65bf7668-b50a-4c80-8bbb-9a6e308081f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779689333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3779689333
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2688367751
Short name T186
Test name
Test status
Simulation time 32261127369 ps
CPU time 235.35 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 06:01:24 PM PDT 24
Peak memory 203380 kb
Host smart-d95219a1-4032-47a7-b82d-0b5d56e26830
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2688367751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.2688367751
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1445098841
Short name T77
Test name
Test status
Simulation time 664315745 ps
CPU time 4.95 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201972 kb
Host smart-992e07de-d36e-46dc-914d-d608c60ebe8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1445098841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1445098841
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.1933967664
Short name T587
Test name
Test status
Simulation time 2293906132 ps
CPU time 10.72 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:57:37 PM PDT 24
Peak memory 201920 kb
Host smart-d41d4ada-f4d2-4947-96ec-7de1864c6cbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1933967664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1933967664
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.995960555
Short name T889
Test name
Test status
Simulation time 61834101 ps
CPU time 1.96 seconds
Started Jul 07 05:57:24 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 201916 kb
Host smart-f31e622a-8045-46bc-8d26-68d6d6a6c015
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=995960555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.995960555
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1632598536
Short name T847
Test name
Test status
Simulation time 29094460043 ps
CPU time 138.31 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 202040 kb
Host smart-c3be9856-f298-41a6-83d6-3d29eff3fa65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632598536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1632598536
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.4079347120
Short name T496
Test name
Test status
Simulation time 1871696789 ps
CPU time 7.95 seconds
Started Jul 07 05:57:25 PM PDT 24
Finished Jul 07 05:57:33 PM PDT 24
Peak memory 201952 kb
Host smart-4fc35807-9c7c-4b11-8396-44037e612838
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4079347120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4079347120
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2744992093
Short name T328
Test name
Test status
Simulation time 55852875 ps
CPU time 3.4 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:34 PM PDT 24
Peak memory 201864 kb
Host smart-9e7538fd-9d21-41b7-a909-8c48f0d16347
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744992093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2744992093
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.378135363
Short name T164
Test name
Test status
Simulation time 22938986 ps
CPU time 2.28 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201880 kb
Host smart-6edf0f46-df9f-4735-b472-57bcbead3e78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=378135363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.378135363
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.2244814413
Short name T79
Test name
Test status
Simulation time 188944698 ps
CPU time 1.69 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:57:28 PM PDT 24
Peak memory 201816 kb
Host smart-0d49c073-5d17-4d6e-b485-636569b19314
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2244814413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2244814413
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.217687590
Short name T694
Test name
Test status
Simulation time 4733417450 ps
CPU time 10.37 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:57:37 PM PDT 24
Peak memory 201996 kb
Host smart-d93c5b30-c52e-4a6c-976a-106c3596c3eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=217687590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.217687590
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3587585593
Short name T417
Test name
Test status
Simulation time 2209952890 ps
CPU time 5.81 seconds
Started Jul 07 05:57:24 PM PDT 24
Finished Jul 07 05:57:30 PM PDT 24
Peak memory 201976 kb
Host smart-5e1484f5-177a-4f15-b6e5-5f903cf9730c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3587585593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3587585593
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3626688820
Short name T793
Test name
Test status
Simulation time 8893805 ps
CPU time 1.15 seconds
Started Jul 07 05:57:26 PM PDT 24
Finished Jul 07 05:57:27 PM PDT 24
Peak memory 201880 kb
Host smart-cbb7c0ad-c4d4-4a11-b204-f139b304ab45
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626688820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3626688820
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2052670144
Short name T52
Test name
Test status
Simulation time 231068139 ps
CPU time 15.8 seconds
Started Jul 07 05:57:32 PM PDT 24
Finished Jul 07 05:57:48 PM PDT 24
Peak memory 203232 kb
Host smart-359286a4-4e71-40af-aa0f-76e22eefbb96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2052670144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2052670144
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1495563861
Short name T177
Test name
Test status
Simulation time 9570489403 ps
CPU time 29.25 seconds
Started Jul 07 05:57:32 PM PDT 24
Finished Jul 07 05:58:01 PM PDT 24
Peak memory 202072 kb
Host smart-89f0aaa5-e77c-43f9-8991-16dd93dbb317
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1495563861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1495563861
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2705932850
Short name T88
Test name
Test status
Simulation time 246920551 ps
CPU time 16.86 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 203984 kb
Host smart-fb89bb86-3fb2-4000-80af-0103054df6e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2705932850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.2705932850
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.7412260
Short name T431
Test name
Test status
Simulation time 270272757 ps
CPU time 2.8 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:31 PM PDT 24
Peak memory 201916 kb
Host smart-09189bb3-a0c3-43e9-8c41-8c0b072a6e90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7412260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.7412260
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1039060904
Short name T800
Test name
Test status
Simulation time 72300995 ps
CPU time 12.83 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 201900 kb
Host smart-19f7bf07-c68e-47af-bf1f-288ee2e4b0ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1039060904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1039060904
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.108645979
Short name T477
Test name
Test status
Simulation time 2720640197 ps
CPU time 17.89 seconds
Started Jul 07 05:57:37 PM PDT 24
Finished Jul 07 05:57:55 PM PDT 24
Peak memory 201932 kb
Host smart-38c46684-8b55-47b7-b83e-2009ff230166
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=108645979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo
w_rsp.108645979
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3714512646
Short name T284
Test name
Test status
Simulation time 231199185 ps
CPU time 5.04 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:57:36 PM PDT 24
Peak memory 201968 kb
Host smart-0bbb08c4-e2b5-4f0e-a512-e2107e43d89f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3714512646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3714512646
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.3789056617
Short name T799
Test name
Test status
Simulation time 73525919 ps
CPU time 4.67 seconds
Started Jul 07 05:57:34 PM PDT 24
Finished Jul 07 05:57:38 PM PDT 24
Peak memory 201812 kb
Host smart-965a2b58-24d7-4307-9cee-17c4f56c89b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3789056617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3789056617
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.194549612
Short name T161
Test name
Test status
Simulation time 1677977777 ps
CPU time 11.69 seconds
Started Jul 07 05:57:28 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 201920 kb
Host smart-1181d000-aa5a-4298-b9b9-7213e9c37683
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=194549612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.194549612
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2091927396
Short name T109
Test name
Test status
Simulation time 141897185452 ps
CPU time 162.22 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 06:00:13 PM PDT 24
Peak memory 202040 kb
Host smart-7cb641cc-08d5-407c-a93e-99e708b93d7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091927396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2091927396
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2357141829
Short name T725
Test name
Test status
Simulation time 19687430840 ps
CPU time 116.28 seconds
Started Jul 07 05:57:27 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 202360 kb
Host smart-52e1c256-de22-47f2-9cef-660d0656113a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2357141829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2357141829
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2875664064
Short name T632
Test name
Test status
Simulation time 94966266 ps
CPU time 4.11 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:35 PM PDT 24
Peak memory 201948 kb
Host smart-7e08ad62-25bf-40cb-9090-61b98d0979ff
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875664064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2875664064
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.827586905
Short name T298
Test name
Test status
Simulation time 39135361 ps
CPU time 4.49 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:57:36 PM PDT 24
Peak memory 201916 kb
Host smart-1ce41421-f776-40c0-8a53-543c0783d6ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=827586905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.827586905
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2836019279
Short name T414
Test name
Test status
Simulation time 7957423 ps
CPU time 1.17 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201904 kb
Host smart-5e359287-c756-4d4a-a856-82264ce7e1bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836019279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2836019279
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3421179900
Short name T387
Test name
Test status
Simulation time 3496709103 ps
CPU time 10.01 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 201984 kb
Host smart-93efec4a-9ea8-4ab9-af66-0632f431961c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421179900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3421179900
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1561120785
Short name T312
Test name
Test status
Simulation time 1604496543 ps
CPU time 7.22 seconds
Started Jul 07 05:57:34 PM PDT 24
Finished Jul 07 05:57:41 PM PDT 24
Peak memory 201928 kb
Host smart-adceb7f9-92c9-4298-9193-e6d571af028e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1561120785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1561120785
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2354442287
Short name T179
Test name
Test status
Simulation time 9731685 ps
CPU time 1.14 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:32 PM PDT 24
Peak memory 201892 kb
Host smart-351980ae-5258-42e1-b97f-a8b9c81b3274
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354442287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2354442287
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.2819035142
Short name T101
Test name
Test status
Simulation time 5040540433 ps
CPU time 25.69 seconds
Started Jul 07 05:57:37 PM PDT 24
Finished Jul 07 05:58:03 PM PDT 24
Peak memory 201964 kb
Host smart-42f71b92-3cf1-47ea-a917-8a205998b9e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819035142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2819035142
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.701645845
Short name T774
Test name
Test status
Simulation time 3930170705 ps
CPU time 48.62 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:58:21 PM PDT 24
Peak memory 203012 kb
Host smart-7cb50235-d34c-4f00-b46e-82597005a47c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=701645845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.701645845
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3652515640
Short name T529
Test name
Test status
Simulation time 623968070 ps
CPU time 122.65 seconds
Started Jul 07 05:57:37 PM PDT 24
Finished Jul 07 05:59:39 PM PDT 24
Peak memory 204724 kb
Host smart-a7cb6c1c-423a-4d94-b682-53c8cfa1a240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3652515640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.3652515640
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1471002681
Short name T672
Test name
Test status
Simulation time 88205192 ps
CPU time 12.16 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:57:44 PM PDT 24
Peak memory 201940 kb
Host smart-30ee002b-94bd-40ae-aa6f-ba1d9cb46351
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1471002681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.1471002681
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1001969383
Short name T455
Test name
Test status
Simulation time 150540665 ps
CPU time 3.16 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:57:35 PM PDT 24
Peak memory 201796 kb
Host smart-63e91b75-4da1-42bd-af0a-88c5cb6b6e1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1001969383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1001969383
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1678931674
Short name T182
Test name
Test status
Simulation time 1045108145 ps
CPU time 14.72 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201880 kb
Host smart-ea71289d-fa1e-45f0-9b3f-8c05bf819e7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1678931674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1678931674
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.806991165
Short name T437
Test name
Test status
Simulation time 11068612269 ps
CPU time 19.69 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:56:49 PM PDT 24
Peak memory 202044 kb
Host smart-bda16d7a-7427-4137-8b90-81c5515573eb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=806991165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow
_rsp.806991165
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.967893380
Short name T810
Test name
Test status
Simulation time 594727280 ps
CPU time 9.36 seconds
Started Jul 07 05:56:34 PM PDT 24
Finished Jul 07 05:56:43 PM PDT 24
Peak memory 201984 kb
Host smart-e1c23268-1340-4a19-be9d-39521ce92ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=967893380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.967893380
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.938438489
Short name T628
Test name
Test status
Simulation time 4378859232 ps
CPU time 12.78 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:53 PM PDT 24
Peak memory 201948 kb
Host smart-746e9c2d-64ac-45fb-a7b5-273bbbe64b1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=938438489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.938438489
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.22178388
Short name T157
Test name
Test status
Simulation time 962581704 ps
CPU time 14.01 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:40 PM PDT 24
Peak memory 201920 kb
Host smart-b7e12dd0-146e-4a3a-9cb8-29976a6746c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22178388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.22178388
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4132278217
Short name T227
Test name
Test status
Simulation time 98492661869 ps
CPU time 93.89 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:58:07 PM PDT 24
Peak memory 201948 kb
Host smart-cb69c24c-b579-49d8-bf49-7faed3fc4c88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132278217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4132278217
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1234464557
Short name T126
Test name
Test status
Simulation time 32762350364 ps
CPU time 71.33 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:57:41 PM PDT 24
Peak memory 202072 kb
Host smart-273d429d-05d3-44ae-8f11-e9c7327c5336
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1234464557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1234464557
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3973441844
Short name T705
Test name
Test status
Simulation time 14988989 ps
CPU time 1.36 seconds
Started Jul 07 05:56:32 PM PDT 24
Finished Jul 07 05:56:33 PM PDT 24
Peak memory 201904 kb
Host smart-2e7c84e6-24aa-4b7b-b235-0ff197cf751d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973441844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3973441844
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.551068885
Short name T798
Test name
Test status
Simulation time 164700650 ps
CPU time 3.02 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:56:36 PM PDT 24
Peak memory 201736 kb
Host smart-aedc56d9-b2b5-4104-8500-3b8f7175e663
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551068885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.551068885
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.2993886907
Short name T900
Test name
Test status
Simulation time 37813441 ps
CPU time 1.33 seconds
Started Jul 07 05:56:26 PM PDT 24
Finished Jul 07 05:56:27 PM PDT 24
Peak memory 201900 kb
Host smart-4f1b055e-d8fd-4643-a763-ab07c70a3758
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2993886907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2993886907
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1992810453
Short name T824
Test name
Test status
Simulation time 3082201511 ps
CPU time 12.17 seconds
Started Jul 07 05:56:25 PM PDT 24
Finished Jul 07 05:56:38 PM PDT 24
Peak memory 201928 kb
Host smart-e40a22f3-6895-49e4-9ed1-cf66f5e48b44
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992810453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1992810453
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3831898916
Short name T631
Test name
Test status
Simulation time 1549593799 ps
CPU time 7.77 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:56:37 PM PDT 24
Peak memory 201952 kb
Host smart-c52b93d2-f95a-43f8-ae08-60376ac4327f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3831898916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3831898916
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1421791181
Short name T630
Test name
Test status
Simulation time 12598499 ps
CPU time 1.34 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:56:31 PM PDT 24
Peak memory 201908 kb
Host smart-a863a691-aef9-455b-836b-e03bc8c262ee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421791181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1421791181
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3754824843
Short name T279
Test name
Test status
Simulation time 543798298 ps
CPU time 15.75 seconds
Started Jul 07 05:56:31 PM PDT 24
Finished Jul 07 05:56:47 PM PDT 24
Peak memory 203004 kb
Host smart-923d4670-b193-4538-8d8a-5a7a1eb7ecfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3754824843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3754824843
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.750048828
Short name T644
Test name
Test status
Simulation time 1023863063 ps
CPU time 11.63 seconds
Started Jul 07 05:56:34 PM PDT 24
Finished Jul 07 05:56:46 PM PDT 24
Peak memory 201908 kb
Host smart-26555293-0cf3-4daa-8c72-dcfb24dd0b06
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=750048828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.750048828
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2836703356
Short name T855
Test name
Test status
Simulation time 256130646 ps
CPU time 6.19 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:46 PM PDT 24
Peak memory 201820 kb
Host smart-33f631b7-fd23-474b-a9de-a5da12dbbec7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836703356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2836703356
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3423012078
Short name T51
Test name
Test status
Simulation time 67523456 ps
CPU time 10.88 seconds
Started Jul 07 05:57:35 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201928 kb
Host smart-fe45cdd6-e919-4ddc-87b4-f14ae6b6b605
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3423012078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3423012078
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3238901719
Short name T108
Test name
Test status
Simulation time 192681271848 ps
CPU time 386.41 seconds
Started Jul 07 05:57:37 PM PDT 24
Finished Jul 07 06:04:04 PM PDT 24
Peak memory 203016 kb
Host smart-0d113445-8235-4bb3-ae2b-aa92dd35f6d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3238901719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3238901719
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3313989796
Short name T559
Test name
Test status
Simulation time 1293155448 ps
CPU time 7.5 seconds
Started Jul 07 05:57:39 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 201964 kb
Host smart-c5f93965-a0c1-4206-b461-195f3e9d2fa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313989796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3313989796
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.4253092348
Short name T498
Test name
Test status
Simulation time 996195199 ps
CPU time 6.57 seconds
Started Jul 07 05:57:34 PM PDT 24
Finished Jul 07 05:57:41 PM PDT 24
Peak memory 201928 kb
Host smart-16eb5fb8-9aaf-4f18-8a6b-07ec697ffb27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4253092348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4253092348
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.3379937737
Short name T515
Test name
Test status
Simulation time 42532018 ps
CPU time 2.57 seconds
Started Jul 07 05:57:33 PM PDT 24
Finished Jul 07 05:57:36 PM PDT 24
Peak memory 201872 kb
Host smart-b4b96c53-ceee-4692-840f-5b5537e5882b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379937737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3379937737
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.287475631
Short name T120
Test name
Test status
Simulation time 242539014136 ps
CPU time 182.02 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 06:00:34 PM PDT 24
Peak memory 201920 kb
Host smart-640e54ae-3e91-4090-a458-63db66b3a21d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=287475631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.287475631
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2783464963
Short name T307
Test name
Test status
Simulation time 16306848380 ps
CPU time 70.77 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:58:42 PM PDT 24
Peak memory 202104 kb
Host smart-3bdd0530-3c0c-4b94-8ea0-fd1b77dcce62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2783464963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2783464963
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2132910305
Short name T365
Test name
Test status
Simulation time 109245328 ps
CPU time 2.82 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:34 PM PDT 24
Peak memory 201884 kb
Host smart-e96f9fa0-be3b-4af4-82d7-2d12534b107b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132910305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2132910305
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.3856029714
Short name T489
Test name
Test status
Simulation time 1140995955 ps
CPU time 13.95 seconds
Started Jul 07 05:57:39 PM PDT 24
Finished Jul 07 05:57:53 PM PDT 24
Peak memory 201740 kb
Host smart-2edcca7c-569e-461a-8601-40ad226318e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3856029714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3856029714
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.171097781
Short name T864
Test name
Test status
Simulation time 23739312 ps
CPU time 1.18 seconds
Started Jul 07 05:57:32 PM PDT 24
Finished Jul 07 05:57:34 PM PDT 24
Peak memory 201792 kb
Host smart-5f7f64d8-ce74-4db8-abd2-9ebed86a9b28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=171097781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.171097781
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1767932766
Short name T771
Test name
Test status
Simulation time 3607413642 ps
CPU time 7.99 seconds
Started Jul 07 05:57:30 PM PDT 24
Finished Jul 07 05:57:38 PM PDT 24
Peak memory 201984 kb
Host smart-b19eb76c-f8bc-4c0f-99bf-cb93f2ab4018
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767932766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1767932766
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1375546898
Short name T91
Test name
Test status
Simulation time 3236301229 ps
CPU time 12.51 seconds
Started Jul 07 05:57:31 PM PDT 24
Finished Jul 07 05:57:44 PM PDT 24
Peak memory 202016 kb
Host smart-c9704817-f3b7-44eb-93a7-78cec999aae8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1375546898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1375546898
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3741529336
Short name T302
Test name
Test status
Simulation time 25128762 ps
CPU time 1.12 seconds
Started Jul 07 05:57:32 PM PDT 24
Finished Jul 07 05:57:34 PM PDT 24
Peak memory 201784 kb
Host smart-6142483d-d124-4f39-8641-6b7210d80bf4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741529336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3741529336
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3277207553
Short name T127
Test name
Test status
Simulation time 35123948221 ps
CPU time 70.66 seconds
Started Jul 07 05:57:39 PM PDT 24
Finished Jul 07 05:58:50 PM PDT 24
Peak memory 204220 kb
Host smart-032d8736-41d9-4096-afe3-de5aa4da5013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3277207553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3277207553
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2427034392
Short name T402
Test name
Test status
Simulation time 21553189223 ps
CPU time 84.71 seconds
Started Jul 07 05:57:35 PM PDT 24
Finished Jul 07 05:59:00 PM PDT 24
Peak memory 202384 kb
Host smart-299e0564-c593-43aa-9983-b5b0444cd97f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2427034392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2427034392
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.191841126
Short name T566
Test name
Test status
Simulation time 644915786 ps
CPU time 74.63 seconds
Started Jul 07 05:57:38 PM PDT 24
Finished Jul 07 05:58:53 PM PDT 24
Peak memory 204764 kb
Host smart-05d8927c-bd46-4bbf-b3bf-dab79d3564df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=191841126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.191841126
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1688549346
Short name T270
Test name
Test status
Simulation time 342377533 ps
CPU time 13.29 seconds
Started Jul 07 05:57:36 PM PDT 24
Finished Jul 07 05:57:50 PM PDT 24
Peak memory 201860 kb
Host smart-6d1c962a-ac57-4073-af6c-9b5616876696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1688549346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1688549346
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1142721957
Short name T577
Test name
Test status
Simulation time 45811371 ps
CPU time 5.09 seconds
Started Jul 07 05:57:35 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 201924 kb
Host smart-eae4e085-1059-43a8-8f26-6c37dd9ac497
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1142721957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1142721957
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3969348869
Short name T676
Test name
Test status
Simulation time 217951028 ps
CPU time 2.66 seconds
Started Jul 07 05:57:43 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201844 kb
Host smart-b96f1455-809a-4a03-8140-0b36ecf81d61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3969348869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3969348869
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1322554848
Short name T61
Test name
Test status
Simulation time 140864200003 ps
CPU time 208.97 seconds
Started Jul 07 05:57:43 PM PDT 24
Finished Jul 07 06:01:12 PM PDT 24
Peak memory 203024 kb
Host smart-53c2867a-8b01-494e-8b90-1c409479f0c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1322554848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.1322554848
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.4215384511
Short name T288
Test name
Test status
Simulation time 57159320 ps
CPU time 5.04 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 201976 kb
Host smart-c19ba855-21f9-4722-9ce8-7bb0747003f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4215384511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4215384511
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.1365389051
Short name T249
Test name
Test status
Simulation time 117674871 ps
CPU time 5.74 seconds
Started Jul 07 05:57:38 PM PDT 24
Finished Jul 07 05:57:44 PM PDT 24
Peak memory 201928 kb
Host smart-b0433aa2-7090-4153-8bb0-41409d20010a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1365389051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1365389051
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.2870119869
Short name T540
Test name
Test status
Simulation time 5839684866 ps
CPU time 13.44 seconds
Started Jul 07 05:57:43 PM PDT 24
Finished Jul 07 05:57:56 PM PDT 24
Peak memory 202048 kb
Host smart-e19e8bba-9540-4194-80a7-f681016bfd10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2870119869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2870119869
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.755203500
Short name T653
Test name
Test status
Simulation time 45744155833 ps
CPU time 131.06 seconds
Started Jul 07 05:57:40 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 202312 kb
Host smart-9a707849-b668-4648-b64e-279c0cda4a44
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=755203500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.755203500
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.571037784
Short name T468
Test name
Test status
Simulation time 15366782793 ps
CPU time 93.87 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 202072 kb
Host smart-a3e4844b-cf02-4d8d-a7ee-85e8767f8d62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=571037784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.571037784
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.792908579
Short name T695
Test name
Test status
Simulation time 129719781 ps
CPU time 5.25 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 201908 kb
Host smart-8f5b247b-a5ad-4676-9381-17aabc5bd7d8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792908579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.792908579
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.1665269493
Short name T363
Test name
Test status
Simulation time 538074877 ps
CPU time 3.56 seconds
Started Jul 07 05:57:43 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 201836 kb
Host smart-d4c335ab-6230-40b8-9aa5-96bc0535e0bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1665269493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1665269493
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1846683931
Short name T29
Test name
Test status
Simulation time 67690463 ps
CPU time 1.33 seconds
Started Jul 07 05:57:34 PM PDT 24
Finished Jul 07 05:57:36 PM PDT 24
Peak memory 201876 kb
Host smart-77477a19-5e5e-49e3-afa7-c158df494aea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846683931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1846683931
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1540874511
Short name T627
Test name
Test status
Simulation time 15083973629 ps
CPU time 10.3 seconds
Started Jul 07 05:57:34 PM PDT 24
Finished Jul 07 05:57:45 PM PDT 24
Peak memory 202040 kb
Host smart-4ebaedbc-10f8-45f4-9ea1-3bbae4c41212
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540874511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1540874511
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.147566092
Short name T565
Test name
Test status
Simulation time 1989021258 ps
CPU time 4.88 seconds
Started Jul 07 05:57:37 PM PDT 24
Finished Jul 07 05:57:42 PM PDT 24
Peak memory 201916 kb
Host smart-d3f90978-1efc-499d-9e45-19858ecfee37
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=147566092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.147566092
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1551481567
Short name T409
Test name
Test status
Simulation time 10188639 ps
CPU time 1.2 seconds
Started Jul 07 05:57:40 PM PDT 24
Finished Jul 07 05:57:41 PM PDT 24
Peak memory 201880 kb
Host smart-3656b43e-a76d-40b0-be4e-c98ddf6aefbc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551481567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1551481567
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3363483893
Short name T304
Test name
Test status
Simulation time 3746673717 ps
CPU time 62.9 seconds
Started Jul 07 05:57:38 PM PDT 24
Finished Jul 07 05:58:42 PM PDT 24
Peak memory 203344 kb
Host smart-1afefae1-037f-4895-a286-0a9d47b8eaff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3363483893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3363483893
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4294394603
Short name T367
Test name
Test status
Simulation time 736869675 ps
CPU time 33.85 seconds
Started Jul 07 05:57:38 PM PDT 24
Finished Jul 07 05:58:12 PM PDT 24
Peak memory 201980 kb
Host smart-4320e1e5-94d5-4e4e-8726-dabf062707ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4294394603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4294394603
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4124483868
Short name T714
Test name
Test status
Simulation time 183678409 ps
CPU time 30.42 seconds
Started Jul 07 05:57:39 PM PDT 24
Finished Jul 07 05:58:10 PM PDT 24
Peak memory 204040 kb
Host smart-0b1c98e0-4b77-4b8f-ad28-69bff4f8af42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4124483868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.4124483868
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2657287298
Short name T181
Test name
Test status
Simulation time 927455624 ps
CPU time 121.46 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 205828 kb
Host smart-382f4a0c-40bb-4ca9-a7e2-1069870fb92d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657287298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.2657287298
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3117395524
Short name T316
Test name
Test status
Simulation time 538036982 ps
CPU time 6.59 seconds
Started Jul 07 05:57:37 PM PDT 24
Finished Jul 07 05:57:44 PM PDT 24
Peak memory 201828 kb
Host smart-857245cd-5ddc-4ad9-877a-d79156820916
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3117395524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3117395524
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.992788761
Short name T38
Test name
Test status
Simulation time 227931282 ps
CPU time 3.11 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:57:45 PM PDT 24
Peak memory 201920 kb
Host smart-1329d2f5-e5e9-42bd-a28f-a684c4b3fa02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=992788761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.992788761
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2619568089
Short name T184
Test name
Test status
Simulation time 66393052236 ps
CPU time 341.81 seconds
Started Jul 07 05:57:41 PM PDT 24
Finished Jul 07 06:03:23 PM PDT 24
Peak memory 204120 kb
Host smart-a77e9606-e1d6-49dc-a8a6-cca4b3dd5e20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2619568089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.2619568089
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2593647198
Short name T641
Test name
Test status
Simulation time 38075771 ps
CPU time 3.87 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201972 kb
Host smart-84b9774b-c934-4ba6-af88-5de526a22540
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2593647198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2593647198
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.3444559309
Short name T586
Test name
Test status
Simulation time 68277965 ps
CPU time 5.84 seconds
Started Jul 07 05:57:40 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201900 kb
Host smart-b4e19c01-67b6-4ea5-9630-a52cd6177699
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3444559309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3444559309
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.3741225316
Short name T493
Test name
Test status
Simulation time 28475182 ps
CPU time 3.5 seconds
Started Jul 07 05:57:47 PM PDT 24
Finished Jul 07 05:57:51 PM PDT 24
Peak memory 201884 kb
Host smart-ca410595-e4fe-4c16-81f7-ee0f6b07ddf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3741225316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3741225316
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3862232177
Short name T659
Test name
Test status
Simulation time 43144931580 ps
CPU time 102.1 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 202044 kb
Host smart-8f1c8ab2-3505-4d81-9277-d9bfeb671f59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862232177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3862232177
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3716259157
Short name T278
Test name
Test status
Simulation time 24874828566 ps
CPU time 140.22 seconds
Started Jul 07 05:57:40 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 202080 kb
Host smart-133be5b8-4828-4426-9b44-91869d1242c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3716259157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3716259157
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.4116499711
Short name T738
Test name
Test status
Simulation time 94826732 ps
CPU time 5.16 seconds
Started Jul 07 05:57:40 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201904 kb
Host smart-00a9c881-5791-488d-bba2-2d701f1bbb5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116499711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.4116499711
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.294856807
Short name T883
Test name
Test status
Simulation time 72781210 ps
CPU time 1.44 seconds
Started Jul 07 05:57:45 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 201872 kb
Host smart-18a49add-65b1-4531-b390-acbcee086c83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=294856807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.294856807
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.3850231541
Short name T303
Test name
Test status
Simulation time 19559476 ps
CPU time 1.12 seconds
Started Jul 07 05:57:38 PM PDT 24
Finished Jul 07 05:57:39 PM PDT 24
Peak memory 201916 kb
Host smart-a7ed59c0-7f20-4014-92c3-844d82726d24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3850231541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3850231541
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1348892562
Short name T315
Test name
Test status
Simulation time 1926382026 ps
CPU time 9.21 seconds
Started Jul 07 05:57:42 PM PDT 24
Finished Jul 07 05:57:51 PM PDT 24
Peak memory 202180 kb
Host smart-dbe4a77f-6978-4728-a29d-9efad3e5fe53
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348892562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1348892562
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3164043457
Short name T490
Test name
Test status
Simulation time 855644732 ps
CPU time 5.02 seconds
Started Jul 07 05:57:41 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 201960 kb
Host smart-c603f5d2-08ae-40e3-b4c3-9aab416bdebe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3164043457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3164043457
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1967125749
Short name T42
Test name
Test status
Simulation time 10825776 ps
CPU time 1.14 seconds
Started Jul 07 05:57:40 PM PDT 24
Finished Jul 07 05:57:42 PM PDT 24
Peak memory 201876 kb
Host smart-e0c7d41d-e1d2-4b81-a387-129b70af03bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967125749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1967125749
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1488352464
Short name T469
Test name
Test status
Simulation time 8384401378 ps
CPU time 58.28 seconds
Started Jul 07 05:57:44 PM PDT 24
Finished Jul 07 05:58:43 PM PDT 24
Peak memory 203040 kb
Host smart-57671c44-7358-4e9d-8f9c-a7311913ec7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1488352464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1488352464
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3248499380
Short name T526
Test name
Test status
Simulation time 9194297516 ps
CPU time 66.76 seconds
Started Jul 07 05:57:44 PM PDT 24
Finished Jul 07 05:58:51 PM PDT 24
Peak memory 202072 kb
Host smart-94baca9d-d429-417f-8972-6ef9677f0481
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3248499380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3248499380
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.164780533
Short name T159
Test name
Test status
Simulation time 7554942400 ps
CPU time 103.67 seconds
Started Jul 07 05:57:48 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 204876 kb
Host smart-6ce2fee4-41fb-4931-8ce3-7fcfe22bcb47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=164780533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand
_reset.164780533
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1984729045
Short name T602
Test name
Test status
Simulation time 31445581 ps
CPU time 12.43 seconds
Started Jul 07 05:57:46 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 201968 kb
Host smart-9c887fc2-986b-4ef1-a552-a6f372794ad5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1984729045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.1984729045
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.5511894
Short name T349
Test name
Test status
Simulation time 25857680 ps
CPU time 2.52 seconds
Started Jul 07 05:57:41 PM PDT 24
Finished Jul 07 05:57:43 PM PDT 24
Peak memory 202200 kb
Host smart-3ef507db-48cd-4072-909f-95e95662bce2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5511894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.5511894
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3241980857
Short name T853
Test name
Test status
Simulation time 28972327 ps
CPU time 5.67 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:57:59 PM PDT 24
Peak memory 201740 kb
Host smart-5818e320-f94b-483d-8075-4e115d1fe553
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3241980857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3241980857
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1849428990
Short name T886
Test name
Test status
Simulation time 30301693472 ps
CPU time 149.98 seconds
Started Jul 07 05:57:52 PM PDT 24
Finished Jul 07 06:00:22 PM PDT 24
Peak memory 203208 kb
Host smart-3d77cc47-3daf-4263-a651-3dcfc8970933
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1849428990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.1849428990
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3134697324
Short name T896
Test name
Test status
Simulation time 87831222 ps
CPU time 6.04 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:57:57 PM PDT 24
Peak memory 201976 kb
Host smart-f0b93179-b483-43b6-a96f-0c5dd3ff9e0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3134697324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3134697324
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.1675378933
Short name T141
Test name
Test status
Simulation time 34918396 ps
CPU time 2.29 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:57:54 PM PDT 24
Peak memory 201920 kb
Host smart-063b658d-fc49-4bf9-8513-56ebb49a12f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1675378933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1675378933
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1305536879
Short name T494
Test name
Test status
Simulation time 127112113 ps
CPU time 7.17 seconds
Started Jul 07 05:57:49 PM PDT 24
Finished Jul 07 05:57:56 PM PDT 24
Peak memory 201840 kb
Host smart-374e8a0e-203e-45e2-a3d4-089db89432f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1305536879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1305536879
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.4192506673
Short name T760
Test name
Test status
Simulation time 14027054401 ps
CPU time 51.15 seconds
Started Jul 07 05:57:44 PM PDT 24
Finished Jul 07 05:58:35 PM PDT 24
Peak memory 202032 kb
Host smart-d86842cd-0f01-44b6-8ef1-152b1819be9a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192506673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4192506673
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2091293349
Short name T788
Test name
Test status
Simulation time 11121204670 ps
CPU time 84.12 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 202040 kb
Host smart-61b8810f-b80b-411e-9346-ec6fae208fb2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2091293349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2091293349
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.932611857
Short name T299
Test name
Test status
Simulation time 69913075 ps
CPU time 2.01 seconds
Started Jul 07 05:57:44 PM PDT 24
Finished Jul 07 05:57:46 PM PDT 24
Peak memory 201912 kb
Host smart-c06f797a-e3ff-46fe-857b-d87ca44be0eb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932611857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.932611857
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.1238482108
Short name T761
Test name
Test status
Simulation time 44560728 ps
CPU time 5.16 seconds
Started Jul 07 05:57:50 PM PDT 24
Finished Jul 07 05:57:55 PM PDT 24
Peak memory 201920 kb
Host smart-a976d5f0-bdf6-4b74-8713-ef1c11090e64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1238482108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1238482108
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.3112783540
Short name T777
Test name
Test status
Simulation time 101921768 ps
CPU time 1.45 seconds
Started Jul 07 05:57:47 PM PDT 24
Finished Jul 07 05:57:49 PM PDT 24
Peak memory 201820 kb
Host smart-1d3a4284-c096-4a66-8765-b3a7f31c22b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3112783540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3112783540
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3730862458
Short name T180
Test name
Test status
Simulation time 5809692550 ps
CPU time 10.26 seconds
Started Jul 07 05:57:50 PM PDT 24
Finished Jul 07 05:58:00 PM PDT 24
Peak memory 202036 kb
Host smart-2016160f-4c7e-4923-9160-187e921ce253
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730862458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3730862458
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1906558215
Short name T250
Test name
Test status
Simulation time 947471288 ps
CPU time 5.22 seconds
Started Jul 07 05:57:44 PM PDT 24
Finished Jul 07 05:57:50 PM PDT 24
Peak memory 201932 kb
Host smart-1813aed6-56f3-4592-b7ab-ec74e7957bab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1906558215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1906558215
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.459183108
Short name T277
Test name
Test status
Simulation time 17432153 ps
CPU time 1.07 seconds
Started Jul 07 05:57:44 PM PDT 24
Finished Jul 07 05:57:45 PM PDT 24
Peak memory 201884 kb
Host smart-d356d11f-762b-4374-b739-bd248ed5456f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459183108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.459183108
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3570109246
Short name T46
Test name
Test status
Simulation time 281901930 ps
CPU time 24.36 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201980 kb
Host smart-02ecd6a5-7305-4046-b002-b6f501769355
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3570109246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3570109246
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2714324391
Short name T416
Test name
Test status
Simulation time 6019246066 ps
CPU time 38.66 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:58:32 PM PDT 24
Peak memory 202112 kb
Host smart-650d1f0e-5a76-40c6-99a1-bead3f797ccd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2714324391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2714324391
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4273505354
Short name T7
Test name
Test status
Simulation time 15965010453 ps
CPU time 129.09 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 205620 kb
Host smart-bded285b-b0ee-4c5d-81ed-9d18ce884c02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4273505354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.4273505354
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.441309851
Short name T513
Test name
Test status
Simulation time 4327988520 ps
CPU time 42.76 seconds
Started Jul 07 05:57:52 PM PDT 24
Finished Jul 07 05:58:35 PM PDT 24
Peak memory 203104 kb
Host smart-aaf79152-fc7a-48ff-a86e-5782f2339b04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=441309851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res
et_error.441309851
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1279488076
Short name T373
Test name
Test status
Simulation time 46268628 ps
CPU time 4.28 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 201912 kb
Host smart-c08fae9c-3db4-44c1-9b44-ed7b4680c98a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1279488076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1279488076
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2805663773
Short name T506
Test name
Test status
Simulation time 215641343 ps
CPU time 4.37 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 05:57:59 PM PDT 24
Peak memory 201832 kb
Host smart-653ca435-7517-4c9a-8ad9-fec89dfc1f8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2805663773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2805663773
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.50789963
Short name T732
Test name
Test status
Simulation time 91847764 ps
CPU time 3.04 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:57:55 PM PDT 24
Peak memory 202248 kb
Host smart-fd898f38-e39e-4b66-9218-5d4d51080d7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50789963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.50789963
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.3462516070
Short name T840
Test name
Test status
Simulation time 869889947 ps
CPU time 12.53 seconds
Started Jul 07 05:57:56 PM PDT 24
Finished Jul 07 05:58:08 PM PDT 24
Peak memory 201924 kb
Host smart-7c7c27cb-c33e-449c-9ecf-7e1cff95b27c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3462516070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3462516070
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.774469627
Short name T642
Test name
Test status
Simulation time 1754676321 ps
CPU time 14.77 seconds
Started Jul 07 05:57:56 PM PDT 24
Finished Jul 07 05:58:11 PM PDT 24
Peak memory 201836 kb
Host smart-db3323ac-5a29-4dbe-8f7d-b437d4fba1ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=774469627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.774469627
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3591573013
Short name T563
Test name
Test status
Simulation time 19990957763 ps
CPU time 85.65 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:59:19 PM PDT 24
Peak memory 202036 kb
Host smart-83be7fa3-476f-4c54-888a-4c9f6fbdf6c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591573013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3591573013
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1541557297
Short name T37
Test name
Test status
Simulation time 19394064100 ps
CPU time 118.75 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 05:59:53 PM PDT 24
Peak memory 202072 kb
Host smart-1c198861-d754-450d-8600-ce8619a553c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1541557297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1541557297
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3674785527
Short name T461
Test name
Test status
Simulation time 55267607 ps
CPU time 5.09 seconds
Started Jul 07 05:57:52 PM PDT 24
Finished Jul 07 05:57:57 PM PDT 24
Peak memory 201900 kb
Host smart-98546334-f7c1-400b-8d1b-aee2daff40bf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674785527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3674785527
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3161387190
Short name T383
Test name
Test status
Simulation time 83504060 ps
CPU time 4.12 seconds
Started Jul 07 05:57:55 PM PDT 24
Finished Jul 07 05:57:59 PM PDT 24
Peak memory 201908 kb
Host smart-9aeb91bc-c5ae-4e0b-94ff-c0b289850baa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3161387190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3161387190
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.3036842137
Short name T229
Test name
Test status
Simulation time 101215735 ps
CPU time 1.22 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:57:53 PM PDT 24
Peak memory 201876 kb
Host smart-95f33c45-340e-4a17-98bd-25b94b12b9b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3036842137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3036842137
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1624512088
Short name T614
Test name
Test status
Simulation time 6252083692 ps
CPU time 11.18 seconds
Started Jul 07 05:57:48 PM PDT 24
Finished Jul 07 05:58:00 PM PDT 24
Peak memory 202036 kb
Host smart-3ae60821-b5d8-4529-b765-17ccf59d06f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624512088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1624512088
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3809556647
Short name T346
Test name
Test status
Simulation time 2759944153 ps
CPU time 10.85 seconds
Started Jul 07 05:57:48 PM PDT 24
Finished Jul 07 05:57:59 PM PDT 24
Peak memory 202300 kb
Host smart-04f46111-3133-4d41-adf0-5511fcfe9084
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3809556647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3809556647
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.648955675
Short name T457
Test name
Test status
Simulation time 8381802 ps
CPU time 1.12 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 05:57:55 PM PDT 24
Peak memory 201908 kb
Host smart-d98ae1a3-535b-4962-9805-15f380d2b7fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648955675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.648955675
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.722569338
Short name T165
Test name
Test status
Simulation time 1182718729 ps
CPU time 33.73 seconds
Started Jul 07 05:57:52 PM PDT 24
Finished Jul 07 05:58:26 PM PDT 24
Peak memory 202024 kb
Host smart-ec51e9c0-305c-42b3-be9b-b3f7b0e4b3ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=722569338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.722569338
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.427989927
Short name T576
Test name
Test status
Simulation time 2275677782 ps
CPU time 16.44 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:58:09 PM PDT 24
Peak memory 201948 kb
Host smart-10a51f4d-0967-4658-ba31-a42d3b17e185
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=427989927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.427989927
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3305464141
Short name T545
Test name
Test status
Simulation time 579801387 ps
CPU time 32.71 seconds
Started Jul 07 05:57:51 PM PDT 24
Finished Jul 07 05:58:24 PM PDT 24
Peak memory 204100 kb
Host smart-4e0550f8-6eba-4652-9271-b0533c2a6d4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3305464141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.3305464141
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3605306148
Short name T93
Test name
Test status
Simulation time 902285691 ps
CPU time 34.92 seconds
Started Jul 07 05:57:52 PM PDT 24
Finished Jul 07 05:58:27 PM PDT 24
Peak memory 203488 kb
Host smart-95bc4126-b940-4769-8e3d-bbe6127fd06e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3605306148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.3605306148
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2089910651
Short name T149
Test name
Test status
Simulation time 390337746 ps
CPU time 4.84 seconds
Started Jul 07 05:57:55 PM PDT 24
Finished Jul 07 05:58:00 PM PDT 24
Peak memory 201908 kb
Host smart-dd35d8da-d6fa-476b-8861-cf1a560dd83b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2089910651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2089910651
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2774791543
Short name T151
Test name
Test status
Simulation time 2663545739 ps
CPU time 22.63 seconds
Started Jul 07 05:57:57 PM PDT 24
Finished Jul 07 05:58:20 PM PDT 24
Peak memory 201996 kb
Host smart-e0098405-0049-49c5-873c-03d027f17c14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2774791543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2774791543
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2144357564
Short name T185
Test name
Test status
Simulation time 129827204550 ps
CPU time 240.05 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 06:01:54 PM PDT 24
Peak memory 203076 kb
Host smart-092da7b8-1085-4901-8b05-f56f76178e82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2144357564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.2144357564
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2766241167
Short name T865
Test name
Test status
Simulation time 53167339 ps
CPU time 4.41 seconds
Started Jul 07 05:57:57 PM PDT 24
Finished Jul 07 05:58:02 PM PDT 24
Peak memory 201940 kb
Host smart-86977e60-a5ab-4b53-ad1d-dc19598d40ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2766241167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2766241167
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.3727196159
Short name T21
Test name
Test status
Simulation time 815371383 ps
CPU time 12.03 seconds
Started Jul 07 05:57:55 PM PDT 24
Finished Jul 07 05:58:07 PM PDT 24
Peak memory 201908 kb
Host smart-916f0fd7-de59-4061-a3e5-a5f97928b105
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3727196159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3727196159
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.1264142988
Short name T744
Test name
Test status
Simulation time 763093685 ps
CPU time 14.96 seconds
Started Jul 07 05:57:58 PM PDT 24
Finished Jul 07 05:58:13 PM PDT 24
Peak memory 201916 kb
Host smart-980dc1d8-dc9c-44d1-90e8-6af0ca20e1fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1264142988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1264142988
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.474545232
Short name T851
Test name
Test status
Simulation time 8959698938 ps
CPU time 28.51 seconds
Started Jul 07 05:57:56 PM PDT 24
Finished Jul 07 05:58:25 PM PDT 24
Peak memory 202048 kb
Host smart-a1405d1c-5e86-4d41-8c1d-138c0fb6072d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=474545232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.474545232
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1078657254
Short name T726
Test name
Test status
Simulation time 28334677030 ps
CPU time 78.45 seconds
Started Jul 07 05:57:55 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 202048 kb
Host smart-4f3ce95e-1a05-42fb-9129-588fa40464f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1078657254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1078657254
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3336121851
Short name T167
Test name
Test status
Simulation time 11368582 ps
CPU time 1.06 seconds
Started Jul 07 05:57:56 PM PDT 24
Finished Jul 07 05:57:57 PM PDT 24
Peak memory 201908 kb
Host smart-669c6b08-0af4-4f2d-80c4-87911430c9d0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336121851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3336121851
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.877074128
Short name T751
Test name
Test status
Simulation time 407767397 ps
CPU time 3.83 seconds
Started Jul 07 05:57:57 PM PDT 24
Finished Jul 07 05:58:01 PM PDT 24
Peak memory 201920 kb
Host smart-93d4bc30-72a6-4139-b695-a9b092bc0b75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=877074128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.877074128
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.3482180135
Short name T68
Test name
Test status
Simulation time 78197842 ps
CPU time 1.45 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:57:55 PM PDT 24
Peak memory 201884 kb
Host smart-19dbcba8-250b-41cb-9822-f8b5afb1ce76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3482180135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3482180135
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2590822837
Short name T58
Test name
Test status
Simulation time 1950138421 ps
CPU time 7.11 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:58:00 PM PDT 24
Peak memory 201892 kb
Host smart-64e01aca-e765-4785-b13f-d1e40b5ab7ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590822837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2590822837
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3233555891
Short name T645
Test name
Test status
Simulation time 4744493578 ps
CPU time 9.96 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 05:58:04 PM PDT 24
Peak memory 202052 kb
Host smart-5f23c19d-5286-4273-ac17-0821620fb113
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3233555891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3233555891
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1266815116
Short name T650
Test name
Test status
Simulation time 9040242 ps
CPU time 1.05 seconds
Started Jul 07 05:57:56 PM PDT 24
Finished Jul 07 05:57:57 PM PDT 24
Peak memory 201868 kb
Host smart-b65f28d5-dd6c-4bf3-a3e8-138f75137de1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266815116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1266815116
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1449500195
Short name T142
Test name
Test status
Simulation time 296413852 ps
CPU time 21.86 seconds
Started Jul 07 05:57:55 PM PDT 24
Finished Jul 07 05:58:17 PM PDT 24
Peak memory 201912 kb
Host smart-0af58064-a6b1-43f7-85ec-617333329157
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449500195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1449500195
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3685528911
Short name T882
Test name
Test status
Simulation time 116708802 ps
CPU time 17.33 seconds
Started Jul 07 05:57:58 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201968 kb
Host smart-1f3b132d-a24d-46d9-9025-9001ab3b8554
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3685528911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3685528911
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1977160115
Short name T219
Test name
Test status
Simulation time 3093242145 ps
CPU time 17.12 seconds
Started Jul 07 05:57:58 PM PDT 24
Finished Jul 07 05:58:15 PM PDT 24
Peak memory 202984 kb
Host smart-2c68b779-1fea-49bd-8760-2c7ef927e414
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1977160115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.1977160115
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1630677545
Short name T135
Test name
Test status
Simulation time 148334799 ps
CPU time 16.23 seconds
Started Jul 07 05:57:58 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 201944 kb
Host smart-1a777cb3-7735-4a39-a970-4b2e86831c8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1630677545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.1630677545
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.521835094
Short name T262
Test name
Test status
Simulation time 1204437229 ps
CPU time 6.05 seconds
Started Jul 07 05:57:54 PM PDT 24
Finished Jul 07 05:58:00 PM PDT 24
Peak memory 201932 kb
Host smart-69221b5f-bc80-4558-8070-b198ee5d053f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=521835094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.521835094
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1433292615
Short name T708
Test name
Test status
Simulation time 1931507400 ps
CPU time 19.05 seconds
Started Jul 07 05:58:04 PM PDT 24
Finished Jul 07 05:58:23 PM PDT 24
Peak memory 201892 kb
Host smart-cb39c795-f601-4686-97e0-46b69d8e7bb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1433292615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1433292615
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.400161724
Short name T200
Test name
Test status
Simulation time 38394667718 ps
CPU time 222.65 seconds
Started Jul 07 05:57:59 PM PDT 24
Finished Jul 07 06:01:42 PM PDT 24
Peak memory 203096 kb
Host smart-24cf0fbd-b9b8-42ad-900d-22aad89f9102
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=400161724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo
w_rsp.400161724
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.169842810
Short name T78
Test name
Test status
Simulation time 59530114 ps
CPU time 3.8 seconds
Started Jul 07 05:57:57 PM PDT 24
Finished Jul 07 05:58:01 PM PDT 24
Peak memory 201968 kb
Host smart-c0de0701-7c19-4fb2-a2c7-d815390c8654
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=169842810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.169842810
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.3447122526
Short name T352
Test name
Test status
Simulation time 16089050 ps
CPU time 1.19 seconds
Started Jul 07 05:58:02 PM PDT 24
Finished Jul 07 05:58:03 PM PDT 24
Peak memory 201900 kb
Host smart-0a6a81ae-d01b-4581-8410-d0b9735f5259
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3447122526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3447122526
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.2328771681
Short name T527
Test name
Test status
Simulation time 158468020 ps
CPU time 3.03 seconds
Started Jul 07 05:57:58 PM PDT 24
Finished Jul 07 05:58:01 PM PDT 24
Peak memory 201896 kb
Host smart-cba6afdf-b636-426c-8035-c3ecd5ca57fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2328771681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2328771681
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1989814225
Short name T422
Test name
Test status
Simulation time 13648657832 ps
CPU time 55.71 seconds
Started Jul 07 05:57:57 PM PDT 24
Finished Jul 07 05:58:53 PM PDT 24
Peak memory 202012 kb
Host smart-f41b15f9-be1b-4d81-ad47-c2ff1b512e6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989814225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1989814225
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2803529619
Short name T419
Test name
Test status
Simulation time 11423275451 ps
CPU time 65.18 seconds
Started Jul 07 05:58:03 PM PDT 24
Finished Jul 07 05:59:08 PM PDT 24
Peak memory 202044 kb
Host smart-4b082aed-63b8-4769-a077-3a3d8e7b979b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2803529619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2803529619
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.59842762
Short name T881
Test name
Test status
Simulation time 109454605 ps
CPU time 7.5 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:15 PM PDT 24
Peak memory 201904 kb
Host smart-3400506b-2cf2-4e50-82b9-0771c34b0c15
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59842762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.59842762
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.652216963
Short name T306
Test name
Test status
Simulation time 53499369 ps
CPU time 4.84 seconds
Started Jul 07 05:58:06 PM PDT 24
Finished Jul 07 05:58:11 PM PDT 24
Peak memory 201920 kb
Host smart-03dd1c73-6dde-40f7-b3bd-0d2d62639a4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=652216963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.652216963
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.4056577550
Short name T711
Test name
Test status
Simulation time 42398158 ps
CPU time 1.36 seconds
Started Jul 07 05:57:53 PM PDT 24
Finished Jul 07 05:57:54 PM PDT 24
Peak memory 201912 kb
Host smart-e3c382d3-bae0-47b8-80f0-93957972c73d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4056577550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4056577550
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2145051466
Short name T673
Test name
Test status
Simulation time 3613987193 ps
CPU time 9.02 seconds
Started Jul 07 05:57:59 PM PDT 24
Finished Jul 07 05:58:08 PM PDT 24
Peak memory 201956 kb
Host smart-c588698e-973f-4510-b118-e37d9a2edd3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145051466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2145051466
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3479489307
Short name T713
Test name
Test status
Simulation time 671602560 ps
CPU time 5.08 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:20 PM PDT 24
Peak memory 201972 kb
Host smart-18111aaf-b6e0-4353-9c17-7eaf6bdc02b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3479489307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3479489307
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3208607043
Short name T621
Test name
Test status
Simulation time 8309791 ps
CPU time 1.17 seconds
Started Jul 07 05:57:57 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 201908 kb
Host smart-16f53010-8eb2-4148-8121-0c5312ee39fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208607043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3208607043
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2583773072
Short name T696
Test name
Test status
Simulation time 6242684779 ps
CPU time 17.83 seconds
Started Jul 07 05:58:01 PM PDT 24
Finished Jul 07 05:58:19 PM PDT 24
Peak memory 203040 kb
Host smart-4449d827-1404-4426-9403-fed638b302fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2583773072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2583773072
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2710720868
Short name T132
Test name
Test status
Simulation time 8912167044 ps
CPU time 112.16 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 203132 kb
Host smart-34a11a73-147b-423e-9d0b-dff02bc31e14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2710720868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2710720868
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3037387845
Short name T71
Test name
Test status
Simulation time 3468547063 ps
CPU time 60.57 seconds
Started Jul 07 05:57:58 PM PDT 24
Finished Jul 07 05:58:59 PM PDT 24
Peak memory 204080 kb
Host smart-d8b2873c-6284-4150-b5ae-76eca1368f7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037387845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.3037387845
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.170087262
Short name T54
Test name
Test status
Simulation time 1053405756 ps
CPU time 110.5 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 204148 kb
Host smart-f0838a4e-18b9-47ad-b529-4101ce80040c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=170087262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res
et_error.170087262
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2492184462
Short name T27
Test name
Test status
Simulation time 709776857 ps
CPU time 8.74 seconds
Started Jul 07 05:57:59 PM PDT 24
Finished Jul 07 05:58:08 PM PDT 24
Peak memory 201796 kb
Host smart-02c40f2a-5b70-4315-844e-1811155ad0c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2492184462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2492184462
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.58581650
Short name T393
Test name
Test status
Simulation time 25506561 ps
CPU time 5.98 seconds
Started Jul 07 05:58:09 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201800 kb
Host smart-44ba4283-035e-47ca-b716-89eb44a72ffb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58581650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.58581650
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3590974948
Short name T750
Test name
Test status
Simulation time 29930658347 ps
CPU time 39.65 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:51 PM PDT 24
Peak memory 202040 kb
Host smart-c6969058-09b1-4180-9997-99ead12d92c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3590974948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.3590974948
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1793074410
Short name T683
Test name
Test status
Simulation time 771000898 ps
CPU time 6.56 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 201896 kb
Host smart-f794203f-ee91-416f-9a28-b791d959d914
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1793074410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1793074410
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.973639354
Short name T153
Test name
Test status
Simulation time 849368063 ps
CPU time 8.38 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201896 kb
Host smart-0d7226f0-98f1-4d39-94de-96ab35dea652
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=973639354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.973639354
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.2601625216
Short name T514
Test name
Test status
Simulation time 980300419 ps
CPU time 10.06 seconds
Started Jul 07 05:58:08 PM PDT 24
Finished Jul 07 05:58:18 PM PDT 24
Peak memory 201912 kb
Host smart-5fd93b87-ab6f-4557-9d2a-8299840565e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2601625216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2601625216
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.337417857
Short name T484
Test name
Test status
Simulation time 44984598909 ps
CPU time 48.6 seconds
Started Jul 07 05:58:05 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 202020 kb
Host smart-d6a3d35e-5cfb-4012-beb5-77d5a4a17df1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=337417857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.337417857
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.339868556
Short name T147
Test name
Test status
Simulation time 137022679750 ps
CPU time 146.1 seconds
Started Jul 07 05:58:08 PM PDT 24
Finished Jul 07 06:00:34 PM PDT 24
Peak memory 202060 kb
Host smart-f233c301-dbbe-4990-96d2-e27929816291
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=339868556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.339868556
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.4109569396
Short name T366
Test name
Test status
Simulation time 15970520 ps
CPU time 2.3 seconds
Started Jul 07 05:58:08 PM PDT 24
Finished Jul 07 05:58:10 PM PDT 24
Peak memory 201908 kb
Host smart-29476ddb-d8d2-4a2d-8df9-614a86840f4a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109569396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.4109569396
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.748288426
Short name T557
Test name
Test status
Simulation time 638023062 ps
CPU time 8.71 seconds
Started Jul 07 05:58:04 PM PDT 24
Finished Jul 07 05:58:13 PM PDT 24
Peak memory 201884 kb
Host smart-0316c017-f8f6-4ac5-896b-0aaeaf1f2fd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748288426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.748288426
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.1922688596
Short name T836
Test name
Test status
Simulation time 48807347 ps
CPU time 1.59 seconds
Started Jul 07 05:58:08 PM PDT 24
Finished Jul 07 05:58:10 PM PDT 24
Peak memory 201908 kb
Host smart-9c8d2433-8065-4cc1-bcd3-1a52a6e393c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1922688596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1922688596
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4139886472
Short name T342
Test name
Test status
Simulation time 5002287772 ps
CPU time 7.03 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:19 PM PDT 24
Peak memory 201984 kb
Host smart-f9f95618-f002-478e-a1cd-f58854ba4394
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139886472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4139886472
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3549274859
Short name T491
Test name
Test status
Simulation time 706042758 ps
CPU time 5.16 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201928 kb
Host smart-85c7c8aa-9be1-4d9f-a8a2-e780a089071e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3549274859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3549274859
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1284567999
Short name T252
Test name
Test status
Simulation time 8588452 ps
CPU time 1.17 seconds
Started Jul 07 05:58:03 PM PDT 24
Finished Jul 07 05:58:04 PM PDT 24
Peak memory 202204 kb
Host smart-13d2bfdd-8178-4c9a-aeee-d6f5a84d494d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284567999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1284567999
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.544722087
Short name T593
Test name
Test status
Simulation time 1235761247 ps
CPU time 11.22 seconds
Started Jul 07 05:58:09 PM PDT 24
Finished Jul 07 05:58:20 PM PDT 24
Peak memory 201896 kb
Host smart-d4ef1735-ddb0-4f7a-baff-00ed27db35a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=544722087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.544722087
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.683883262
Short name T648
Test name
Test status
Simulation time 135081251 ps
CPU time 10.51 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:18 PM PDT 24
Peak memory 201900 kb
Host smart-7b6336c2-65a1-4bae-9f8d-3ffc4baa4609
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=683883262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.683883262
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3348272303
Short name T83
Test name
Test status
Simulation time 1547306104 ps
CPU time 116.16 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 204404 kb
Host smart-4900d7dc-1927-47ea-85dd-95043fc7c4fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3348272303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.3348272303
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1969743195
Short name T214
Test name
Test status
Simulation time 5870635816 ps
CPU time 142.91 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 06:00:35 PM PDT 24
Peak memory 205728 kb
Host smart-5512f10e-4b09-4dc6-824a-551a8adba628
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969743195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.1969743195
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3545931113
Short name T245
Test name
Test status
Simulation time 550039373 ps
CPU time 7.86 seconds
Started Jul 07 05:58:04 PM PDT 24
Finished Jul 07 05:58:12 PM PDT 24
Peak memory 201892 kb
Host smart-f86a42e0-3356-457e-bcc0-f34b7b2bc67e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3545931113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3545931113
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1459623288
Short name T207
Test name
Test status
Simulation time 1318547715 ps
CPU time 22.57 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:34 PM PDT 24
Peak memory 201892 kb
Host smart-87b86c04-81a1-4995-a4df-fe07177ff12c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1459623288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1459623288
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2241499219
Short name T773
Test name
Test status
Simulation time 102549345539 ps
CPU time 261.54 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 06:02:34 PM PDT 24
Peak memory 203096 kb
Host smart-8b1ac275-de59-46e8-826e-239afc893b25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2241499219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2241499219
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1843405679
Short name T759
Test name
Test status
Simulation time 525350385 ps
CPU time 10.57 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201968 kb
Host smart-0e1efe0a-3184-426c-bce2-c11dff6bb54b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1843405679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1843405679
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.442458388
Short name T89
Test name
Test status
Simulation time 1257192827 ps
CPU time 15.47 seconds
Started Jul 07 05:58:10 PM PDT 24
Finished Jul 07 05:58:26 PM PDT 24
Peak memory 201912 kb
Host smart-0f83b8c0-68cf-483b-bc03-45807f8cf316
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=442458388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.442458388
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.4010545676
Short name T765
Test name
Test status
Simulation time 71039359 ps
CPU time 7.06 seconds
Started Jul 07 05:58:10 PM PDT 24
Finished Jul 07 05:58:17 PM PDT 24
Peak memory 201880 kb
Host smart-932ea6c1-83a0-44e2-8df5-16a980984bb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4010545676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4010545676
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1019594888
Short name T20
Test name
Test status
Simulation time 113722292429 ps
CPU time 72.23 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 201964 kb
Host smart-f89bed4f-d914-4f42-b281-317cadbcebd3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019594888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1019594888
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3587838578
Short name T710
Test name
Test status
Simulation time 4296172494 ps
CPU time 8.63 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 202044 kb
Host smart-145a4e47-09c9-46fb-a0c4-3d8e310d4dc3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3587838578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3587838578
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.4289775722
Short name T720
Test name
Test status
Simulation time 104819196 ps
CPU time 2.59 seconds
Started Jul 07 05:58:13 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201904 kb
Host smart-ae78eae2-587c-420c-ab1f-dfa3780ad7ec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289775722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.4289775722
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.2082890041
Short name T347
Test name
Test status
Simulation time 95358685 ps
CPU time 6.26 seconds
Started Jul 07 05:58:10 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201832 kb
Host smart-af614b2a-f3ef-448e-8137-15a2cda336b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2082890041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2082890041
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.3833043374
Short name T433
Test name
Test status
Simulation time 26675506 ps
CPU time 1.07 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:09 PM PDT 24
Peak memory 201904 kb
Host smart-bcccec6c-84e9-4eb1-b9e6-fb5862c2bd2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3833043374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3833043374
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.169535780
Short name T223
Test name
Test status
Simulation time 6559200229 ps
CPU time 7.33 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:15 PM PDT 24
Peak memory 201992 kb
Host smart-7e7552b8-c069-4711-85c3-dc6de3c403a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=169535780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.169535780
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1642622136
Short name T445
Test name
Test status
Simulation time 603049472 ps
CPU time 5.3 seconds
Started Jul 07 05:58:09 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 201956 kb
Host smart-660a1d1b-849d-423e-b947-3c7ea327852b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1642622136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1642622136
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3760451777
Short name T420
Test name
Test status
Simulation time 12452869 ps
CPU time 1.25 seconds
Started Jul 07 05:58:09 PM PDT 24
Finished Jul 07 05:58:11 PM PDT 24
Peak memory 201784 kb
Host smart-ee5ff310-25d8-45cd-8bbe-7a39a31e8402
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760451777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3760451777
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.219976813
Short name T543
Test name
Test status
Simulation time 382544458 ps
CPU time 19.65 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:27 PM PDT 24
Peak memory 202612 kb
Host smart-6bd1ae16-5919-4ad9-b486-608d89af30fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=219976813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.219976813
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2003074245
Short name T518
Test name
Test status
Simulation time 35738984221 ps
CPU time 80.25 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 202940 kb
Host smart-88edb66f-e557-4228-82cb-1d3d57c895c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2003074245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2003074245
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1919474349
Short name T60
Test name
Test status
Simulation time 1506784217 ps
CPU time 41.74 seconds
Started Jul 07 05:58:10 PM PDT 24
Finished Jul 07 05:58:52 PM PDT 24
Peak memory 204012 kb
Host smart-624ea673-20c3-4e52-a60f-f6ec6a8f90ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1919474349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.1919474349
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3471642063
Short name T212
Test name
Test status
Simulation time 262004377 ps
CPU time 32.96 seconds
Started Jul 07 05:58:13 PM PDT 24
Finished Jul 07 05:58:46 PM PDT 24
Peak memory 202992 kb
Host smart-1843ee34-94a7-4f9a-917a-d4ae69cb31b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3471642063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.3471642063
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1541677172
Short name T251
Test name
Test status
Simulation time 370650444 ps
CPU time 8.72 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:23 PM PDT 24
Peak memory 201932 kb
Host smart-52d8d7a5-ccbd-435d-9f6a-f9f1e0ca1cc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541677172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1541677172
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1149926864
Short name T375
Test name
Test status
Simulation time 168644305 ps
CPU time 6.08 seconds
Started Jul 07 05:58:08 PM PDT 24
Finished Jul 07 05:58:15 PM PDT 24
Peak memory 201916 kb
Host smart-a722d055-b545-4853-9ab9-ade59176e342
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1149926864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1149926864
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2273569217
Short name T814
Test name
Test status
Simulation time 34208328089 ps
CPU time 267 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 06:02:42 PM PDT 24
Peak memory 204048 kb
Host smart-e934e8d9-779a-452c-b335-21d90b706c99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2273569217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.2273569217
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.952871847
Short name T330
Test name
Test status
Simulation time 43311083 ps
CPU time 3.47 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:19 PM PDT 24
Peak memory 201924 kb
Host smart-23b5d8bf-19a6-49ea-8059-77c492496246
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952871847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.952871847
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.575446321
Short name T727
Test name
Test status
Simulation time 19166538 ps
CPU time 2.46 seconds
Started Jul 07 05:58:17 PM PDT 24
Finished Jul 07 05:58:20 PM PDT 24
Peak memory 201904 kb
Host smart-3f043622-99af-44da-a1a5-75ccaa8073d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=575446321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.575446321
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2415576727
Short name T172
Test name
Test status
Simulation time 765697700 ps
CPU time 9.16 seconds
Started Jul 07 05:58:12 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201872 kb
Host smart-d47d80de-cfcc-4030-a091-1e9b80fa73b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2415576727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2415576727
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.589105856
Short name T440
Test name
Test status
Simulation time 51449154268 ps
CPU time 117.6 seconds
Started Jul 07 05:58:13 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 202028 kb
Host smart-b40f835f-9266-49fb-b52e-5e61ead6ed81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=589105856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.589105856
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.88058874
Short name T555
Test name
Test status
Simulation time 20008344479 ps
CPU time 51.62 seconds
Started Jul 07 05:58:09 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 202040 kb
Host smart-35053780-8bd6-491e-95f3-1543903d296f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=88058874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.88058874
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1805082588
Short name T337
Test name
Test status
Simulation time 57359317 ps
CPU time 7.51 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:23 PM PDT 24
Peak memory 201816 kb
Host smart-5da13f4f-f4a5-4d79-b192-0bf5e93b41f4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805082588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1805082588
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1913135865
Short name T780
Test name
Test status
Simulation time 28255409 ps
CPU time 2.38 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:18 PM PDT 24
Peak memory 201872 kb
Host smart-7b47ba27-b2e3-4dd3-8a51-a80ce6521ef3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1913135865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1913135865
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.3979842117
Short name T266
Test name
Test status
Simulation time 214568293 ps
CPU time 1.47 seconds
Started Jul 07 05:58:07 PM PDT 24
Finished Jul 07 05:58:09 PM PDT 24
Peak memory 201912 kb
Host smart-051bcd7a-470d-48a5-a7a6-81126b2c43c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3979842117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3979842117
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1979685502
Short name T746
Test name
Test status
Simulation time 7425171654 ps
CPU time 7.82 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 202020 kb
Host smart-c11a0084-f895-43c7-b5d6-e318370327cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979685502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1979685502
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1120799296
Short name T572
Test name
Test status
Simulation time 1663703585 ps
CPU time 12.37 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 201928 kb
Host smart-e951c031-1dfb-4d2b-ac81-d2a803f21c6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1120799296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1120799296
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3521702065
Short name T334
Test name
Test status
Simulation time 13980901 ps
CPU time 1.26 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:12 PM PDT 24
Peak memory 201880 kb
Host smart-f4ba6a49-dcf3-4074-92b8-18556a1e92db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521702065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3521702065
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.986156420
Short name T832
Test name
Test status
Simulation time 469400731 ps
CPU time 6.98 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:23 PM PDT 24
Peak memory 201892 kb
Host smart-299b4797-378c-466e-aa19-c8fe306a9491
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=986156420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.986156420
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3943311312
Short name T843
Test name
Test status
Simulation time 110861935 ps
CPU time 14.16 seconds
Started Jul 07 05:58:17 PM PDT 24
Finished Jul 07 05:58:32 PM PDT 24
Peak memory 201952 kb
Host smart-e6dfd0d0-105c-413e-935e-28cddd45df28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3943311312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3943311312
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2814635661
Short name T687
Test name
Test status
Simulation time 118422350 ps
CPU time 20.5 seconds
Started Jul 07 05:58:08 PM PDT 24
Finished Jul 07 05:58:29 PM PDT 24
Peak memory 202924 kb
Host smart-6af09a9b-6811-401e-bba5-8be48ed29154
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2814635661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.2814635661
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1683203472
Short name T15
Test name
Test status
Simulation time 4383420999 ps
CPU time 30.48 seconds
Started Jul 07 05:58:17 PM PDT 24
Finished Jul 07 05:58:48 PM PDT 24
Peak memory 203456 kb
Host smart-2247447a-d717-4efd-b239-ff80c73d9a73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683203472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1683203472
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.362989974
Short name T719
Test name
Test status
Simulation time 1870541909 ps
CPU time 12.34 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:26 PM PDT 24
Peak memory 201896 kb
Host smart-feeddfea-0aca-47b7-9d80-8ca11f7ec058
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=362989974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.362989974
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.465656732
Short name T368
Test name
Test status
Simulation time 1321971725 ps
CPU time 20.26 seconds
Started Jul 07 05:56:32 PM PDT 24
Finished Jul 07 05:56:53 PM PDT 24
Peak memory 201892 kb
Host smart-571e0c28-7d1c-4999-8852-8599f9fb90e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=465656732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.465656732
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2717045231
Short name T305
Test name
Test status
Simulation time 237477915 ps
CPU time 5.13 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:56:38 PM PDT 24
Peak memory 201968 kb
Host smart-371b03a3-92e4-4651-83cc-c1290ba056c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2717045231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2717045231
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.2371851528
Short name T290
Test name
Test status
Simulation time 1510868887 ps
CPU time 10.34 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:56:46 PM PDT 24
Peak memory 201856 kb
Host smart-2ab9a549-e4b6-4f52-ab3e-0cd88a283675
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2371851528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2371851528
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.1189795866
Short name T48
Test name
Test status
Simulation time 996695217 ps
CPU time 13.61 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:56:47 PM PDT 24
Peak memory 201828 kb
Host smart-1ac8c303-52ec-4870-a2f1-7a080145bc75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1189795866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1189795866
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3546579225
Short name T525
Test name
Test status
Simulation time 81839278120 ps
CPU time 194.21 seconds
Started Jul 07 05:56:28 PM PDT 24
Finished Jul 07 05:59:42 PM PDT 24
Peak memory 202020 kb
Host smart-2689844f-88c0-4969-8372-0d105dd3608c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546579225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3546579225
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1103347162
Short name T662
Test name
Test status
Simulation time 13044752707 ps
CPU time 86.24 seconds
Started Jul 07 05:56:31 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 202048 kb
Host smart-af37191e-d801-4fcf-b351-38f46d95a176
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1103347162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1103347162
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2077399078
Short name T458
Test name
Test status
Simulation time 61625680 ps
CPU time 4.71 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:56:34 PM PDT 24
Peak memory 201880 kb
Host smart-a5db569c-083d-44f5-8803-5fcc2472527e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077399078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2077399078
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.1362324675
Short name T820
Test name
Test status
Simulation time 765593944 ps
CPU time 10.7 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:56:47 PM PDT 24
Peak memory 201920 kb
Host smart-dcee5bc9-2342-4933-b435-3dfeb30845c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1362324675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1362324675
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.3855866532
Short name T174
Test name
Test status
Simulation time 104342731 ps
CPU time 1.52 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:56:31 PM PDT 24
Peak memory 202196 kb
Host smart-5365404a-cc28-44ac-b607-10705f21b9fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3855866532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3855866532
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1150191424
Short name T128
Test name
Test status
Simulation time 2151138321 ps
CPU time 9.16 seconds
Started Jul 07 05:56:29 PM PDT 24
Finished Jul 07 05:56:38 PM PDT 24
Peak memory 201932 kb
Host smart-169e4988-ea64-4b93-85ed-f9a6550cc9f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150191424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1150191424
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3626726505
Short name T858
Test name
Test status
Simulation time 1014054772 ps
CPU time 7.15 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:56:42 PM PDT 24
Peak memory 201952 kb
Host smart-48f45957-a1a2-4049-aee8-630158dad5b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3626726505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3626726505
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2298259250
Short name T358
Test name
Test status
Simulation time 10542561 ps
CPU time 1.23 seconds
Started Jul 07 05:56:34 PM PDT 24
Finished Jul 07 05:56:36 PM PDT 24
Peak memory 201868 kb
Host smart-7c7a4559-cda2-48dc-9d1a-c4c4c11b5a3e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298259250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2298259250
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.195004587
Short name T809
Test name
Test status
Simulation time 113374792 ps
CPU time 13.69 seconds
Started Jul 07 05:56:31 PM PDT 24
Finished Jul 07 05:56:45 PM PDT 24
Peak memory 201936 kb
Host smart-3670c122-588b-41f0-a73e-82ee489a0599
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=195004587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.195004587
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1571540447
Short name T397
Test name
Test status
Simulation time 18205738193 ps
CPU time 84.75 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 203316 kb
Host smart-a20604c7-ed76-42e4-a2aa-355716bc535a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1571540447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1571540447
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.979819492
Short name T171
Test name
Test status
Simulation time 395721003 ps
CPU time 40.12 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:57:20 PM PDT 24
Peak memory 204184 kb
Host smart-160e8e11-a35d-4ff7-a37f-fc58ec1d369a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=979819492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_
reset.979819492
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1786613546
Short name T867
Test name
Test status
Simulation time 234975639 ps
CPU time 15.32 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:56:51 PM PDT 24
Peak memory 201936 kb
Host smart-52e20bc3-ba12-4059-bca2-2fb8a12bee60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1786613546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1786613546
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1653618489
Short name T63
Test name
Test status
Simulation time 1041866863 ps
CPU time 11.88 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:56:48 PM PDT 24
Peak memory 201928 kb
Host smart-3fe89b61-00a6-4293-8f0b-c603faf8d784
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1653618489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1653618489
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3457286252
Short name T139
Test name
Test status
Simulation time 915202306 ps
CPU time 10.23 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:26 PM PDT 24
Peak memory 201868 kb
Host smart-49a757f0-3f7e-4b39-a864-e85d1c8b9e21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457286252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3457286252
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3374807101
Short name T605
Test name
Test status
Simulation time 85995884968 ps
CPU time 159.54 seconds
Started Jul 07 05:58:12 PM PDT 24
Finished Jul 07 06:00:52 PM PDT 24
Peak memory 203092 kb
Host smart-13679668-4bc6-49e9-a334-64d224d1d291
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3374807101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.3374807101
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.4005586797
Short name T521
Test name
Test status
Simulation time 70029672 ps
CPU time 1.9 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:21 PM PDT 24
Peak memory 201952 kb
Host smart-4d325e65-1b6a-4eb4-9148-fd9a39083271
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005586797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.4005586797
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.4108163817
Short name T325
Test name
Test status
Simulation time 488931201 ps
CPU time 7.24 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201812 kb
Host smart-7c557be7-fee3-488a-b15d-d84fdb696e9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4108163817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.4108163817
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.646642585
Short name T30
Test name
Test status
Simulation time 927775338 ps
CPU time 12.93 seconds
Started Jul 07 05:58:16 PM PDT 24
Finished Jul 07 05:58:30 PM PDT 24
Peak memory 201932 kb
Host smart-6eb1b726-7602-46ea-acb3-3c6e26d02efb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=646642585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.646642585
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1031180490
Short name T585
Test name
Test status
Simulation time 36170079988 ps
CPU time 29.44 seconds
Started Jul 07 05:58:13 PM PDT 24
Finished Jul 07 05:58:43 PM PDT 24
Peak memory 202052 kb
Host smart-372425b0-b24e-412b-837a-bc6c75798684
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031180490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1031180490
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.4184370726
Short name T104
Test name
Test status
Simulation time 46729241108 ps
CPU time 187.48 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 06:01:23 PM PDT 24
Peak memory 202044 kb
Host smart-4beb29ac-aff7-43df-86d9-2d1b04f74313
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4184370726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4184370726
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.791610851
Short name T786
Test name
Test status
Simulation time 41959408 ps
CPU time 4.94 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201912 kb
Host smart-df414c7c-b662-4cd3-9151-31e3375d7cb7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791610851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.791610851
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.752296651
Short name T17
Test name
Test status
Simulation time 10865176 ps
CPU time 1.11 seconds
Started Jul 07 05:58:12 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 201896 kb
Host smart-e17cb1bc-2985-4ed8-8202-81a62311eb2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=752296651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.752296651
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.1131659548
Short name T446
Test name
Test status
Simulation time 11487711 ps
CPU time 1.15 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201816 kb
Host smart-8f08f2fe-2999-492a-8f37-226678261453
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1131659548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1131659548
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.588856580
Short name T265
Test name
Test status
Simulation time 2078529580 ps
CPU time 8.21 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201836 kb
Host smart-b804cac9-9fdb-4920-8508-9e998260c923
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=588856580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.588856580
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3676886626
Short name T528
Test name
Test status
Simulation time 2596376243 ps
CPU time 12.78 seconds
Started Jul 07 05:58:16 PM PDT 24
Finished Jul 07 05:58:29 PM PDT 24
Peak memory 201992 kb
Host smart-b3113240-d14b-435e-8c46-b93df83ae9d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3676886626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3676886626
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.426087754
Short name T95
Test name
Test status
Simulation time 9630245 ps
CPU time 1.25 seconds
Started Jul 07 05:58:12 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 201876 kb
Host smart-4337deaf-42fb-40ca-9a0c-aaa4ed205c7d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426087754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.426087754
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1308480325
Short name T318
Test name
Test status
Simulation time 111461039 ps
CPU time 7.91 seconds
Started Jul 07 05:58:16 PM PDT 24
Finished Jul 07 05:58:24 PM PDT 24
Peak memory 201880 kb
Host smart-5ea60722-77b5-451c-81d1-f47aee8fa7f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1308480325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1308480325
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1614738850
Short name T476
Test name
Test status
Simulation time 144348952 ps
CPU time 14.83 seconds
Started Jul 07 05:58:20 PM PDT 24
Finished Jul 07 05:58:35 PM PDT 24
Peak memory 201952 kb
Host smart-900fcd2e-a605-42e5-8318-5527fd855114
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1614738850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1614738850
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1558203810
Short name T503
Test name
Test status
Simulation time 2523408162 ps
CPU time 42.65 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 204580 kb
Host smart-be37ca0b-7767-475d-a86a-3b76090e1631
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1558203810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.1558203810
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3794922178
Short name T699
Test name
Test status
Simulation time 4466961840 ps
CPU time 129.91 seconds
Started Jul 07 05:58:20 PM PDT 24
Finished Jul 07 06:00:31 PM PDT 24
Peak memory 205248 kb
Host smart-5614aea6-9772-4876-9e64-a1d23dab348d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3794922178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.3794922178
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1595161902
Short name T803
Test name
Test status
Simulation time 152671536 ps
CPU time 2.49 seconds
Started Jul 07 05:58:11 PM PDT 24
Finished Jul 07 05:58:14 PM PDT 24
Peak memory 201924 kb
Host smart-15bd9f0b-c574-4cb2-bbfe-7100032f1a1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1595161902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1595161902
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1519090358
Short name T608
Test name
Test status
Simulation time 662969863 ps
CPU time 15.2 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:34 PM PDT 24
Peak memory 201888 kb
Host smart-ae0294ee-7e25-4941-af1a-c2bc3c176210
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1519090358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1519090358
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.4243779530
Short name T600
Test name
Test status
Simulation time 12919533606 ps
CPU time 64.23 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:59:22 PM PDT 24
Peak memory 202088 kb
Host smart-18cc58ea-0971-4ecc-9a01-84007ac0c21e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4243779530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.4243779530
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2086630636
Short name T544
Test name
Test status
Simulation time 1331064696 ps
CPU time 6.74 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:26 PM PDT 24
Peak memory 201976 kb
Host smart-677ba145-f1c9-455b-a319-3f7ad65cf7e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2086630636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2086630636
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.328172342
Short name T162
Test name
Test status
Simulation time 73485113 ps
CPU time 7.12 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201932 kb
Host smart-b52390f4-cdc2-422f-82c5-a2354b754b42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328172342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.328172342
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.2097815993
Short name T300
Test name
Test status
Simulation time 614338719 ps
CPU time 5.65 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:25 PM PDT 24
Peak memory 201908 kb
Host smart-1067dca1-fe66-407f-9b1c-c59b69629d1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2097815993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2097815993
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.502833351
Short name T592
Test name
Test status
Simulation time 25309645355 ps
CPU time 62.41 seconds
Started Jul 07 05:58:20 PM PDT 24
Finished Jul 07 05:59:23 PM PDT 24
Peak memory 202012 kb
Host smart-a13f50a2-855d-4035-9601-27ccc25a6ae5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=502833351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.502833351
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.52094289
Short name T111
Test name
Test status
Simulation time 66749764192 ps
CPU time 178.11 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 06:01:17 PM PDT 24
Peak memory 202072 kb
Host smart-6d6c47c5-4088-43b1-acc7-ce83c5f955bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=52094289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.52094289
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3972750557
Short name T297
Test name
Test status
Simulation time 162678458 ps
CPU time 6.1 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:24 PM PDT 24
Peak memory 201916 kb
Host smart-9a6440b5-81ee-40db-be35-2563f9fd5fe7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972750557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3972750557
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.2257357888
Short name T808
Test name
Test status
Simulation time 573873891 ps
CPU time 7.7 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:23 PM PDT 24
Peak memory 201916 kb
Host smart-810895d7-0f46-48fd-9633-0c0810ceb338
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2257357888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2257357888
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.1589008787
Short name T748
Test name
Test status
Simulation time 41455551 ps
CPU time 1.36 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:17 PM PDT 24
Peak memory 201876 kb
Host smart-2827df11-d256-4b9f-b7ae-f8c442062e7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1589008787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1589008787
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1350396146
Short name T870
Test name
Test status
Simulation time 3500567928 ps
CPU time 8.53 seconds
Started Jul 07 05:58:20 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 201956 kb
Host smart-edeea988-9010-4cb2-a5f3-bec92189f715
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350396146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1350396146
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.986327411
Short name T259
Test name
Test status
Simulation time 792239527 ps
CPU time 5.22 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:24 PM PDT 24
Peak memory 201960 kb
Host smart-5d9d251a-7d71-4a02-8685-5de1ccd97dd7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=986327411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.986327411
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3835402851
Short name T668
Test name
Test status
Simulation time 8209691 ps
CPU time 1.06 seconds
Started Jul 07 05:58:14 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 201904 kb
Host smart-0fcb6ea8-6f31-4778-bc16-75cd40fa8cd5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835402851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3835402851
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3772926005
Short name T594
Test name
Test status
Simulation time 577852973 ps
CPU time 82.46 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 204072 kb
Host smart-ee28ac04-c618-4b26-afae-30de906af57d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3772926005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3772926005
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3034370720
Short name T287
Test name
Test status
Simulation time 3102386248 ps
CPU time 16.29 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:35 PM PDT 24
Peak memory 202012 kb
Host smart-ae8172c0-2c00-4130-ac07-86faa1aea674
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3034370720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3034370720
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1769712561
Short name T208
Test name
Test status
Simulation time 5342610368 ps
CPU time 219.7 seconds
Started Jul 07 05:58:17 PM PDT 24
Finished Jul 07 06:01:57 PM PDT 24
Peak memory 209180 kb
Host smart-4b87627b-ade0-40a1-9f8e-dd83b155bb7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1769712561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.1769712561
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.393322475
Short name T728
Test name
Test status
Simulation time 760937530 ps
CPU time 109.83 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 206944 kb
Host smart-568e68af-c0b0-4666-9679-c2c172e82922
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=393322475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res
et_error.393322475
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3554482810
Short name T785
Test name
Test status
Simulation time 1060178565 ps
CPU time 9.55 seconds
Started Jul 07 05:58:15 PM PDT 24
Finished Jul 07 05:58:25 PM PDT 24
Peak memory 201900 kb
Host smart-4723abc0-bb3d-4b60-b3c1-401034f9ef78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3554482810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3554482810
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.4180322984
Short name T204
Test name
Test status
Simulation time 1187455139 ps
CPU time 13.79 seconds
Started Jul 07 05:58:22 PM PDT 24
Finished Jul 07 05:58:36 PM PDT 24
Peak memory 201944 kb
Host smart-c0a7a900-3f03-4eb7-ab0d-b7dffddc8a8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4180322984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.4180322984
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1740977091
Short name T197
Test name
Test status
Simulation time 4362272888 ps
CPU time 19.41 seconds
Started Jul 07 05:58:23 PM PDT 24
Finished Jul 07 05:58:43 PM PDT 24
Peak memory 202100 kb
Host smart-16f96e9e-0a44-40fb-b7cf-ff7cb59f9f2c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1740977091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1740977091
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2364042356
Short name T580
Test name
Test status
Simulation time 66153177 ps
CPU time 6.18 seconds
Started Jul 07 05:58:22 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 201984 kb
Host smart-fa153f48-5c8e-41b2-9a6b-3ad743b7eb9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2364042356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2364042356
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.3759682801
Short name T18
Test name
Test status
Simulation time 756169195 ps
CPU time 14.61 seconds
Started Jul 07 05:58:26 PM PDT 24
Finished Jul 07 05:58:41 PM PDT 24
Peak memory 201912 kb
Host smart-621d49c8-066c-4a0a-a35c-3b34442e2637
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3759682801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3759682801
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2264563710
Short name T413
Test name
Test status
Simulation time 72171136 ps
CPU time 7.46 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:25 PM PDT 24
Peak memory 201912 kb
Host smart-2d0dbf04-744f-4e25-bce3-9bfed2f5fa5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2264563710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2264563710
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.4259623991
Short name T280
Test name
Test status
Simulation time 60611585476 ps
CPU time 61.63 seconds
Started Jul 07 05:58:22 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 202016 kb
Host smart-df553803-809a-48fc-bebf-a3a79e76598f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259623991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.4259623991
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.870181870
Short name T466
Test name
Test status
Simulation time 6512130732 ps
CPU time 12.17 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:31 PM PDT 24
Peak memory 202072 kb
Host smart-587f2c28-08db-480d-b1ff-7f9dde6d1e81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=870181870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.870181870
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1641738362
Short name T122
Test name
Test status
Simulation time 36439072 ps
CPU time 4.4 seconds
Started Jul 07 05:58:17 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201908 kb
Host smart-ce1d5590-1252-4b56-8eb2-04a0a9827fa4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641738362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1641738362
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.1481352772
Short name T782
Test name
Test status
Simulation time 2307366289 ps
CPU time 11.54 seconds
Started Jul 07 05:58:21 PM PDT 24
Finished Jul 07 05:58:32 PM PDT 24
Peak memory 201904 kb
Host smart-292e6af5-2179-4d53-ae46-bcaef35c9b49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1481352772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1481352772
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.625708494
Short name T734
Test name
Test status
Simulation time 34686064 ps
CPU time 1.39 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:19 PM PDT 24
Peak memory 201920 kb
Host smart-bb6e374f-14ec-4baa-8ea7-aeb70b6e2fa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=625708494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.625708494
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.135142580
Short name T388
Test name
Test status
Simulation time 7085836572 ps
CPU time 10.06 seconds
Started Jul 07 05:58:18 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 201996 kb
Host smart-69295da4-89dc-4f05-b5cc-f6d9250546d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=135142580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.135142580
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2487438690
Short name T612
Test name
Test status
Simulation time 1325015246 ps
CPU time 6.34 seconds
Started Jul 07 05:58:17 PM PDT 24
Finished Jul 07 05:58:24 PM PDT 24
Peak memory 201956 kb
Host smart-5d5545cf-e70b-426a-98fe-a0b6b496691f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2487438690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2487438690
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.495978514
Short name T384
Test name
Test status
Simulation time 10059297 ps
CPU time 1.31 seconds
Started Jul 07 05:58:20 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 201904 kb
Host smart-81942ab3-2bef-4cad-b3b6-4a32e6b8c089
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495978514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.495978514
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.384259752
Short name T105
Test name
Test status
Simulation time 6464231036 ps
CPU time 54.37 seconds
Started Jul 07 05:58:24 PM PDT 24
Finished Jul 07 05:59:19 PM PDT 24
Peak memory 202948 kb
Host smart-70ed64dd-2ae2-4f24-973d-2af592204928
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=384259752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.384259752
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2478527831
Short name T689
Test name
Test status
Simulation time 8597730685 ps
CPU time 91.98 seconds
Started Jul 07 05:58:25 PM PDT 24
Finished Jul 07 05:59:57 PM PDT 24
Peak memory 202080 kb
Host smart-87395d13-05b8-46f6-913b-869b6c3d40ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2478527831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2478527831
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2377312296
Short name T415
Test name
Test status
Simulation time 2286100414 ps
CPU time 64.48 seconds
Started Jul 07 05:58:25 PM PDT 24
Finished Jul 07 05:59:29 PM PDT 24
Peak memory 204264 kb
Host smart-0d4c923e-6f76-4302-9ade-c29223c588b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2377312296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.2377312296
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1255101964
Short name T173
Test name
Test status
Simulation time 1552214391 ps
CPU time 46.33 seconds
Started Jul 07 05:58:26 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 203312 kb
Host smart-e01338a0-278e-4d4f-968d-88ddc7fd1cb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1255101964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.1255101964
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3773068306
Short name T802
Test name
Test status
Simulation time 1385207198 ps
CPU time 11.82 seconds
Started Jul 07 05:58:21 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 201832 kb
Host smart-7e68bfb1-64f9-487d-ac38-7f51235586be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3773068306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3773068306
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.365627235
Short name T524
Test name
Test status
Simulation time 42425786 ps
CPU time 6.89 seconds
Started Jul 07 05:58:28 PM PDT 24
Finished Jul 07 05:58:35 PM PDT 24
Peak memory 201924 kb
Host smart-ab43fe6a-cf42-4415-bdf3-4ea473f3364c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=365627235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.365627235
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2152404102
Short name T201
Test name
Test status
Simulation time 93872440746 ps
CPU time 266.68 seconds
Started Jul 07 05:58:24 PM PDT 24
Finished Jul 07 06:02:51 PM PDT 24
Peak memory 203076 kb
Host smart-a3cc0843-c2f7-4d13-a8b4-01df7784a6e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2152404102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.2152404102
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.4246122770
Short name T535
Test name
Test status
Simulation time 513283454 ps
CPU time 3.6 seconds
Started Jul 07 05:58:33 PM PDT 24
Finished Jul 07 05:58:37 PM PDT 24
Peak memory 201940 kb
Host smart-55d471c5-9041-41e4-bdd6-216bbd604ff6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4246122770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.4246122770
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.1304069295
Short name T377
Test name
Test status
Simulation time 26506950 ps
CPU time 3.57 seconds
Started Jul 07 05:58:29 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 201872 kb
Host smart-6a6f01ef-940b-4233-aaa1-085ed55dab9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1304069295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1304069295
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.2532600704
Short name T674
Test name
Test status
Simulation time 205167091 ps
CPU time 2.5 seconds
Started Jul 07 05:58:25 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 201892 kb
Host smart-06e57ee8-2ee2-47aa-8dcf-23ce3fae2062
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2532600704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2532600704
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.535573365
Short name T622
Test name
Test status
Simulation time 71142209845 ps
CPU time 58.23 seconds
Started Jul 07 05:58:23 PM PDT 24
Finished Jul 07 05:59:21 PM PDT 24
Peak memory 202308 kb
Host smart-15cd4492-ed6a-4156-b100-766d64d77f20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=535573365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.535573365
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2810345893
Short name T276
Test name
Test status
Simulation time 4671269866 ps
CPU time 31.39 seconds
Started Jul 07 05:58:26 PM PDT 24
Finished Jul 07 05:58:58 PM PDT 24
Peak memory 202356 kb
Host smart-cb620746-8424-4be2-9444-9fcb953b5368
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2810345893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2810345893
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2281042074
Short name T264
Test name
Test status
Simulation time 50369195 ps
CPU time 5.52 seconds
Started Jul 07 05:58:25 PM PDT 24
Finished Jul 07 05:58:31 PM PDT 24
Peak memory 201832 kb
Host smart-2dfa6a87-f860-4f1d-8bc1-d8b186842207
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281042074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2281042074
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.3081418456
Short name T831
Test name
Test status
Simulation time 118445316 ps
CPU time 2.36 seconds
Started Jul 07 05:58:29 PM PDT 24
Finished Jul 07 05:58:31 PM PDT 24
Peak memory 201804 kb
Host smart-0a0334e8-b627-4e30-bb9b-088aa2e3aa65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3081418456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3081418456
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.4283164500
Short name T336
Test name
Test status
Simulation time 8958793 ps
CPU time 1.02 seconds
Started Jul 07 05:58:25 PM PDT 24
Finished Jul 07 05:58:27 PM PDT 24
Peak memory 201904 kb
Host smart-418b5930-1bd6-459e-98f4-556ab1fe47ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4283164500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.4283164500
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1168266380
Short name T472
Test name
Test status
Simulation time 9996053684 ps
CPU time 10.3 seconds
Started Jul 07 05:58:28 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 201856 kb
Host smart-47b37601-d84c-4b4b-b4d1-674206660329
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168266380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1168266380
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.20775985
Short name T308
Test name
Test status
Simulation time 930603482 ps
CPU time 4.91 seconds
Started Jul 07 05:58:27 PM PDT 24
Finished Jul 07 05:58:32 PM PDT 24
Peak memory 201860 kb
Host smart-406b7761-347a-4eab-b871-df233268e5e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=20775985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.20775985
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.4138603094
Short name T255
Test name
Test status
Simulation time 13873687 ps
CPU time 1.29 seconds
Started Jul 07 05:58:25 PM PDT 24
Finished Jul 07 05:58:27 PM PDT 24
Peak memory 201916 kb
Host smart-60392575-8938-4012-b8d6-44103eb4aa15
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138603094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.4138603094
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1360497634
Short name T50
Test name
Test status
Simulation time 7411526597 ps
CPU time 91.18 seconds
Started Jul 07 05:58:34 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 204244 kb
Host smart-a7db0bda-a440-4c2c-901f-e1d2fb250fd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1360497634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1360497634
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.344602745
Short name T666
Test name
Test status
Simulation time 3389600234 ps
CPU time 16.09 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:58:52 PM PDT 24
Peak memory 201960 kb
Host smart-499dffbc-ef6c-49bd-83bd-28ebe5521108
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=344602745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.344602745
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1459271846
Short name T813
Test name
Test status
Simulation time 250780571 ps
CPU time 49 seconds
Started Jul 07 05:58:30 PM PDT 24
Finished Jul 07 05:59:19 PM PDT 24
Peak memory 204524 kb
Host smart-fb2e9600-5eb4-42c4-8277-b28efd740de4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1459271846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1459271846
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2129719516
Short name T815
Test name
Test status
Simulation time 1484442803 ps
CPU time 73.02 seconds
Started Jul 07 05:58:28 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 205812 kb
Host smart-53484003-6050-4e18-927a-008732a4c6b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2129719516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.2129719516
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2890364572
Short name T448
Test name
Test status
Simulation time 36520940 ps
CPU time 4.67 seconds
Started Jul 07 05:58:26 PM PDT 24
Finished Jul 07 05:58:31 PM PDT 24
Peak memory 201828 kb
Host smart-5c0de84d-27a6-48bc-b09f-60e3d8131098
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2890364572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2890364572
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1923272786
Short name T268
Test name
Test status
Simulation time 2827946373 ps
CPU time 15.24 seconds
Started Jul 07 05:58:34 PM PDT 24
Finished Jul 07 05:58:50 PM PDT 24
Peak memory 201956 kb
Host smart-aef62b26-bda6-47bf-92a1-907c1e09478d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1923272786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1923272786
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3767322775
Short name T797
Test name
Test status
Simulation time 30449735031 ps
CPU time 195.41 seconds
Started Jul 07 05:58:32 PM PDT 24
Finished Jul 07 06:01:48 PM PDT 24
Peak memory 203360 kb
Host smart-19ccd61d-4ad1-4e0e-afa6-6a4e10d54ff9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3767322775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.3767322775
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.330526738
Short name T447
Test name
Test status
Simulation time 39517533 ps
CPU time 1.3 seconds
Started Jul 07 05:58:32 PM PDT 24
Finished Jul 07 05:58:34 PM PDT 24
Peak memory 201784 kb
Host smart-bfae228f-8752-4a6b-ab08-6c002a7af72f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=330526738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.330526738
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.3833147277
Short name T626
Test name
Test status
Simulation time 310922530 ps
CPU time 4.42 seconds
Started Jul 07 05:58:29 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 201856 kb
Host smart-1bc680b4-a041-46e9-a7b5-79bf914930ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3833147277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3833147277
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.4291604538
Short name T156
Test name
Test status
Simulation time 2282561971 ps
CPU time 7.7 seconds
Started Jul 07 05:58:30 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 201972 kb
Host smart-b2fe7c56-6e4d-4d55-9af4-004b1f6b0edb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4291604538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.4291604538
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2273640984
Short name T311
Test name
Test status
Simulation time 125185719821 ps
CPU time 125.85 seconds
Started Jul 07 05:58:29 PM PDT 24
Finished Jul 07 06:00:35 PM PDT 24
Peak memory 202308 kb
Host smart-9b13382c-3bb4-4a05-9d67-924d17ab3859
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273640984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2273640984
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3785079113
Short name T859
Test name
Test status
Simulation time 40587694600 ps
CPU time 70.74 seconds
Started Jul 07 05:58:30 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 202072 kb
Host smart-b7d45c89-ed21-48d1-9410-ad784b77def4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3785079113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3785079113
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3036323727
Short name T390
Test name
Test status
Simulation time 90634876 ps
CPU time 5.2 seconds
Started Jul 07 05:58:31 PM PDT 24
Finished Jul 07 05:58:36 PM PDT 24
Peak memory 201824 kb
Host smart-017181c3-59a5-4e7d-9ec7-69396e2bab99
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036323727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3036323727
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.3469560194
Short name T475
Test name
Test status
Simulation time 2001417592 ps
CPU time 9.19 seconds
Started Jul 07 05:58:33 PM PDT 24
Finished Jul 07 05:58:42 PM PDT 24
Peak memory 201888 kb
Host smart-d4aff485-fc1b-4f43-8059-5cf80291663d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3469560194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3469560194
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.3029242233
Short name T263
Test name
Test status
Simulation time 16995019 ps
CPU time 1.3 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:58:37 PM PDT 24
Peak memory 201884 kb
Host smart-54a7bc50-77cc-4738-a8a2-80e7900fd0b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3029242233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3029242233
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.295914729
Short name T574
Test name
Test status
Simulation time 4327922664 ps
CPU time 7.45 seconds
Started Jul 07 05:58:30 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 202052 kb
Host smart-059ba6d7-2882-4767-b3e7-48405104477f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=295914729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.295914729
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1979325572
Short name T552
Test name
Test status
Simulation time 2830345918 ps
CPU time 10.41 seconds
Started Jul 07 05:58:27 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 201988 kb
Host smart-6c5a66d9-9122-4e3a-b43a-8b756e52998a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1979325572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1979325572
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.458190686
Short name T49
Test name
Test status
Simulation time 15431845 ps
CPU time 1.22 seconds
Started Jul 07 05:58:29 PM PDT 24
Finished Jul 07 05:58:30 PM PDT 24
Peak memory 201916 kb
Host smart-daf677f2-dc33-4833-875f-21b4db4915b3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458190686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.458190686
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.152608267
Short name T206
Test name
Test status
Simulation time 2363682420 ps
CPU time 35.49 seconds
Started Jul 07 05:58:34 PM PDT 24
Finished Jul 07 05:59:10 PM PDT 24
Peak memory 202672 kb
Host smart-1159f8b5-460e-46f2-92fc-72ff1d48fa7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=152608267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.152608267
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3443231980
Short name T879
Test name
Test status
Simulation time 4793296799 ps
CPU time 45.38 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:59:21 PM PDT 24
Peak memory 202064 kb
Host smart-35d69f9b-911c-47d8-8f1c-9c12a9d49e67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3443231980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3443231980
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.557726397
Short name T787
Test name
Test status
Simulation time 418690465 ps
CPU time 105.9 seconds
Started Jul 07 05:58:32 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 204356 kb
Host smart-4193854d-3499-4060-ad67-8386cc381697
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=557726397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand
_reset.557726397
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.174399164
Short name T564
Test name
Test status
Simulation time 6394388425 ps
CPU time 100.78 seconds
Started Jul 07 05:58:32 PM PDT 24
Finished Jul 07 06:00:13 PM PDT 24
Peak memory 206688 kb
Host smart-601ee0b0-a9cf-4a20-b698-5012ee514b91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=174399164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res
et_error.174399164
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3384719875
Short name T691
Test name
Test status
Simulation time 60844174 ps
CPU time 6.1 seconds
Started Jul 07 05:58:33 PM PDT 24
Finished Jul 07 05:58:39 PM PDT 24
Peak memory 201848 kb
Host smart-e5ac2737-f418-46c8-bc5d-954b33f159c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3384719875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3384719875
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.244909786
Short name T866
Test name
Test status
Simulation time 301082807 ps
CPU time 7.11 seconds
Started Jul 07 05:58:33 PM PDT 24
Finished Jul 07 05:58:41 PM PDT 24
Peak memory 201916 kb
Host smart-8d140770-e379-4b0e-b0c3-6359a881a82b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=244909786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.244909786
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2367169596
Short name T407
Test name
Test status
Simulation time 9484649743 ps
CPU time 53.37 seconds
Started Jul 07 05:58:31 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 202048 kb
Host smart-c025865d-1da7-47ee-a2f1-640d129e1216
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2367169596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.2367169596
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2766264997
Short name T421
Test name
Test status
Simulation time 1531017352 ps
CPU time 4.2 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:58:45 PM PDT 24
Peak memory 201940 kb
Host smart-3cdb8ef0-37e4-47ec-bcfc-434c96fe87ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2766264997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2766264997
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.2956826358
Short name T439
Test name
Test status
Simulation time 344321896 ps
CPU time 5.2 seconds
Started Jul 07 05:58:32 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 201916 kb
Host smart-991df2a5-7843-4e45-b2b6-4c7df830c218
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2956826358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2956826358
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.3887189147
Short name T652
Test name
Test status
Simulation time 1242201696 ps
CPU time 4.24 seconds
Started Jul 07 05:58:31 PM PDT 24
Finished Jul 07 05:58:36 PM PDT 24
Peak memory 201912 kb
Host smart-841490a4-f34a-4ea9-8abb-53fc1ec7d746
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3887189147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3887189147
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3650096089
Short name T114
Test name
Test status
Simulation time 47711731460 ps
CPU time 118.93 seconds
Started Jul 07 05:58:36 PM PDT 24
Finished Jul 07 06:00:35 PM PDT 24
Peak memory 202044 kb
Host smart-c76b0466-1713-4ffd-bf81-6b7f80f31dac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650096089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3650096089
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.462975512
Short name T244
Test name
Test status
Simulation time 46915121569 ps
CPU time 49.4 seconds
Started Jul 07 05:58:36 PM PDT 24
Finished Jul 07 05:59:26 PM PDT 24
Peak memory 202068 kb
Host smart-6e3e9b98-df77-441f-ac1c-e6c1f6ef5852
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=462975512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.462975512
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1289175512
Short name T723
Test name
Test status
Simulation time 75636037 ps
CPU time 3.06 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:58:39 PM PDT 24
Peak memory 201856 kb
Host smart-a9505355-74e7-4759-96ae-d10f848cd84d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289175512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1289175512
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.4121631097
Short name T893
Test name
Test status
Simulation time 56018576 ps
CPU time 5.08 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:58:40 PM PDT 24
Peak memory 201896 kb
Host smart-c94b67a1-2d1f-46f8-bc02-adf6e4f5720e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4121631097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4121631097
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.1754707608
Short name T310
Test name
Test status
Simulation time 11528498 ps
CPU time 1.18 seconds
Started Jul 07 05:58:31 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 201908 kb
Host smart-8366ffab-e458-4167-9814-89f477e3ddb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1754707608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1754707608
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2868117745
Short name T488
Test name
Test status
Simulation time 2833834054 ps
CPU time 10.96 seconds
Started Jul 07 05:58:34 PM PDT 24
Finished Jul 07 05:58:45 PM PDT 24
Peak memory 201996 kb
Host smart-50a7b1bd-ac5c-436f-9ca1-4835cb05e8bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868117745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2868117745
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3563881834
Short name T742
Test name
Test status
Simulation time 3460402065 ps
CPU time 8.12 seconds
Started Jul 07 05:58:34 PM PDT 24
Finished Jul 07 05:58:42 PM PDT 24
Peak memory 201920 kb
Host smart-54af8cb2-0841-4d52-b569-d59ebd05f5bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3563881834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3563881834
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2808642135
Short name T892
Test name
Test status
Simulation time 8610973 ps
CPU time 1.18 seconds
Started Jul 07 05:58:33 PM PDT 24
Finished Jul 07 05:58:34 PM PDT 24
Peak memory 202192 kb
Host smart-c612325f-ece8-4989-9f96-47eddb79fab3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808642135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2808642135
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3143719432
Short name T895
Test name
Test status
Simulation time 4661181561 ps
CPU time 67.37 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:59:43 PM PDT 24
Peak memory 203048 kb
Host smart-a3f47865-c812-4f1f-8004-8d7db12d0774
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3143719432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3143719432
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1458080840
Short name T331
Test name
Test status
Simulation time 2461981693 ps
CPU time 15.86 seconds
Started Jul 07 05:58:38 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 202028 kb
Host smart-43fb6e23-b921-4e2d-bc8e-6bbc71d603f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1458080840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1458080840
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1463883422
Short name T560
Test name
Test status
Simulation time 38778369 ps
CPU time 6.33 seconds
Started Jul 07 05:58:40 PM PDT 24
Finished Jul 07 05:58:46 PM PDT 24
Peak memory 201960 kb
Host smart-d7baaea0-f12e-4dc3-bb78-e0fbe45714e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1463883422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.1463883422
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.4173600263
Short name T210
Test name
Test status
Simulation time 939775323 ps
CPU time 114.28 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 06:00:30 PM PDT 24
Peak memory 204460 kb
Host smart-045529e2-4e49-450e-bd83-455d1651591c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4173600263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.4173600263
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.361330343
Short name T680
Test name
Test status
Simulation time 150770462 ps
CPU time 5.82 seconds
Started Jul 07 05:58:35 PM PDT 24
Finished Jul 07 05:58:41 PM PDT 24
Peak memory 201896 kb
Host smart-18e3c9cb-e3b5-45b4-9ec9-cb6170bc2303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=361330343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.361330343
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3189035577
Short name T199
Test name
Test status
Simulation time 898090834 ps
CPU time 9.62 seconds
Started Jul 07 05:58:40 PM PDT 24
Finished Jul 07 05:58:50 PM PDT 24
Peak memory 201732 kb
Host smart-8997ead8-1a86-4215-8545-967669d01030
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3189035577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3189035577
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3622884692
Short name T897
Test name
Test status
Simulation time 48639371726 ps
CPU time 359.79 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 06:04:42 PM PDT 24
Peak memory 203104 kb
Host smart-26439fba-0bf5-4c81-8929-b1b8b92c5ae7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3622884692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.3622884692
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2579176049
Short name T228
Test name
Test status
Simulation time 320887604 ps
CPU time 6.98 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:58:48 PM PDT 24
Peak memory 201972 kb
Host smart-a22f694f-c2bb-470c-8828-836eae8c08d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2579176049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2579176049
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.3896239499
Short name T670
Test name
Test status
Simulation time 393949763 ps
CPU time 2.5 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:58:44 PM PDT 24
Peak memory 201856 kb
Host smart-22f6486c-e034-4a10-8f7f-db0160980e29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3896239499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3896239499
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.4080023288
Short name T320
Test name
Test status
Simulation time 77448762 ps
CPU time 8.2 seconds
Started Jul 07 05:58:44 PM PDT 24
Finished Jul 07 05:58:52 PM PDT 24
Peak memory 201900 kb
Host smart-dd6c540b-063b-4c16-8ae9-71f605067019
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4080023288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4080023288
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1600967479
Short name T654
Test name
Test status
Simulation time 77838820472 ps
CPU time 112.75 seconds
Started Jul 07 05:58:44 PM PDT 24
Finished Jul 07 06:00:37 PM PDT 24
Peak memory 202040 kb
Host smart-b2fbef0d-ca8e-451f-b736-b12d97b5d878
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600967479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1600967479
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2978760780
Short name T533
Test name
Test status
Simulation time 17576536648 ps
CPU time 119.5 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 06:00:45 PM PDT 24
Peak memory 202092 kb
Host smart-4b4c9e2c-be13-42dc-be00-9609d231e189
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2978760780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2978760780
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.4089098476
Short name T633
Test name
Test status
Simulation time 45487490 ps
CPU time 6.29 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 05:58:49 PM PDT 24
Peak memory 201824 kb
Host smart-404aa197-e8d7-495c-b9b2-157f394c494c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089098476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4089098476
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.65744952
Short name T121
Test name
Test status
Simulation time 559510148 ps
CPU time 8.16 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:58:50 PM PDT 24
Peak memory 201900 kb
Host smart-950690d9-55d0-4425-8707-52df0c378e3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65744952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.65744952
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.408323276
Short name T675
Test name
Test status
Simulation time 18487009 ps
CPU time 1.39 seconds
Started Jul 07 05:58:36 PM PDT 24
Finished Jul 07 05:58:38 PM PDT 24
Peak memory 201920 kb
Host smart-f96d49e9-e588-43f3-aa62-29456781925d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=408323276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.408323276
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2788710129
Short name T583
Test name
Test status
Simulation time 5446301473 ps
CPU time 16 seconds
Started Jul 07 05:58:39 PM PDT 24
Finished Jul 07 05:58:55 PM PDT 24
Peak memory 202044 kb
Host smart-6d1dfc49-bfd6-4b9d-8cde-eb394bcc80f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788710129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2788710129
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1147742637
Short name T863
Test name
Test status
Simulation time 2212549880 ps
CPU time 7.69 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:58:49 PM PDT 24
Peak memory 202012 kb
Host smart-609bbfe4-fb01-48ed-aa0e-90f8be4b4e66
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1147742637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1147742637
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3327700900
Short name T232
Test name
Test status
Simulation time 8737882 ps
CPU time 1.18 seconds
Started Jul 07 05:58:38 PM PDT 24
Finished Jul 07 05:58:40 PM PDT 24
Peak memory 201724 kb
Host smart-de72dc50-919d-4c9d-823e-9849623d0484
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327700900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3327700900
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.188585552
Short name T519
Test name
Test status
Simulation time 3903520513 ps
CPU time 38.23 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:59:20 PM PDT 24
Peak memory 202984 kb
Host smart-c018a844-ff05-4faf-a748-3c7c26994de9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=188585552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.188585552
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2321473813
Short name T170
Test name
Test status
Simulation time 3237328991 ps
CPU time 18.89 seconds
Started Jul 07 05:58:39 PM PDT 24
Finished Jul 07 05:58:59 PM PDT 24
Peak memory 202312 kb
Host smart-aa31df83-ce72-4e69-914b-915d9d57d3ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2321473813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2321473813
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2171377911
Short name T218
Test name
Test status
Simulation time 277696801 ps
CPU time 29.12 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:59:15 PM PDT 24
Peak memory 204032 kb
Host smart-b17c93b3-871c-4dd0-a1a9-fdc54fa840c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2171377911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.2171377911
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4130912999
Short name T539
Test name
Test status
Simulation time 3132884202 ps
CPU time 82.41 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 204208 kb
Host smart-5d496ade-f012-4d06-a563-1e2eb900889f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4130912999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.4130912999
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2178371903
Short name T485
Test name
Test status
Simulation time 353728467 ps
CPU time 6 seconds
Started Jul 07 05:58:41 PM PDT 24
Finished Jul 07 05:58:47 PM PDT 24
Peak memory 201916 kb
Host smart-cf83d1dd-f1b7-4ba5-85b8-c660ab504597
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2178371903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2178371903
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3611413168
Short name T443
Test name
Test status
Simulation time 490087942 ps
CPU time 10.74 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:58:58 PM PDT 24
Peak memory 201856 kb
Host smart-6a5667a7-565a-4964-903e-eecf8a91d958
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3611413168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3611413168
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2644364985
Short name T146
Test name
Test status
Simulation time 16143549703 ps
CPU time 55.58 seconds
Started Jul 07 05:58:45 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 202072 kb
Host smart-0155cd88-1aa7-4843-8689-f778e59b5f8f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2644364985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.2644364985
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1895223815
Short name T872
Test name
Test status
Simulation time 134995873 ps
CPU time 2.22 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 05:58:45 PM PDT 24
Peak memory 201976 kb
Host smart-7085a935-782c-4df3-bf84-3fba5150f04e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1895223815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1895223815
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.272641322
Short name T643
Test name
Test status
Simulation time 35623169 ps
CPU time 4.45 seconds
Started Jul 07 05:58:44 PM PDT 24
Finished Jul 07 05:58:49 PM PDT 24
Peak memory 201932 kb
Host smart-3b4dc7da-fbdb-43fe-81f7-4b9b8e9c93a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=272641322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.272641322
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.2331281231
Short name T588
Test name
Test status
Simulation time 447301146 ps
CPU time 3.47 seconds
Started Jul 07 05:58:45 PM PDT 24
Finished Jul 07 05:58:49 PM PDT 24
Peak memory 201916 kb
Host smart-332d3608-485b-4a25-a59c-5dd45a6252c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2331281231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2331281231
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1030730053
Short name T582
Test name
Test status
Simulation time 21763412757 ps
CPU time 47.2 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 05:59:29 PM PDT 24
Peak memory 202044 kb
Host smart-700cd8c1-8fe8-4ce7-b85c-07915bdf8db8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030730053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1030730053
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.740921904
Short name T818
Test name
Test status
Simulation time 14313212128 ps
CPU time 25.96 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 05:59:09 PM PDT 24
Peak memory 202072 kb
Host smart-359481a7-b333-4116-a8c3-21e4e68b427f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=740921904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.740921904
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1298584921
Short name T44
Test name
Test status
Simulation time 12039441 ps
CPU time 1.18 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:49 PM PDT 24
Peak memory 201908 kb
Host smart-f7260fbf-cba0-4f3e-bfec-4580f05ccbfe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298584921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1298584921
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.4006559419
Short name T354
Test name
Test status
Simulation time 398241350 ps
CPU time 2.58 seconds
Started Jul 07 05:58:44 PM PDT 24
Finished Jul 07 05:58:48 PM PDT 24
Peak memory 201924 kb
Host smart-881a1163-7a8d-4c2c-bb81-deb8f137c429
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4006559419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4006559419
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.3100384060
Short name T606
Test name
Test status
Simulation time 28690673 ps
CPU time 1.3 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 05:58:44 PM PDT 24
Peak memory 201904 kb
Host smart-d8410889-5977-48a7-9481-793efe71164c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3100384060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3100384060
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1480830625
Short name T603
Test name
Test status
Simulation time 4140137157 ps
CPU time 7.14 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:55 PM PDT 24
Peak memory 201984 kb
Host smart-0be5c799-089f-497c-bffd-797f98ddbc61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480830625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1480830625
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3229248900
Short name T434
Test name
Test status
Simulation time 1515386228 ps
CPU time 8.61 seconds
Started Jul 07 05:58:45 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 201960 kb
Host smart-c51892a2-3cd2-4c48-8768-e431c9850a5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3229248900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3229248900
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3487850322
Short name T143
Test name
Test status
Simulation time 21110067 ps
CPU time 1.18 seconds
Started Jul 07 05:58:43 PM PDT 24
Finished Jul 07 05:58:44 PM PDT 24
Peak memory 201788 kb
Host smart-6ac797f0-7b59-4316-a434-2821bbe333b5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487850322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3487850322
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1377107941
Short name T70
Test name
Test status
Simulation time 3468704746 ps
CPU time 37.62 seconds
Started Jul 07 05:58:44 PM PDT 24
Finished Jul 07 05:59:22 PM PDT 24
Peak memory 201960 kb
Host smart-8c92e45f-5cc0-456e-b918-548d2cfc005b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1377107941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1377107941
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.886499056
Short name T357
Test name
Test status
Simulation time 37229297847 ps
CPU time 77.93 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 204968 kb
Host smart-bb7b59e0-acda-4e31-8ccb-959ef5b1e20b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=886499056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.886499056
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3810698320
Short name T768
Test name
Test status
Simulation time 893794481 ps
CPU time 128.65 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 06:00:55 PM PDT 24
Peak memory 204536 kb
Host smart-e91d28c1-733e-41b6-aad8-ea4388590ad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810698320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.3810698320
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3488062349
Short name T9
Test name
Test status
Simulation time 8111161586 ps
CPU time 66.51 seconds
Started Jul 07 05:58:45 PM PDT 24
Finished Jul 07 05:59:52 PM PDT 24
Peak memory 204532 kb
Host smart-17e8392c-5421-43e7-8be7-67097dc5653d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3488062349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.3488062349
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.941915398
Short name T578
Test name
Test status
Simulation time 218971615 ps
CPU time 3.9 seconds
Started Jul 07 05:58:42 PM PDT 24
Finished Jul 07 05:58:47 PM PDT 24
Peak memory 201920 kb
Host smart-1f9d2710-0d85-497f-9017-23868a278d8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=941915398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.941915398
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.129552211
Short name T857
Test name
Test status
Simulation time 432246293 ps
CPU time 4.57 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 201824 kb
Host smart-6a69626a-984f-4b43-a99f-7a546fb51aa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=129552211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.129552211
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4002384225
Short name T869
Test name
Test status
Simulation time 24971768386 ps
CPU time 148.83 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 06:01:25 PM PDT 24
Peak memory 203008 kb
Host smart-6a8d4afe-dd39-439a-9720-251af0a83678
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4002384225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.4002384225
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3347603631
Short name T688
Test name
Test status
Simulation time 32173171 ps
CPU time 2.51 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:50 PM PDT 24
Peak memory 201952 kb
Host smart-e1e69f61-c57b-48f8-abcf-19099e86c615
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3347603631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3347603631
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2806695056
Short name T381
Test name
Test status
Simulation time 56996477 ps
CPU time 1.46 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:58:57 PM PDT 24
Peak memory 201820 kb
Host smart-bd333f5c-592f-426a-bccb-e08ea7160487
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2806695056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2806695056
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.1451843357
Short name T294
Test name
Test status
Simulation time 478498046 ps
CPU time 8.17 seconds
Started Jul 07 05:58:50 PM PDT 24
Finished Jul 07 05:58:59 PM PDT 24
Peak memory 201884 kb
Host smart-8a3ca86b-25cf-4ae2-9c47-669e4711df56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1451843357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1451843357
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2581749192
Short name T394
Test name
Test status
Simulation time 24527599063 ps
CPU time 59 seconds
Started Jul 07 05:58:52 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201984 kb
Host smart-e17d10e8-33ce-41ad-bb31-217afbb281ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581749192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2581749192
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3665810345
Short name T530
Test name
Test status
Simulation time 14493439086 ps
CPU time 51.11 seconds
Started Jul 07 05:58:49 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 202048 kb
Host smart-13acacc8-6862-4bb2-ab33-15b0953031f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3665810345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3665810345
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2153454565
Short name T781
Test name
Test status
Simulation time 93568926 ps
CPU time 5.85 seconds
Started Jul 07 05:58:45 PM PDT 24
Finished Jul 07 05:58:51 PM PDT 24
Peak memory 201916 kb
Host smart-0ff6da33-b329-487e-a5f8-fdd78dbcc4c8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153454565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2153454565
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.276688140
Short name T868
Test name
Test status
Simulation time 17050234 ps
CPU time 1.44 seconds
Started Jul 07 05:58:50 PM PDT 24
Finished Jul 07 05:58:51 PM PDT 24
Peak memory 201852 kb
Host smart-e81fe601-3d8b-4451-8e53-1e90e2bf427b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=276688140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.276688140
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.2235971289
Short name T160
Test name
Test status
Simulation time 64825160 ps
CPU time 1.36 seconds
Started Jul 07 05:58:44 PM PDT 24
Finished Jul 07 05:58:46 PM PDT 24
Peak memory 201884 kb
Host smart-e89b3d91-a0cd-4653-82ba-69789443312f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2235971289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2235971289
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1441757406
Short name T4
Test name
Test status
Simulation time 2112756575 ps
CPU time 6.06 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:53 PM PDT 24
Peak memory 201888 kb
Host smart-fbd3eeb6-0bc0-4d89-896b-9d540ef38295
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441757406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1441757406
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2164960878
Short name T637
Test name
Test status
Simulation time 847007835 ps
CPU time 5.61 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:53 PM PDT 24
Peak memory 201924 kb
Host smart-ec5ebe90-753c-4701-af0c-b62653731c82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2164960878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2164960878
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2938231657
Short name T364
Test name
Test status
Simulation time 11539108 ps
CPU time 1.17 seconds
Started Jul 07 05:58:55 PM PDT 24
Finished Jul 07 05:58:57 PM PDT 24
Peak memory 201812 kb
Host smart-05668f17-00e8-456c-8b5a-32d36055d452
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938231657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2938231657
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3183542593
Short name T258
Test name
Test status
Simulation time 299280642 ps
CPU time 15.45 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:59:12 PM PDT 24
Peak memory 201832 kb
Host smart-0c4fce25-8e0b-4f5c-8ca6-4fac78765638
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3183542593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3183542593
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1495695517
Short name T241
Test name
Test status
Simulation time 1577571891 ps
CPU time 26.89 seconds
Started Jul 07 05:58:57 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 203060 kb
Host smart-6fc7f9c6-0b23-435e-8ecf-d9a995cbbe5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1495695517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.1495695517
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.783927685
Short name T209
Test name
Test status
Simulation time 284309585 ps
CPU time 30.01 seconds
Started Jul 07 05:58:51 PM PDT 24
Finished Jul 07 05:59:21 PM PDT 24
Peak memory 203444 kb
Host smart-21b48e29-2af4-4b28-a82f-3b3f80efc29d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=783927685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_res
et_error.783927685
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1814022539
Short name T292
Test name
Test status
Simulation time 12595005 ps
CPU time 1.44 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:58:48 PM PDT 24
Peak memory 201932 kb
Host smart-b1d91a3b-6578-4fc2-954b-e573945899d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1814022539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1814022539
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.691595092
Short name T554
Test name
Test status
Simulation time 213161762 ps
CPU time 3.59 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:51 PM PDT 24
Peak memory 201920 kb
Host smart-0ecb1e75-6c9f-411e-bf6d-4caa6b61af84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=691595092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.691595092
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3441344374
Short name T616
Test name
Test status
Simulation time 44709968634 ps
CPU time 149.26 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 06:01:17 PM PDT 24
Peak memory 203096 kb
Host smart-d9bf67b2-249c-4580-9235-2e2ce540184e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3441344374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.3441344374
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2632958022
Short name T481
Test name
Test status
Simulation time 2829495358 ps
CPU time 11.19 seconds
Started Jul 07 05:58:50 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 202032 kb
Host smart-d4588dfa-b315-4451-837b-59b198f0040f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2632958022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2632958022
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.4279793140
Short name T238
Test name
Test status
Simulation time 210903794 ps
CPU time 3.83 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:58:50 PM PDT 24
Peak memory 201932 kb
Host smart-1360ffb2-18fc-43da-8e48-a5d4946043a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4279793140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4279793140
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.4130712015
Short name T690
Test name
Test status
Simulation time 105317496 ps
CPU time 7.26 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 201836 kb
Host smart-15ce57bd-e228-4a02-a0c1-302c46eabb13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4130712015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.4130712015
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1493160177
Short name T615
Test name
Test status
Simulation time 48496974261 ps
CPU time 112.62 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 06:00:40 PM PDT 24
Peak memory 202036 kb
Host smart-7eebf28e-77ce-4c64-9ad0-9ff38f5cc4dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493160177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1493160177
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2955892430
Short name T231
Test name
Test status
Simulation time 2774671105 ps
CPU time 17.3 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:59:04 PM PDT 24
Peak memory 201924 kb
Host smart-b65e4837-de8e-4535-8079-2cb0af51ff30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2955892430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2955892430
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.563243080
Short name T553
Test name
Test status
Simulation time 8577890 ps
CPU time 1.1 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:58:48 PM PDT 24
Peak memory 201876 kb
Host smart-394de495-efc9-4ef6-901c-6039b93c232a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563243080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.563243080
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.133882937
Short name T596
Test name
Test status
Simulation time 516053142 ps
CPU time 7.47 seconds
Started Jul 07 05:58:49 PM PDT 24
Finished Jul 07 05:58:57 PM PDT 24
Peak memory 201892 kb
Host smart-dccbc7f5-7a6f-41f7-bf56-8016679fd577
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=133882937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.133882937
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3314357058
Short name T766
Test name
Test status
Simulation time 17870364 ps
CPU time 1.27 seconds
Started Jul 07 05:58:47 PM PDT 24
Finished Jul 07 05:58:49 PM PDT 24
Peak memory 201908 kb
Host smart-f33da882-67eb-4018-a67b-5974d59d0e71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3314357058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3314357058
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2079405636
Short name T801
Test name
Test status
Simulation time 11995412859 ps
CPU time 15 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:59:12 PM PDT 24
Peak memory 201944 kb
Host smart-ce646aed-a56d-4013-a086-8103a9460bee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079405636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2079405636
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1572857510
Short name T589
Test name
Test status
Simulation time 642462276 ps
CPU time 4.81 seconds
Started Jul 07 05:58:46 PM PDT 24
Finished Jul 07 05:58:52 PM PDT 24
Peak memory 201828 kb
Host smart-d13ff98b-fe6c-425e-980c-57f1b4089154
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1572857510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1572857510
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2469227866
Short name T43
Test name
Test status
Simulation time 25768195 ps
CPU time 1.39 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:58:58 PM PDT 24
Peak memory 201816 kb
Host smart-9050b6ac-ff43-47a2-9fb3-f916608dc417
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469227866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2469227866
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.4030534180
Short name T816
Test name
Test status
Simulation time 12669340516 ps
CPU time 104.69 seconds
Started Jul 07 05:58:49 PM PDT 24
Finished Jul 07 06:00:34 PM PDT 24
Peak memory 204060 kb
Host smart-d826db27-6b06-4b78-940b-8ec43ca3c679
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4030534180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4030534180
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1771383701
Short name T678
Test name
Test status
Simulation time 374769851 ps
CPU time 26.99 seconds
Started Jul 07 05:58:50 PM PDT 24
Finished Jul 07 05:59:17 PM PDT 24
Peak memory 201956 kb
Host smart-9dd8505d-0d94-4d85-8f0a-b52e3ab64cbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1771383701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1771383701
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2459728440
Short name T684
Test name
Test status
Simulation time 240505908 ps
CPU time 71.28 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 204776 kb
Host smart-cd78259f-e40c-467f-a1dc-add78a25b1c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2459728440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.2459728440
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3024524203
Short name T140
Test name
Test status
Simulation time 606805991 ps
CPU time 64.69 seconds
Started Jul 07 05:58:48 PM PDT 24
Finished Jul 07 05:59:53 PM PDT 24
Peak memory 203924 kb
Host smart-5c1c293e-972b-45ee-a763-ddd2dac5925a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3024524203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.3024524203
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.44150453
Short name T150
Test name
Test status
Simulation time 725199936 ps
CPU time 8.58 seconds
Started Jul 07 05:58:51 PM PDT 24
Finished Jul 07 05:59:00 PM PDT 24
Peak memory 201892 kb
Host smart-e208adfc-c504-4c6f-bd17-9667beee0899
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44150453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.44150453
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3898525396
Short name T428
Test name
Test status
Simulation time 123347911 ps
CPU time 3.29 seconds
Started Jul 07 05:56:42 PM PDT 24
Finished Jul 07 05:56:46 PM PDT 24
Peak memory 201920 kb
Host smart-97fa33e8-025d-4b9b-a3ad-f0ece6ccd2eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3898525396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3898525396
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3904046503
Short name T275
Test name
Test status
Simulation time 3203862797 ps
CPU time 19.56 seconds
Started Jul 07 05:56:37 PM PDT 24
Finished Jul 07 05:56:57 PM PDT 24
Peak memory 202020 kb
Host smart-9903e7cb-f80d-4e92-b69f-af74ad4a814d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3904046503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3904046503
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3548020080
Short name T862
Test name
Test status
Simulation time 281637473 ps
CPU time 3.71 seconds
Started Jul 07 05:56:37 PM PDT 24
Finished Jul 07 05:56:41 PM PDT 24
Peak memory 201944 kb
Host smart-63ddcf3f-2cf7-4a8a-a6ba-8e644df75e22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3548020080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3548020080
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.874801416
Short name T401
Test name
Test status
Simulation time 2006948246 ps
CPU time 8.92 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201924 kb
Host smart-f09d921f-146e-40cb-bc8a-b230287770fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=874801416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.874801416
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.3803636695
Short name T623
Test name
Test status
Simulation time 1222595495 ps
CPU time 10.49 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201824 kb
Host smart-4581a6b9-521a-445e-bd79-23220f281505
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3803636695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3803636695
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3531268824
Short name T651
Test name
Test status
Simulation time 35704761951 ps
CPU time 39.98 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:57:21 PM PDT 24
Peak memory 201772 kb
Host smart-21b94f82-cec4-431f-a242-f827cd5193e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531268824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3531268824
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3951312422
Short name T599
Test name
Test status
Simulation time 6706038904 ps
CPU time 47.35 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:57:28 PM PDT 24
Peak memory 201784 kb
Host smart-e6b50d57-a38d-4f12-9291-362317c099e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3951312422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3951312422
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1892665092
Short name T314
Test name
Test status
Simulation time 37024543 ps
CPU time 3.83 seconds
Started Jul 07 05:56:33 PM PDT 24
Finished Jul 07 05:56:37 PM PDT 24
Peak memory 201880 kb
Host smart-f7a69a65-412b-4135-8a2c-2a57da33e6c9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892665092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1892665092
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.3184461970
Short name T549
Test name
Test status
Simulation time 36223001 ps
CPU time 3.99 seconds
Started Jul 07 05:56:37 PM PDT 24
Finished Jul 07 05:56:41 PM PDT 24
Peak memory 201924 kb
Host smart-b81ed9a1-bf0c-4745-a6cc-8f6c30a859e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3184461970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3184461970
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1106753115
Short name T480
Test name
Test status
Simulation time 137497947 ps
CPU time 1.32 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:56:37 PM PDT 24
Peak memory 201920 kb
Host smart-5681194e-4430-4b9b-a51e-3e65ad681634
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1106753115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1106753115
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1550691902
Short name T743
Test name
Test status
Simulation time 5888066342 ps
CPU time 9.02 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:49 PM PDT 24
Peak memory 201948 kb
Host smart-7fe3be17-00aa-460b-a9d1-caa698fd68d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550691902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1550691902
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.4237642614
Short name T175
Test name
Test status
Simulation time 1980152762 ps
CPU time 9.39 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201952 kb
Host smart-df4aafc4-4c81-4c32-b83a-f636a00e7202
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4237642614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.4237642614
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.994466002
Short name T888
Test name
Test status
Simulation time 9329650 ps
CPU time 1.41 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:56:38 PM PDT 24
Peak memory 201724 kb
Host smart-48587adc-42bb-4834-a1d9-7513fc54722d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994466002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.994466002
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.15437377
Short name T117
Test name
Test status
Simulation time 7539810026 ps
CPU time 71.7 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 203376 kb
Host smart-44b42fa2-fb01-4551-9fd0-8151c174ef18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15437377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.15437377
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3004970739
Short name T459
Test name
Test status
Simulation time 280286028 ps
CPU time 30.16 seconds
Started Jul 07 05:56:38 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 201904 kb
Host smart-3a9c7faf-49c8-4c43-a235-f1db68e023a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3004970739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3004970739
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.625141815
Short name T473
Test name
Test status
Simulation time 877981496 ps
CPU time 88.4 seconds
Started Jul 07 05:56:42 PM PDT 24
Finished Jul 07 05:58:11 PM PDT 24
Peak memory 203476 kb
Host smart-b6ca7613-2f4b-4730-84a2-0c478fed4b3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=625141815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese
t_error.625141815
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.394918557
Short name T737
Test name
Test status
Simulation time 154356468 ps
CPU time 2.79 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:56:39 PM PDT 24
Peak memory 201908 kb
Host smart-78f00cfb-b9b7-4eef-8218-17abdafb07a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=394918557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.394918557
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3799094941
Short name T442
Test name
Test status
Simulation time 889153111 ps
CPU time 18.38 seconds
Started Jul 07 05:58:55 PM PDT 24
Finished Jul 07 05:59:14 PM PDT 24
Peak memory 201892 kb
Host smart-2fdad1f3-17f9-4490-a45a-d8909aee3b87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3799094941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3799094941
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.696410178
Short name T568
Test name
Test status
Simulation time 33849335735 ps
CPU time 258.44 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 06:03:15 PM PDT 24
Peak memory 204128 kb
Host smart-4ebf7c17-1279-41ec-8e38-abfead11ee8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=696410178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.696410178
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1876222956
Short name T512
Test name
Test status
Simulation time 86507090 ps
CPU time 5.99 seconds
Started Jul 07 05:58:58 PM PDT 24
Finished Jul 07 05:59:04 PM PDT 24
Peak memory 201940 kb
Host smart-36bbfc09-d23a-4bf2-9d5d-0c78fce8eae1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1876222956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1876222956
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.1530272883
Short name T718
Test name
Test status
Simulation time 417360063 ps
CPU time 4.88 seconds
Started Jul 07 05:58:52 PM PDT 24
Finished Jul 07 05:58:58 PM PDT 24
Peak memory 201924 kb
Host smart-5c47381d-9d78-445e-96ee-76528fabefec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1530272883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1530272883
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.2793755793
Short name T166
Test name
Test status
Simulation time 341181891 ps
CPU time 4.6 seconds
Started Jul 07 05:58:51 PM PDT 24
Finished Jul 07 05:58:56 PM PDT 24
Peak memory 201916 kb
Host smart-555ade86-b395-440e-8fad-38b56053212b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2793755793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2793755793
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3401548779
Short name T462
Test name
Test status
Simulation time 22824255187 ps
CPU time 44.72 seconds
Started Jul 07 05:58:52 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 202012 kb
Host smart-a63218ab-d43a-4194-ba45-888b4072e7c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401548779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3401548779
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2819342292
Short name T103
Test name
Test status
Simulation time 57591531184 ps
CPU time 162.67 seconds
Started Jul 07 05:58:50 PM PDT 24
Finished Jul 07 06:01:33 PM PDT 24
Peak memory 202084 kb
Host smart-98d8252c-1d1c-4a91-899b-c69d8b3538c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2819342292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2819342292
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.335317111
Short name T894
Test name
Test status
Simulation time 197778246 ps
CPU time 4.53 seconds
Started Jul 07 05:58:51 PM PDT 24
Finished Jul 07 05:58:55 PM PDT 24
Peak memory 201880 kb
Host smart-27122d40-058c-4ce3-bd7d-870f685ad11d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335317111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.335317111
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2640496084
Short name T876
Test name
Test status
Simulation time 40140882 ps
CPU time 4.47 seconds
Started Jul 07 05:58:55 PM PDT 24
Finished Jul 07 05:59:00 PM PDT 24
Peak memory 201924 kb
Host smart-d540258c-2ae3-4c67-a207-8ac1b4c1409a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2640496084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2640496084
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.730971662
Short name T604
Test name
Test status
Simulation time 78066224 ps
CPU time 1.36 seconds
Started Jul 07 05:58:55 PM PDT 24
Finished Jul 07 05:58:56 PM PDT 24
Peak memory 201880 kb
Host smart-ed0fb00e-7e44-41ec-b38c-67bfd2c4b1fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=730971662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.730971662
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2134000427
Short name T282
Test name
Test status
Simulation time 2652481982 ps
CPU time 11.8 seconds
Started Jul 07 05:58:51 PM PDT 24
Finished Jul 07 05:59:03 PM PDT 24
Peak memory 201856 kb
Host smart-40385c9d-038b-4c03-99ac-4c52474c0746
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134000427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2134000427
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1182726127
Short name T253
Test name
Test status
Simulation time 1148207647 ps
CPU time 6.29 seconds
Started Jul 07 05:58:54 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 201964 kb
Host smart-8417ba7d-9527-4374-9281-71c42f94390c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1182726127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1182726127
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.794361502
Short name T664
Test name
Test status
Simulation time 12709607 ps
CPU time 1.35 seconds
Started Jul 07 05:58:52 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 201884 kb
Host smart-60b7fb52-b4f9-4d0c-b803-d17a94f66557
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794361502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.794361502
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3232899761
Short name T712
Test name
Test status
Simulation time 8610184189 ps
CPU time 127.25 seconds
Started Jul 07 05:58:57 PM PDT 24
Finished Jul 07 06:01:05 PM PDT 24
Peak memory 205560 kb
Host smart-28800ad2-33ff-40f0-bab0-706ce9e8efca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3232899761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3232899761
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1609790921
Short name T187
Test name
Test status
Simulation time 5849698104 ps
CPU time 91.31 seconds
Started Jul 07 05:58:54 PM PDT 24
Finished Jul 07 06:00:26 PM PDT 24
Peak memory 202004 kb
Host smart-35de9c98-d72c-4d97-ab77-66dd6401319a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1609790921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1609790921
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1949925952
Short name T106
Test name
Test status
Simulation time 12487187550 ps
CPU time 199.12 seconds
Started Jul 07 05:58:54 PM PDT 24
Finished Jul 07 06:02:13 PM PDT 24
Peak memory 206420 kb
Host smart-98462ee5-1bda-454b-8834-235527c9b35f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1949925952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.1949925952
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4068155186
Short name T609
Test name
Test status
Simulation time 479753361 ps
CPU time 74.86 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 204264 kb
Host smart-e565ea28-2fbf-46dd-ad12-781d1fb25b52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4068155186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.4068155186
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2885129051
Short name T362
Test name
Test status
Simulation time 128706809 ps
CPU time 7.79 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 201912 kb
Host smart-c79291f7-e1a5-43da-80a2-3df506c38d3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2885129051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2885129051
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1223446463
Short name T474
Test name
Test status
Simulation time 59189650 ps
CPU time 3.07 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:59:00 PM PDT 24
Peak memory 201844 kb
Host smart-c2eae3b6-c85c-478d-87e6-b27ca7514744
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1223446463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1223446463
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.705173566
Short name T590
Test name
Test status
Simulation time 11344685704 ps
CPU time 63.39 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 05:59:57 PM PDT 24
Peak memory 202052 kb
Host smart-9129cfeb-a40e-4a6c-90f7-00b7a767007e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=705173566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.705173566
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4274651625
Short name T242
Test name
Test status
Simulation time 663212293 ps
CPU time 12.51 seconds
Started Jul 07 05:58:59 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 201972 kb
Host smart-8be8b775-13f4-465e-8837-3c04bb350b78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4274651625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4274651625
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.4188958343
Short name T613
Test name
Test status
Simulation time 129568424 ps
CPU time 4.95 seconds
Started Jul 07 05:58:55 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 201928 kb
Host smart-b2415881-efe4-4cd6-93a4-b842269561f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4188958343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4188958343
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.2613823953
Short name T64
Test name
Test status
Simulation time 228073756 ps
CPU time 3.66 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 05:58:57 PM PDT 24
Peak memory 201912 kb
Host smart-922530f4-ecb8-42fd-89d2-b4e273716ea5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2613823953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2613823953
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.639432809
Short name T871
Test name
Test status
Simulation time 11077198335 ps
CPU time 35.87 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 05:59:29 PM PDT 24
Peak memory 202008 kb
Host smart-062a6f7b-e165-429d-a93f-7de72ac4e559
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=639432809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.639432809
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1656608621
Short name T33
Test name
Test status
Simulation time 23547347087 ps
CPU time 72.93 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 202048 kb
Host smart-f32f59d5-6d3d-4eea-8713-41250f75afbe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1656608621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1656608621
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1400861248
Short name T406
Test name
Test status
Simulation time 73053339 ps
CPU time 5.04 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 201884 kb
Host smart-53ee887e-6bf7-4676-a73d-0420eec7fa8e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400861248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1400861248
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.678588511
Short name T548
Test name
Test status
Simulation time 788892940 ps
CPU time 2.12 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 05:58:56 PM PDT 24
Peak memory 201844 kb
Host smart-3121c7e1-d792-49f9-a2d5-52416077742b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=678588511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.678588511
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1810615567
Short name T343
Test name
Test status
Simulation time 9767275 ps
CPU time 1.06 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:58:58 PM PDT 24
Peak memory 201908 kb
Host smart-31adc770-7f15-4684-ab2f-a0280a8522cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810615567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1810615567
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2322161522
Short name T891
Test name
Test status
Simulation time 1959683682 ps
CPU time 9.48 seconds
Started Jul 07 05:58:52 PM PDT 24
Finished Jul 07 05:59:01 PM PDT 24
Peak memory 201892 kb
Host smart-70af5164-d618-49c3-94ec-efc950472ec7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322161522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2322161522
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3265586589
Short name T792
Test name
Test status
Simulation time 1499043527 ps
CPU time 10.6 seconds
Started Jul 07 05:58:58 PM PDT 24
Finished Jul 07 05:59:09 PM PDT 24
Peak memory 201928 kb
Host smart-30803d24-98e5-47e3-bf46-5859cfd6c045
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3265586589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3265586589
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1352160476
Short name T658
Test name
Test status
Simulation time 9809070 ps
CPU time 1.29 seconds
Started Jul 07 05:58:53 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 201884 kb
Host smart-cdac390e-a6a9-4198-9e27-562be01253e0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352160476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1352160476
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.4006383917
Short name T693
Test name
Test status
Simulation time 1715871670 ps
CPU time 16.14 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 201892 kb
Host smart-3c70af6f-9231-466a-b658-1a7a01f81c2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4006383917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.4006383917
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1367110969
Short name T701
Test name
Test status
Simulation time 656815469 ps
CPU time 12.38 seconds
Started Jul 07 05:58:59 PM PDT 24
Finished Jul 07 05:59:12 PM PDT 24
Peak memory 201960 kb
Host smart-2ede6589-d769-4c64-8eef-f1874979ae12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1367110969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1367110969
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2435526037
Short name T215
Test name
Test status
Simulation time 794718003 ps
CPU time 134.92 seconds
Started Jul 07 05:58:59 PM PDT 24
Finished Jul 07 06:01:14 PM PDT 24
Peak memory 207788 kb
Host smart-79c25c5e-0817-4489-b095-59bcc794ffdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2435526037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2435526037
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2575314019
Short name T523
Test name
Test status
Simulation time 25958781 ps
CPU time 3.11 seconds
Started Jul 07 05:58:58 PM PDT 24
Finished Jul 07 05:59:02 PM PDT 24
Peak memory 201912 kb
Host smart-853537c6-0305-4381-b58d-b5b3b35b85a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2575314019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2575314019
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2489042295
Short name T289
Test name
Test status
Simulation time 39161388 ps
CPU time 6.52 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 05:59:09 PM PDT 24
Peak memory 201904 kb
Host smart-a2d87450-a522-4234-95d1-62b4606614e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2489042295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2489042295
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1487550477
Short name T844
Test name
Test status
Simulation time 24284738523 ps
CPU time 155.24 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 06:01:31 PM PDT 24
Peak memory 203064 kb
Host smart-0c37a719-5c46-475c-8b3c-0c81ee5c5fc9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1487550477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.1487550477
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2600651782
Short name T451
Test name
Test status
Simulation time 41621841 ps
CPU time 4.29 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 05:59:07 PM PDT 24
Peak memory 201912 kb
Host smart-0141adc5-34e3-46a7-a3ec-25a1ded5b983
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2600651782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2600651782
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.1435778766
Short name T435
Test name
Test status
Simulation time 364146570 ps
CPU time 3.79 seconds
Started Jul 07 05:59:07 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 201932 kb
Host smart-5fa49da7-b88a-4909-b9b9-edb8a779e78f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1435778766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1435778766
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.828514477
Short name T329
Test name
Test status
Simulation time 23584095 ps
CPU time 3.12 seconds
Started Jul 07 05:58:59 PM PDT 24
Finished Jul 07 05:59:03 PM PDT 24
Peak memory 201880 kb
Host smart-23bfe9e3-1e1d-49c0-a6c0-30481a2ead60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=828514477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.828514477
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1670089274
Short name T825
Test name
Test status
Simulation time 58286103769 ps
CPU time 174.45 seconds
Started Jul 07 05:58:56 PM PDT 24
Finished Jul 07 06:01:51 PM PDT 24
Peak memory 202044 kb
Host smart-9e5e8966-996b-44bf-baa5-ac769ac2ee65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670089274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1670089274
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2090445403
Short name T322
Test name
Test status
Simulation time 32491164814 ps
CPU time 52.03 seconds
Started Jul 07 05:58:58 PM PDT 24
Finished Jul 07 05:59:50 PM PDT 24
Peak memory 202076 kb
Host smart-b43be00a-81eb-495c-ad83-1aab8808bea9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2090445403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2090445403
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3164790373
Short name T581
Test name
Test status
Simulation time 84742719 ps
CPU time 3.84 seconds
Started Jul 07 05:59:01 PM PDT 24
Finished Jul 07 05:59:06 PM PDT 24
Peak memory 201904 kb
Host smart-93c0cae0-62b3-45bf-938c-f2eee993f1fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164790373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3164790373
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3179318404
Short name T898
Test name
Test status
Simulation time 67761321 ps
CPU time 2.92 seconds
Started Jul 07 05:58:55 PM PDT 24
Finished Jul 07 05:58:59 PM PDT 24
Peak memory 201912 kb
Host smart-1cd0408f-2ff1-49b9-92bd-0e5fc85f4f91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3179318404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3179318404
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.711426184
Short name T163
Test name
Test status
Simulation time 102871888 ps
CPU time 1.68 seconds
Started Jul 07 05:59:01 PM PDT 24
Finished Jul 07 05:59:03 PM PDT 24
Peak memory 201924 kb
Host smart-e2de3069-9777-42c7-95c6-3907ae3053dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=711426184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.711426184
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1020453427
Short name T778
Test name
Test status
Simulation time 20100224783 ps
CPU time 10.97 seconds
Started Jul 07 05:59:00 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 202012 kb
Host smart-de506dd0-fdc0-4575-bc06-280b60a30f81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020453427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1020453427
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3235640208
Short name T671
Test name
Test status
Simulation time 16266107499 ps
CPU time 13.3 seconds
Started Jul 07 05:58:57 PM PDT 24
Finished Jul 07 05:59:10 PM PDT 24
Peak memory 201984 kb
Host smart-1c2e15b5-db60-4305-a18a-66e03b4eeff4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3235640208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3235640208
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3873467633
Short name T144
Test name
Test status
Simulation time 12413683 ps
CPU time 1.06 seconds
Started Jul 07 05:58:58 PM PDT 24
Finished Jul 07 05:58:59 PM PDT 24
Peak memory 201792 kb
Host smart-db2f1913-d2d6-4941-9510-614b88331d91
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873467633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3873467633
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1361347998
Short name T195
Test name
Test status
Simulation time 7165527279 ps
CPU time 46.54 seconds
Started Jul 07 05:59:01 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 203036 kb
Host smart-42df1a19-32da-49d3-ad60-64e697b51ea1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1361347998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1361347998
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3664288086
Short name T345
Test name
Test status
Simulation time 19971873646 ps
CPU time 75.18 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 203136 kb
Host smart-e3f25849-6af5-4e81-a9ac-8da959a84c03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3664288086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3664288086
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.790624701
Short name T874
Test name
Test status
Simulation time 1512336518 ps
CPU time 175.22 seconds
Started Jul 07 05:58:59 PM PDT 24
Finished Jul 07 06:01:54 PM PDT 24
Peak memory 207304 kb
Host smart-51b3bf7c-f2d2-4f30-8f4c-b8aebcb94d39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=790624701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand
_reset.790624701
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.235601471
Short name T217
Test name
Test status
Simulation time 1855450760 ps
CPU time 32.94 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 202924 kb
Host smart-d6110222-cd71-470b-909a-2a152592e499
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=235601471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res
et_error.235601471
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3100078010
Short name T715
Test name
Test status
Simulation time 1029289354 ps
CPU time 13.51 seconds
Started Jul 07 05:59:03 PM PDT 24
Finished Jul 07 05:59:17 PM PDT 24
Peak memory 201928 kb
Host smart-23f55625-badf-4b06-9116-55bd78f73637
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3100078010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3100078010
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1335105045
Short name T158
Test name
Test status
Simulation time 1144397137 ps
CPU time 4 seconds
Started Jul 07 05:59:04 PM PDT 24
Finished Jul 07 05:59:08 PM PDT 24
Peak memory 201888 kb
Host smart-6c77a303-8d6d-4dda-871a-617defdbdfee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1335105045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1335105045
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3515096029
Short name T341
Test name
Test status
Simulation time 52763941 ps
CPU time 4.42 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 201992 kb
Host smart-9bf9825b-5494-4436-ba37-ac7e139d2bab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3515096029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3515096029
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1650970564
Short name T224
Test name
Test status
Simulation time 115162930 ps
CPU time 2.19 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:07 PM PDT 24
Peak memory 201848 kb
Host smart-eda26acf-17bb-43a5-a96f-bee5ad764f44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1650970564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1650970564
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.1720668666
Short name T807
Test name
Test status
Simulation time 18842113 ps
CPU time 1.72 seconds
Started Jul 07 05:59:03 PM PDT 24
Finished Jul 07 05:59:05 PM PDT 24
Peak memory 201920 kb
Host smart-85575d98-a0ad-4068-a1c2-b7a3b8888f8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1720668666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1720668666
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1740829600
Short name T148
Test name
Test status
Simulation time 23667124559 ps
CPU time 57.36 seconds
Started Jul 07 05:59:00 PM PDT 24
Finished Jul 07 05:59:58 PM PDT 24
Peak memory 202032 kb
Host smart-ac904fa7-f86b-4164-81dc-5d717c021ba7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740829600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1740829600
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4263739541
Short name T757
Test name
Test status
Simulation time 5923632124 ps
CPU time 29.53 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 202040 kb
Host smart-4acb70ac-9f19-4d0a-bec2-b995a2950a25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4263739541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4263739541
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1547464805
Short name T829
Test name
Test status
Simulation time 89273748 ps
CPU time 7.85 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 05:59:10 PM PDT 24
Peak memory 201888 kb
Host smart-65b32773-b52a-44bb-805c-3e2b9f99b9e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547464805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1547464805
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.53093756
Short name T747
Test name
Test status
Simulation time 211525751 ps
CPU time 4.41 seconds
Started Jul 07 05:59:03 PM PDT 24
Finished Jul 07 05:59:08 PM PDT 24
Peak memory 201920 kb
Host smart-aea1fbdd-6ddb-431c-97fb-b8e9c9129ea8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53093756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.53093756
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.810390174
Short name T395
Test name
Test status
Simulation time 11060050 ps
CPU time 1.22 seconds
Started Jul 07 05:59:01 PM PDT 24
Finished Jul 07 05:59:03 PM PDT 24
Peak memory 201912 kb
Host smart-02721874-f1d3-4a62-ae14-05ac8ca25ccf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=810390174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.810390174
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2790593104
Short name T80
Test name
Test status
Simulation time 6438008972 ps
CPU time 7.46 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 202052 kb
Host smart-e40c36e0-aa90-4029-ae87-989ebf7208b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790593104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2790593104
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.909945422
Short name T860
Test name
Test status
Simulation time 5855927275 ps
CPU time 9.89 seconds
Started Jul 07 05:59:03 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 202064 kb
Host smart-dae860f1-1bea-43c9-9444-5012f8ad299a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=909945422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.909945422
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.798266237
Short name T679
Test name
Test status
Simulation time 9785668 ps
CPU time 1.49 seconds
Started Jul 07 05:59:00 PM PDT 24
Finished Jul 07 05:59:02 PM PDT 24
Peak memory 201900 kb
Host smart-49e7d9f3-55a6-42e2-9916-9b38ea83ea69
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798266237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.798266237
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3875148482
Short name T380
Test name
Test status
Simulation time 2356331537 ps
CPU time 38.62 seconds
Started Jul 07 05:59:03 PM PDT 24
Finished Jul 07 05:59:42 PM PDT 24
Peak memory 203012 kb
Host smart-e3266dda-1209-4c4f-86ef-29e3079ae99d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3875148482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3875148482
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3506135257
Short name T398
Test name
Test status
Simulation time 1154921534 ps
CPU time 13.81 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:20 PM PDT 24
Peak memory 201976 kb
Host smart-97099eb7-0c0f-4cfb-b641-6418ff7f22b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3506135257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3506135257
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1042484500
Short name T216
Test name
Test status
Simulation time 758443798 ps
CPU time 92.44 seconds
Started Jul 07 05:59:04 PM PDT 24
Finished Jul 07 06:00:37 PM PDT 24
Peak memory 205996 kb
Host smart-6e4c38ca-3559-4051-ae72-2e7d33d5fe2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1042484500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.1042484500
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1776364791
Short name T3
Test name
Test status
Simulation time 9295661293 ps
CPU time 194.06 seconds
Started Jul 07 05:59:11 PM PDT 24
Finished Jul 07 06:02:25 PM PDT 24
Peak memory 206144 kb
Host smart-bf951d29-ebc9-4a81-92a4-fbb89601139d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1776364791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1776364791
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2671907815
Short name T403
Test name
Test status
Simulation time 901698908 ps
CPU time 11.24 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 05:59:22 PM PDT 24
Peak memory 201892 kb
Host smart-1eb0f775-b821-431f-ad15-887a3ad3417f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2671907815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2671907815
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2041962244
Short name T269
Test name
Test status
Simulation time 182217866 ps
CPU time 8.03 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:14 PM PDT 24
Peak memory 201920 kb
Host smart-555c1118-dda5-4d81-a519-7b04d60cfbe7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2041962244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2041962244
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1454094096
Short name T754
Test name
Test status
Simulation time 708888377 ps
CPU time 8.21 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 201944 kb
Host smart-a8a72176-558c-41d5-b095-efbaa352a559
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1454094096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1454094096
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3811832736
Short name T313
Test name
Test status
Simulation time 897697868 ps
CPU time 9.96 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 201920 kb
Host smart-e19cc6b0-2e56-417d-8599-b3a1f2505b4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3811832736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3811832736
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2752942595
Short name T646
Test name
Test status
Simulation time 696143944 ps
CPU time 9.33 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 201912 kb
Host smart-5e4a1eb6-6172-442f-bdcd-6c7562441627
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2752942595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2752942595
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1511036884
Short name T73
Test name
Test status
Simulation time 39673624847 ps
CPU time 107.03 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 06:00:58 PM PDT 24
Peak memory 202000 kb
Host smart-a89141c7-f056-469f-b5bf-03a53e83f15c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511036884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1511036884
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.4194226437
Short name T579
Test name
Test status
Simulation time 13743111636 ps
CPU time 84.45 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 06:00:35 PM PDT 24
Peak memory 202044 kb
Host smart-ffa0850f-6a5c-4187-ada2-2e8a1ca26d4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4194226437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4194226437
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2941093989
Short name T709
Test name
Test status
Simulation time 235838393 ps
CPU time 5.65 seconds
Started Jul 07 05:59:02 PM PDT 24
Finished Jul 07 05:59:08 PM PDT 24
Peak memory 201908 kb
Host smart-de765947-b78e-482a-9f85-c1bd5262ffee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941093989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2941093989
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.353600072
Short name T618
Test name
Test status
Simulation time 132176499 ps
CPU time 4.66 seconds
Started Jul 07 05:59:01 PM PDT 24
Finished Jul 07 05:59:06 PM PDT 24
Peak memory 201912 kb
Host smart-be230521-cc9c-4963-8938-4e53ae02f00b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=353600072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.353600072
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.2565532790
Short name T76
Test name
Test status
Simulation time 108902967 ps
CPU time 1.44 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:06 PM PDT 24
Peak memory 201920 kb
Host smart-163a11c1-08be-4c42-a72b-51c3f1c2f7c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2565532790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2565532790
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2711490374
Short name T729
Test name
Test status
Simulation time 4067942280 ps
CPU time 9.82 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 201964 kb
Host smart-9943df13-19bb-44de-ad7c-9f3c67629e88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711490374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2711490374
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2324241248
Short name T682
Test name
Test status
Simulation time 2384284562 ps
CPU time 5.78 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 201988 kb
Host smart-2ac2921c-f9a8-4794-8255-a8ca126687fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2324241248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2324241248
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3346881480
Short name T169
Test name
Test status
Simulation time 9103974 ps
CPU time 1.31 seconds
Started Jul 07 05:59:01 PM PDT 24
Finished Jul 07 05:59:03 PM PDT 24
Peak memory 201880 kb
Host smart-a0748d8d-fa71-4ae8-9a2f-3155ff5b6a24
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346881480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3346881480
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1109238321
Short name T123
Test name
Test status
Simulation time 40246285 ps
CPU time 2.77 seconds
Started Jul 07 05:59:07 PM PDT 24
Finished Jul 07 05:59:10 PM PDT 24
Peak memory 201920 kb
Host smart-e1cd8b8a-3d2b-4357-8a75-7fd8d8e3a6d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1109238321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1109238321
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2421008974
Short name T510
Test name
Test status
Simulation time 407434037 ps
CPU time 29.43 seconds
Started Jul 07 05:59:08 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201884 kb
Host smart-82e2d91d-6237-4281-802b-4da4bbd3c263
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2421008974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2421008974
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3274248105
Short name T211
Test name
Test status
Simulation time 599926416 ps
CPU time 43.82 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 203164 kb
Host smart-e651759b-0182-48ef-b9fb-8cfeb9158802
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3274248105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3274248105
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1427692189
Short name T817
Test name
Test status
Simulation time 99269514 ps
CPU time 6.45 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:12 PM PDT 24
Peak memory 201896 kb
Host smart-b98652b6-6c61-40de-928f-4df40ea72f30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1427692189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1427692189
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3389187305
Short name T333
Test name
Test status
Simulation time 1575425420 ps
CPU time 16.38 seconds
Started Jul 07 05:59:15 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201844 kb
Host smart-ab7b3ef7-e47f-42d2-aa29-de883e6d4a8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3389187305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3389187305
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1299715410
Short name T822
Test name
Test status
Simulation time 86573443018 ps
CPU time 299.7 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 06:04:10 PM PDT 24
Peak memory 204056 kb
Host smart-1aa77eba-b5fb-44e2-81f7-42434c85a5a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1299715410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.1299715410
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2621238454
Short name T273
Test name
Test status
Simulation time 968402341 ps
CPU time 2.29 seconds
Started Jul 07 05:59:15 PM PDT 24
Finished Jul 07 05:59:17 PM PDT 24
Peak memory 201944 kb
Host smart-ea7b89b6-360c-4366-9b2d-42b0fc9758d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2621238454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2621238454
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2170071734
Short name T351
Test name
Test status
Simulation time 981139611 ps
CPU time 11.71 seconds
Started Jul 07 05:59:14 PM PDT 24
Finished Jul 07 05:59:25 PM PDT 24
Peak memory 201848 kb
Host smart-30847fa8-3cb0-4045-8978-938d3f018e56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2170071734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2170071734
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.1455300038
Short name T655
Test name
Test status
Simulation time 549407339 ps
CPU time 11.34 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 201916 kb
Host smart-5cb91f0e-d6a1-420f-ba7b-0275cdb84ee2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1455300038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1455300038
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2347235258
Short name T361
Test name
Test status
Simulation time 19264377824 ps
CPU time 81.73 seconds
Started Jul 07 05:59:06 PM PDT 24
Finished Jul 07 06:00:29 PM PDT 24
Peak memory 202048 kb
Host smart-7a03d628-7b8f-49ed-b66b-6c6e0a50cf9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2347235258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2347235258
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.753826283
Short name T601
Test name
Test status
Simulation time 317667930 ps
CPU time 6.88 seconds
Started Jul 07 05:59:05 PM PDT 24
Finished Jul 07 05:59:12 PM PDT 24
Peak memory 201836 kb
Host smart-135c5a96-0c35-4717-a52f-72cecba5c07f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753826283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.753826283
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.1083730239
Short name T116
Test name
Test status
Simulation time 1111299952 ps
CPU time 13.34 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 201916 kb
Host smart-6cc94d0c-73fd-40c7-a86d-392fd5818b4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1083730239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1083730239
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.3156920197
Short name T635
Test name
Test status
Simulation time 77412335 ps
CPU time 1.62 seconds
Started Jul 07 05:59:11 PM PDT 24
Finished Jul 07 05:59:13 PM PDT 24
Peak memory 201844 kb
Host smart-e991b22e-5b88-4753-a1d2-1004b40619b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3156920197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3156920197
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2461185304
Short name T692
Test name
Test status
Simulation time 2232440664 ps
CPU time 11.11 seconds
Started Jul 07 05:59:04 PM PDT 24
Finished Jul 07 05:59:15 PM PDT 24
Peak memory 201980 kb
Host smart-f11ae264-071e-4fce-acd5-24992d9ce147
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461185304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2461185304
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.4196457772
Short name T450
Test name
Test status
Simulation time 1193250475 ps
CPU time 6.44 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 201836 kb
Host smart-c390db17-57d8-4342-9cab-e7e7a1d64688
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4196457772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4196457772
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2558207735
Short name T41
Test name
Test status
Simulation time 9623837 ps
CPU time 1.03 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 201904 kb
Host smart-53856eca-9ed8-4307-8eda-9d20d11799bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558207735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2558207735
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1319699703
Short name T749
Test name
Test status
Simulation time 7628836631 ps
CPU time 53.51 seconds
Started Jul 07 05:59:14 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 203040 kb
Host smart-ffa387a8-5dba-4184-ab95-f10278865f31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1319699703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1319699703
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.23305589
Short name T225
Test name
Test status
Simulation time 749735522 ps
CPU time 7.34 seconds
Started Jul 07 05:59:12 PM PDT 24
Finished Jul 07 05:59:20 PM PDT 24
Peak memory 201836 kb
Host smart-42f144dc-ca2e-450f-9af5-c66a832228e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23305589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.23305589
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1677092577
Short name T389
Test name
Test status
Simulation time 7124176330 ps
CPU time 114.84 seconds
Started Jul 07 05:59:11 PM PDT 24
Finished Jul 07 06:01:06 PM PDT 24
Peak memory 205860 kb
Host smart-eb344d30-8278-4c10-8433-62c2697f6cae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1677092577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1677092577
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1050257742
Short name T338
Test name
Test status
Simulation time 137051448 ps
CPU time 10.55 seconds
Started Jul 07 05:59:12 PM PDT 24
Finished Jul 07 05:59:23 PM PDT 24
Peak memory 201904 kb
Host smart-7fc3bc7a-26f6-4b20-9ad1-8be9325a6607
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1050257742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1050257742
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.272454907
Short name T423
Test name
Test status
Simulation time 118721083 ps
CPU time 5.66 seconds
Started Jul 07 05:59:10 PM PDT 24
Finished Jul 07 05:59:16 PM PDT 24
Peak memory 201916 kb
Host smart-5f684f2f-a57b-4d8d-813e-90c7564233af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=272454907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.272454907
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1038461523
Short name T811
Test name
Test status
Simulation time 134460758 ps
CPU time 9.39 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 05:59:26 PM PDT 24
Peak memory 201944 kb
Host smart-20971bcf-4a7d-4474-aad7-a326cccbf2b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1038461523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1038461523
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4005236170
Short name T205
Test name
Test status
Simulation time 41290724743 ps
CPU time 291.24 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 06:04:08 PM PDT 24
Peak memory 204168 kb
Host smart-0927ee82-5e30-4330-94b1-cc0b3543d860
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4005236170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.4005236170
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3293811078
Short name T821
Test name
Test status
Simulation time 434754453 ps
CPU time 3.17 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 05:59:20 PM PDT 24
Peak memory 201964 kb
Host smart-74f25c60-bb17-438e-817a-f01248aa6e8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3293811078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3293811078
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.1710450819
Short name T154
Test name
Test status
Simulation time 858577536 ps
CPU time 8.75 seconds
Started Jul 07 05:59:19 PM PDT 24
Finished Jul 07 05:59:28 PM PDT 24
Peak memory 201940 kb
Host smart-73845a23-ee13-4160-a6ac-4c0851b2179f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1710450819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1710450819
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.532709607
Short name T638
Test name
Test status
Simulation time 88264739 ps
CPU time 6.85 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 05:59:23 PM PDT 24
Peak memory 201908 kb
Host smart-967817fb-69e2-41e2-a0bd-7b7a7427295a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=532709607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.532709607
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.648685074
Short name T124
Test name
Test status
Simulation time 96971493928 ps
CPU time 141.47 seconds
Started Jul 07 05:59:19 PM PDT 24
Finished Jul 07 06:01:41 PM PDT 24
Peak memory 202052 kb
Host smart-73270275-7d47-4be9-8988-145cec0132e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=648685074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.648685074
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1624009285
Short name T374
Test name
Test status
Simulation time 16582948836 ps
CPU time 106.13 seconds
Started Jul 07 05:59:15 PM PDT 24
Finished Jul 07 06:01:01 PM PDT 24
Peak memory 202052 kb
Host smart-a113ff53-60df-4076-b1a9-b328c7d1cf53
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1624009285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1624009285
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2887830817
Short name T784
Test name
Test status
Simulation time 8745911 ps
CPU time 1.15 seconds
Started Jul 07 05:59:26 PM PDT 24
Finished Jul 07 05:59:28 PM PDT 24
Peak memory 201912 kb
Host smart-dbb08be8-c21e-43ce-926e-1e1fc7de8157
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887830817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2887830817
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.698105330
Short name T235
Test name
Test status
Simulation time 1698388670 ps
CPU time 8.2 seconds
Started Jul 07 05:59:12 PM PDT 24
Finished Jul 07 05:59:20 PM PDT 24
Peak memory 201916 kb
Host smart-350b5676-723a-4bd6-9700-72885fe72ded
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=698105330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.698105330
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.785193151
Short name T118
Test name
Test status
Simulation time 86988383 ps
CPU time 1.57 seconds
Started Jul 07 05:59:09 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 202184 kb
Host smart-75ac15e7-340e-4a10-bbde-f63f6ada0382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=785193151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.785193151
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2543980971
Short name T805
Test name
Test status
Simulation time 5765723830 ps
CPU time 9.54 seconds
Started Jul 07 05:59:14 PM PDT 24
Finished Jul 07 05:59:23 PM PDT 24
Peak memory 201960 kb
Host smart-f2c09eb1-36f2-44a2-a06d-f7ce687e3d2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543980971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2543980971
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3715796104
Short name T505
Test name
Test status
Simulation time 1832056241 ps
CPU time 7.84 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 201988 kb
Host smart-b1aefcbc-7849-4756-9f27-d683f97a0d4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3715796104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3715796104
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1803326559
Short name T285
Test name
Test status
Simulation time 8887224 ps
CPU time 1.14 seconds
Started Jul 07 05:59:14 PM PDT 24
Finished Jul 07 05:59:15 PM PDT 24
Peak memory 201876 kb
Host smart-e4c96e22-4e50-46f0-b8d7-fed0735030af
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803326559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1803326559
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2547806419
Short name T155
Test name
Test status
Simulation time 5944499102 ps
CPU time 18.09 seconds
Started Jul 07 05:59:13 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 202020 kb
Host smart-dc479fa4-3d62-4ef5-9e08-adf88b08d35a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2547806419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2547806419
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.4036794490
Short name T410
Test name
Test status
Simulation time 1888773187 ps
CPU time 27.38 seconds
Started Jul 07 05:59:17 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201972 kb
Host smart-155a7736-6c06-491b-9f3f-34c6a73c2c5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4036794490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.4036794490
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1137949491
Short name T849
Test name
Test status
Simulation time 533078789 ps
CPU time 97.61 seconds
Started Jul 07 05:59:20 PM PDT 24
Finished Jul 07 06:00:58 PM PDT 24
Peak memory 204436 kb
Host smart-915c07c8-425d-4c4f-848b-2d325ce50557
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1137949491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.1137949491
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3003717809
Short name T391
Test name
Test status
Simulation time 66113817 ps
CPU time 18.32 seconds
Started Jul 07 05:59:15 PM PDT 24
Finished Jul 07 05:59:34 PM PDT 24
Peak memory 201980 kb
Host smart-368d60b4-888e-4456-ab64-b1172209e625
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3003717809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.3003717809
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.93106678
Short name T453
Test name
Test status
Simulation time 549173939 ps
CPU time 5.59 seconds
Started Jul 07 05:59:19 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 201912 kb
Host smart-bef3b4a3-5081-4501-9da1-efd2c3c39679
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93106678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.93106678
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3735076415
Short name T90
Test name
Test status
Simulation time 729318167 ps
CPU time 14.23 seconds
Started Jul 07 05:59:21 PM PDT 24
Finished Jul 07 05:59:35 PM PDT 24
Peak memory 201920 kb
Host smart-bdeb29da-f9cc-446a-910c-1be5378b23fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3735076415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3735076415
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.4261596333
Short name T188
Test name
Test status
Simulation time 359399721406 ps
CPU time 294.34 seconds
Started Jul 07 05:59:19 PM PDT 24
Finished Jul 07 06:04:13 PM PDT 24
Peak memory 203604 kb
Host smart-235ec7f7-8bab-4d13-b367-e17b158e8a61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4261596333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.4261596333
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3936755767
Short name T1
Test name
Test status
Simulation time 48002345 ps
CPU time 1.33 seconds
Started Jul 07 05:59:22 PM PDT 24
Finished Jul 07 05:59:24 PM PDT 24
Peak memory 201964 kb
Host smart-1cbf1bd4-301f-4f9e-a84d-de24233ec238
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3936755767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3936755767
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2435461862
Short name T176
Test name
Test status
Simulation time 798241752 ps
CPU time 13.62 seconds
Started Jul 07 05:59:22 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 201876 kb
Host smart-6fa66a73-915d-4ec0-910d-f5ac31ef4398
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2435461862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2435461862
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.693907819
Short name T517
Test name
Test status
Simulation time 102310748 ps
CPU time 5.33 seconds
Started Jul 07 05:59:19 PM PDT 24
Finished Jul 07 05:59:25 PM PDT 24
Peak memory 201888 kb
Host smart-35cad907-d745-470d-8122-08b19c5bdca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=693907819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.693907819
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1887028245
Short name T534
Test name
Test status
Simulation time 6918224941 ps
CPU time 25.4 seconds
Started Jul 07 05:59:17 PM PDT 24
Finished Jul 07 05:59:42 PM PDT 24
Peak memory 202040 kb
Host smart-f23f465b-fd8a-4315-ba52-6758ca6f184f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887028245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1887028245
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1769281235
Short name T887
Test name
Test status
Simulation time 31362113015 ps
CPU time 73.49 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 06:00:42 PM PDT 24
Peak memory 202080 kb
Host smart-27f7ce00-7642-4ede-afe0-6c2dbfa35010
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1769281235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1769281235
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1293258112
Short name T567
Test name
Test status
Simulation time 283683413 ps
CPU time 7.05 seconds
Started Jul 07 05:59:15 PM PDT 24
Finished Jul 07 05:59:23 PM PDT 24
Peak memory 201884 kb
Host smart-b0ee7286-2710-49cb-98a6-22a4a6f99f04
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293258112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1293258112
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.1935491204
Short name T724
Test name
Test status
Simulation time 1112549970 ps
CPU time 3.9 seconds
Started Jul 07 05:59:21 PM PDT 24
Finished Jul 07 05:59:25 PM PDT 24
Peak memory 201872 kb
Host smart-b99eca88-0cbe-4fa0-8bcb-65a6f896d65e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1935491204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1935491204
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.507147569
Short name T452
Test name
Test status
Simulation time 21923845 ps
CPU time 1.09 seconds
Started Jul 07 05:59:13 PM PDT 24
Finished Jul 07 05:59:14 PM PDT 24
Peak memory 201916 kb
Host smart-ccb40d2b-cc05-4988-a9e3-d75ff115b60d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=507147569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.507147569
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1936046973
Short name T899
Test name
Test status
Simulation time 1836128059 ps
CPU time 8.82 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 05:59:25 PM PDT 24
Peak memory 201888 kb
Host smart-a511fe21-b9d3-4348-97f9-b7e8759361b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936046973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1936046973
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1395800133
Short name T640
Test name
Test status
Simulation time 7776133260 ps
CPU time 8.68 seconds
Started Jul 07 05:59:16 PM PDT 24
Finished Jul 07 05:59:25 PM PDT 24
Peak memory 202004 kb
Host smart-2fe62687-a047-4168-97ec-c34d5fc55172
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1395800133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1395800133
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1163317995
Short name T685
Test name
Test status
Simulation time 9858970 ps
CPU time 1.2 seconds
Started Jul 07 05:59:19 PM PDT 24
Finished Jul 07 05:59:21 PM PDT 24
Peak memory 201912 kb
Host smart-a32c02b2-7db7-4bf3-bccb-835785ab9adb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163317995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1163317995
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1421179201
Short name T74
Test name
Test status
Simulation time 9258853032 ps
CPU time 109.6 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 06:01:13 PM PDT 24
Peak memory 204888 kb
Host smart-3b4d43cc-634f-4f36-9cac-1ee11b68a357
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1421179201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1421179201
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4198337683
Short name T861
Test name
Test status
Simulation time 240172488 ps
CPU time 20.53 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201884 kb
Host smart-2a19fed6-4a59-437b-8abe-c36fe439d214
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4198337683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4198337683
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.91330271
Short name T762
Test name
Test status
Simulation time 1567895916 ps
CPU time 188 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 06:02:37 PM PDT 24
Peak memory 207800 kb
Host smart-44c90866-f9be-4fab-b934-1435298997c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91330271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_
reset.91330271
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1110411953
Short name T819
Test name
Test status
Simulation time 41999291 ps
CPU time 3.07 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201860 kb
Host smart-973d49f3-9329-459f-937c-7065743ce678
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1110411953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1110411953
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2164442347
Short name T65
Test name
Test status
Simulation time 857985225 ps
CPU time 10.9 seconds
Started Jul 07 05:59:20 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201916 kb
Host smart-89ccaa58-62dd-4f1a-8dcc-07e51f2b16df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2164442347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2164442347
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.5174767
Short name T359
Test name
Test status
Simulation time 100530032 ps
CPU time 2.43 seconds
Started Jul 07 05:59:20 PM PDT 24
Finished Jul 07 05:59:22 PM PDT 24
Peak memory 201796 kb
Host smart-639875d2-6b48-4ac9-b305-3291556b398f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5174767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.5174767
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.2665948047
Short name T133
Test name
Test status
Simulation time 838678855 ps
CPU time 8.84 seconds
Started Jul 07 05:59:22 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201928 kb
Host smart-60fc0684-563c-475b-8094-daa03768c49f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2665948047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2665948047
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.4034776987
Short name T56
Test name
Test status
Simulation time 2325166197 ps
CPU time 8.36 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201872 kb
Host smart-06f1a7d5-7728-4b05-b316-bd73fc48352d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4034776987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.4034776987
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2123194812
Short name T370
Test name
Test status
Simulation time 46547979774 ps
CPU time 172.67 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 06:02:15 PM PDT 24
Peak memory 202004 kb
Host smart-cb1d9146-7297-4c3f-8f8b-624ac41bf48a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123194812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2123194812
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.670290489
Short name T584
Test name
Test status
Simulation time 29485177046 ps
CPU time 105.73 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 06:01:14 PM PDT 24
Peak memory 201960 kb
Host smart-66ea2c61-410f-4ea4-be46-098e13bde359
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=670290489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.670290489
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1240273808
Short name T492
Test name
Test status
Simulation time 18447641 ps
CPU time 1.94 seconds
Started Jul 07 05:59:21 PM PDT 24
Finished Jul 07 05:59:23 PM PDT 24
Peak memory 201904 kb
Host smart-08bf8b3e-54c4-4441-aa05-7ebe63ac1e5b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240273808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1240273808
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.221633478
Short name T880
Test name
Test status
Simulation time 453232847 ps
CPU time 6.41 seconds
Started Jul 07 05:59:21 PM PDT 24
Finished Jul 07 05:59:27 PM PDT 24
Peak memory 201932 kb
Host smart-5125a3e1-06f8-4809-b07b-30b6f91c5311
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=221633478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.221633478
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.1592252802
Short name T404
Test name
Test status
Simulation time 13477996 ps
CPU time 1.16 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 201804 kb
Host smart-27cf72c2-793f-402f-af58-e04fd6a30c48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1592252802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1592252802
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3262291628
Short name T57
Test name
Test status
Simulation time 10624383939 ps
CPU time 12.05 seconds
Started Jul 07 05:59:20 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 202036 kb
Host smart-e169ccac-607d-4527-a40d-cc7bc25b5f41
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262291628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3262291628
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2161437820
Short name T706
Test name
Test status
Simulation time 1362491242 ps
CPU time 10.93 seconds
Started Jul 07 05:59:21 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201960 kb
Host smart-198303b7-6b1f-4bff-81ee-e1037d24e513
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2161437820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2161437820
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.943757504
Short name T730
Test name
Test status
Simulation time 14600946 ps
CPU time 1.14 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 201912 kb
Host smart-d10bfd4a-b878-4a43-9da9-7c24c591eb1d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943757504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.943757504
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3988573556
Short name T591
Test name
Test status
Simulation time 660423260 ps
CPU time 13.93 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201920 kb
Host smart-1ed3d521-f035-4e03-ba7f-382c3f9bbb91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3988573556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3988573556
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3393334405
Short name T636
Test name
Test status
Simulation time 28898196171 ps
CPU time 58.83 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 06:00:22 PM PDT 24
Peak memory 202096 kb
Host smart-8a052ef6-e6c8-421b-8e82-6e580c7f8b52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3393334405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3393334405
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3033736782
Short name T360
Test name
Test status
Simulation time 1591613610 ps
CPU time 73.15 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 06:00:40 PM PDT 24
Peak memory 204172 kb
Host smart-2e2f7df7-937b-4c27-80b1-e0d0c2bcb1b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3033736782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.3033736782
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1693420796
Short name T220
Test name
Test status
Simulation time 1198665637 ps
CPU time 144.37 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 06:01:51 PM PDT 24
Peak memory 206684 kb
Host smart-f8c30dee-2589-42cb-a80c-950a7f10c4f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1693420796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.1693420796
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.4249434108
Short name T243
Test name
Test status
Simulation time 445830210 ps
CPU time 9.3 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201924 kb
Host smart-5d61cfd7-e883-418f-bd32-fcbfce0e6c85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4249434108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4249434108
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2697620429
Short name T890
Test name
Test status
Simulation time 80340237 ps
CPU time 1.82 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:29 PM PDT 24
Peak memory 201852 kb
Host smart-04634bf1-35ca-4364-9a93-7e9740c7859f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2697620429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2697620429
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.4272993948
Short name T183
Test name
Test status
Simulation time 46401562485 ps
CPU time 209.32 seconds
Started Jul 07 05:59:22 PM PDT 24
Finished Jul 07 06:02:51 PM PDT 24
Peak memory 203104 kb
Host smart-244b5394-d116-4c86-aaee-d99d33fc44f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4272993948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.4272993948
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1403050423
Short name T634
Test name
Test status
Simulation time 2564941262 ps
CPU time 9.69 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 202000 kb
Host smart-b3eca915-4a8e-4c8e-be37-dd53e1964ef2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1403050423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1403050423
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.1465661805
Short name T570
Test name
Test status
Simulation time 69808926 ps
CPU time 1.98 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201884 kb
Host smart-8fc7ae34-b36f-4611-845d-80a25ee58a7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465661805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1465661805
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.4178056734
Short name T504
Test name
Test status
Simulation time 893265819 ps
CPU time 12.7 seconds
Started Jul 07 05:59:25 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201840 kb
Host smart-f4923775-f63d-4cc7-8666-a8ffe3476303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178056734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.4178056734
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1241127422
Short name T32
Test name
Test status
Simulation time 9734986208 ps
CPU time 44.13 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 06:00:07 PM PDT 24
Peak memory 202044 kb
Host smart-b03cf4a3-0a1c-4c93-9e91-e4c80d75b157
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241127422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1241127422
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4130483073
Short name T753
Test name
Test status
Simulation time 7347296838 ps
CPU time 55.85 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 202040 kb
Host smart-5c284804-62f2-4464-b5f7-db0bd7fb1b41
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4130483073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4130483073
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1152348441
Short name T806
Test name
Test status
Simulation time 59250391 ps
CPU time 7.59 seconds
Started Jul 07 05:59:26 PM PDT 24
Finished Jul 07 05:59:34 PM PDT 24
Peak memory 201820 kb
Host smart-a3b21f7b-607c-4070-8a57-5a273b781f3a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152348441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1152348441
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.3386421109
Short name T75
Test name
Test status
Simulation time 39508520 ps
CPU time 4.02 seconds
Started Jul 07 05:59:26 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201892 kb
Host smart-808421b9-1fbb-47a3-93b8-5d3d432d4cce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3386421109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3386421109
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.2412765594
Short name T69
Test name
Test status
Simulation time 38178467 ps
CPU time 1.49 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:29 PM PDT 24
Peak memory 201904 kb
Host smart-f7bbbdf3-0df9-4705-b2a3-582a034f2a57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2412765594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2412765594
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2386466216
Short name T301
Test name
Test status
Simulation time 2225533197 ps
CPU time 11.36 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:40 PM PDT 24
Peak memory 201960 kb
Host smart-c51c376d-f436-415c-80a7-5a53f482565e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386466216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2386466216
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2296979497
Short name T317
Test name
Test status
Simulation time 1349571790 ps
CPU time 7.08 seconds
Started Jul 07 05:59:23 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 201956 kb
Host smart-fedb11b5-38d3-4a00-adc6-d225185ed6c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2296979497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2296979497
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2997319385
Short name T649
Test name
Test status
Simulation time 11371188 ps
CPU time 1.26 seconds
Started Jul 07 05:59:30 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201900 kb
Host smart-e16c7bc5-333e-48c2-bfa4-80c094ad27eb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997319385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2997319385
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1942514371
Short name T272
Test name
Test status
Simulation time 13354493773 ps
CPU time 121.03 seconds
Started Jul 07 05:59:26 PM PDT 24
Finished Jul 07 06:01:28 PM PDT 24
Peak memory 203060 kb
Host smart-0a1fe5c1-83c0-49cc-9243-0bddf471f30f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1942514371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1942514371
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3396984258
Short name T131
Test name
Test status
Simulation time 4755271775 ps
CPU time 85.92 seconds
Started Jul 07 05:59:22 PM PDT 24
Finished Jul 07 06:00:48 PM PDT 24
Peak memory 204628 kb
Host smart-579bfe44-255a-437a-a0a7-6322e4be9dcd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3396984258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3396984258
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1383251615
Short name T731
Test name
Test status
Simulation time 5348707184 ps
CPU time 127.76 seconds
Started Jul 07 05:59:26 PM PDT 24
Finished Jul 07 06:01:34 PM PDT 24
Peak memory 205976 kb
Host smart-8c206802-72d8-46df-9e96-fc4ce52d642e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1383251615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1383251615
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1718455791
Short name T878
Test name
Test status
Simulation time 2772804356 ps
CPU time 46.12 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 204028 kb
Host smart-9f27b262-6cbf-41e3-a488-e594003486bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1718455791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.1718455791
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3257814444
Short name T339
Test name
Test status
Simulation time 62836684 ps
CPU time 5.09 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:34 PM PDT 24
Peak memory 201896 kb
Host smart-b8cc2d6f-9143-4d46-8832-db4d15a40152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3257814444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3257814444
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3953969489
Short name T239
Test name
Test status
Simulation time 177919058 ps
CPU time 8.35 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:56:43 PM PDT 24
Peak memory 201916 kb
Host smart-ddb4f1c7-b025-4dd0-a549-261ef2de5463
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3953969489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3953969489
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4069186575
Short name T826
Test name
Test status
Simulation time 69272841 ps
CPU time 4.88 seconds
Started Jul 07 05:56:43 PM PDT 24
Finished Jul 07 05:56:48 PM PDT 24
Peak memory 201948 kb
Host smart-95166644-7d55-4432-be99-f8c05cd76d4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4069186575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4069186575
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.3801682
Short name T295
Test name
Test status
Simulation time 772142020 ps
CPU time 13.88 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:57:03 PM PDT 24
Peak memory 201920 kb
Host smart-d25ff0ae-3c89-40a5-9776-32ba93ce4562
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3801682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3801682
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.1928317339
Short name T848
Test name
Test status
Simulation time 239442086 ps
CPU time 5.09 seconds
Started Jul 07 05:56:40 PM PDT 24
Finished Jul 07 05:56:46 PM PDT 24
Peak memory 201908 kb
Host smart-e0251ab6-0025-4fb9-ba0f-ccc5d803a749
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1928317339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1928317339
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.3330729766
Short name T256
Test name
Test status
Simulation time 35361330198 ps
CPU time 108.02 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:58:24 PM PDT 24
Peak memory 202012 kb
Host smart-e01d05b5-d00f-4f28-abe1-4480205477f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330729766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3330729766
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.789852270
Short name T531
Test name
Test status
Simulation time 8846668293 ps
CPU time 36.22 seconds
Started Jul 07 05:56:36 PM PDT 24
Finished Jul 07 05:57:13 PM PDT 24
Peak memory 202000 kb
Host smart-f0e56c61-e9b0-4c9f-8575-ae1c88e05ff8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=789852270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.789852270
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.347470514
Short name T852
Test name
Test status
Simulation time 25507725 ps
CPU time 4.4 seconds
Started Jul 07 05:57:02 PM PDT 24
Finished Jul 07 05:57:06 PM PDT 24
Peak memory 201904 kb
Host smart-854eec18-1b02-4394-bb93-36b74c236c52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347470514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.347470514
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.3378953200
Short name T681
Test name
Test status
Simulation time 2428390635 ps
CPU time 8.4 seconds
Started Jul 07 05:56:41 PM PDT 24
Finished Jul 07 05:56:49 PM PDT 24
Peak memory 201976 kb
Host smart-73311445-4224-4286-a038-c7f512fd899f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3378953200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3378953200
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.3253901416
Short name T350
Test name
Test status
Simulation time 8597409 ps
CPU time 1.11 seconds
Started Jul 07 05:56:38 PM PDT 24
Finished Jul 07 05:56:40 PM PDT 24
Peak memory 201912 kb
Host smart-71d3de72-10fb-4b05-8299-910e25219152
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3253901416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3253901416
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1070747399
Short name T134
Test name
Test status
Simulation time 4533693905 ps
CPU time 9.58 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:56:45 PM PDT 24
Peak memory 202024 kb
Host smart-fef8dad0-d817-4373-8ef4-71f24fe2eef4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070747399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1070747399
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3203696388
Short name T400
Test name
Test status
Simulation time 1219617091 ps
CPU time 4.77 seconds
Started Jul 07 05:56:35 PM PDT 24
Finished Jul 07 05:56:40 PM PDT 24
Peak memory 201932 kb
Host smart-defb4ad5-3e86-472e-9638-f0375fa93a2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3203696388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3203696388
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3680691421
Short name T92
Test name
Test status
Simulation time 9268232 ps
CPU time 1.14 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:41 PM PDT 24
Peak memory 201884 kb
Host smart-a758b393-f448-4f82-b4f7-d2ce7c97dcf7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680691421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3680691421
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1472761869
Short name T482
Test name
Test status
Simulation time 315313536 ps
CPU time 39.05 seconds
Started Jul 07 05:56:40 PM PDT 24
Finished Jul 07 05:57:20 PM PDT 24
Peak memory 201900 kb
Host smart-45d35767-403c-409d-bc33-d2e2a2c51a58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1472761869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1472761869
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2921770711
Short name T830
Test name
Test status
Simulation time 5748084110 ps
CPU time 25.75 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:57:14 PM PDT 24
Peak memory 202056 kb
Host smart-c181bcd1-6004-488c-b84c-dd16c28fcc47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2921770711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2921770711
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2220156497
Short name T427
Test name
Test status
Simulation time 45218917 ps
CPU time 15.29 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:55 PM PDT 24
Peak memory 202976 kb
Host smart-5eabb23a-088d-4ac1-83bc-3bb91dc918a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2220156497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.2220156497
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3396366306
Short name T372
Test name
Test status
Simulation time 304071856 ps
CPU time 6.92 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:47 PM PDT 24
Peak memory 201896 kb
Host smart-5514452f-3e05-4348-a178-51b2165ea38f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3396366306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3396366306
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.783669936
Short name T247
Test name
Test status
Simulation time 11990842 ps
CPU time 2.13 seconds
Started Jul 07 05:56:43 PM PDT 24
Finished Jul 07 05:56:46 PM PDT 24
Peak memory 201924 kb
Host smart-3933cb7c-308b-4159-8e6e-4f95d5811675
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=783669936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.783669936
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2898652866
Short name T575
Test name
Test status
Simulation time 14654806328 ps
CPU time 48.91 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:57:38 PM PDT 24
Peak memory 203116 kb
Host smart-86683214-5cde-4738-b1d4-5304a2b86be2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2898652866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.2898652866
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3111123174
Short name T703
Test name
Test status
Simulation time 680000520 ps
CPU time 9.94 seconds
Started Jul 07 05:56:41 PM PDT 24
Finished Jul 07 05:56:51 PM PDT 24
Peak memory 201892 kb
Host smart-ea27f2e8-3bbb-49f2-8df9-35bb13ba0a70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3111123174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3111123174
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.1362172043
Short name T542
Test name
Test status
Simulation time 142281803 ps
CPU time 5.2 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:56:53 PM PDT 24
Peak memory 201924 kb
Host smart-70fe15bb-8ab2-4823-a232-73e3d7c66430
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1362172043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1362172043
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.912620888
Short name T254
Test name
Test status
Simulation time 114507520 ps
CPU time 9.32 seconds
Started Jul 07 05:56:40 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201892 kb
Host smart-541af9ec-7bc5-413e-8046-3d7ba805fc6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912620888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.912620888
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1871854798
Short name T31
Test name
Test status
Simulation time 14113299333 ps
CPU time 59.27 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 202052 kb
Host smart-46b0b002-7550-43a1-a472-59797c36f381
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871854798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1871854798
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2675513401
Short name T573
Test name
Test status
Simulation time 6991266621 ps
CPU time 40.63 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:57:21 PM PDT 24
Peak memory 202080 kb
Host smart-12690010-6fb3-4a8a-86f4-5e0669844127
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2675513401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2675513401
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3055049933
Short name T426
Test name
Test status
Simulation time 21542799 ps
CPU time 2.48 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:49 PM PDT 24
Peak memory 201948 kb
Host smart-83d6503f-be7d-46e6-8201-8402846556a9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055049933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3055049933
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.3025357519
Short name T509
Test name
Test status
Simulation time 11701616 ps
CPU time 1.35 seconds
Started Jul 07 05:56:42 PM PDT 24
Finished Jul 07 05:56:44 PM PDT 24
Peak memory 201920 kb
Host smart-21b965a7-60a6-4b72-b405-32057c01f699
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3025357519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3025357519
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.2699290967
Short name T532
Test name
Test status
Simulation time 31391416 ps
CPU time 1.38 seconds
Started Jul 07 05:56:39 PM PDT 24
Finished Jul 07 05:56:42 PM PDT 24
Peak memory 201796 kb
Host smart-77b2e9e6-9fde-482b-9219-88fa43fbe7fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2699290967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2699290967
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3212528711
Short name T776
Test name
Test status
Simulation time 3320681915 ps
CPU time 8.2 seconds
Started Jul 07 05:56:45 PM PDT 24
Finished Jul 07 05:56:53 PM PDT 24
Peak memory 201960 kb
Host smart-28466f7f-bede-4ab2-964b-91f33f702240
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212528711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3212528711
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.591871883
Short name T321
Test name
Test status
Simulation time 741096602 ps
CPU time 4.53 seconds
Started Jul 07 05:56:43 PM PDT 24
Finished Jul 07 05:56:47 PM PDT 24
Peak memory 201888 kb
Host smart-9da20881-2376-4fa9-8014-ae86f322adc6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=591871883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.591871883
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.134659388
Short name T624
Test name
Test status
Simulation time 11312942 ps
CPU time 1.12 seconds
Started Jul 07 05:56:38 PM PDT 24
Finished Jul 07 05:56:40 PM PDT 24
Peak memory 201948 kb
Host smart-43b80e0b-4f84-4239-88e0-436537cd41ef
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134659388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.134659388
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2193048946
Short name T877
Test name
Test status
Simulation time 10787634386 ps
CPU time 67.21 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:57:54 PM PDT 24
Peak memory 202992 kb
Host smart-b1815275-4c39-4afc-8d8f-fc78d9b7d488
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193048946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2193048946
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3180523446
Short name T702
Test name
Test status
Simulation time 127430333 ps
CPU time 9.47 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:56 PM PDT 24
Peak memory 201924 kb
Host smart-b844052b-4ea6-4558-99a1-4a01acdb0fa4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3180523446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3180523446
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3326369998
Short name T779
Test name
Test status
Simulation time 3545157655 ps
CPU time 104.62 seconds
Started Jul 07 05:56:48 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 204540 kb
Host smart-23f0322c-edcc-4638-b234-9eb374b47f0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3326369998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.3326369998
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2778167504
Short name T839
Test name
Test status
Simulation time 199050003 ps
CPU time 16.46 seconds
Started Jul 07 05:56:45 PM PDT 24
Finished Jul 07 05:57:02 PM PDT 24
Peak memory 201940 kb
Host smart-13a903e7-969a-4331-9a4d-2dd15059ec74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2778167504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.2778167504
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.715989283
Short name T845
Test name
Test status
Simulation time 255035636 ps
CPU time 4.32 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:56:52 PM PDT 24
Peak memory 201936 kb
Host smart-8bb2fa80-e64b-445b-9044-ba11f174a86c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=715989283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.715989283
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1197652341
Short name T323
Test name
Test status
Simulation time 56698109 ps
CPU time 4.44 seconds
Started Jul 07 05:56:48 PM PDT 24
Finished Jul 07 05:56:53 PM PDT 24
Peak memory 201828 kb
Host smart-0533f39d-1842-4e4c-9073-4d1accb77295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1197652341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1197652341
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1551867832
Short name T97
Test name
Test status
Simulation time 56695732868 ps
CPU time 144.25 seconds
Started Jul 07 05:56:42 PM PDT 24
Finished Jul 07 05:59:07 PM PDT 24
Peak memory 202096 kb
Host smart-987b3e07-d0df-4022-921c-506ac363beb1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1551867832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.1551867832
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2784508821
Short name T309
Test name
Test status
Simulation time 42912445 ps
CPU time 4.1 seconds
Started Jul 07 05:56:48 PM PDT 24
Finished Jul 07 05:56:52 PM PDT 24
Peak memory 201992 kb
Host smart-868ed802-b489-401b-a57a-7c786d24ba4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2784508821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2784508821
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3967373803
Short name T522
Test name
Test status
Simulation time 858715608 ps
CPU time 3.04 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:56:52 PM PDT 24
Peak memory 201908 kb
Host smart-a7f25d47-a841-4698-a3ec-95d0577ba43c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3967373803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3967373803
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.3346280201
Short name T508
Test name
Test status
Simulation time 17506196 ps
CPU time 2.59 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201896 kb
Host smart-86955fa5-2762-46d9-a01e-3c8b9cc11c8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3346280201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3346280201
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3312314882
Short name T501
Test name
Test status
Simulation time 32098822530 ps
CPU time 22.94 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:57:10 PM PDT 24
Peak memory 201952 kb
Host smart-ea455075-41bd-42b7-a8de-fcd12fd27704
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312314882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3312314882
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4167138494
Short name T335
Test name
Test status
Simulation time 11128426299 ps
CPU time 24.52 seconds
Started Jul 07 05:56:45 PM PDT 24
Finished Jul 07 05:57:10 PM PDT 24
Peak memory 202076 kb
Host smart-eebd274f-f0a1-4559-b018-857b00d7b6f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4167138494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4167138494
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2249124920
Short name T53
Test name
Test status
Simulation time 78657641 ps
CPU time 7.68 seconds
Started Jul 07 05:56:42 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201876 kb
Host smart-5cca253f-4dd8-4317-80a8-0752cb5910bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249124920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2249124920
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2542339820
Short name T841
Test name
Test status
Simulation time 1485645782 ps
CPU time 9.79 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:56 PM PDT 24
Peak memory 201916 kb
Host smart-a7ac9441-2153-4cf4-b468-df006417cfc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2542339820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2542339820
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.2570994915
Short name T261
Test name
Test status
Simulation time 8371941 ps
CPU time 1.19 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:56:49 PM PDT 24
Peak memory 201900 kb
Host smart-f6f0e97f-1737-4e96-a21f-223e30487fed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2570994915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2570994915
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.930644892
Short name T607
Test name
Test status
Simulation time 2320991609 ps
CPU time 8.98 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:56 PM PDT 24
Peak memory 201960 kb
Host smart-a26bb3b2-86bc-4d5b-8224-ba7a79638d8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=930644892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.930644892
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.242021931
Short name T293
Test name
Test status
Simulation time 4649219909 ps
CPU time 8.79 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:55 PM PDT 24
Peak memory 202068 kb
Host smart-63f5fcb7-b0b7-4e44-8411-8540e5b85246
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=242021931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.242021931
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3006932947
Short name T344
Test name
Test status
Simulation time 10078197 ps
CPU time 1.28 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:48 PM PDT 24
Peak memory 201868 kb
Host smart-08be6d28-dd44-492d-902c-53e628803029
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006932947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3006932947
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2400849258
Short name T81
Test name
Test status
Simulation time 6348460816 ps
CPU time 83.57 seconds
Started Jul 07 05:56:48 PM PDT 24
Finished Jul 07 05:58:12 PM PDT 24
Peak memory 203000 kb
Host smart-ce570272-58da-49a0-82d4-4d2c3e24989d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2400849258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2400849258
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1554673349
Short name T353
Test name
Test status
Simulation time 367555899 ps
CPU time 30.4 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:57:18 PM PDT 24
Peak memory 201956 kb
Host smart-a090f254-65b7-4554-88db-39cb8d9024fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1554673349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1554673349
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2822002627
Short name T716
Test name
Test status
Simulation time 507473120 ps
CPU time 77.3 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:58:07 PM PDT 24
Peak memory 204588 kb
Host smart-7163e7bc-db78-4140-b8e4-0e6e77a15c4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2822002627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.2822002627
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.494031503
Short name T168
Test name
Test status
Simulation time 7710490268 ps
CPU time 105.1 seconds
Started Jul 07 05:56:48 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 204616 kb
Host smart-c249a9b8-a4b0-4593-a886-81715fc5135d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=494031503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese
t_error.494031503
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.4081469959
Short name T639
Test name
Test status
Simulation time 319843262 ps
CPU time 4.54 seconds
Started Jul 07 05:56:45 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201888 kb
Host smart-1bff7e2a-75d8-478b-b8cf-ee39e2428d45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4081469959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4081469959
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.57844228
Short name T237
Test name
Test status
Simulation time 69531637 ps
CPU time 10 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:56:59 PM PDT 24
Peak memory 201920 kb
Host smart-cf244053-eed7-4133-b314-70febde0212c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57844228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.57844228
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2070921733
Short name T190
Test name
Test status
Simulation time 38277694676 ps
CPU time 173.04 seconds
Started Jul 07 05:56:45 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 203028 kb
Host smart-2ed146e1-97cc-4342-97c7-236520ac8288
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2070921733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.2070921733
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2138154084
Short name T755
Test name
Test status
Simulation time 67170648 ps
CPU time 3.11 seconds
Started Jul 07 05:56:50 PM PDT 24
Finished Jul 07 05:56:53 PM PDT 24
Peak memory 202252 kb
Host smart-de07ae8e-216b-4fb5-99d6-7d807180feb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2138154084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2138154084
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.1501752392
Short name T152
Test name
Test status
Simulation time 310628356 ps
CPU time 2.21 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:56:51 PM PDT 24
Peak memory 201940 kb
Host smart-faa44d0d-97af-4543-bd2e-f6ea068a9dbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1501752392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1501752392
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.301569552
Short name T23
Test name
Test status
Simulation time 108225867 ps
CPU time 6.37 seconds
Started Jul 07 05:56:50 PM PDT 24
Finished Jul 07 05:56:56 PM PDT 24
Peak memory 201900 kb
Host smart-a9392aca-2d40-4080-93d9-15cfba565237
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=301569552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.301569552
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.516252340
Short name T137
Test name
Test status
Simulation time 39396020830 ps
CPU time 138.8 seconds
Started Jul 07 05:56:48 PM PDT 24
Finished Jul 07 05:59:07 PM PDT 24
Peak memory 202032 kb
Host smart-0729fa1a-2ba2-46e2-9896-c988df36c8f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=516252340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.516252340
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.170571428
Short name T551
Test name
Test status
Simulation time 71647388118 ps
CPU time 136.72 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:59:06 PM PDT 24
Peak memory 201984 kb
Host smart-c3d28283-7370-439a-a37c-5e1abe15f473
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=170571428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.170571428
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.905462596
Short name T629
Test name
Test status
Simulation time 8553575 ps
CPU time 1.04 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:56:54 PM PDT 24
Peak memory 201884 kb
Host smart-b10596c8-404a-4c7d-90a9-873def033882
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905462596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.905462596
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2180632904
Short name T741
Test name
Test status
Simulation time 27564107 ps
CPU time 1.8 seconds
Started Jul 07 05:56:52 PM PDT 24
Finished Jul 07 05:56:54 PM PDT 24
Peak memory 201920 kb
Host smart-d6604c8b-8efa-42e4-a67b-faae25e4c145
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2180632904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2180632904
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.1488759817
Short name T812
Test name
Test status
Simulation time 9491780 ps
CPU time 1.26 seconds
Started Jul 07 05:56:49 PM PDT 24
Finished Jul 07 05:56:50 PM PDT 24
Peak memory 201888 kb
Host smart-68d654da-c568-47ff-ac20-d1f5fef0643f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1488759817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1488759817
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3649866166
Short name T234
Test name
Test status
Simulation time 15585621590 ps
CPU time 11.06 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:58 PM PDT 24
Peak memory 201896 kb
Host smart-1a25644d-26c9-4ad4-8361-fee7c2e50b52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649866166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3649866166
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.377984306
Short name T36
Test name
Test status
Simulation time 1347781345 ps
CPU time 9.06 seconds
Started Jul 07 05:56:47 PM PDT 24
Finished Jul 07 05:56:56 PM PDT 24
Peak memory 201832 kb
Host smart-2ff294b4-6c86-4a69-a99d-579fd09d894e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=377984306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.377984306
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2937989452
Short name T550
Test name
Test status
Simulation time 14302975 ps
CPU time 1.3 seconds
Started Jul 07 05:56:46 PM PDT 24
Finished Jul 07 05:56:48 PM PDT 24
Peak memory 201908 kb
Host smart-764c0ed3-f936-4c50-8289-491377428ad5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937989452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2937989452
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.2193365520
Short name T382
Test name
Test status
Simulation time 2364386762 ps
CPU time 39.45 seconds
Started Jul 07 05:56:51 PM PDT 24
Finished Jul 07 05:57:31 PM PDT 24
Peak memory 203028 kb
Host smart-c7df9ac1-68d2-4ab9-b7ee-4c27ad857989
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193365520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2193365520
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1427825220
Short name T571
Test name
Test status
Simulation time 932078895 ps
CPU time 17.67 seconds
Started Jul 07 05:56:50 PM PDT 24
Finished Jul 07 05:57:08 PM PDT 24
Peak memory 201896 kb
Host smart-fcafbcb0-9866-452b-b37c-36943f96f66d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1427825220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1427825220
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3145514358
Short name T823
Test name
Test status
Simulation time 12158703457 ps
CPU time 95.03 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 204676 kb
Host smart-be310a3f-d2e7-4704-9124-38fc7564d409
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3145514358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.3145514358
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2903174727
Short name T669
Test name
Test status
Simulation time 763147973 ps
CPU time 74.93 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 05:58:10 PM PDT 24
Peak memory 205088 kb
Host smart-6fd7f68a-4f7e-4638-b5de-fc420ef4ed6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2903174727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.2903174727
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1985330340
Short name T418
Test name
Test status
Simulation time 104430880 ps
CPU time 3.03 seconds
Started Jul 07 05:56:45 PM PDT 24
Finished Jul 07 05:56:49 PM PDT 24
Peak memory 201920 kb
Host smart-5245f136-cfa8-46cc-bd85-b60074f66e5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1985330340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1985330340
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.640572261
Short name T449
Test name
Test status
Simulation time 388923880 ps
CPU time 7.5 seconds
Started Jul 07 05:56:51 PM PDT 24
Finished Jul 07 05:56:58 PM PDT 24
Peak memory 201928 kb
Host smart-a1611ca3-70d1-4f09-b048-792cf235647c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=640572261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.640572261
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3793493860
Short name T854
Test name
Test status
Simulation time 53756191703 ps
CPU time 231.36 seconds
Started Jul 07 05:56:50 PM PDT 24
Finished Jul 07 06:00:41 PM PDT 24
Peak memory 203100 kb
Host smart-4407bade-f84e-4f8b-be96-cfb1da09a760
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3793493860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.3793493860
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1680866023
Short name T827
Test name
Test status
Simulation time 46747547 ps
CPU time 3.2 seconds
Started Jul 07 05:56:53 PM PDT 24
Finished Jul 07 05:56:57 PM PDT 24
Peak memory 201944 kb
Host smart-2b30b6bb-c0b9-43bf-85ba-d22a3a38d6ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1680866023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1680866023
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2492781082
Short name T597
Test name
Test status
Simulation time 141449992 ps
CPU time 7.12 seconds
Started Jul 07 05:56:52 PM PDT 24
Finished Jul 07 05:56:59 PM PDT 24
Peak memory 201812 kb
Host smart-cc2cc5c3-c398-429a-8825-1f02ede100ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2492781082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2492781082
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.3477636215
Short name T47
Test name
Test status
Simulation time 41224339 ps
CPU time 3.84 seconds
Started Jul 07 05:56:55 PM PDT 24
Finished Jul 07 05:56:59 PM PDT 24
Peak memory 201888 kb
Host smart-d2054311-2095-4ac4-8ad9-1e78af2769bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3477636215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3477636215
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2944358343
Short name T884
Test name
Test status
Simulation time 45311110639 ps
CPU time 96.57 seconds
Started Jul 07 05:56:51 PM PDT 24
Finished Jul 07 05:58:28 PM PDT 24
Peak memory 202044 kb
Host smart-735e9d3d-4c5b-4977-bf40-656f2753a26a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944358343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2944358343
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2420269264
Short name T536
Test name
Test status
Simulation time 31098525079 ps
CPU time 130.34 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 05:59:05 PM PDT 24
Peak memory 202044 kb
Host smart-2fbf36a0-7807-4c75-9fc9-6aa95fdb0f4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2420269264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2420269264
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3493121832
Short name T467
Test name
Test status
Simulation time 88948521 ps
CPU time 6.7 seconds
Started Jul 07 05:56:51 PM PDT 24
Finished Jul 07 05:56:58 PM PDT 24
Peak memory 201908 kb
Host smart-8a442863-3dca-4ff2-ba3a-90bb44b4b359
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493121832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3493121832
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.367816045
Short name T758
Test name
Test status
Simulation time 34321574 ps
CPU time 3.35 seconds
Started Jul 07 05:56:51 PM PDT 24
Finished Jul 07 05:56:55 PM PDT 24
Peak memory 201804 kb
Host smart-52c01a4a-f42c-4053-bcd9-d811869a575b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=367816045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.367816045
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.1267513135
Short name T756
Test name
Test status
Simulation time 90467514 ps
CPU time 1.86 seconds
Started Jul 07 05:56:50 PM PDT 24
Finished Jul 07 05:56:52 PM PDT 24
Peak memory 201896 kb
Host smart-6f38130a-be95-4ca4-aa99-4463c6eda5f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1267513135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1267513135
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.898997492
Short name T538
Test name
Test status
Simulation time 3055656159 ps
CPU time 10.5 seconds
Started Jul 07 05:56:55 PM PDT 24
Finished Jul 07 05:57:06 PM PDT 24
Peak memory 201924 kb
Host smart-cfb3cf67-4601-4670-900c-442c4247fbd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=898997492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.898997492
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2974722790
Short name T385
Test name
Test status
Simulation time 4717333265 ps
CPU time 7.63 seconds
Started Jul 07 05:56:50 PM PDT 24
Finished Jul 07 05:56:58 PM PDT 24
Peak memory 201892 kb
Host smart-8c0243ad-4633-429b-b289-9839a0b521ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2974722790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2974722790
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3003647740
Short name T483
Test name
Test status
Simulation time 15086194 ps
CPU time 1.18 seconds
Started Jul 07 05:56:52 PM PDT 24
Finished Jul 07 05:56:54 PM PDT 24
Peak memory 201904 kb
Host smart-9509100f-79b9-4ba3-b56b-481d140038ba
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003647740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3003647740
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2276781783
Short name T547
Test name
Test status
Simulation time 34350374448 ps
CPU time 122.98 seconds
Started Jul 07 05:56:54 PM PDT 24
Finished Jul 07 05:58:57 PM PDT 24
Peak memory 204352 kb
Host smart-bf96a983-4f96-4ae2-b3a9-91d27e29c9fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2276781783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2276781783
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4199846917
Short name T611
Test name
Test status
Simulation time 9761712717 ps
CPU time 77.68 seconds
Started Jul 07 05:56:58 PM PDT 24
Finished Jul 07 05:58:16 PM PDT 24
Peak memory 203444 kb
Host smart-137ac2e5-3455-4e5b-b9c1-fd02a2ad04c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4199846917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4199846917
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3406262761
Short name T378
Test name
Test status
Simulation time 170373309 ps
CPU time 36.83 seconds
Started Jul 07 05:56:56 PM PDT 24
Finished Jul 07 05:57:33 PM PDT 24
Peak memory 204064 kb
Host smart-87749bc7-21c3-44e9-96d1-c9a99040b2b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3406262761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.3406262761
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2351371129
Short name T656
Test name
Test status
Simulation time 205996047 ps
CPU time 34.93 seconds
Started Jul 07 05:56:52 PM PDT 24
Finished Jul 07 05:57:27 PM PDT 24
Peak memory 203988 kb
Host smart-9871f753-f1c5-44cc-baed-42b6c37b5f2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2351371129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2351371129
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.239990655
Short name T460
Test name
Test status
Simulation time 38491508 ps
CPU time 2.28 seconds
Started Jul 07 05:56:58 PM PDT 24
Finished Jul 07 05:57:01 PM PDT 24
Peak memory 201924 kb
Host smart-63aa2962-e351-4207-ac3e-40e87fe75002
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=239990655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.239990655
Directory /workspace/9.xbar_unmapped_addr/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%