Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	400	1			T15	3		T23	2		T116	1
all_values[1]	427	1			T17	1		T15	4		T113	1
all_values[2]	451	1			T16	1		T17	1		T15	5
all_values[3]	450	1			T15	7		T23	4		T116	1
all_values[4]	418	1			T17	2		T15	3		T23	3
all_values[5]	450	1			T15	12		T113	1		T23	1
all_values[6]	432	1			T15	6		T23	3		T116	1
all_values[7]	406	1			T15	5		T23	3		T225	1
all_values[8]	424	1			T15	10		T23	4		T40	1
all_values[9]	430	1			T16	1		T15	5		T113	1
all_values[10]	434	1			T15	5		T113	3		T23	4
all_values[11]	442	1			T15	3		T23	5		T116	1
all_values[12]	431	1			T16	2		T15	7		T23	4
all_values[13]	450	1			T15	6		T23	4		T42	1
all_values[14]	437	1			T17	1		T15	12		T23	6
all_values[15]	417	1			T16	1		T17	1		T15	6
all_values[16]	464	1			T17	1		T15	9		T113	1
all_values[17]	446	1			T16	2		T17	1		T15	7
all_values[18]	414	1			T15	5		T113	3		T23	3
all_values[19]	451	1			T15	6		T23	3		T116	2
all_values[20]	433	1			T15	9		T23	2		T116	3
all_values[21]	435	1			T16	1		T15	3		T113	1
all_values[22]	416	1			T15	8		T113	1		T23	2
all_values[23]	424	1			T16	1		T17	1		T15	3
all_values[24]	436	1			T15	3		T23	4		T116	1
all_values[25]	422	1			T16	1		T15	7		T113	1
all_values[26]	400	1			T15	7		T23	3		T225	1