Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	464	1			T4	1		T16	2		T35	5
all_values[1]	448	1			T4	1		T16	1		T35	8
all_values[2]	472	1			T2	1		T4	1		T15	1
all_values[3]	459	1			T4	3		T15	1		T16	1
all_values[4]	458	1			T2	1		T16	3		T35	5
all_values[5]	470	1			T4	2		T35	7		T23	1
all_values[6]	467	1			T15	1		T35	10		T23	1
all_values[7]	478	1			T4	1		T16	1		T35	12
all_values[8]	440	1			T16	1		T35	13		T23	1
all_values[9]	437	1			T15	2		T16	1		T35	3
all_values[10]	462	1			T2	1		T4	2		T15	1
all_values[11]	476	1			T4	1		T35	9		T26	1
all_values[12]	455	1			T35	5		T23	1		T26	1
all_values[13]	471	1			T4	2		T35	4		T26	3
all_values[14]	517	1			T2	1		T4	2		T35	7
all_values[15]	436	1			T2	2		T35	11		T34	2
all_values[16]	458	1			T15	2		T16	1		T35	6
all_values[17]	418	1			T16	1		T35	3		T23	2
all_values[18]	504	1			T2	1		T35	14		T23	3
all_values[19]	487	1			T15	1		T16	1		T35	10
all_values[20]	439	1			T2	1		T16	2		T35	9
all_values[21]	497	1			T4	1		T16	1		T35	8
all_values[22]	476	1			T4	1		T16	1		T35	14
all_values[23]	467	1			T35	9		T23	1		T34	1
all_values[24]	443	1			T16	1		T35	8		T71	2
all_values[25]	487	1			T4	2		T16	2		T35	8
all_values[26]	478	1			T2	1		T4	1		T35	16