Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 412 1 T21 4 T20 1 T35 13
all_values[1] 447 1 T2 1 T13 1 T21 2
all_values[2] 457 1 T4 1 T13 1 T21 5
all_values[3] 403 1 T21 5 T20 4 T35 6
all_values[4] 454 1 T4 1 T13 2 T21 2
all_values[5] 396 1 T2 1 T4 1 T13 2
all_values[6] 450 1 T13 2 T21 1 T20 2
all_values[7] 440 1 T4 1 T13 1 T21 5
all_values[8] 395 1 T4 1 T13 3 T21 6
all_values[9] 404 1 T2 1 T4 1 T13 2
all_values[10] 459 1 T2 1 T4 1 T13 2
all_values[11] 412 1 T13 1 T21 3 T20 1
all_values[12] 421 1 T13 1 T21 2 T20 3
all_values[13] 414 1 T2 3 T4 1 T13 2
all_values[14] 464 1 T13 2 T21 4 T20 4
all_values[15] 417 1 T2 2 T4 2 T21 1
all_values[16] 420 1 T2 1 T13 2 T21 5
all_values[17] 430 1 T4 1 T13 4 T21 4
all_values[18] 462 1 T2 1 T4 2 T21 2
all_values[19] 452 1 T2 1 T4 1 T13 1
all_values[20] 402 1 T13 2 T21 4 T20 5
all_values[21] 401 1 T2 1 T13 3 T21 4
all_values[22] 396 1 T4 1 T13 4 T21 3
all_values[23] 416 1 T13 1 T21 3 T35 9
all_values[24] 436 1 T13 2 T21 5 T20 2
all_values[25] 412 1 T4 2 T13 2 T21 2
all_values[26] 386 1 T2 1 T13 2 T21 2

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