Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	482	1			T3	1		T18	1		T53	1
all_values[1]	498	1			T3	5		T4	2		T17	2
all_values[2]	500	1			T3	2		T17	1		T53	1
all_values[3]	492	1			T3	6		T4	1		T22	1
all_values[4]	470	1			T3	3		T4	2		T17	3
all_values[5]	494	1			T3	3		T17	2		T18	1
all_values[6]	450	1			T3	6		T4	1		T17	5
all_values[7]	467	1			T3	1		T4	1		T17	2
all_values[8]	452	1			T3	1		T4	4		T17	2
all_values[9]	490	1			T3	4		T4	1		T53	1
all_values[10]	508	1			T3	2		T4	1		T17	3
all_values[11]	485	1			T3	1		T4	1		T22	1
all_values[12]	464	1			T3	1		T17	2		T18	1
all_values[13]	474	1			T3	5		T4	2		T17	2
all_values[14]	478	1			T3	1		T4	2		T17	3
all_values[15]	456	1			T3	2		T4	2		T17	2
all_values[16]	501	1			T3	2		T4	1		T17	3
all_values[17]	471	1			T3	2		T4	2		T17	3
all_values[18]	488	1			T3	1		T4	1		T17	2
all_values[19]	510	1			T3	1		T4	2		T17	2
all_values[20]	450	1			T3	3		T4	1		T17	4
all_values[21]	487	1			T3	2		T4	1		T17	2
all_values[22]	449	1			T3	4		T4	3		T17	1
all_values[23]	503	1			T3	1		T4	2		T17	3
all_values[24]	510	1			T3	2		T4	1		T17	2
all_values[25]	546	1			T3	2		T4	1		T17	2
all_values[26]	492	1			T3	2		T4	2		T17	2