Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	497	1			T46	6		T47	4		T56	1
all_values[1]	517	1			T12	2		T46	5		T47	3
all_values[2]	481	1			T46	5		T56	1		T40	1
all_values[3]	499	1			T14	1		T19	1		T46	2
all_values[4]	446	1			T12	1		T46	5		T47	1
all_values[5]	500	1			T14	1		T46	4		T47	2
all_values[6]	504	1			T46	3		T47	4		T56	1
all_values[7]	501	1			T14	1		T46	2		T47	5
all_values[8]	484	1			T46	4		T47	3		T56	1
all_values[9]	506	1			T46	1		T47	1		T36	1
all_values[10]	479	1			T14	2		T46	3		T47	4
all_values[11]	496	1			T46	9		T47	2		T56	1
all_values[12]	464	1			T46	4		T56	1		T5	4
all_values[13]	493	1			T19	1		T46	2		T47	3
all_values[14]	502	1			T46	6		T47	1		T56	1
all_values[15]	459	1			T46	2		T47	3		T171	1
all_values[16]	465	1			T46	4		T47	3		T56	1
all_values[17]	492	1			T14	1		T12	1		T46	4
all_values[18]	479	1			T46	2		T47	3		T56	1
all_values[19]	490	1			T14	1		T12	1		T46	2
all_values[20]	491	1			T14	1		T46	4		T47	5
all_values[21]	502	1			T19	1		T46	3		T47	2
all_values[22]	465	1			T46	2		T47	3		T56	1
all_values[23]	479	1			T19	1		T46	3		T47	2
all_values[24]	450	1			T14	1		T46	3		T47	4
all_values[25]	449	1			T12	1		T46	4		T47	2
all_values[26]	529	1			T46	1		T47	5		T56	1