Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	378	1			T3	2		T15	1		T16	1
all_values[1]	339	1			T3	5		T15	1		T16	1
all_values[2]	431	1			T3	4		T15	2		T16	1
all_values[3]	336	1			T3	4		T242	2		T274	3
all_values[4]	372	1			T3	1		T15	2		T9	2
all_values[5]	367	1			T3	2		T16	1		T9	1
all_values[6]	395	1			T3	8		T274	4		T240	1
all_values[7]	385	1			T3	1		T15	1		T9	3
all_values[8]	375	1			T3	4		T9	1		T240	1
all_values[9]	361	1			T3	4		T15	1		T242	3
all_values[10]	376	1			T3	3		T274	3		T212	1
all_values[11]	394	1			T3	5		T242	2		T274	2
all_values[12]	386	1			T3	6		T16	1		T242	4
all_values[13]	398	1			T3	3		T16	1		T274	2
all_values[14]	348	1			T3	1		T8	1		T242	1
all_values[15]	386	1			T3	2		T9	2		T242	1
all_values[16]	399	1			T3	4		T15	1		T9	2
all_values[17]	368	1			T3	4		T15	1		T16	1
all_values[18]	361	1			T3	2		T15	1		T16	1
all_values[19]	376	1			T3	4		T9	2		T242	1
all_values[20]	411	1			T3	3		T9	1		T242	3
all_values[21]	386	1			T3	2		T15	2		T274	1
all_values[22]	393	1			T3	3		T15	1		T9	1
all_values[23]	393	1			T3	5		T15	2		T9	1
all_values[24]	407	1			T3	8		T15	2		T16	1
all_values[25]	400	1			T3	6		T9	3		T242	1
all_values[26]	401	1			T3	2		T15	1		T9	1