Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 467 1 T4 2 T2 2 T3 1
all_values[1] 483 1 T4 1 T2 2 T3 1
all_values[2] 448 1 T2 1 T22 1 T25 1
all_values[3] 445 1 T2 1 T22 1 T25 2
all_values[4] 420 1 T2 3 T20 1 T25 2
all_values[5] 443 1 T2 2 T57 1 T69 2
all_values[6] 406 1 T2 5 T3 1 T69 3
all_values[7] 472 1 T2 6 T3 2 T25 1
all_values[8] 458 1 T2 3 T25 1 T69 1
all_values[9] 411 1 T2 5 T20 1 T25 1
all_values[10] 454 1 T2 5 T3 1 T20 1
all_values[11] 452 1 T4 1 T2 1 T3 1
all_values[12] 470 1 T2 10 T25 2 T69 2
all_values[13] 441 1 T4 1 T2 5 T3 2
all_values[14] 499 1 T4 1 T2 2 T3 1
all_values[15] 463 1 T2 4 T22 3 T25 4
all_values[16] 488 1 T2 1 T20 2 T25 3
all_values[17] 471 1 T2 3 T20 1 T22 1
all_values[18] 443 1 T4 1 T2 1 T3 1
all_values[19] 428 1 T4 2 T3 1 T20 2
all_values[20] 470 1 T2 3 T22 2 T57 1
all_values[21] 443 1 T2 3 T20 1 T57 1
all_values[22] 444 1 T2 4 T22 3 T69 2
all_values[23] 480 1 T2 3 T20 1 T25 3
all_values[24] 468 1 T2 5 T22 2 T25 2
all_values[25] 420 1 T4 1 T2 3 T3 1
all_values[26] 446 1 T2 1 T22 2 T69 1

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