Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	411	1			T1	1		T15	4		T16	1
all_values[1]	421	1			T1	5		T15	6		T16	1
all_values[2]	413	1			T1	2		T15	3		T16	1
all_values[3]	436	1			T1	2		T15	5		T45	1
all_values[4]	430	1			T1	7		T15	6		T16	1
all_values[5]	452	1			T1	5		T15	6		T45	3
all_values[6]	429	1			T1	3		T15	9		T16	1
all_values[7]	431	1			T1	2		T15	10		T16	1
all_values[8]	420	1			T1	1		T15	7		T16	1
all_values[9]	400	1			T1	4		T15	6		T16	2
all_values[10]	418	1			T1	4		T15	6		T45	1
all_values[11]	433	1			T1	4		T15	8		T16	1
all_values[12]	451	1			T1	3		T15	9		T45	1
all_values[13]	445	1			T1	7		T15	5		T16	1
all_values[14]	425	1			T1	8		T15	4		T16	1
all_values[15]	417	1			T1	3		T15	1		T45	2
all_values[16]	463	1			T1	7		T15	7		T45	1
all_values[17]	454	1			T1	4		T15	11		T45	3
all_values[18]	415	1			T1	10		T15	6		T16	2
all_values[19]	393	1			T1	2		T15	5		T16	1
all_values[20]	449	1			T1	2		T15	3		T45	4
all_values[21]	433	1			T1	6		T15	9		T248	1
all_values[22]	425	1			T1	5		T15	5		T45	3
all_values[23]	424	1			T1	7		T15	8		T45	4
all_values[24]	452	1			T1	4		T15	4		T45	1
all_values[25]	450	1			T1	4		T15	4		T16	3
all_values[26]	410	1			T1	2		T15	4		T16	1