Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70151 |
1 |
|
|
T1 |
4 |
|
T2 |
34 |
|
T3 |
3 |
| auto[1] |
41248 |
1 |
|
|
T1 |
1 |
|
T5 |
42 |
|
T4 |
23 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
28263 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
78301 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
33098 |
1 |
|
|
T2 |
8 |
|
T3 |
1 |
|
T5 |
21 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8839 |
1 |
|
|
T3 |
1 |
|
T5 |
6 |
|
T4 |
7 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68664 |
1 |
|
|
T1 |
3 |
|
T2 |
32 |
|
T3 |
8 |
| auto[1] |
37149 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26327 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
74615 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31198 |
1 |
|
|
T1 |
4 |
|
T2 |
10 |
|
T3 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8061 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
72229 |
1 |
|
|
T1 |
6 |
|
T2 |
12 |
|
T3 |
2 |
| auto[1] |
37839 |
1 |
|
|
T2 |
23 |
|
T3 |
6 |
|
T5 |
54 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26746 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
77809 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
32259 |
1 |
|
|
T1 |
2 |
|
T2 |
12 |
|
T3 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8352 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70743 |
1 |
|
|
T1 |
1 |
|
T2 |
26 |
|
T3 |
5 |
| auto[1] |
37094 |
1 |
|
|
T1 |
3 |
|
T2 |
20 |
|
T3 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26487 |
1 |
|
|
T2 |
6 |
|
T5 |
32 |
|
T4 |
23 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
76144 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31693 |
1 |
|
|
T1 |
3 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8293 |
1 |
|
|
T2 |
2 |
|
T5 |
9 |
|
T4 |
9 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69750 |
1 |
|
|
T1 |
11 |
|
T2 |
15 |
|
T3 |
1 |
| auto[1] |
36567 |
1 |
|
|
T2 |
36 |
|
T3 |
5 |
|
T5 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27116 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
74544 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31773 |
1 |
|
|
T2 |
14 |
|
T5 |
20 |
|
T4 |
31 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8602 |
1 |
|
|
T2 |
2 |
|
T5 |
10 |
|
T4 |
11 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68069 |
1 |
|
|
T1 |
3 |
|
T2 |
11 |
|
T3 |
9 |
| auto[1] |
39106 |
1 |
|
|
T1 |
4 |
|
T2 |
34 |
|
T3 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26902 |
1 |
|
|
T1 |
3 |
|
T2 |
4 |
|
T3 |
7 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
75303 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31872 |
1 |
|
|
T1 |
2 |
|
T2 |
14 |
|
T3 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8489 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69342 |
1 |
|
|
T1 |
7 |
|
T2 |
32 |
|
T3 |
6 |
| auto[1] |
40317 |
1 |
|
|
T2 |
19 |
|
T3 |
6 |
|
T5 |
34 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27398 |
1 |
|
|
T1 |
2 |
|
T2 |
12 |
|
T3 |
5 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
77254 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
32405 |
1 |
|
|
T1 |
2 |
|
T2 |
14 |
|
T3 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8439 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73514 |
1 |
|
|
T1 |
8 |
|
T2 |
27 |
|
T3 |
3 |
| auto[1] |
39618 |
1 |
|
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
28841 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
79517 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
33615 |
1 |
|
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
9049 |
1 |
|
|
T2 |
1 |
|
T5 |
12 |
|
T4 |
9 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69125 |
1 |
|
|
T1 |
4 |
|
T2 |
17 |
|
T3 |
7 |
| auto[1] |
36285 |
1 |
|
|
T1 |
1 |
|
T2 |
30 |
|
T3 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26434 |
1 |
|
|
T1 |
1 |
|
T2 |
9 |
|
T5 |
26 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
74143 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31267 |
1 |
|
|
T1 |
3 |
|
T2 |
13 |
|
T3 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8267 |
1 |
|
|
T2 |
3 |
|
T5 |
12 |
|
T4 |
11 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66456 |
1 |
|
|
T1 |
1 |
|
T2 |
23 |
|
T3 |
3 |
| auto[1] |
35313 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
25501 |
1 |
|
|
T1 |
2 |
|
T2 |
5 |
|
T3 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
71682 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
30087 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
7885 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70078 |
1 |
|
|
T1 |
3 |
|
T2 |
35 |
|
T5 |
34 |
| auto[1] |
35423 |
1 |
|
|
T1 |
3 |
|
T2 |
12 |
|
T3 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26861 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
73787 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31714 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8480 |
1 |
|
|
T2 |
1 |
|
T5 |
8 |
|
T4 |
13 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70184 |
1 |
|
|
T1 |
3 |
|
T2 |
48 |
|
T3 |
1 |
| auto[1] |
36959 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T3 |
8 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27019 |
1 |
|
|
T1 |
3 |
|
T2 |
10 |
|
T3 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
75373 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31770 |
1 |
|
|
T1 |
4 |
|
T2 |
9 |
|
T3 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8319 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69935 |
1 |
|
|
T1 |
5 |
|
T2 |
34 |
|
T3 |
6 |
| auto[1] |
36451 |
1 |
|
|
T1 |
2 |
|
T2 |
5 |
|
T3 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26830 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T3 |
5 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
75076 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31310 |
1 |
|
|
T1 |
4 |
|
T2 |
8 |
|
T3 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8291 |
1 |
|
|
T1 |
3 |
|
T3 |
2 |
|
T5 |
7 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71297 |
1 |
|
|
T1 |
1 |
|
T2 |
26 |
|
T3 |
4 |
| auto[1] |
37634 |
1 |
|
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27370 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
76096 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
32835 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T3 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8634 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
13 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70568 |
1 |
|
|
T1 |
2 |
|
T2 |
20 |
|
T3 |
1 |
| auto[1] |
39362 |
1 |
|
|
T1 |
3 |
|
T2 |
24 |
|
T3 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27862 |
1 |
|
|
T1 |
2 |
|
T2 |
5 |
|
T3 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
77223 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
32707 |
1 |
|
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8697 |
1 |
|
|
T2 |
1 |
|
T5 |
10 |
|
T4 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73945 |
1 |
|
|
T1 |
3 |
|
T2 |
21 |
|
T3 |
5 |
| auto[1] |
39735 |
1 |
|
|
T1 |
5 |
|
T2 |
20 |
|
T3 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27805 |
1 |
|
|
T1 |
4 |
|
T2 |
8 |
|
T3 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
80083 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
33597 |
1 |
|
|
T1 |
1 |
|
T2 |
15 |
|
T3 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8640 |
1 |
|
|
T2 |
3 |
|
T3 |
2 |
|
T5 |
10 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69690 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T3 |
3 |
| auto[1] |
40785 |
1 |
|
|
T2 |
23 |
|
T3 |
4 |
|
T5 |
47 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27842 |
1 |
|
|
T2 |
4 |
|
T3 |
3 |
|
T5 |
22 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
77606 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
32869 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T5 |
17 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8673 |
1 |
|
|
T2 |
1 |
|
T5 |
3 |
|
T4 |
7 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65748 |
1 |
|
|
T1 |
5 |
|
T2 |
38 |
|
T3 |
5 |
| auto[1] |
37771 |
1 |
|
|
T1 |
3 |
|
T2 |
11 |
|
T3 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
25937 |
1 |
|
|
T1 |
4 |
|
T2 |
8 |
|
T3 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
72869 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
30650 |
1 |
|
|
T1 |
2 |
|
T2 |
17 |
|
T5 |
25 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8023 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T5 |
10 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66562 |
1 |
|
|
T1 |
3 |
|
T2 |
30 |
|
T3 |
7 |
| auto[1] |
35039 |
1 |
|
|
T2 |
5 |
|
T3 |
4 |
|
T5 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
25345 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
71581 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
30020 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T5 |
22 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
7737 |
1 |
|
|
T5 |
9 |
|
T4 |
10 |
|
T11 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68702 |
1 |
|
|
T1 |
5 |
|
T2 |
35 |
|
T3 |
3 |
| auto[1] |
34761 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T5 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
25577 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
72267 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31196 |
1 |
|
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8064 |
1 |
|
|
T3 |
1 |
|
T5 |
10 |
|
T4 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73365 |
1 |
|
|
T1 |
2 |
|
T2 |
42 |
|
T3 |
4 |
| auto[1] |
38261 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
28245 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
77763 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
33863 |
1 |
|
|
T1 |
3 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
9049 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68392 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
18 |
| auto[1] |
38461 |
1 |
|
|
T1 |
4 |
|
T2 |
31 |
|
T5 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26196 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
75551 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31302 |
1 |
|
|
T1 |
4 |
|
T2 |
13 |
|
T3 |
10 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8008 |
1 |
|
|
T2 |
3 |
|
T3 |
3 |
|
T5 |
5 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68688 |
1 |
|
|
T1 |
3 |
|
T2 |
23 |
|
T3 |
7 |
| auto[1] |
36124 |
1 |
|
|
T2 |
8 |
|
T3 |
5 |
|
T5 |
25 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
25679 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
73778 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31034 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8025 |
1 |
|
|
T1 |
1 |
|
T5 |
6 |
|
T4 |
14 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
72770 |
1 |
|
|
T1 |
6 |
|
T2 |
27 |
|
T3 |
3 |
| auto[1] |
35865 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
26336 |
1 |
|
|
T1 |
2 |
|
T2 |
5 |
|
T3 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
76699 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
31936 |
1 |
|
|
T1 |
4 |
|
T2 |
7 |
|
T3 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8141 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67829 |
1 |
|
|
T1 |
4 |
|
T2 |
30 |
|
T3 |
6 |
| auto[1] |
34723 |
1 |
|
|
T1 |
4 |
|
T2 |
11 |
|
T3 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
25168 |
1 |
|
|
T1 |
3 |
|
T2 |
4 |
|
T3 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
72367 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
30185 |
1 |
|
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
7858 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70739 |
1 |
|
|
T1 |
2 |
|
T2 |
31 |
|
T3 |
9 |
| auto[1] |
40457 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
27388 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
5 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
78338 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
32858 |
1 |
|
|
T2 |
11 |
|
T3 |
3 |
|
T5 |
22 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
8468 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T5 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71900 |
1 |
|
|
T1 |
1 |
|
T2 |
17 |
|
T3 |
4 |
| auto[1] |
36708 |
1 |
|
|
T1 |
1 |
|
T2 |
19 |
|
T3 |
2 |