Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	476	1			T9	1		T6	10		T21	1
all_values[1]	418	1			T8	3		T9	2		T6	10
all_values[2]	465	1			T9	1		T6	10		T34	2
all_values[3]	452	1			T8	2		T9	3		T6	3
all_values[4]	430	1			T8	3		T9	2		T6	6
all_values[5]	474	1			T9	1		T6	9		T21	1
all_values[6]	432	1			T8	3		T6	6		T21	1
all_values[7]	409	1			T8	3		T9	2		T6	6
all_values[8]	468	1			T8	1		T9	1		T6	9
all_values[9]	463	1			T9	2		T6	10		T22	1
all_values[10]	458	1			T8	1		T6	3		T214	1
all_values[11]	438	1			T9	1		T6	3		T34	6
all_values[12]	447	1			T8	2		T9	2		T6	5
all_values[13]	479	1			T8	1		T9	2		T6	3
all_values[14]	433	1			T8	2		T6	9		T14	1
all_values[15]	470	1			T8	1		T9	1		T6	7
all_values[16]	446	1			T9	3		T6	6		T21	1
all_values[17]	462	1			T8	2		T6	6		T22	2
all_values[18]	434	1			T9	3		T6	9		T34	4
all_values[19]	407	1			T8	1		T9	1		T6	6
all_values[20]	445	1			T8	2		T9	1		T6	11
all_values[21]	431	1			T8	1		T9	4		T6	5
all_values[22]	483	1			T8	2		T9	2		T6	7
all_values[23]	479	1			T8	2		T9	3		T6	4
all_values[24]	444	1			T9	3		T6	12		T21	2
all_values[25]	455	1			T8	2		T9	4		T6	8
all_values[26]	469	1			T8	1		T9	4		T6	5