Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	452	1			T2	1		T41	2		T48	3
all_values[1]	473	1			T15	7		T41	1		T48	3
all_values[2]	489	1			T4	1		T15	4		T41	1
all_values[3]	460	1			T15	7		T41	1		T48	5
all_values[4]	453	1			T15	5		T41	2		T48	1
all_values[5]	461	1			T2	4		T15	3		T37	1
all_values[6]	474	1			T2	1		T15	4		T40	1
all_values[7]	447	1			T2	1		T15	1		T41	7
all_values[8]	487	1			T2	2		T15	3		T41	2
all_values[9]	434	1			T2	1		T15	2		T37	1
all_values[10]	458	1			T2	3		T15	2		T37	3
all_values[11]	427	1			T15	1		T41	3		T48	4
all_values[12]	452	1			T2	1		T4	1		T15	3
all_values[13]	445	1			T40	1		T41	2		T48	6
all_values[14]	519	1			T15	8		T41	1		T48	7
all_values[15]	477	1			T2	2		T15	7		T41	1
all_values[16]	457	1			T15	4		T41	1		T48	1
all_values[17]	498	1			T2	1		T15	8		T37	1
all_values[18]	446	1			T4	1		T15	4		T41	3
all_values[19]	497	1			T15	3		T40	1		T41	1
all_values[20]	455	1			T2	2		T4	1		T15	4
all_values[21]	482	1			T2	1		T15	4		T37	1
all_values[22]	438	1			T15	4		T37	1		T41	1
all_values[23]	495	1			T2	1		T4	1		T15	1
all_values[24]	462	1			T15	2		T37	1		T40	1
all_values[25]	491	1			T2	2		T15	4		T37	2
all_values[26]	444	1			T2	2		T15	2		T41	3