Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	485	1			T24	8		T115	4		T48	3
all_values[1]	490	1			T2	3		T16	1		T14	1
all_values[2]	489	1			T2	1		T14	3		T24	7
all_values[3]	470	1			T2	1		T24	4		T38	1
all_values[4]	457	1			T2	1		T24	5		T38	3
all_values[5]	475	1			T2	1		T24	3		T45	2
all_values[6]	459	1			T2	2		T24	6		T45	2
all_values[7]	464	1			T24	8		T38	1		T43	1
all_values[8]	456	1			T16	2		T24	6		T38	3
all_values[9]	470	1			T24	6		T43	2		T45	1
all_values[10]	474	1			T2	1		T24	6		T45	1
all_values[11]	477	1			T2	2		T16	1		T14	1
all_values[12]	453	1			T2	1		T24	2		T43	1
all_values[13]	457	1			T2	1		T16	1		T24	6
all_values[14]	481	1			T2	1		T16	1		T24	8
all_values[15]	441	1			T14	1		T24	4		T38	4
all_values[16]	457	1			T2	1		T24	2		T38	2
all_values[17]	445	1			T2	1		T24	6		T38	2
all_values[18]	498	1			T2	1		T24	7		T38	2
all_values[19]	474	1			T2	2		T24	7		T45	1
all_values[20]	453	1			T24	9		T38	1		T45	1
all_values[21]	444	1			T2	1		T24	5		T46	1
all_values[22]	458	1			T16	1		T14	1		T24	5
all_values[23]	490	1			T2	2		T16	1		T24	6
all_values[24]	462	1			T16	1		T24	9		T38	1
all_values[25]	483	1			T24	6		T45	1		T46	1
all_values[26]	463	1			T2	1		T16	2		T24	7