Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 489 1 T3 2 T21 1 T24 1
all_values[1] 483 1 T21 1 T110 1 T146 1
all_values[2] 481 1 T21 1 T39 2 T54 3
all_values[3] 468 1 T10 1 T39 1 T40 1
all_values[4] 509 1 T10 1 T12 2 T21 2
all_values[5] 451 1 T3 1 T10 1 T21 1
all_values[6] 485 1 T3 2 T54 3 T110 2
all_values[7] 481 1 T3 1 T10 2 T12 1
all_values[8] 445 1 T12 1 T21 2 T24 1
all_values[9] 499 1 T3 1 T24 1 T39 2
all_values[10] 485 1 T3 1 T10 1 T20 1
all_values[11] 486 1 T3 1 T10 1 T54 3
all_values[12] 476 1 T21 1 T54 6 T146 1
all_values[13] 484 1 T12 1 T54 2 T146 3
all_values[14] 478 1 T12 2 T21 1 T54 1
all_values[15] 515 1 T3 1 T10 1 T12 1
all_values[16] 493 1 T10 1 T21 2 T39 1
all_values[17] 480 1 T10 1 T20 1 T39 3
all_values[18] 474 1 T21 1 T39 1 T54 2
all_values[19] 497 1 T10 2 T12 2 T39 1
all_values[20] 474 1 T12 1 T24 1 T146 3
all_values[21] 461 1 T10 1 T12 1 T21 1
all_values[22] 454 1 T3 1 T12 1 T54 1
all_values[23] 514 1 T3 1 T10 1 T12 3
all_values[24] 470 1 T20 1 T54 1 T110 1
all_values[25] 498 1 T10 2 T24 1 T39 1
all_values[26] 472 1 T3 1 T10 1 T21 1

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