Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	451	1			T2	2		T17	1		T227	2
all_values[1]	438	1			T2	2		T17	1		T36	1
all_values[2]	478	1			T1	1		T69	8		T218	7
all_values[3]	460	1			T1	3		T17	1		T36	1
all_values[4]	462	1			T2	2		T228	1		T69	3
all_values[5]	433	1			T1	1		T227	1		T69	5
all_values[6]	459	1			T2	2		T16	2		T17	1
all_values[7]	448	1			T36	2		T227	1		T69	6
all_values[8]	441	1			T17	1		T36	1		T227	1
all_values[9]	481	1			T2	1		T16	1		T17	1
all_values[10]	476	1			T2	2		T17	1		T36	1
all_values[11]	480	1			T16	1		T17	1		T69	3
all_values[12]	424	1			T1	1		T2	3		T16	1
all_values[13]	455	1			T1	1		T2	1		T16	1
all_values[14]	463	1			T1	1		T2	1		T17	1
all_values[15]	451	1			T2	1		T16	1		T228	1
all_values[16]	477	1			T1	1		T2	3		T16	1
all_values[17]	464	1			T1	3		T16	1		T36	1
all_values[18]	448	1			T2	2		T16	1		T17	2
all_values[19]	485	1			T2	2		T16	1		T36	1
all_values[20]	449	1			T1	1		T2	1		T16	1
all_values[21]	453	1			T1	1		T2	1		T16	1
all_values[22]	455	1			T2	2		T16	1		T37	1
all_values[23]	482	1			T2	1		T16	1		T227	2
all_values[24]	457	1			T1	2		T16	1		T17	2
all_values[25]	450	1			T2	1		T17	1		T36	2
all_values[26]	490	1			T1	1		T16	1		T17	1