Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	465	1			T1	1		T22	5		T36	4
all_values[1]	466	1			T1	2		T19	1		T15	2
all_values[2]	413	1			T1	4		T19	3		T15	2
all_values[3]	459	1			T1	4		T5	1		T19	1
all_values[4]	440	1			T5	1		T19	1		T15	3
all_values[5]	477	1			T1	4		T3	2		T15	2
all_values[6]	458	1			T1	2		T15	6		T22	4
all_values[7]	450	1			T1	1		T5	1		T19	1
all_values[8]	461	1			T3	2		T19	1		T15	2
all_values[9]	446	1			T1	5		T19	1		T22	8
all_values[10]	425	1			T1	3		T5	1		T22	3
all_values[11]	476	1			T1	8		T3	1		T22	9
all_values[12]	479	1			T1	6		T3	1		T5	1
all_values[13]	466	1			T1	2		T5	2		T15	1
all_values[14]	447	1			T1	2		T15	1		T22	7
all_values[15]	478	1			T1	1		T5	1		T19	1
all_values[16]	497	1			T1	5		T6	1		T19	2
all_values[17]	429	1			T1	3		T6	1		T19	1
all_values[18]	456	1			T1	2		T5	2		T15	1
all_values[19]	486	1			T1	4		T5	2		T15	3
all_values[20]	505	1			T1	5		T3	1		T15	3
all_values[21]	463	1			T1	1		T3	1		T5	2
all_values[22]	443	1			T1	1		T19	2		T22	7
all_values[23]	440	1			T1	6		T5	1		T6	1
all_values[24]	436	1			T1	4		T3	1		T22	7
all_values[25]	440	1			T1	2		T19	1		T15	2
all_values[26]	477	1			T1	1		T3	1		T5	3