Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	256	0	256	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[1]	108995	1		T1	84	T2	87	T3	425
values[2]	3407	1		T1	8	T3	1	T18	1
values[3]	1126	1		T11	15	T56	40	T10	1
values[4]	577	1		T11	2	T56	22	T46	2
values[5]	332	1		T56	8	T46	2	T52	3
values[6]	185	1		T56	1	T46	2	T52	1
values[7]	132	1		T46	2	T82	1	T84	13
values[8]	145	1		T46	2	T82	1	T84	27
values[9]	116	1		T46	2	T82	1	T84	22
values[10]	103	1		T46	2	T82	1	T84	15
values[11]	93	1		T46	2	T82	1	T84	5
values[12]	76	1		T46	2	T82	1	T84	3
values[13]	47	1		T46	2	T82	1	T84	2
values[14]	42	1		T46	2	T82	1	T178	7
values[15]	35	1		T46	2	T82	1	T178	3
values[16]	24	1		T46	2	T82	1	T178	1
values[17]	36	1		T46	2	T82	1	T178	4
values[18]	42	1		T46	2	T82	1	T178	6
values[19]	33	1		T46	2	T82	1	T178	5
values[20]	24	1		T46	2	T82	1	T178	5
values[21]	27	1		T46	2	T82	1	T178	1
values[22]	25	1		T46	2	T82	1	T178	2
values[23]	29	1		T46	2	T82	1	T178	6
values[24]	33	1		T46	2	T82	1	T178	7
values[25]	26	1		T46	2	T82	1	T178	3
values[26]	25	1		T46	2	T82	1	T178	3
values[27]	31	1		T46	2	T82	1	T178	6
values[28]	32	1		T46	2	T82	1	T178	5
values[29]	26	1		T46	2	T82	1	T178	2
values[30]	24	1		T46	2	T82	1	T178	1
values[31]	26	1		T46	2	T82	1	T178	4
values[32]	23	1		T46	2	T82	1	T178	2
values[33]	25	1		T46	2	T82	1	T178	4
values[34]	31	1		T46	2	T82	1	T178	6
values[35]	31	1		T46	2	T82	1	T178	9
values[36]	37	1		T46	2	T82	1	T178	15
values[37]	23	1		T46	2	T82	1	T178	3
values[38]	22	1		T46	2	T82	1	T178	2
values[39]	24	1		T46	2	T82	1	T178	4
values[40]	30	1		T46	2	T82	1	T178	8
values[41]	29	1		T46	2	T82	1	T178	4
values[42]	40	1		T46	2	T82	1	T178	7
values[43]	28	1		T46	2	T82	1	T178	3
values[44]	20	1		T46	2	T82	1	T178	1
values[45]	19	1		T46	2	T82	1	T178	1
values[46]	21	1		T46	2	T82	1	T178	3
values[47]	23	1		T46	2	T82	1	T178	5
values[48]	22	1		T46	2	T82	1	T178	2
values[49]	19	1		T46	2	T82	1	T178	1
values[50]	21	1		T46	2	T82	1	T178	3
values[51]	19	1		T46	2	T82	1	T178	1
values[52]	18	1		T46	2	T82	1	T168	2
values[53]	18	1		T46	2	T82	1	T168	2
values[54]	18	1		T46	2	T82	1	T168	2
values[55]	18	1		T46	2	T82	1	T168	2
values[56]	18	1		T46	2	T82	1	T168	2
values[57]	18	1		T46	2	T82	1	T168	2
values[58]	18	1		T46	2	T82	1	T168	2
values[59]	19	1		T46	2	T82	1	T168	2
values[60]	18	1		T46	2	T82	1	T168	2
values[61]	18	1		T46	2	T82	1	T168	2
values[62]	18	1		T46	2	T82	1	T168	2
values[63]	19	1		T46	3	T82	1	T168	2
values[64]	18	1		T46	2	T82	1	T168	2
values[65]	18	1		T46	2	T82	1	T168	2
values[66]	19	1		T46	2	T82	1	T168	2
values[67]	19	1		T46	3	T82	1	T168	2
values[68]	19	1		T46	2	T82	1	T168	2
values[69]	18	1		T46	2	T82	1	T168	2
values[70]	18	1		T46	2	T82	1	T168	2
values[71]	18	1		T46	2	T82	1	T168	2
values[72]	18	1		T46	2	T82	1	T168	2
values[73]	18	1		T46	2	T82	1	T168	2
values[74]	18	1		T46	2	T82	1	T168	2
values[75]	19	1		T46	2	T82	1	T168	2
values[76]	18	1		T46	2	T82	1	T168	2
values[77]	18	1		T46	2	T82	1	T168	2
values[78]	18	1		T46	2	T82	1	T168	2
values[79]	19	1		T46	2	T82	1	T168	2
values[80]	18	1		T46	2	T82	1	T168	2
values[81]	18	1		T46	2	T82	1	T168	2
values[82]	18	1		T46	2	T82	1	T168	2
values[83]	18	1		T46	2	T82	1	T168	2
values[84]	19	1		T46	2	T82	1	T168	3
values[85]	18	1		T46	2	T82	1	T168	2
values[86]	18	1		T46	2	T82	1	T168	2
values[87]	18	1		T46	2	T82	1	T168	2
values[88]	18	1		T46	2	T82	1	T168	2
values[89]	18	1		T46	2	T82	1	T168	2
values[90]	18	1		T46	2	T82	1	T168	2
values[91]	18	1		T46	2	T82	1	T168	2
values[92]	19	1		T46	2	T82	1	T168	2
values[93]	18	1		T46	2	T82	1	T168	2
values[94]	20	1		T46	2	T82	1	T168	2
values[95]	19	1		T46	2	T82	1	T168	2
values[96]	19	1		T46	2	T82	1	T168	3
values[97]	19	1		T46	2	T82	1	T168	3
values[98]	18	1		T46	2	T82	1	T168	2
values[99]	18	1		T46	2	T82	1	T168	2
values[100]	18	1		T46	2	T82	1	T168	2
values[101]	19	1		T46	2	T82	1	T168	2
values[102]	18	1		T46	2	T82	1	T168	2
values[103]	18	1		T46	2	T82	1	T168	2
values[104]	19	1		T46	2	T82	1	T168	2
values[105]	18	1		T46	2	T82	1	T168	2
values[106]	19	1		T46	2	T82	1	T168	3
values[107]	18	1		T46	2	T82	1	T168	2
values[108]	19	1		T46	2	T82	1	T168	2
values[109]	18	1		T46	2	T82	1	T168	2
values[110]	18	1		T46	2	T82	1	T168	2
values[111]	18	1		T46	2	T82	1	T168	2
values[112]	18	1		T46	2	T82	1	T168	2
values[113]	19	1		T46	2	T82	1	T168	3
values[114]	18	1		T46	2	T82	1	T168	2
values[115]	20	1		T46	2	T82	1	T168	2
values[116]	18	1		T46	2	T82	1	T168	2
values[117]	18	1		T46	2	T82	1	T168	2
values[118]	20	1		T46	2	T82	1	T168	2
values[119]	18	1		T46	2	T82	1	T168	2
values[120]	18	1		T46	2	T82	1	T168	2
values[121]	18	1		T46	2	T82	1	T168	2
values[122]	18	1		T46	2	T82	1	T168	2
values[123]	18	1		T46	2	T82	1	T168	2
values[124]	18	1		T46	2	T82	1	T168	2
values[125]	18	1		T46	2	T82	1	T168	2
values[126]	20	1		T46	2	T82	1	T168	2
values[127]	18	1		T46	2	T82	1	T168	2
values[128]	18	1		T46	2	T82	1	T168	2
values[129]	18	1		T46	2	T82	1	T168	2
values[130]	18	1		T46	2	T82	1	T168	2
values[131]	18	1		T46	2	T82	1	T168	2
values[132]	19	1		T46	2	T82	1	T168	2
values[133]	18	1		T46	2	T82	1	T168	2
values[134]	18	1		T46	2	T82	1	T168	2
values[135]	18	1		T46	2	T82	1	T168	2
values[136]	18	1		T46	2	T82	1	T168	2
values[137]	18	1		T46	2	T82	1	T168	2
values[138]	18	1		T46	2	T82	1	T168	2
values[139]	18	1		T46	2	T82	1	T168	2
values[140]	18	1		T46	2	T82	1	T168	2
values[141]	18	1		T46	2	T82	1	T168	2
values[142]	18	1		T46	2	T82	1	T168	2
values[143]	18	1		T46	2	T82	1	T168	2
values[144]	18	1		T46	2	T82	1	T168	2
values[145]	19	1		T46	3	T82	1	T168	2
values[146]	18	1		T46	2	T82	1	T168	2
values[147]	19	1		T46	2	T82	2	T168	2
values[148]	18	1		T46	2	T82	1	T168	2
values[149]	18	1		T46	2	T82	1	T168	2
values[150]	18	1		T46	2	T82	1	T168	2
values[151]	18	1		T46	2	T82	1	T168	2
values[152]	18	1		T46	2	T82	1	T168	2
values[153]	18	1		T46	2	T82	1	T168	2
values[154]	19	1		T46	2	T82	1	T168	2
values[155]	18	1		T46	2	T82	1	T168	2
values[156]	18	1		T46	2	T82	1	T168	2
values[157]	18	1		T46	2	T82	1	T168	2
values[158]	18	1		T46	2	T82	1	T168	2
values[159]	18	1		T46	2	T82	1	T168	2
values[160]	18	1		T46	2	T82	1	T168	2
values[161]	18	1		T46	2	T82	1	T168	2
values[162]	18	1		T46	2	T82	1	T168	2
values[163]	18	1		T46	2	T82	1	T168	2
values[164]	18	1		T46	2	T82	1	T168	2
values[165]	18	1		T46	2	T82	1	T168	2
values[166]	18	1		T46	2	T82	1	T168	2
values[167]	18	1		T46	2	T82	1	T168	2
values[168]	18	1		T46	2	T82	1	T168	2
values[169]	19	1		T46	2	T82	1	T168	2
values[170]	19	1		T46	2	T82	1	T168	2
values[171]	19	1		T46	2	T82	1	T168	3
values[172]	18	1		T46	2	T82	1	T168	2
values[173]	18	1		T46	2	T82	1	T168	2
values[174]	19	1		T46	2	T82	1	T168	2
values[175]	18	1		T46	2	T82	1	T168	2
values[176]	18	1		T46	2	T82	1	T168	2
values[177]	18	1		T46	2	T82	1	T168	2
values[178]	18	1		T46	2	T82	1	T168	2
values[179]	18	1		T46	2	T82	1	T168	2
values[180]	19	1		T46	2	T82	1	T168	2
values[181]	18	1		T46	2	T82	1	T168	2
values[182]	18	1		T46	2	T82	1	T168	2
values[183]	18	1		T46	2	T82	1	T168	2
values[184]	19	1		T46	2	T82	1	T168	2
values[185]	19	1		T46	2	T82	1	T168	2
values[186]	18	1		T46	2	T82	1	T168	2
values[187]	18	1		T46	2	T82	1	T168	2
values[188]	19	1		T46	2	T82	1	T168	2
values[189]	19	1		T46	2	T82	1	T168	2
values[190]	19	1		T46	3	T82	1	T168	2
values[191]	18	1		T46	2	T82	1	T168	2
values[192]	18	1		T46	2	T82	1	T168	2
values[193]	18	1		T46	2	T82	1	T168	2
values[194]	19	1		T46	2	T82	1	T168	2
values[195]	20	1		T46	2	T82	1	T168	3
values[196]	18	1		T46	2	T82	1	T168	2
values[197]	18	1		T46	2	T82	1	T168	2
values[198]	19	1		T46	2	T82	1	T168	2
values[199]	18	1		T46	2	T82	1	T168	2
values[200]	18	1		T46	2	T82	1	T168	2
values[201]	17	1		T46	2	T82	1	T168	2
values[202]	16	1		T46	1	T82	1	T168	2
values[203]	17	1		T46	1	T82	1	T168	2
values[204]	16	1		T46	1	T82	1	T168	2
values[205]	16	1		T46	1	T82	1	T168	2
values[206]	16	1		T46	1	T82	1	T168	2
values[207]	15	1		T46	1	T82	1	T168	2
values[208]	15	1		T46	1	T82	1	T168	2
values[209]	15	1		T46	1	T82	1	T168	2
values[210]	14	1		T46	1	T82	1	T168	2
values[211]	14	1		T46	1	T82	1	T168	2
values[212]	14	1		T46	1	T82	1	T168	2
values[213]	14	1		T46	1	T82	1	T168	2
values[214]	14	1		T46	1	T82	1	T168	2
values[215]	14	1		T46	1	T82	1	T168	2
values[216]	14	1		T46	1	T82	1	T168	2
values[217]	14	1		T46	1	T82	1	T168	2
values[218]	13	1		T46	1	T82	1	T168	2
values[219]	13	1		T46	1	T82	1	T168	2
values[220]	13	1		T46	1	T82	1	T168	2
values[221]	12	1		T46	1	T82	1	T168	2
values[222]	12	1		T46	1	T82	1	T168	2
values[223]	12	1		T46	1	T82	1	T168	2
values[224]	12	1		T46	1	T82	1	T168	2
values[225]	12	1		T46	1	T82	1	T168	2
values[226]	12	1		T46	1	T82	1	T168	2
values[227]	12	1		T46	1	T82	1	T168	2
values[228]	12	1		T46	1	T82	1	T168	2
values[229]	12	1		T46	1	T82	1	T168	2
values[230]	12	1		T46	1	T82	1	T168	2
values[231]	12	1		T46	1	T82	1	T168	2
values[232]	12	1		T46	1	T82	1	T168	2
values[233]	13	1		T46	1	T82	1	T168	3
values[234]	11	1		T46	1	T82	1	T168	2
values[235]	11	1		T46	1	T82	1	T168	2
values[236]	10	1		T46	1	T82	1	T168	1
values[237]	10	1		T46	1	T82	1	T168	1
values[238]	10	1		T46	1	T82	1	T168	1
values[239]	10	1		T46	1	T82	1	T168	1
values[240]	10	1		T46	1	T82	1	T168	1
values[241]	11	1		T46	1	T82	2	T168	1
values[242]	10	1		T46	1	T82	1	T168	1
values[243]	10	1		T46	1	T82	1	T168	1
values[244]	10	1		T46	1	T82	1	T168	1
values[245]	11	1		T46	1	T82	1	T168	1
values[246]	10	1		T46	1	T82	1	T168	1
values[247]	11	1		T46	1	T82	1	T168	1
values[248]	11	1		T46	1	T82	1	T168	1
values[249]	10	1		T46	1	T82	1	T168	1
values[250]	8	1		T46	1	T168	1	T165	1
values[251]	8	1		T46	1	T168	1	T165	1
values[252]	7	1		T46	1	T168	1	T165	1
values[253]	7	1		T46	1	T168	1	T165	1
values[254]	7	1		T46	1	T168	1	T165	1
values[255]	8	1		T46	1	T168	2	T165	1
values[256]	134	1		T46	2	T168	33	T165	7