Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	482	1			T3	1		T11	4		T55	8
all_values[1]	453	1			T11	2		T55	3		T56	12
all_values[2]	471	1			T3	1		T4	2		T11	4
all_values[3]	410	1			T3	1		T17	1		T11	2
all_values[4]	485	1			T3	1		T14	1		T11	2
all_values[5]	436	1			T4	1		T11	6		T55	9
all_values[6]	461	1			T3	2		T4	1		T11	2
all_values[7]	431	1			T3	1		T14	1		T11	2
all_values[8]	482	1			T3	1		T11	2		T55	6
all_values[9]	464	1			T3	1		T11	2		T55	4
all_values[10]	443	1			T14	2		T55	5		T56	3
all_values[11]	461	1			T55	4		T21	1		T56	8
all_values[12]	463	1			T3	1		T14	3		T11	3
all_values[13]	445	1			T4	1		T14	2		T11	3
all_values[14]	443	1			T11	1		T55	8		T56	9
all_values[15]	467	1			T3	1		T11	2		T55	6
all_values[16]	472	1			T3	1		T11	3		T55	5
all_values[17]	469	1			T3	1		T4	1		T14	1
all_values[18]	481	1			T3	1		T14	1		T11	2
all_values[19]	471	1			T3	1		T11	2		T55	7
all_values[20]	454	1			T3	1		T14	1		T11	3
all_values[21]	469	1			T3	4		T11	1		T55	7
all_values[22]	469	1			T3	1		T14	4		T11	2
all_values[23]	443	1			T14	1		T11	1		T55	3
all_values[24]	439	1			T3	2		T14	1		T11	5
all_values[25]	455	1			T3	2		T55	7		T56	9
all_values[26]	415	1			T3	2		T14	1		T11	1