SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
99.40 | 100.00 | 96.37 | 100.00 | 100.00 | 100.00 | 100.00 |
T764 | /workspace/coverage/xbar_build_mode/19.xbar_same_source.855901229 | Aug 05 05:06:55 PM PDT 24 | Aug 05 05:07:00 PM PDT 24 | 606011826 ps | ||
T765 | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3713615547 | Aug 05 05:06:55 PM PDT 24 | Aug 05 05:07:00 PM PDT 24 | 36237167 ps | ||
T766 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.357441930 | Aug 05 05:06:55 PM PDT 24 | Aug 05 05:06:59 PM PDT 24 | 489258879 ps | ||
T11 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4096152134 | Aug 05 05:07:43 PM PDT 24 | Aug 05 05:10:24 PM PDT 24 | 7012986120 ps | ||
T767 | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3893678198 | Aug 05 05:07:30 PM PDT 24 | Aug 05 05:09:30 PM PDT 24 | 33101428302 ps | ||
T768 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1974666007 | Aug 05 05:07:30 PM PDT 24 | Aug 05 05:07:31 PM PDT 24 | 10490970 ps | ||
T163 | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1605368436 | Aug 05 05:06:36 PM PDT 24 | Aug 05 05:07:41 PM PDT 24 | 11991916489 ps | ||
T769 | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.4051246506 | Aug 05 05:06:24 PM PDT 24 | Aug 05 05:06:59 PM PDT 24 | 10391075762 ps | ||
T770 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.285063760 | Aug 05 05:07:34 PM PDT 24 | Aug 05 05:10:54 PM PDT 24 | 21443416459 ps | ||
T771 | /workspace/coverage/xbar_build_mode/8.xbar_same_source.831792620 | Aug 05 05:06:45 PM PDT 24 | Aug 05 05:06:49 PM PDT 24 | 39146942 ps | ||
T772 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.584539929 | Aug 05 05:06:57 PM PDT 24 | Aug 05 05:10:13 PM PDT 24 | 25267802351 ps | ||
T773 | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2115570433 | Aug 05 05:07:34 PM PDT 24 | Aug 05 05:09:20 PM PDT 24 | 14970119271 ps | ||
T774 | /workspace/coverage/xbar_build_mode/24.xbar_random.3908984729 | Aug 05 05:07:08 PM PDT 24 | Aug 05 05:07:16 PM PDT 24 | 574589586 ps | ||
T775 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4239735411 | Aug 05 05:07:09 PM PDT 24 | Aug 05 05:07:45 PM PDT 24 | 672320457 ps | ||
T776 | /workspace/coverage/xbar_build_mode/33.xbar_random.2344172069 | Aug 05 05:07:26 PM PDT 24 | Aug 05 05:07:33 PM PDT 24 | 300285904 ps | ||
T777 | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1755084863 | Aug 05 05:07:36 PM PDT 24 | Aug 05 05:07:42 PM PDT 24 | 51333801 ps | ||
T778 | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1703228936 | Aug 05 05:06:27 PM PDT 24 | Aug 05 05:06:31 PM PDT 24 | 55341823 ps | ||
T112 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.690267027 | Aug 05 05:07:41 PM PDT 24 | Aug 05 05:07:45 PM PDT 24 | 206561149 ps | ||
T779 | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2719512827 | Aug 05 05:07:04 PM PDT 24 | Aug 05 05:07:05 PM PDT 24 | 11553702 ps | ||
T118 | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.843528652 | Aug 05 05:07:11 PM PDT 24 | Aug 05 05:07:20 PM PDT 24 | 2224274552 ps | ||
T780 | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2825734356 | Aug 05 05:06:54 PM PDT 24 | Aug 05 05:07:02 PM PDT 24 | 289973909 ps | ||
T781 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1485001541 | Aug 05 05:06:38 PM PDT 24 | Aug 05 05:08:48 PM PDT 24 | 1635866255 ps | ||
T782 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3089964346 | Aug 05 05:07:00 PM PDT 24 | Aug 05 05:07:05 PM PDT 24 | 1206890651 ps | ||
T783 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.569548716 | Aug 05 05:06:22 PM PDT 24 | Aug 05 05:06:23 PM PDT 24 | 9451590 ps | ||
T784 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3295601693 | Aug 05 05:07:03 PM PDT 24 | Aug 05 05:07:38 PM PDT 24 | 475833574 ps | ||
T785 | /workspace/coverage/xbar_build_mode/41.xbar_error_random.3982328098 | Aug 05 05:07:48 PM PDT 24 | Aug 05 05:07:51 PM PDT 24 | 20757181 ps | ||
T786 | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.622353494 | Aug 05 05:08:09 PM PDT 24 | Aug 05 05:08:14 PM PDT 24 | 182949187 ps | ||
T787 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4232282710 | Aug 05 05:07:09 PM PDT 24 | Aug 05 05:10:15 PM PDT 24 | 6542663963 ps | ||
T788 | /workspace/coverage/xbar_build_mode/26.xbar_random.3128933460 | Aug 05 05:07:28 PM PDT 24 | Aug 05 05:07:35 PM PDT 24 | 468684523 ps | ||
T789 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2979166202 | Aug 05 05:07:17 PM PDT 24 | Aug 05 05:07:26 PM PDT 24 | 48136022 ps | ||
T790 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3921453858 | Aug 05 05:07:29 PM PDT 24 | Aug 05 05:07:45 PM PDT 24 | 160928585 ps | ||
T791 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.287735421 | Aug 05 05:07:13 PM PDT 24 | Aug 05 05:08:03 PM PDT 24 | 458646364 ps | ||
T792 | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2138545566 | Aug 05 05:07:42 PM PDT 24 | Aug 05 05:07:49 PM PDT 24 | 1975310681 ps | ||
T793 | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1988180075 | Aug 05 05:06:31 PM PDT 24 | Aug 05 05:06:37 PM PDT 24 | 478723548 ps | ||
T794 | /workspace/coverage/xbar_build_mode/42.xbar_error_random.4129728926 | Aug 05 05:07:48 PM PDT 24 | Aug 05 05:07:54 PM PDT 24 | 405895585 ps | ||
T795 | /workspace/coverage/xbar_build_mode/39.xbar_same_source.2087556271 | Aug 05 05:07:44 PM PDT 24 | Aug 05 05:07:47 PM PDT 24 | 55817025 ps | ||
T796 | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3781014429 | Aug 05 05:07:29 PM PDT 24 | Aug 05 05:07:33 PM PDT 24 | 137792564 ps | ||
T797 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3972402324 | Aug 05 05:08:04 PM PDT 24 | Aug 05 05:08:05 PM PDT 24 | 8948209 ps | ||
T798 | /workspace/coverage/xbar_build_mode/15.xbar_smoke.563431330 | Aug 05 05:06:57 PM PDT 24 | Aug 05 05:06:58 PM PDT 24 | 9577012 ps | ||
T799 | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.191693823 | Aug 05 05:07:22 PM PDT 24 | Aug 05 05:07:32 PM PDT 24 | 228658604 ps | ||
T800 | /workspace/coverage/xbar_build_mode/23.xbar_smoke.3209196145 | Aug 05 05:07:02 PM PDT 24 | Aug 05 05:07:03 PM PDT 24 | 10352328 ps | ||
T801 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3801839479 | Aug 05 05:07:22 PM PDT 24 | Aug 05 05:07:31 PM PDT 24 | 47903597 ps | ||
T802 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3970483909 | Aug 05 05:07:02 PM PDT 24 | Aug 05 05:07:11 PM PDT 24 | 1256402518 ps | ||
T803 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.602133842 | Aug 05 05:06:54 PM PDT 24 | Aug 05 05:07:04 PM PDT 24 | 99610386 ps | ||
T804 | /workspace/coverage/xbar_build_mode/0.xbar_error_random.780256626 | Aug 05 05:06:01 PM PDT 24 | Aug 05 05:06:05 PM PDT 24 | 37402155 ps | ||
T805 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1707400015 | Aug 05 05:06:17 PM PDT 24 | Aug 05 05:07:44 PM PDT 24 | 561414697 ps | ||
T183 | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.365754016 | Aug 05 05:07:29 PM PDT 24 | Aug 05 05:09:54 PM PDT 24 | 33906814122 ps | ||
T806 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1480638673 | Aug 05 05:07:00 PM PDT 24 | Aug 05 05:07:18 PM PDT 24 | 2523983110 ps | ||
T807 | /workspace/coverage/xbar_build_mode/29.xbar_random.3637747251 | Aug 05 05:07:17 PM PDT 24 | Aug 05 05:07:19 PM PDT 24 | 19029403 ps | ||
T808 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1606470757 | Aug 05 05:06:20 PM PDT 24 | Aug 05 05:08:55 PM PDT 24 | 27622130110 ps | ||
T809 | /workspace/coverage/xbar_build_mode/22.xbar_random.1625632792 | Aug 05 05:06:54 PM PDT 24 | Aug 05 05:06:57 PM PDT 24 | 331203689 ps | ||
T810 | /workspace/coverage/xbar_build_mode/7.xbar_random.2044165852 | Aug 05 05:06:11 PM PDT 24 | Aug 05 05:06:13 PM PDT 24 | 45694279 ps | ||
T811 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2632798045 | Aug 05 05:06:07 PM PDT 24 | Aug 05 05:07:04 PM PDT 24 | 9990093286 ps | ||
T812 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1530419712 | Aug 05 05:06:31 PM PDT 24 | Aug 05 05:06:47 PM PDT 24 | 2368585207 ps | ||
T813 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.752797654 | Aug 05 05:08:16 PM PDT 24 | Aug 05 05:08:18 PM PDT 24 | 17499857 ps | ||
T814 | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2647415593 | Aug 05 05:06:54 PM PDT 24 | Aug 05 05:06:56 PM PDT 24 | 78971548 ps | ||
T815 | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.279450237 | Aug 05 05:07:35 PM PDT 24 | Aug 05 05:10:36 PM PDT 24 | 34453053340 ps | ||
T816 | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1438714097 | Aug 05 05:06:21 PM PDT 24 | Aug 05 05:06:30 PM PDT 24 | 607544243 ps | ||
T817 | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3689649433 | Aug 05 05:07:44 PM PDT 24 | Aug 05 05:07:49 PM PDT 24 | 851139660 ps | ||
T818 | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3028084793 | Aug 05 05:06:43 PM PDT 24 | Aug 05 05:06:44 PM PDT 24 | 10080078 ps | ||
T819 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3691942047 | Aug 05 05:07:56 PM PDT 24 | Aug 05 05:11:11 PM PDT 24 | 6428174147 ps | ||
T820 | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2914633515 | Aug 05 05:07:11 PM PDT 24 | Aug 05 05:07:23 PM PDT 24 | 4609347805 ps | ||
T821 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.974231091 | Aug 05 05:06:07 PM PDT 24 | Aug 05 05:06:10 PM PDT 24 | 64103314 ps | ||
T822 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1539102473 | Aug 05 05:07:35 PM PDT 24 | Aug 05 05:07:37 PM PDT 24 | 8623721 ps | ||
T823 | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1548035079 | Aug 05 05:07:47 PM PDT 24 | Aug 05 05:07:48 PM PDT 24 | 13344108 ps | ||
T113 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3126329980 | Aug 05 05:07:41 PM PDT 24 | Aug 05 05:10:28 PM PDT 24 | 29830026010 ps | ||
T211 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.14019452 | Aug 05 05:07:30 PM PDT 24 | Aug 05 05:09:16 PM PDT 24 | 27800068022 ps | ||
T824 | /workspace/coverage/xbar_build_mode/14.xbar_random.4112671578 | Aug 05 05:06:46 PM PDT 24 | Aug 05 05:06:48 PM PDT 24 | 406888406 ps | ||
T825 | /workspace/coverage/xbar_build_mode/16.xbar_random.1509379082 | Aug 05 05:06:51 PM PDT 24 | Aug 05 05:06:52 PM PDT 24 | 9010309 ps | ||
T826 | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.613141636 | Aug 05 05:06:44 PM PDT 24 | Aug 05 05:06:48 PM PDT 24 | 184156617 ps | ||
T827 | /workspace/coverage/xbar_build_mode/48.xbar_error_random.2052481495 | Aug 05 05:08:16 PM PDT 24 | Aug 05 05:08:21 PM PDT 24 | 648601471 ps | ||
T828 | /workspace/coverage/xbar_build_mode/21.xbar_random.11994113 | Aug 05 05:07:00 PM PDT 24 | Aug 05 05:07:03 PM PDT 24 | 26677296 ps | ||
T829 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.658185651 | Aug 05 05:07:17 PM PDT 24 | Aug 05 05:09:20 PM PDT 24 | 1032320475 ps | ||
T830 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3039036835 | Aug 05 05:06:07 PM PDT 24 | Aug 05 05:06:16 PM PDT 24 | 4556341619 ps | ||
T831 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3819070285 | Aug 05 05:06:29 PM PDT 24 | Aug 05 05:07:48 PM PDT 24 | 9843225617 ps | ||
T832 | /workspace/coverage/xbar_build_mode/27.xbar_error_random.621789929 | Aug 05 05:07:23 PM PDT 24 | Aug 05 05:07:25 PM PDT 24 | 49298308 ps | ||
T833 | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1822734840 | Aug 05 05:07:28 PM PDT 24 | Aug 05 05:07:40 PM PDT 24 | 4890117652 ps | ||
T834 | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1813562858 | Aug 05 05:07:14 PM PDT 24 | Aug 05 05:07:18 PM PDT 24 | 98351890 ps | ||
T835 | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2258701608 | Aug 05 05:06:04 PM PDT 24 | Aug 05 05:06:08 PM PDT 24 | 45010172 ps | ||
T836 | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3823787939 | Aug 05 05:07:00 PM PDT 24 | Aug 05 05:07:03 PM PDT 24 | 68904117 ps | ||
T837 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.516311914 | Aug 05 05:06:49 PM PDT 24 | Aug 05 05:06:55 PM PDT 24 | 4929673732 ps | ||
T838 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1280826828 | Aug 05 05:07:12 PM PDT 24 | Aug 05 05:07:46 PM PDT 24 | 3271832238 ps | ||
T839 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3440470986 | Aug 05 05:07:29 PM PDT 24 | Aug 05 05:07:46 PM PDT 24 | 908469048 ps | ||
T840 | /workspace/coverage/xbar_build_mode/31.xbar_smoke.397528392 | Aug 05 05:07:19 PM PDT 24 | Aug 05 05:07:21 PM PDT 24 | 144390050 ps | ||
T841 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2177766318 | Aug 05 05:07:34 PM PDT 24 | Aug 05 05:07:55 PM PDT 24 | 1176975878 ps | ||
T842 | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3467609978 | Aug 05 05:06:47 PM PDT 24 | Aug 05 05:06:50 PM PDT 24 | 96298967 ps | ||
T843 | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1219109622 | Aug 05 05:06:55 PM PDT 24 | Aug 05 05:07:01 PM PDT 24 | 56190286 ps | ||
T844 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2642002770 | Aug 05 05:07:34 PM PDT 24 | Aug 05 05:07:47 PM PDT 24 | 4569498778 ps | ||
T114 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2381464674 | Aug 05 05:06:50 PM PDT 24 | Aug 05 05:09:38 PM PDT 24 | 5463678593 ps | ||
T845 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2525443440 | Aug 05 05:07:42 PM PDT 24 | Aug 05 05:07:53 PM PDT 24 | 2906755804 ps | ||
T846 | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.210912258 | Aug 05 05:08:23 PM PDT 24 | Aug 05 05:08:33 PM PDT 24 | 103364528 ps | ||
T847 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1968672352 | Aug 05 05:06:57 PM PDT 24 | Aug 05 05:06:58 PM PDT 24 | 10028070 ps | ||
T848 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.2608292817 | Aug 05 05:06:05 PM PDT 24 | Aug 05 05:06:11 PM PDT 24 | 303775105 ps | ||
T849 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1729053790 | Aug 05 05:07:56 PM PDT 24 | Aug 05 05:08:04 PM PDT 24 | 495500253 ps | ||
T850 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1420988006 | Aug 05 05:06:44 PM PDT 24 | Aug 05 05:06:54 PM PDT 24 | 2057105206 ps | ||
T851 | /workspace/coverage/xbar_build_mode/39.xbar_smoke.3921197272 | Aug 05 05:07:57 PM PDT 24 | Aug 05 05:07:59 PM PDT 24 | 55265356 ps | ||
T852 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3300945445 | Aug 05 05:07:58 PM PDT 24 | Aug 05 05:08:03 PM PDT 24 | 25489717 ps | ||
T853 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3571463724 | Aug 05 05:06:53 PM PDT 24 | Aug 05 05:07:00 PM PDT 24 | 3427460734 ps | ||
T854 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.3211110384 | Aug 05 05:08:09 PM PDT 24 | Aug 05 05:08:10 PM PDT 24 | 44710094 ps | ||
T855 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1045915563 | Aug 05 05:06:43 PM PDT 24 | Aug 05 05:06:49 PM PDT 24 | 2231738426 ps | ||
T856 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2898268812 | Aug 05 05:06:10 PM PDT 24 | Aug 05 05:06:18 PM PDT 24 | 152452526 ps | ||
T857 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.4052693649 | Aug 05 05:07:22 PM PDT 24 | Aug 05 05:07:34 PM PDT 24 | 3023932503 ps | ||
T858 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.587108401 | Aug 05 05:07:04 PM PDT 24 | Aug 05 05:12:46 PM PDT 24 | 44365009805 ps | ||
T859 | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.4054400850 | Aug 05 05:06:00 PM PDT 24 | Aug 05 05:06:08 PM PDT 24 | 198536583 ps | ||
T172 | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.434994037 | Aug 05 05:06:50 PM PDT 24 | Aug 05 05:08:38 PM PDT 24 | 43144246425 ps | ||
T43 | /workspace/coverage/xbar_build_mode/42.xbar_smoke.985971436 | Aug 05 05:07:46 PM PDT 24 | Aug 05 05:07:48 PM PDT 24 | 63287589 ps | ||
T860 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1611457741 | Aug 05 05:07:12 PM PDT 24 | Aug 05 05:10:15 PM PDT 24 | 2324394841 ps | ||
T861 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2362488915 | Aug 05 05:06:47 PM PDT 24 | Aug 05 05:06:53 PM PDT 24 | 42230240 ps | ||
T862 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.134199305 | Aug 05 05:08:16 PM PDT 24 | Aug 05 05:08:27 PM PDT 24 | 13108824985 ps | ||
T863 | /workspace/coverage/xbar_build_mode/24.xbar_smoke.2910688542 | Aug 05 05:06:56 PM PDT 24 | Aug 05 05:06:57 PM PDT 24 | 9630284 ps | ||
T864 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3682377771 | Aug 05 05:07:14 PM PDT 24 | Aug 05 05:07:28 PM PDT 24 | 96152726 ps | ||
T865 | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3443923849 | Aug 05 05:07:48 PM PDT 24 | Aug 05 05:07:50 PM PDT 24 | 48872368 ps | ||
T866 | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1839842893 | Aug 05 05:07:42 PM PDT 24 | Aug 05 05:07:47 PM PDT 24 | 104367174 ps | ||
T867 | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.651567712 | Aug 05 05:06:51 PM PDT 24 | Aug 05 05:07:02 PM PDT 24 | 49094543 ps | ||
T868 | /workspace/coverage/xbar_build_mode/11.xbar_same_source.4028739226 | Aug 05 05:06:25 PM PDT 24 | Aug 05 05:06:38 PM PDT 24 | 2214123058 ps | ||
T869 | /workspace/coverage/xbar_build_mode/16.xbar_smoke.472282094 | Aug 05 05:06:47 PM PDT 24 | Aug 05 05:06:48 PM PDT 24 | 8788661 ps | ||
T870 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1840532360 | Aug 05 05:07:15 PM PDT 24 | Aug 05 05:07:17 PM PDT 24 | 8231910 ps | ||
T871 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.373434533 | Aug 05 05:06:10 PM PDT 24 | Aug 05 05:06:48 PM PDT 24 | 2397398700 ps | ||
T872 | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1323113615 | Aug 05 05:07:47 PM PDT 24 | Aug 05 05:07:52 PM PDT 24 | 32538514 ps | ||
T873 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2484539824 | Aug 05 05:06:29 PM PDT 24 | Aug 05 05:06:39 PM PDT 24 | 4780191387 ps | ||
T874 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2690619453 | Aug 05 05:07:11 PM PDT 24 | Aug 05 05:07:12 PM PDT 24 | 10523706 ps | ||
T875 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2115280470 | Aug 05 05:06:57 PM PDT 24 | Aug 05 05:07:03 PM PDT 24 | 609151509 ps | ||
T876 | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2339440674 | Aug 05 05:07:12 PM PDT 24 | Aug 05 05:08:16 PM PDT 24 | 33588638516 ps | ||
T877 | /workspace/coverage/xbar_build_mode/46.xbar_random.3634403309 | Aug 05 05:08:16 PM PDT 24 | Aug 05 05:08:22 PM PDT 24 | 372742108 ps | ||
T15 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2756566809 | Aug 05 05:07:55 PM PDT 24 | Aug 05 05:09:10 PM PDT 24 | 499426737 ps | ||
T878 | /workspace/coverage/xbar_build_mode/47.xbar_error_random.3157245476 | Aug 05 05:08:23 PM PDT 24 | Aug 05 05:08:27 PM PDT 24 | 56619980 ps | ||
T879 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.948500756 | Aug 05 05:06:26 PM PDT 24 | Aug 05 05:06:39 PM PDT 24 | 10935088387 ps | ||
T880 | /workspace/coverage/xbar_build_mode/7.xbar_same_source.82805856 | Aug 05 05:06:11 PM PDT 24 | Aug 05 05:06:18 PM PDT 24 | 417434677 ps | ||
T115 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3740112598 | Aug 05 05:07:33 PM PDT 24 | Aug 05 05:08:08 PM PDT 24 | 9995404921 ps | ||
T881 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.723599503 | Aug 05 05:06:43 PM PDT 24 | Aug 05 05:06:57 PM PDT 24 | 3640823926 ps | ||
T882 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3878830732 | Aug 05 05:07:34 PM PDT 24 | Aug 05 05:07:55 PM PDT 24 | 209695032 ps | ||
T883 | /workspace/coverage/xbar_build_mode/18.xbar_same_source.2425433756 | Aug 05 05:06:58 PM PDT 24 | Aug 05 05:07:00 PM PDT 24 | 79078713 ps | ||
T884 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1249249996 | Aug 05 05:06:33 PM PDT 24 | Aug 05 05:06:43 PM PDT 24 | 2073446053 ps | ||
T885 | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3335786743 | Aug 05 05:07:55 PM PDT 24 | Aug 05 05:08:04 PM PDT 24 | 629100395 ps | ||
T16 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1789710791 | Aug 05 05:07:22 PM PDT 24 | Aug 05 05:08:30 PM PDT 24 | 5365955635 ps | ||
T886 | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1233522946 | Aug 05 05:08:03 PM PDT 24 | Aug 05 05:08:16 PM PDT 24 | 958476033 ps | ||
T887 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3637972883 | Aug 05 05:07:15 PM PDT 24 | Aug 05 05:07:34 PM PDT 24 | 91187612 ps | ||
T888 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1417000617 | Aug 05 05:06:32 PM PDT 24 | Aug 05 05:06:35 PM PDT 24 | 214903739 ps | ||
T889 | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1478281839 | Aug 05 05:06:21 PM PDT 24 | Aug 05 05:07:08 PM PDT 24 | 8134438079 ps | ||
T890 | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.898251837 | Aug 05 05:06:48 PM PDT 24 | Aug 05 05:06:53 PM PDT 24 | 707693853 ps | ||
T891 | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1555843745 | Aug 05 05:06:55 PM PDT 24 | Aug 05 05:06:56 PM PDT 24 | 13919425 ps | ||
T892 | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2882471977 | Aug 05 05:07:03 PM PDT 24 | Aug 05 05:07:12 PM PDT 24 | 527102707 ps | ||
T893 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3772349415 | Aug 05 05:06:28 PM PDT 24 | Aug 05 05:07:20 PM PDT 24 | 4124267801 ps | ||
T894 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.680300742 | Aug 05 05:06:50 PM PDT 24 | Aug 05 05:06:58 PM PDT 24 | 1331341617 ps | ||
T895 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1401496094 | Aug 05 05:06:26 PM PDT 24 | Aug 05 05:06:34 PM PDT 24 | 1228016047 ps | ||
T896 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1512950486 | Aug 05 05:06:38 PM PDT 24 | Aug 05 05:06:59 PM PDT 24 | 2819366223 ps | ||
T897 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1177502246 | Aug 05 05:07:30 PM PDT 24 | Aug 05 05:08:57 PM PDT 24 | 2929913205 ps | ||
T898 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2027526071 | Aug 05 05:07:16 PM PDT 24 | Aug 05 05:08:22 PM PDT 24 | 492477022 ps | ||
T899 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1828927586 | Aug 05 05:07:43 PM PDT 24 | Aug 05 05:07:54 PM PDT 24 | 12191997074 ps | ||
T900 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.257918990 | Aug 05 05:06:00 PM PDT 24 | Aug 05 05:06:18 PM PDT 24 | 2436382386 ps |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3997540604 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2328435604 ps |
CPU time | 14.61 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:07:12 PM PDT 24 |
Peak memory | 202128 kb |
Host | smart-36a4e4ca-8bb7-4464-b52f-3a83c9ee774c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3997540604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3997540604 |
Directory | /workspace/16.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4060372895 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 41288657251 ps |
CPU time | 268.02 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:11:04 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-586112ec-25c9-483d-b5a6-d620e6c60d97 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4060372895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.4060372895 |
Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3427153655 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 35048117570 ps |
CPU time | 257.48 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:12:15 PM PDT 24 |
Peak memory | 203628 kb |
Host | smart-544894c8-47b1-461f-a165-e2c66b333498 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3427153655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3427153655 |
Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3862152407 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 125054112490 ps |
CPU time | 326.49 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:11:56 PM PDT 24 |
Peak memory | 203180 kb |
Host | smart-421451ee-dc49-4278-bb1f-2b311f6d2885 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3862152407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3862152407 |
Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2095096266 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 38844227624 ps |
CPU time | 243.46 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:10:13 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-dcf6501f-de88-40ff-9840-4dfc5d16f981 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2095096266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2095096266 |
Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.762928320 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 777460347 ps |
CPU time | 97.96 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:10:02 PM PDT 24 |
Peak memory | 206844 kb |
Host | smart-3ea1f125-d532-4014-afcf-d28c1fdb1840 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762928320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand _reset.762928320 |
Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3006389220 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 14330024281 ps |
CPU time | 99.66 seconds |
Started | Aug 05 05:06:38 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202124 kb |
Host | smart-eed3dad7-0551-4b2c-a95c-007613102e50 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3006389220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3006389220 |
Directory | /workspace/12.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2534574077 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 83145095371 ps |
CPU time | 348.99 seconds |
Started | Aug 05 05:06:23 PM PDT 24 |
Finished | Aug 05 05:12:12 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-a27140b8-3205-4efb-9dc2-30042ab53826 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2534574077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2534574077 |
Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3496141413 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 7517443277 ps |
CPU time | 237.97 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:10:34 PM PDT 24 |
Peak memory | 208876 kb |
Host | smart-f128e2d2-ad3f-45fd-97db-2284acc2ee4f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3496141413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.3496141413 |
Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1789710791 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 5365955635 ps |
CPU time | 67.71 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:08:30 PM PDT 24 |
Peak memory | 204396 kb |
Host | smart-75c0da7c-60ad-48da-b41b-50003640e83f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1789710791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1789710791 |
Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2895540902 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 855125121 ps |
CPU time | 71.7 seconds |
Started | Aug 05 05:06:21 PM PDT 24 |
Finished | Aug 05 05:07:33 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-13fb37e5-978f-474c-bd11-3ea109814d96 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895540902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2895540902 |
Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1794078339 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 39667767478 ps |
CPU time | 281.07 seconds |
Started | Aug 05 05:07:37 PM PDT 24 |
Finished | Aug 05 05:12:18 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-1cc7d059-5743-4a7d-82eb-ee86986242fe |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1794078339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1794078339 |
Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1854054546 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 5785007825 ps |
CPU time | 9.65 seconds |
Started | Aug 05 05:05:58 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 202108 kb |
Host | smart-1ff5a284-8dc7-47f7-b5d1-d4ca24f579c2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854054546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1854054546 |
Directory | /workspace/0.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3560211981 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1362440638 ps |
CPU time | 166.63 seconds |
Started | Aug 05 05:06:18 PM PDT 24 |
Finished | Aug 05 05:09:05 PM PDT 24 |
Peak memory | 206176 kb |
Host | smart-2b997c93-8eb1-483e-b116-f198ac7b37aa |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3560211981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.3560211981 |
Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.173257712 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 37369834361 ps |
CPU time | 250.87 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:12:11 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-643ca681-d4cf-4055-8508-097d26bb6e6a |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=173257712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo w_rsp.173257712 |
Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3957068661 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2876890416 ps |
CPU time | 142.23 seconds |
Started | Aug 05 05:06:20 PM PDT 24 |
Finished | Aug 05 05:08:42 PM PDT 24 |
Peak memory | 205716 kb |
Host | smart-5435a934-2b6d-426c-84d2-c0e9401c4898 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3957068661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3957068661 |
Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.4096152134 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 7012986120 ps |
CPU time | 160.73 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:10:24 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-a8ae89a0-fb13-47fc-befb-0d5c82610405 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096152134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.4096152134 |
Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1636785484 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 2507975344 ps |
CPU time | 27.9 seconds |
Started | Aug 05 05:08:15 PM PDT 24 |
Finished | Aug 05 05:08:43 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-d5d94f03-65f9-43be-bf12-212f132618fa |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636785484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1636785484 |
Directory | /workspace/49.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.14019452 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 27800068022 ps |
CPU time | 105.58 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:09:16 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-e152404d-2c39-48ab-a477-ccacd968bbe2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=14019452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow _rsp.14019452 |
Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2339312644 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2400273603 ps |
CPU time | 49.74 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-ea50b687-ed87-4f1a-8740-bc919f9ca304 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2339312644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.2339312644 |
Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3822444574 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 4381698720 ps |
CPU time | 135.82 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:08:45 PM PDT 24 |
Peak memory | 206360 kb |
Host | smart-21e7db15-e0c9-47e0-bd35-b4e37b0605a2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3822444574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3822444574 |
Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.462280566 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 40830513000 ps |
CPU time | 276.65 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:12:23 PM PDT 24 |
Peak memory | 203596 kb |
Host | smart-c50217ca-6e22-44c9-aa06-f60266e762f3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=462280566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo w_rsp.462280566 |
Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1876279647 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 353597312 ps |
CPU time | 46.68 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:47 PM PDT 24 |
Peak memory | 204408 kb |
Host | smart-2f730b00-0d5d-447a-bad5-c543623be5e9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1876279647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.1876279647 |
Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1483247335 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 3756543918 ps |
CPU time | 82.9 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 204532 kb |
Host | smart-90a61346-84f3-426d-b30c-2aa4721666dd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1483247335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1483247335 |
Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.901883045 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 13127920272 ps |
CPU time | 101.64 seconds |
Started | Aug 05 05:06:39 PM PDT 24 |
Finished | Aug 05 05:08:21 PM PDT 24 |
Peak memory | 202196 kb |
Host | smart-0ecc3e03-bfab-4390-bc7e-1eb8055a6365 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=901883045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo w_rsp.901883045 |
Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2410145635 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 2300436322 ps |
CPU time | 18.67 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-4282a71a-7dad-43cd-8798-df5aad70df5e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2410145635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2410145635 |
Directory | /workspace/0.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.402817052 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 66259603694 ps |
CPU time | 296.76 seconds |
Started | Aug 05 05:06:22 PM PDT 24 |
Finished | Aug 05 05:11:18 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-78ceed38-916a-4d48-a3ad-29cdbd1a2aa2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=402817052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.402817052 |
Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3121697783 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 235885329 ps |
CPU time | 3.67 seconds |
Started | Aug 05 05:06:02 PM PDT 24 |
Finished | Aug 05 05:06:06 PM PDT 24 |
Peak memory | 202056 kb |
Host | smart-2b2796ee-8b33-41c7-bc58-cc68e48f59d8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3121697783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3121697783 |
Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.780256626 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 37402155 ps |
CPU time | 2.9 seconds |
Started | Aug 05 05:06:01 PM PDT 24 |
Finished | Aug 05 05:06:05 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-b2410aab-3921-45dc-b02e-b501fb2363a3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=780256626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.780256626 |
Directory | /workspace/0.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.3551184264 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 1171739483 ps |
CPU time | 9.04 seconds |
Started | Aug 05 05:05:57 PM PDT 24 |
Finished | Aug 05 05:06:06 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-f2d15c1a-920c-46ac-8243-25adbd443514 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3551184264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3551184264 |
Directory | /workspace/0.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3425781589 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 135188668414 ps |
CPU time | 150.35 seconds |
Started | Aug 05 05:06:04 PM PDT 24 |
Finished | Aug 05 05:08:35 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-dab2c343-6522-45ce-b9ed-412ffb62494c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425781589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3425781589 |
Directory | /workspace/0.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1593239036 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 3087362872 ps |
CPU time | 18.97 seconds |
Started | Aug 05 05:05:57 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-3cb901bc-692b-4c95-93cc-3a74b8b5b9f6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1593239036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1593239036 |
Directory | /workspace/0.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2321525281 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 118589561 ps |
CPU time | 6.53 seconds |
Started | Aug 05 05:06:04 PM PDT 24 |
Finished | Aug 05 05:06:11 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-173f2ea5-1107-4f8c-9d98-05f318fb524d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321525281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2321525281 |
Directory | /workspace/0.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2193105111 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 68847571 ps |
CPU time | 1.71 seconds |
Started | Aug 05 05:06:14 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-1ce2dee2-ec70-421d-b5b8-00ad51bfa278 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2193105111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2193105111 |
Directory | /workspace/0.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.2581466942 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 13316784 ps |
CPU time | 1.14 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:06:14 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-43299372-3900-4669-a841-5498dea20a72 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581466942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2581466942 |
Directory | /workspace/0.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3807650174 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 499266653 ps |
CPU time | 4.25 seconds |
Started | Aug 05 05:05:58 PM PDT 24 |
Finished | Aug 05 05:06:03 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-5ed91d1c-c1e3-45b6-97ad-260bc9b938de |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3807650174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3807650174 |
Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1816595424 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 14704774 ps |
CPU time | 1.16 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-f8b41c50-e5f1-4564-b520-a8e30429dd0d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816595424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1816595424 |
Directory | /workspace/0.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2426745616 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 5335816889 ps |
CPU time | 65.25 seconds |
Started | Aug 05 05:06:12 PM PDT 24 |
Finished | Aug 05 05:07:17 PM PDT 24 |
Peak memory | 204064 kb |
Host | smart-c9777f47-eb1c-4ea7-af94-ee10d26d6ae7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426745616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2426745616 |
Directory | /workspace/0.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3494076597 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2387102209 ps |
CPU time | 10.2 seconds |
Started | Aug 05 05:06:23 PM PDT 24 |
Finished | Aug 05 05:06:33 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-3fde9b8a-5351-4aa6-b6b3-27acc18fe66b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3494076597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3494076597 |
Directory | /workspace/0.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1378843784 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 1831816482 ps |
CPU time | 83.21 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:07:24 PM PDT 24 |
Peak memory | 206400 kb |
Host | smart-f0b1e9d1-07f3-4640-b7da-205c495ed996 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378843784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1378843784 |
Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.809106550 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 412392656 ps |
CPU time | 32.54 seconds |
Started | Aug 05 05:06:08 PM PDT 24 |
Finished | Aug 05 05:06:45 PM PDT 24 |
Peak memory | 203460 kb |
Host | smart-38b52edc-f607-4879-9334-57354c966846 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=809106550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.809106550 |
Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3080758319 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 112401666 ps |
CPU time | 3.25 seconds |
Started | Aug 05 05:06:01 PM PDT 24 |
Finished | Aug 05 05:06:05 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-97039aaf-abfc-4251-9c77-89062751ffe2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080758319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3080758319 |
Directory | /workspace/0.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2898268812 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 152452526 ps |
CPU time | 7.73 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:18 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-beb1c6fe-50cb-4cbd-9b24-fdf3575527e4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2898268812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2898268812 |
Directory | /workspace/1.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.257918990 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 2436382386 ps |
CPU time | 17.74 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:18 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-f53130ae-4954-4baa-88d7-8faaa5f2b8c9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=257918990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.257918990 |
Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.399501064 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 669071998 ps |
CPU time | 4.14 seconds |
Started | Aug 05 05:05:57 PM PDT 24 |
Finished | Aug 05 05:06:02 PM PDT 24 |
Peak memory | 202288 kb |
Host | smart-cf1e8440-5a59-4342-b227-93c031b85d4d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=399501064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.399501064 |
Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.2564211939 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 741726295 ps |
CPU time | 13.17 seconds |
Started | Aug 05 05:06:18 PM PDT 24 |
Finished | Aug 05 05:06:31 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-2a867088-045b-4f48-b76b-b54c1aeaa580 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2564211939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2564211939 |
Directory | /workspace/1.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2669559869 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 93417566 ps |
CPU time | 2.19 seconds |
Started | Aug 05 05:06:04 PM PDT 24 |
Finished | Aug 05 05:06:06 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-fc6238c2-bbdb-4e92-bbac-67ed7751caef |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2669559869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2669559869 |
Directory | /workspace/1.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.4051246506 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 10391075762 ps |
CPU time | 35.11 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-49839c90-f389-40ed-a718-b0d4ceb48506 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051246506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4051246506 |
Directory | /workspace/1.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1606470757 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 27622130110 ps |
CPU time | 154.89 seconds |
Started | Aug 05 05:06:20 PM PDT 24 |
Finished | Aug 05 05:08:55 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-884576eb-edc5-4580-a710-aaad03bc4ea8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1606470757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1606470757 |
Directory | /workspace/1.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.4054400850 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 198536583 ps |
CPU time | 7.6 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 201916 kb |
Host | smart-85522d8e-2927-4c10-b598-05376376d9f7 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054400850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.4054400850 |
Directory | /workspace/1.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.3921373223 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 120799127 ps |
CPU time | 1.84 seconds |
Started | Aug 05 05:06:21 PM PDT 24 |
Finished | Aug 05 05:06:23 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-41fd1623-d64a-4b32-97ce-8240faf8e03b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3921373223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3921373223 |
Directory | /workspace/1.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3999514732 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 40116002 ps |
CPU time | 1.41 seconds |
Started | Aug 05 05:05:57 PM PDT 24 |
Finished | Aug 05 05:05:59 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-f5fa0cb7-accc-484f-b68c-b34303348bab |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3999514732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3999514732 |
Directory | /workspace/1.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3107401597 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 3464642238 ps |
CPU time | 7.56 seconds |
Started | Aug 05 05:06:01 PM PDT 24 |
Finished | Aug 05 05:06:09 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-81931aeb-d65f-47dc-8839-a3df226c5b5f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107401597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3107401597 |
Directory | /workspace/1.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.701593911 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3152928678 ps |
CPU time | 6.63 seconds |
Started | Aug 05 05:06:38 PM PDT 24 |
Finished | Aug 05 05:06:45 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-11c8dbf1-27da-4dfe-b5e8-4eb30cc9b906 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=701593911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.701593911 |
Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.389763527 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 10407477 ps |
CPU time | 1.13 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:02 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-4df63581-9a48-46ef-9b70-e85792e2359c |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389763527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.389763527 |
Directory | /workspace/1.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1792126157 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 2553003253 ps |
CPU time | 17.91 seconds |
Started | Aug 05 05:06:21 PM PDT 24 |
Finished | Aug 05 05:06:39 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-179f31b8-cf59-4b17-923e-b5d5275b5410 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1792126157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1792126157 |
Directory | /workspace/1.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.856440225 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 153773209 ps |
CPU time | 1.48 seconds |
Started | Aug 05 05:06:03 PM PDT 24 |
Finished | Aug 05 05:06:04 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-0065c26e-1e35-4242-9761-f3714036598e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=856440225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.856440225 |
Directory | /workspace/1.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3247455823 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 4854530438 ps |
CPU time | 134.07 seconds |
Started | Aug 05 05:05:58 PM PDT 24 |
Finished | Aug 05 05:08:12 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-a4aa4fdf-9e9d-41a7-b668-0ce4241459a1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3247455823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.3247455823 |
Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1683007688 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 619085546 ps |
CPU time | 43.11 seconds |
Started | Aug 05 05:05:59 PM PDT 24 |
Finished | Aug 05 05:06:43 PM PDT 24 |
Peak memory | 204196 kb |
Host | smart-3aea6ea6-59cc-42da-8b2b-b0e1d6b76c4d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683007688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1683007688 |
Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.121646472 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 939463980 ps |
CPU time | 4.25 seconds |
Started | Aug 05 05:06:22 PM PDT 24 |
Finished | Aug 05 05:06:26 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-11287fc9-9a55-45f9-abad-2b44d223ff31 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121646472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.121646472 |
Directory | /workspace/1.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3104417727 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 217846910 ps |
CPU time | 7.01 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-14280e09-8cae-44a9-8204-30724657fe63 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3104417727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3104417727 |
Directory | /workspace/10.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1894265287 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 4117438669 ps |
CPU time | 9.98 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:37 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-67c617cb-6f88-48c4-b264-10671ddf9c12 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1894265287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1894265287 |
Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.1095515335 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 76480197 ps |
CPU time | 6.53 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-c947b689-82c6-4cbb-9ba1-a4b2b4aba4cc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1095515335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1095515335 |
Directory | /workspace/10.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.1238375441 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 60865670 ps |
CPU time | 4.54 seconds |
Started | Aug 05 05:06:25 PM PDT 24 |
Finished | Aug 05 05:06:30 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-8db64d76-30eb-42c8-89ab-c93c191e690f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238375441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1238375441 |
Directory | /workspace/10.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1265380563 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 30734353194 ps |
CPU time | 115.13 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:08:41 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-c83d8e64-b438-474e-85dd-4708195c7e6e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265380563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1265380563 |
Directory | /workspace/10.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.969468914 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 16618201298 ps |
CPU time | 112.03 seconds |
Started | Aug 05 05:06:33 PM PDT 24 |
Finished | Aug 05 05:08:25 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-ca475812-f840-4864-925d-61ce59bbba81 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=969468914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.969468914 |
Directory | /workspace/10.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3491256623 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 98883219 ps |
CPU time | 3.67 seconds |
Started | Aug 05 05:06:26 PM PDT 24 |
Finished | Aug 05 05:06:30 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-3c16f3ea-be86-4c22-876b-0ac941b59b9f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491256623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3491256623 |
Directory | /workspace/10.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1226283787 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 139473449 ps |
CPU time | 4.22 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:36 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-5423259e-f26b-4663-9333-1e9bf33ad037 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1226283787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1226283787 |
Directory | /workspace/10.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.1517150427 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 10764351 ps |
CPU time | 1.25 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:32 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-e34a878f-9f8c-43b8-a64b-2b285b8904e4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1517150427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1517150427 |
Directory | /workspace/10.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1249249996 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 2073446053 ps |
CPU time | 10.24 seconds |
Started | Aug 05 05:06:33 PM PDT 24 |
Finished | Aug 05 05:06:43 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-2b917edc-9ba0-4dde-bc4e-aca2a1c59a9f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249249996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1249249996 |
Directory | /workspace/10.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1920857810 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 1662493990 ps |
CPU time | 5.99 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:06:23 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-6bd3415c-a3b7-410b-a971-847380c0941f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1920857810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1920857810 |
Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2792768126 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 9679904 ps |
CPU time | 1.34 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:31 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-8a368aad-e38e-4ffb-8902-996c57fad1e5 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792768126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2792768126 |
Directory | /workspace/10.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.231744835 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 1515048690 ps |
CPU time | 24.38 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 202164 kb |
Host | smart-7af6679b-2cb3-46b7-b72c-e25743e537e4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=231744835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.231744835 |
Directory | /workspace/10.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.693807848 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 2891020690 ps |
CPU time | 28.78 seconds |
Started | Aug 05 05:06:45 PM PDT 24 |
Finished | Aug 05 05:07:13 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-5694b592-1365-4398-89a1-21b67867cb26 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693807848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.693807848 |
Directory | /workspace/10.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.4085546709 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 2696759289 ps |
CPU time | 92.7 seconds |
Started | Aug 05 05:06:25 PM PDT 24 |
Finished | Aug 05 05:07:58 PM PDT 24 |
Peak memory | 204308 kb |
Host | smart-53fda121-1a1e-4bf7-ba52-55f0d3a47821 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4085546709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.4085546709 |
Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1485001541 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 1635866255 ps |
CPU time | 129.73 seconds |
Started | Aug 05 05:06:38 PM PDT 24 |
Finished | Aug 05 05:08:48 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-7070972b-e32d-4851-a265-b517d0c2f434 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1485001541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1485001541 |
Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2398733125 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 29389444 ps |
CPU time | 1.23 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:33 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-83006540-f571-494e-9761-9af6f8a899ea |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2398733125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2398733125 |
Directory | /workspace/10.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1555843745 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 13919425 ps |
CPU time | 1.5 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:06:56 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-b925bdfb-0d96-46bf-8574-7441837396e9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555843745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1555843745 |
Directory | /workspace/11.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1678554364 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 219210279 ps |
CPU time | 3.12 seconds |
Started | Aug 05 05:06:45 PM PDT 24 |
Finished | Aug 05 05:06:49 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-fb2f3302-96ff-48d2-918f-151ae9595bb4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1678554364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1678554364 |
Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2823806465 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 1192253004 ps |
CPU time | 9.65 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-58712e39-68a1-4378-877b-751f9e5f5454 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823806465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2823806465 |
Directory | /workspace/11.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1566807656 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 31033233 ps |
CPU time | 2.51 seconds |
Started | Aug 05 05:06:22 PM PDT 24 |
Finished | Aug 05 05:06:24 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-1c457f05-0173-4cd5-9c34-a9d5f66754a4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1566807656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1566807656 |
Directory | /workspace/11.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2515478279 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 82314310338 ps |
CPU time | 152.3 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:09:09 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-37bdbc93-9470-4175-9df0-c5d90924f025 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515478279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2515478279 |
Directory | /workspace/11.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.435136776 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 28374573694 ps |
CPU time | 83.2 seconds |
Started | Aug 05 05:06:23 PM PDT 24 |
Finished | Aug 05 05:07:47 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-c8dbc050-3628-46be-b40b-49a303656cf2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=435136776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.435136776 |
Directory | /workspace/11.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1943737596 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 145662698 ps |
CPU time | 8.15 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:06:32 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-e243cda3-90eb-4459-a17d-76616179885d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943737596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1943737596 |
Directory | /workspace/11.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.4028739226 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 2214123058 ps |
CPU time | 12.63 seconds |
Started | Aug 05 05:06:25 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-bccc9969-0fcb-46e2-b810-0adf4040061c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4028739226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4028739226 |
Directory | /workspace/11.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3028084793 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 10080078 ps |
CPU time | 1.04 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:06:44 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-21e1aae7-60a2-4163-9f77-71f3d3fed957 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3028084793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3028084793 |
Directory | /workspace/11.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3057140604 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 5796552951 ps |
CPU time | 6.82 seconds |
Started | Aug 05 05:06:25 PM PDT 24 |
Finished | Aug 05 05:06:32 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-fa12dd55-c32b-4ca1-b3b4-80ab612444df |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057140604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3057140604 |
Directory | /workspace/11.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.723599503 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 3640823926 ps |
CPU time | 13.45 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-f2434289-f53c-4643-83b1-08307b50929b |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=723599503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.723599503 |
Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.569548716 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 9451590 ps |
CPU time | 1.29 seconds |
Started | Aug 05 05:06:22 PM PDT 24 |
Finished | Aug 05 05:06:23 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-af20e4e6-c219-4b67-8c30-110fb8824db5 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569548716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.569548716 |
Directory | /workspace/11.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2798419390 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 65023143 ps |
CPU time | 7.13 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:36 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-5c8bf64d-2c4d-4c0c-b037-975a1ca8918a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2798419390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2798419390 |
Directory | /workspace/11.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1427429804 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 89244758 ps |
CPU time | 10.95 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:06:54 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-18c469b2-b666-49d9-920c-ffb34ba995f3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1427429804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1427429804 |
Directory | /workspace/11.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1272146484 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 103261531 ps |
CPU time | 7.84 seconds |
Started | Aug 05 05:06:41 PM PDT 24 |
Finished | Aug 05 05:06:49 PM PDT 24 |
Peak memory | 202240 kb |
Host | smart-b842d328-6d1b-45ef-ad8e-d6fb3594ecb3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1272146484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1272146484 |
Directory | /workspace/11.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2337392081 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 90287176 ps |
CPU time | 11.28 seconds |
Started | Aug 05 05:06:37 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-1932c3d5-1e93-4f9f-a3f5-6774562a683c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2337392081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2337392081 |
Directory | /workspace/12.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2483379021 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 104891388935 ps |
CPU time | 128.26 seconds |
Started | Aug 05 05:06:42 PM PDT 24 |
Finished | Aug 05 05:08:50 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-ea230e6b-9722-4d79-8865-165d0f411d0a |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2483379021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2483379021 |
Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.424630604 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 760175113 ps |
CPU time | 3.38 seconds |
Started | Aug 05 05:06:34 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-c82bdf67-9a54-40f9-bbc3-2462cf05b686 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424630604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.424630604 |
Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.2483801372 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 846833968 ps |
CPU time | 7.1 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:36 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-632c1d0d-599d-4f5e-b9d9-25023cff1d19 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2483801372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2483801372 |
Directory | /workspace/12.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2089272342 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 43957094 ps |
CPU time | 5 seconds |
Started | Aug 05 05:06:35 PM PDT 24 |
Finished | Aug 05 05:06:40 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-777ff7c9-dee1-4a7c-b54f-ff9eba7aa8bd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2089272342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2089272342 |
Directory | /workspace/12.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2923697450 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 59387169803 ps |
CPU time | 153.22 seconds |
Started | Aug 05 05:06:33 PM PDT 24 |
Finished | Aug 05 05:09:07 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-5e6721bd-a370-413e-b67f-3ef2086ca5a8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923697450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2923697450 |
Directory | /workspace/12.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.188824232 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 253501621 ps |
CPU time | 6.79 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:37 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-069d325a-e378-4052-9030-1c3fd8240396 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188824232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.188824232 |
Directory | /workspace/12.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.4040590046 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 121173533 ps |
CPU time | 5.75 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-f5087491-31aa-4921-9d62-efa82c1c1039 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040590046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4040590046 |
Directory | /workspace/12.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.1161723815 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 8190831 ps |
CPU time | 0.99 seconds |
Started | Aug 05 05:06:42 PM PDT 24 |
Finished | Aug 05 05:06:43 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-f398513a-df53-42f4-965e-4f008a46670a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1161723815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1161723815 |
Directory | /workspace/12.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1436932424 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 2342954922 ps |
CPU time | 10.05 seconds |
Started | Aug 05 05:06:45 PM PDT 24 |
Finished | Aug 05 05:06:55 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-aabd4a85-43a9-4a32-9fdb-de7b78efeddf |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436932424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1436932424 |
Directory | /workspace/12.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.4092580623 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2179334370 ps |
CPU time | 6.04 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:06:55 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-8072e67c-47b9-44f4-a9bf-0faaa6f142d3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4092580623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4092580623 |
Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1949513083 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 13796571 ps |
CPU time | 1.32 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-d166d143-c500-430c-8b14-5c7d7e72a12d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949513083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1949513083 |
Directory | /workspace/12.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3989570202 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 2723844793 ps |
CPU time | 61.01 seconds |
Started | Aug 05 05:06:34 PM PDT 24 |
Finished | Aug 05 05:07:36 PM PDT 24 |
Peak memory | 204492 kb |
Host | smart-3e2f933e-470e-4866-85ea-9ba96fe1c7bd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3989570202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3989570202 |
Directory | /workspace/12.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3772349415 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 4124267801 ps |
CPU time | 51.25 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-dc8e0aac-f2c1-478d-b358-22af32234626 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3772349415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3772349415 |
Directory | /workspace/12.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3366611306 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 256787747 ps |
CPU time | 22.76 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:50 PM PDT 24 |
Peak memory | 203496 kb |
Host | smart-07193d34-136c-4f20-8e1b-2016bf5b59b8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3366611306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3366611306 |
Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1794808679 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 253872611 ps |
CPU time | 1.93 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:49 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-812061ff-3a3d-4fdb-8d38-8bebc99829ba |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1794808679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1794808679 |
Directory | /workspace/12.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.458364897 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 329925512 ps |
CPU time | 6.92 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-37e8a6fc-e4fd-4de8-a873-a2359ce076d1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=458364897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.458364897 |
Directory | /workspace/13.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.4209819874 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 16294561 ps |
CPU time | 1.4 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:31 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-c8a23695-e874-426f-a9a8-41c8ce5eaac5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4209819874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4209819874 |
Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.1597735661 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 97543096 ps |
CPU time | 1.36 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:30 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-ef4ff13e-9ee1-4099-8602-60db437e68db |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1597735661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1597735661 |
Directory | /workspace/13.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.2908015344 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 201354021 ps |
CPU time | 6.08 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-e3420f80-a8f1-41c8-a2ef-559019702fd4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2908015344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2908015344 |
Directory | /workspace/13.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2433931403 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 2605160830 ps |
CPU time | 11.42 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-d15934f1-2d9a-4f31-8e6c-4d5f3c7c7e2c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433931403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2433931403 |
Directory | /workspace/13.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2876747073 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 33525427011 ps |
CPU time | 94.86 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 201644 kb |
Host | smart-3d433c9b-94eb-4f90-87f7-d072178af20b |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2876747073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2876747073 |
Directory | /workspace/13.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2931939433 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 27838467 ps |
CPU time | 2.71 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:33 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-e236e0b5-1e01-454a-9687-f682f972402f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931939433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2931939433 |
Directory | /workspace/13.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.3667762828 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 813088018 ps |
CPU time | 7.02 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:36 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-71eef5d7-b247-4202-b60c-20e31a1a2862 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667762828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3667762828 |
Directory | /workspace/13.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.4161697050 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 133692593 ps |
CPU time | 1.75 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:06:29 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-f083cc67-a73a-44e4-a9ac-301b7090c5b4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4161697050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4161697050 |
Directory | /workspace/13.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2484539824 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 4780191387 ps |
CPU time | 10.47 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:39 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-89689ead-f5c0-4f2d-81a0-b62db76b01b0 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484539824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2484539824 |
Directory | /workspace/13.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1225787449 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 1266864809 ps |
CPU time | 7.56 seconds |
Started | Aug 05 05:06:35 PM PDT 24 |
Finished | Aug 05 05:06:42 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-25fedd1a-f78c-433d-a309-1fc2e1653a4c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1225787449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1225787449 |
Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2198612931 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 13530184 ps |
CPU time | 1.13 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:33 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-5b257dfd-fcb6-4d8a-9f10-b4524e4aae3a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198612931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2198612931 |
Directory | /workspace/13.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3819070285 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 9843225617 ps |
CPU time | 79.07 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:07:48 PM PDT 24 |
Peak memory | 204288 kb |
Host | smart-f5691a54-bb9b-452f-90e2-0beaf4f6d656 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3819070285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3819070285 |
Directory | /workspace/13.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3942755994 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 5932676354 ps |
CPU time | 79.48 seconds |
Started | Aug 05 05:06:34 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 201632 kb |
Host | smart-c5a6f482-efca-42a4-9eb4-be30e12fc9ed |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3942755994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3942755994 |
Directory | /workspace/13.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.163673888 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 2196709181 ps |
CPU time | 43.49 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:07:13 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-49c6e188-802d-4610-8d40-e85ebe57632d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=163673888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.163673888 |
Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2110385846 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 4006950478 ps |
CPU time | 43.09 seconds |
Started | Aug 05 05:06:41 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 203372 kb |
Host | smart-85f008b8-64c5-4816-bb47-c9aefd1a1d48 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2110385846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.2110385846 |
Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2349267101 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 53271236 ps |
CPU time | 6.96 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 201892 kb |
Host | smart-c9657c02-a250-4bc6-86b3-adccf107cb88 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2349267101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2349267101 |
Directory | /workspace/13.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1992774937 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 32488016 ps |
CPU time | 5.07 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:06:41 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-dd21fb68-1dad-4203-a17a-b90b34add93f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1992774937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1992774937 |
Directory | /workspace/14.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3604051629 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 23463109217 ps |
CPU time | 34.57 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-fecb20f0-ef60-44aa-92ef-e51ee64349fb |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3604051629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3604051629 |
Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3859393792 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 3467663673 ps |
CPU time | 10.73 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:06:39 PM PDT 24 |
Peak memory | 202056 kb |
Host | smart-540b2137-8d95-4337-a255-569e8aa1776b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859393792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3859393792 |
Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.4288118931 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 47680529 ps |
CPU time | 3.32 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-8abdad6b-d056-46fc-a05d-d1a5d8075a95 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4288118931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4288118931 |
Directory | /workspace/14.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.4112671578 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 406888406 ps |
CPU time | 1.9 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-f01c5082-95ff-4301-a4e3-b82c8bd0e5d2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4112671578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.4112671578 |
Directory | /workspace/14.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2739655082 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 18099157267 ps |
CPU time | 64.38 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-c3f1554e-8459-4172-8a74-4029c55e84e7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739655082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2739655082 |
Directory | /workspace/14.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3058922288 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2976916439 ps |
CPU time | 12.14 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202136 kb |
Host | smart-f24f08e0-76eb-44d2-92e2-55cf292964ee |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3058922288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3058922288 |
Directory | /workspace/14.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1219109622 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 56190286 ps |
CPU time | 5.82 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:01 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-13a0b290-61bc-4584-9f69-ca3edefb8414 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219109622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1219109622 |
Directory | /workspace/14.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.2040704115 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 3259681854 ps |
CPU time | 10.08 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:07:01 PM PDT 24 |
Peak memory | 202056 kb |
Host | smart-d8aac9a1-163e-4c92-915d-afe0f13e1829 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2040704115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2040704115 |
Directory | /workspace/14.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.4091462415 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 63696034 ps |
CPU time | 1.36 seconds |
Started | Aug 05 05:06:34 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-ddd479df-2549-4171-b488-959360956636 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091462415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4091462415 |
Directory | /workspace/14.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3793012453 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 9996230264 ps |
CPU time | 11.65 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-932fd2b4-a676-4b1a-895c-f85a8ee33b04 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793012453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3793012453 |
Directory | /workspace/14.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2276866160 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 6339540562 ps |
CPU time | 8.26 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:39 PM PDT 24 |
Peak memory | 202140 kb |
Host | smart-2d4f9626-5298-42bd-a395-d27c00232ee1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2276866160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2276866160 |
Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3509822588 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 20624935 ps |
CPU time | 1.08 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:06:47 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-a44d314d-b895-4654-a30c-a58d3808ea4b |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509822588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3509822588 |
Directory | /workspace/14.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.1265396074 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 2173735423 ps |
CPU time | 32.45 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:07:23 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-1e3666ed-1823-4398-9830-77b399498bed |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1265396074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1265396074 |
Directory | /workspace/14.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3110130836 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 14256171 ps |
CPU time | 1.18 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:06:51 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-4cff57f1-20a2-4716-95c0-ae2bc6809a25 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3110130836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3110130836 |
Directory | /workspace/14.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1324074352 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 416101406 ps |
CPU time | 6.18 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-2d8aabf3-1976-4935-b17c-012dc99f4e85 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1324074352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1324074352 |
Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.562781886 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 358339376 ps |
CPU time | 62.36 seconds |
Started | Aug 05 05:06:41 PM PDT 24 |
Finished | Aug 05 05:07:44 PM PDT 24 |
Peak memory | 206096 kb |
Host | smart-eda224fd-ac16-4a69-aeda-5fc67b794676 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=562781886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.562781886 |
Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.898251837 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 707693853 ps |
CPU time | 5.14 seconds |
Started | Aug 05 05:06:48 PM PDT 24 |
Finished | Aug 05 05:06:53 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-fabeae79-33f1-461b-88e6-dfd3358debab |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=898251837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.898251837 |
Directory | /workspace/14.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.4004440495 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 89372684 ps |
CPU time | 5.14 seconds |
Started | Aug 05 05:06:40 PM PDT 24 |
Finished | Aug 05 05:06:46 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-26c8075d-dec1-4115-982d-af622175ba43 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4004440495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.4004440495 |
Directory | /workspace/15.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.4233760884 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 56437553461 ps |
CPU time | 176.43 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:09:48 PM PDT 24 |
Peak memory | 203400 kb |
Host | smart-5661259c-3708-40e6-bc32-d07ae660617f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4233760884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.4233760884 |
Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1777269336 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 47519472 ps |
CPU time | 1.47 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:06:45 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-ccf34b97-c831-48d6-8cdf-fc36369c3b55 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1777269336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1777269336 |
Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.357441930 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 489258879 ps |
CPU time | 4.08 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-d2e5a7d7-16c8-4c5b-9b8d-ebaad7c01162 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=357441930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.357441930 |
Directory | /workspace/15.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.191762166 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 65495523 ps |
CPU time | 8.62 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-550e4736-cd14-4935-b65c-b4c4ee34d806 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=191762166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.191762166 |
Directory | /workspace/15.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.434994037 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 43144246425 ps |
CPU time | 107.75 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:08:38 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-a91db940-4691-47e7-aec3-d92d3d920fe7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=434994037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.434994037 |
Directory | /workspace/15.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3470450750 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 27657806877 ps |
CPU time | 71.46 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202136 kb |
Host | smart-f6771222-8868-4aa6-86d7-a47872f77f7b |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3470450750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3470450750 |
Directory | /workspace/15.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3823787939 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 68904117 ps |
CPU time | 2.54 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-03463af7-c94e-4db4-b243-9e4b210749a3 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823787939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3823787939 |
Directory | /workspace/15.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3842675634 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 204462985 ps |
CPU time | 3.32 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:06:47 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-ab653adb-3829-45f9-900d-7f61b0f289dc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3842675634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3842675634 |
Directory | /workspace/15.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.563431330 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 9577012 ps |
CPU time | 1.01 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-5e8f5287-6a4d-4708-9a8d-f2c883b47a74 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=563431330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.563431330 |
Directory | /workspace/15.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3571463724 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 3427460734 ps |
CPU time | 6.99 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-a3086f9d-4511-4962-9ca1-b69b31411931 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571463724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3571463724 |
Directory | /workspace/15.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1045915563 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 2231738426 ps |
CPU time | 5.08 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:06:49 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-a09488b8-3a13-4b52-a183-4e190473b49b |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1045915563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1045915563 |
Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.392634488 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 9085375 ps |
CPU time | 1.14 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 201980 kb |
Host | smart-ef599785-d507-4641-b9d3-465d5e2263aa |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392634488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.392634488 |
Directory | /workspace/15.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2198554578 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 14169622572 ps |
CPU time | 73.9 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 203780 kb |
Host | smart-6a9e2266-dd57-46b8-9a00-1f9aa10c6300 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2198554578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2198554578 |
Directory | /workspace/15.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3384190489 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 493277456 ps |
CPU time | 30.04 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-8468fc46-f4a2-493b-b580-5ecf54fac8aa |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384190489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3384190489 |
Directory | /workspace/15.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2381464674 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 5463678593 ps |
CPU time | 167.67 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:09:38 PM PDT 24 |
Peak memory | 208168 kb |
Host | smart-a07256e0-8c9e-413d-8015-a03305728427 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2381464674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2381464674 |
Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1948137622 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 1654042393 ps |
CPU time | 37.28 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:07:24 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-5fc87ac6-aa69-4703-8fad-ff4fc6681f45 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1948137622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1948137622 |
Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3871006819 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 512993917 ps |
CPU time | 3.32 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:06:53 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-65fdb018-4ed7-47b4-9d61-a580e2623b34 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3871006819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3871006819 |
Directory | /workspace/15.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2362488915 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 42230240 ps |
CPU time | 5.54 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:53 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-9632fa13-45fc-4b10-9707-7232528d2edf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2362488915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2362488915 |
Directory | /workspace/16.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.584539929 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 25267802351 ps |
CPU time | 195.2 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:10:13 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-ebc3ce24-aa7d-4215-b693-915c350904c1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=584539929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.584539929 |
Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.613141636 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 184156617 ps |
CPU time | 3.52 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-58fe5c55-ce5d-4c4a-b42b-7ab593aa40f2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=613141636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.613141636 |
Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.4017614288 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 4079409165 ps |
CPU time | 12.93 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-8306535b-19b4-47dc-ac0b-4cfd4050bde7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4017614288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.4017614288 |
Directory | /workspace/16.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1509379082 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 9010309 ps |
CPU time | 1.23 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-4f1f3247-b6ae-4d92-9e8c-959ceab264fc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1509379082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1509379082 |
Directory | /workspace/16.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1553941093 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 19487259351 ps |
CPU time | 53.89 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:07:43 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-db604344-9cc8-47e5-a9bc-ca2506868e91 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553941093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1553941093 |
Directory | /workspace/16.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1252603189 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 22546405563 ps |
CPU time | 74.22 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-6e0e2098-7878-42b9-8263-d2e521eee692 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1252603189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1252603189 |
Directory | /workspace/16.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3467609978 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 96298967 ps |
CPU time | 3.35 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:50 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-ba5245df-b6bd-471d-8d8b-d82e16accca8 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467609978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3467609978 |
Directory | /workspace/16.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1834786117 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 727465290 ps |
CPU time | 9.68 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-a0a4855b-3173-4637-b1ae-f23b353f646a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834786117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1834786117 |
Directory | /workspace/16.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.472282094 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 8788661 ps |
CPU time | 1.16 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-04875493-48e9-40e9-9377-f7a1cc0287fe |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=472282094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.472282094 |
Directory | /workspace/16.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3209307401 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 2712234673 ps |
CPU time | 6.22 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-d28339aa-fef6-40c8-8baf-95d424e7bcbb |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209307401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3209307401 |
Directory | /workspace/16.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.452591607 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 834216729 ps |
CPU time | 6.47 seconds |
Started | Aug 05 05:06:48 PM PDT 24 |
Finished | Aug 05 05:06:55 PM PDT 24 |
Peak memory | 202116 kb |
Host | smart-d43fb69e-4ec9-4a01-bfb7-a1f3cb53b1b1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=452591607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.452591607 |
Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.4019121671 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 10264487 ps |
CPU time | 1.33 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-8ec6aa16-7d46-4a9f-969c-210a96a883a8 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019121671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4019121671 |
Directory | /workspace/16.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1492250852 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 26632093 ps |
CPU time | 2.3 seconds |
Started | Aug 05 05:07:04 PM PDT 24 |
Finished | Aug 05 05:07:06 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-bd87208e-40b2-4913-b8a8-20c3ebae9cf1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492250852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1492250852 |
Directory | /workspace/16.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2883169414 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 8290595350 ps |
CPU time | 121.21 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:08:59 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-61a6c6fa-cf6e-48fd-8d07-c6b2b329285c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2883169414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.2883169414 |
Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4077170855 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 339198825 ps |
CPU time | 39.46 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 204032 kb |
Host | smart-668ab781-e2f6-436b-ad33-8e4fe640421a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4077170855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.4077170855 |
Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3499237174 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 9543598 ps |
CPU time | 1.02 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:06:56 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-8b31298f-ea6a-4587-843a-bd6c495fc2e4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499237174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3499237174 |
Directory | /workspace/16.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2301185247 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 331054888 ps |
CPU time | 9.54 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:56 PM PDT 24 |
Peak memory | 201880 kb |
Host | smart-de2f3048-9294-47e6-9971-a8711c16ef25 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301185247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2301185247 |
Directory | /workspace/17.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3021135974 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 111505207830 ps |
CPU time | 93.35 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:08:35 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-aba168d2-6697-4714-a937-b0deea037f11 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3021135974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3021135974 |
Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1443943216 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 116372407 ps |
CPU time | 2.55 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-897f8b72-327a-449d-9e27-6e892565f285 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1443943216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1443943216 |
Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.3186394404 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 785278416 ps |
CPU time | 8.95 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:07:02 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-e25ecc79-fa21-43c7-ba86-2753d91d126b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3186394404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3186394404 |
Directory | /workspace/17.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.1380181632 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 94884899 ps |
CPU time | 5.27 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:06:50 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-e828489a-e27c-4392-ac82-bafa2b77396f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1380181632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1380181632 |
Directory | /workspace/17.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1546316890 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 38843191141 ps |
CPU time | 141.78 seconds |
Started | Aug 05 05:06:42 PM PDT 24 |
Finished | Aug 05 05:09:04 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-daaad24b-c5a1-4294-abc7-a229ccd076d3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546316890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1546316890 |
Directory | /workspace/17.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.718967106 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 77267497216 ps |
CPU time | 67.32 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 202116 kb |
Host | smart-9d36fb3e-3ae4-40c9-b5cc-7c18ff75a1e6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=718967106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.718967106 |
Directory | /workspace/17.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3474567610 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 86765934 ps |
CPU time | 6.22 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:06:56 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-a29e0945-ebd2-415e-9409-6a433aadd65c |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474567610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3474567610 |
Directory | /workspace/17.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.252421889 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 462687372 ps |
CPU time | 4.1 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:06:56 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-c8da109c-650c-4641-b0df-9bba867d8db5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=252421889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.252421889 |
Directory | /workspace/17.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.3103146170 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 80015096 ps |
CPU time | 1.29 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-dbbbdd56-b4a4-46da-b6b1-82251dd722d5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3103146170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3103146170 |
Directory | /workspace/17.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3750028354 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 5384147268 ps |
CPU time | 9.46 seconds |
Started | Aug 05 05:06:48 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-a6433a18-e8f4-4043-9bc1-4665113b742d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750028354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3750028354 |
Directory | /workspace/17.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1420988006 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 2057105206 ps |
CPU time | 10.03 seconds |
Started | Aug 05 05:06:44 PM PDT 24 |
Finished | Aug 05 05:06:54 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-55d5327a-bfce-493d-82d7-5ed08ff21f25 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1420988006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1420988006 |
Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.75324906 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 11091523 ps |
CPU time | 1.37 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:49 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-df8f78d4-05fb-405a-b078-ca24710faaf9 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75324906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.75324906 |
Directory | /workspace/17.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3647055456 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 9223428029 ps |
CPU time | 99.79 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:08:32 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-07e8566c-6a0b-45aa-8cac-b67ab679cae9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3647055456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3647055456 |
Directory | /workspace/17.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.602133842 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 99610386 ps |
CPU time | 9.58 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:07:04 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-68879f61-fb71-4090-94b3-b9d57afa5ca9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=602133842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.602133842 |
Directory | /workspace/17.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1903886538 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 1513083425 ps |
CPU time | 38.99 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 204132 kb |
Host | smart-ff030550-611d-4992-882c-113681ff4cdb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1903886538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1903886538 |
Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2610514654 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 728032781 ps |
CPU time | 88.43 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:08:21 PM PDT 24 |
Peak memory | 204052 kb |
Host | smart-8fdf6606-0fa5-4c64-bb07-2f832d14e8f5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610514654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.2610514654 |
Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1909464729 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 621089989 ps |
CPU time | 8.56 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-de1a3202-b51f-41d8-a1d7-2ada94f51ca6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909464729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1909464729 |
Directory | /workspace/17.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1741198999 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 81690572 ps |
CPU time | 9.13 seconds |
Started | Aug 05 05:06:48 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-6e0df6dc-eece-4ecc-98af-f3a7dbad1044 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1741198999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1741198999 |
Directory | /workspace/18.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.206304669 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 194452035383 ps |
CPU time | 177.57 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:09:48 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-c18070f7-0ffb-4f00-a37c-5cd2a3e19db9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=206304669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo w_rsp.206304669 |
Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3891513719 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 942666222 ps |
CPU time | 5.66 seconds |
Started | Aug 05 05:06:58 PM PDT 24 |
Finished | Aug 05 05:07:04 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-42211647-d9f0-44c2-bc0e-11d697103919 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3891513719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3891513719 |
Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3713615547 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 36237167 ps |
CPU time | 5.06 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-910782cf-df4e-4534-9bd0-90d52ba1e292 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3713615547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3713615547 |
Directory | /workspace/18.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.3317810911 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 112957028 ps |
CPU time | 2.43 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:50 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-829b1e5d-8aae-4594-9078-40624893fd2e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3317810911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3317810911 |
Directory | /workspace/18.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.622009854 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 24584071347 ps |
CPU time | 75.48 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:08:10 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-488416ee-5818-48ac-bb4d-d0689c0e77eb |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=622009854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.622009854 |
Directory | /workspace/18.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.4198217872 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 59170606406 ps |
CPU time | 149.42 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:09:20 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-0ef11f4c-7ff3-4731-97fe-8cb0c7ebef1b |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4198217872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4198217872 |
Directory | /workspace/18.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1003186896 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 196967485 ps |
CPU time | 5.8 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-4ec1e129-c56e-4438-831b-2b74b5b6f602 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003186896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1003186896 |
Directory | /workspace/18.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.2425433756 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 79078713 ps |
CPU time | 1.86 seconds |
Started | Aug 05 05:06:58 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-63ec53d0-78ff-4c65-88f6-5141a341ae8b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2425433756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2425433756 |
Directory | /workspace/18.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.778594912 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 66790037 ps |
CPU time | 1.67 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-18c5e78f-36ff-449d-904a-da07185ee273 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=778594912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.778594912 |
Directory | /workspace/18.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.659517828 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 3494817449 ps |
CPU time | 10.06 seconds |
Started | Aug 05 05:06:48 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-4cc4b5a9-0f11-474c-af18-348ec0370177 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=659517828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.659517828 |
Directory | /workspace/18.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.680300742 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 1331341617 ps |
CPU time | 8.1 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-20ddaf15-711d-44f5-b99e-d9cc976c4499 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=680300742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.680300742 |
Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2499414421 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 17858663 ps |
CPU time | 1.36 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-9df5e2ea-d1a4-4847-99bc-fb0c4906d2cc |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499414421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2499414421 |
Directory | /workspace/18.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.4239735411 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 672320457 ps |
CPU time | 36.51 seconds |
Started | Aug 05 05:07:09 PM PDT 24 |
Finished | Aug 05 05:07:45 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-488eed8a-8eed-4e37-be8b-872852b97ad5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4239735411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4239735411 |
Directory | /workspace/18.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2115280470 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 609151509 ps |
CPU time | 5.07 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-1ec51206-0615-4778-ad7b-53c17a9004a9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2115280470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2115280470 |
Directory | /workspace/18.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1547614179 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 637884593 ps |
CPU time | 56.24 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:08:02 PM PDT 24 |
Peak memory | 204532 kb |
Host | smart-dc0a2d1c-f089-456d-9a55-ff20dbc2c170 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1547614179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.1547614179 |
Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.412865534 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 918056807 ps |
CPU time | 112.92 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:08:43 PM PDT 24 |
Peak memory | 203924 kb |
Host | smart-fb676113-7149-4ac3-8809-aa972eabd908 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=412865534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.412865534 |
Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.812617291 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 10399934 ps |
CPU time | 1.12 seconds |
Started | Aug 05 05:06:50 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-b7e9fe27-0853-4c90-a784-82008d469d9c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812617291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.812617291 |
Directory | /workspace/18.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2131068223 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 8856740 ps |
CPU time | 1.29 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:07:08 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-7f5b6049-405a-484f-a71b-b547de176067 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2131068223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2131068223 |
Directory | /workspace/19.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2316542365 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 240723918004 ps |
CPU time | 331.57 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:12:27 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-66282a8c-30ff-45ca-9b98-5acd8fdaf20a |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2316542365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2316542365 |
Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.414064184 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 132956461 ps |
CPU time | 2.43 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-420e1c48-4367-4318-82bc-6b78fbd456f6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414064184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.414064184 |
Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.153244557 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 401212399 ps |
CPU time | 5.47 seconds |
Started | Aug 05 05:06:47 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-5e47224d-d518-4e7e-b858-d49cbcde9ff8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=153244557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.153244557 |
Directory | /workspace/19.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.2073618504 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1329213522 ps |
CPU time | 7.69 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 201916 kb |
Host | smart-d9ee3197-da86-4f4b-8840-2aa6374ed624 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073618504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2073618504 |
Directory | /workspace/19.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.274830576 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 23480487094 ps |
CPU time | 67.18 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-87e9a091-5e76-472e-a084-cfca9d76fe75 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=274830576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.274830576 |
Directory | /workspace/19.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.301763259 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 11670217347 ps |
CPU time | 27.02 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-1c688f0b-2426-4dbe-aaf7-cd9c2a6aec1c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=301763259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.301763259 |
Directory | /workspace/19.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2549677260 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 90752944 ps |
CPU time | 7.28 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:02 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-743fba4c-69dc-4118-a834-b778ca598a31 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549677260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2549677260 |
Directory | /workspace/19.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.855901229 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 606011826 ps |
CPU time | 5.8 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 201972 kb |
Host | smart-f237070a-c35a-483f-9a59-d29789285d40 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=855901229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.855901229 |
Directory | /workspace/19.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.4013163304 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 62496984 ps |
CPU time | 1.56 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-5567c001-a94b-4e33-ad8d-c3d5c4ad59ba |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013163304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4013163304 |
Directory | /workspace/19.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3985152601 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 3888793949 ps |
CPU time | 13.24 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 201984 kb |
Host | smart-edab635a-93d5-4d29-9ec3-68303ea34384 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985152601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3985152601 |
Directory | /workspace/19.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1730299534 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 802503052 ps |
CPU time | 5.47 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:07:02 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-ac9dec12-eb2f-4cbf-955a-f89ba6bc3c33 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1730299534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1730299534 |
Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1650640509 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 18679254 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:06:52 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-5f6ed6f3-9eff-4de8-b575-90ac6ab5c745 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650640509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1650640509 |
Directory | /workspace/19.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3220537012 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 8451161532 ps |
CPU time | 70.55 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:08:05 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-ab40e507-f46c-405f-8298-8b4a2b6084c9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3220537012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3220537012 |
Directory | /workspace/19.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3239699975 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 722808096 ps |
CPU time | 13.7 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-8f21bc2d-4c4a-41d6-a2d9-87cd1312252c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3239699975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3239699975 |
Directory | /workspace/19.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.176032378 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 457265712 ps |
CPU time | 62.94 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-f9c24a1b-d8e3-4d9f-b5b3-3ac223cc0537 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176032378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.176032378 |
Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1305124465 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 869554005 ps |
CPU time | 92.45 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:08:35 PM PDT 24 |
Peak memory | 206684 kb |
Host | smart-20a3169a-5fb9-4b27-be75-bdc22a195f18 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1305124465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1305124465 |
Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2573310942 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 130620376 ps |
CPU time | 6.51 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:07:10 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-4f6ec049-644e-4d51-bdd8-27a648082146 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573310942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2573310942 |
Directory | /workspace/19.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1330394245 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 26684868 ps |
CPU time | 5.42 seconds |
Started | Aug 05 05:06:03 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-baba26b3-ae3e-4978-95cc-ace123316dab |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1330394245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1330394245 |
Directory | /workspace/2.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.529375676 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 437899813 ps |
CPU time | 7.95 seconds |
Started | Aug 05 05:06:08 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-612d9350-0d5c-4b6d-b0da-6ccb6584e175 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=529375676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.529375676 |
Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2093416792 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 3470177559 ps |
CPU time | 7.77 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:06:21 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-7388de0f-36d7-46cf-ade0-60edd4dff1bb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093416792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2093416792 |
Directory | /workspace/2.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.3636800549 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 1413963557 ps |
CPU time | 5.03 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:06:21 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-a1274168-1f58-4d24-b949-f0d0b6f2d11e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3636800549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3636800549 |
Directory | /workspace/2.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1737247080 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 100776335021 ps |
CPU time | 70.22 seconds |
Started | Aug 05 05:06:06 PM PDT 24 |
Finished | Aug 05 05:07:17 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-54376a4e-dcce-4888-9881-5c9279455abc |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737247080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1737247080 |
Directory | /workspace/2.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.4126454358 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 15703196856 ps |
CPU time | 114.04 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:08:26 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-86cefeb0-9ace-4e5e-b9a8-3ca45340c47c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4126454358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4126454358 |
Directory | /workspace/2.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3946829906 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 60884645 ps |
CPU time | 8.01 seconds |
Started | Aug 05 05:05:58 PM PDT 24 |
Finished | Aug 05 05:06:06 PM PDT 24 |
Peak memory | 201900 kb |
Host | smart-4c451764-0ca3-44e9-9060-04c2ede090fe |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946829906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3946829906 |
Directory | /workspace/2.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.699786549 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 2216139207 ps |
CPU time | 11.05 seconds |
Started | Aug 05 05:05:58 PM PDT 24 |
Finished | Aug 05 05:06:09 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-8bb33e3e-b7a3-4589-80ab-67ac72def621 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=699786549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.699786549 |
Directory | /workspace/2.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2232138347 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 29691776 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:28 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-f0680d80-682e-4cf9-b3ba-3b54cb62c6b7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2232138347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2232138347 |
Directory | /workspace/2.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1501648396 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 2856066423 ps |
CPU time | 11.06 seconds |
Started | Aug 05 05:05:58 PM PDT 24 |
Finished | Aug 05 05:06:09 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-0b660585-050a-4db9-b048-dcd41457c0fd |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501648396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1501648396 |
Directory | /workspace/2.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.232096056 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 2222601704 ps |
CPU time | 6.79 seconds |
Started | Aug 05 05:06:03 PM PDT 24 |
Finished | Aug 05 05:06:10 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-efc2d912-153b-4cc8-b12b-974269d17ee6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=232096056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.232096056 |
Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.640992106 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 10432157 ps |
CPU time | 1.05 seconds |
Started | Aug 05 05:06:21 PM PDT 24 |
Finished | Aug 05 05:06:23 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-fe7fe881-14ba-4692-80f3-479192d3b09a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640992106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.640992106 |
Directory | /workspace/2.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3603188224 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 3545381121 ps |
CPU time | 47.12 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 203132 kb |
Host | smart-e161d4d3-b461-49e8-97c1-5ab8f166ae2e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3603188224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3603188224 |
Directory | /workspace/2.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.78046250 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 2366913048 ps |
CPU time | 35.93 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:36 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-db476b69-b7b4-47fa-a5ac-6e3d710a94fd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=78046250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.78046250 |
Directory | /workspace/2.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2710788809 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 864857130 ps |
CPU time | 8.16 seconds |
Started | Aug 05 05:05:59 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-eaff460f-67ba-4959-9ff1-e73a857a331e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2710788809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2710788809 |
Directory | /workspace/2.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.651567712 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 49094543 ps |
CPU time | 10.71 seconds |
Started | Aug 05 05:06:51 PM PDT 24 |
Finished | Aug 05 05:07:02 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-9b0f8941-b47c-49fc-8279-18bb321bf80a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=651567712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.651567712 |
Directory | /workspace/20.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3949475535 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 29978218246 ps |
CPU time | 96.92 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:08:50 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-4c738538-2d64-4d8e-a033-f8f66ab78c8e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3949475535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.3949475535 |
Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.4070267652 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 1331407698 ps |
CPU time | 6.05 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-a8f1274b-3fcd-4963-ab9b-aa8efbbc58f1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070267652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.4070267652 |
Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3554814096 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 499728573 ps |
CPU time | 8.15 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 201968 kb |
Host | smart-0a1b73d6-783b-4eb2-998b-e0a8fdc031eb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554814096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3554814096 |
Directory | /workspace/20.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.1828023466 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 5085768148 ps |
CPU time | 16.45 seconds |
Started | Aug 05 05:06:48 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-99fe7bda-8bcf-4f7e-b013-f4612f22942a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1828023466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1828023466 |
Directory | /workspace/20.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1994881001 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 23238449286 ps |
CPU time | 41.27 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:07:30 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-a21edf8d-d7b3-4646-b5fc-8a647fa889f0 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994881001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1994881001 |
Directory | /workspace/20.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3222486997 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 26234575105 ps |
CPU time | 74.05 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:08:10 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-b5f9089e-3e14-4288-8ef3-8b95553f5caf |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3222486997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3222486997 |
Directory | /workspace/20.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2825734356 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 289973909 ps |
CPU time | 7.22 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:07:02 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-a2083504-5d3c-410e-b81e-5f36912edd54 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825734356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2825734356 |
Directory | /workspace/20.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.2712344841 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 2063051572 ps |
CPU time | 11.31 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-5e1ee1c0-a150-4941-b63b-445300bcc509 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2712344841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2712344841 |
Directory | /workspace/20.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2647415593 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 78971548 ps |
CPU time | 1.67 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:06:56 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-839d310b-38a8-4cfd-a203-4abf23f92f63 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2647415593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2647415593 |
Directory | /workspace/20.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1780662845 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 2156703211 ps |
CPU time | 10.93 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-4e6207dd-af7a-4519-8e41-ddc715e221c3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780662845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1780662845 |
Directory | /workspace/20.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.516311914 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 4929673732 ps |
CPU time | 6.54 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:06:55 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-a1777b8e-8d7f-4693-ba1a-e0f6b5035207 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=516311914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.516311914 |
Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1083879415 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 16166398 ps |
CPU time | 1.13 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:06:54 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-05cce441-1a93-4f54-90bb-f5c4ea769463 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083879415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1083879415 |
Directory | /workspace/20.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1970907260 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 768527375 ps |
CPU time | 9.47 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:09 PM PDT 24 |
Peak memory | 201972 kb |
Host | smart-27fa3cbf-c81b-410c-9923-1c9e13fb31c5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1970907260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1970907260 |
Directory | /workspace/20.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1301250829 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 1427056577 ps |
CPU time | 22.5 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-2448b9af-f0a3-491f-945e-3dd97832dc2f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301250829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1301250829 |
Directory | /workspace/20.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.61194567 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 428053797 ps |
CPU time | 21.98 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:07:19 PM PDT 24 |
Peak memory | 204048 kb |
Host | smart-b87a6050-1a03-432b-b30f-42a7d1c32a67 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61194567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_ reset.61194567 |
Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2197926641 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 4498617771 ps |
CPU time | 126.71 seconds |
Started | Aug 05 05:07:10 PM PDT 24 |
Finished | Aug 05 05:09:16 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-334eef25-7e30-41fd-b569-eeef0e5d0cd4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2197926641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2197926641 |
Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.995079595 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1010842700 ps |
CPU time | 13.32 seconds |
Started | Aug 05 05:07:05 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-3e89bca1-8173-492d-b04f-e4c74056a44e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=995079595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.995079595 |
Directory | /workspace/20.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3007139809 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 12156670 ps |
CPU time | 1.74 seconds |
Started | Aug 05 05:07:09 PM PDT 24 |
Finished | Aug 05 05:07:11 PM PDT 24 |
Peak memory | 201900 kb |
Host | smart-f7bc31e9-1de9-4fdd-8ab8-6f1689cf4daf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3007139809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3007139809 |
Directory | /workspace/21.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2128188065 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 13618103175 ps |
CPU time | 95.05 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:08:32 PM PDT 24 |
Peak memory | 202168 kb |
Host | smart-4a541e82-ad4e-4221-acbf-876526a19d46 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2128188065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2128188065 |
Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2106476305 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 314476606 ps |
CPU time | 3.83 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-c03bfc5b-274e-4ff0-8f8a-69371bee758b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2106476305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2106476305 |
Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.3467558936 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2194013510 ps |
CPU time | 6.34 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-7c4a18b9-644b-4c84-a341-a31e8225f49a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3467558936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3467558936 |
Directory | /workspace/21.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.11994113 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 26677296 ps |
CPU time | 3.59 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-340c2632-3ab1-4efa-8397-8c327c5c7cce |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=11994113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.11994113 |
Directory | /workspace/21.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.847975678 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 39555075259 ps |
CPU time | 126.89 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:09:13 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-e31231b6-e847-4675-a116-d81d8a01144a |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=847975678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.847975678 |
Directory | /workspace/21.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1912450948 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 16859690772 ps |
CPU time | 114.9 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:08:57 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-aa67d3a3-6afd-45f7-942a-f7b1535d8ab5 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1912450948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1912450948 |
Directory | /workspace/21.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1546907127 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 54543226 ps |
CPU time | 3.2 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 201912 kb |
Host | smart-3948647b-a197-4390-92ed-9853c1b42d2f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546907127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1546907127 |
Directory | /workspace/21.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.1615987055 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 1171799040 ps |
CPU time | 11.37 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-32cbdc8b-d12e-4e0f-8ff3-10ebcc629175 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1615987055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1615987055 |
Directory | /workspace/21.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.3481848085 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 10482410 ps |
CPU time | 1.1 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:06:55 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-d23cdedf-dcfd-4687-a961-410bd643bccd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3481848085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3481848085 |
Directory | /workspace/21.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2892138333 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 2311191113 ps |
CPU time | 6.28 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:01 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-69080466-7bc5-4dd1-b5d9-1c447243e38e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892138333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2892138333 |
Directory | /workspace/21.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.255715257 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 968356678 ps |
CPU time | 5.16 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:07:01 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-faf34139-81c2-45a3-893c-ecc5c2e1db31 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=255715257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.255715257 |
Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2919106052 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 9953157 ps |
CPU time | 1.09 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-3b5945c9-340a-437b-8b34-7e4b6ab06cd8 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919106052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2919106052 |
Directory | /workspace/21.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3378220092 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 6756536486 ps |
CPU time | 66.57 seconds |
Started | Aug 05 05:06:58 PM PDT 24 |
Finished | Aug 05 05:08:05 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-d08f395e-5908-4d35-8d7b-a4a3b8562b41 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3378220092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3378220092 |
Directory | /workspace/21.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3084133036 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 18103583663 ps |
CPU time | 49.9 seconds |
Started | Aug 05 05:07:12 PM PDT 24 |
Finished | Aug 05 05:08:02 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-2ba21383-b1ab-45d6-a0e2-c8c7222ada32 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3084133036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3084133036 |
Directory | /workspace/21.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3945696022 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 1014753083 ps |
CPU time | 90.81 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:08:37 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-5ff4bb0f-dbed-43c0-b9ee-fe7cbe403561 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3945696022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3945696022 |
Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.4109949343 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 918757858 ps |
CPU time | 102.22 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:08:39 PM PDT 24 |
Peak memory | 206088 kb |
Host | smart-0a6b8a8e-5954-445a-8f0f-00634d9f23f0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4109949343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.4109949343 |
Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1425385074 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 1402297700 ps |
CPU time | 12.05 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-ea6d663e-b2f0-4aad-9629-3e70dca0e05e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1425385074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1425385074 |
Directory | /workspace/21.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1875712633 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1748103984 ps |
CPU time | 8.34 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:08 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-82b4eb8c-0f94-4424-8787-84e1efb955d4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1875712633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1875712633 |
Directory | /workspace/22.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2810138357 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 50128876954 ps |
CPU time | 177.38 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:10:01 PM PDT 24 |
Peak memory | 203120 kb |
Host | smart-a5892352-bc82-41d6-8739-60605bd608f6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2810138357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2810138357 |
Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3613529443 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 314464561 ps |
CPU time | 4.43 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:06 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-3bb20ae9-d578-42b6-9a9b-5677a97ea082 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3613529443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3613529443 |
Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.1122676172 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 913774999 ps |
CPU time | 4.66 seconds |
Started | Aug 05 05:06:58 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-730e6501-3679-44d8-847d-e2fecd56f028 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1122676172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1122676172 |
Directory | /workspace/22.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1625632792 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 331203689 ps |
CPU time | 3.49 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-cf169608-683e-48d1-bf3b-ef3cfdcb8884 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1625632792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1625632792 |
Directory | /workspace/22.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3091838071 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 18105312094 ps |
CPU time | 22.27 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:07:26 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-1c2964d4-a374-4fc9-925d-c3a9fe2080c8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091838071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3091838071 |
Directory | /workspace/22.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.257942886 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 107382176258 ps |
CPU time | 151.61 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:09:31 PM PDT 24 |
Peak memory | 202116 kb |
Host | smart-65fa2a77-c12a-44f5-bd3c-a826a10c3601 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=257942886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.257942886 |
Directory | /workspace/22.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2979438583 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 95657918 ps |
CPU time | 8.31 seconds |
Started | Aug 05 05:06:49 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-a3ceb336-d2f6-4845-a67e-b5e2041898c9 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979438583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2979438583 |
Directory | /workspace/22.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.339770628 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2940968869 ps |
CPU time | 13.43 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:16 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-8c21bdc2-329c-4775-8d7b-3476822caa32 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=339770628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.339770628 |
Directory | /workspace/22.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2534520349 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 87456212 ps |
CPU time | 1.76 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-347feccd-3a9e-44b1-af7e-09558c946b66 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534520349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2534520349 |
Directory | /workspace/22.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.975435207 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 7658434989 ps |
CPU time | 11.46 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:14 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-181b9cdf-e482-4e6d-9c44-f41312632eaa |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=975435207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.975435207 |
Directory | /workspace/22.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2515207856 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 1925282459 ps |
CPU time | 9.21 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:11 PM PDT 24 |
Peak memory | 201984 kb |
Host | smart-141639d6-c84e-4e90-a348-16e4680eebbe |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2515207856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2515207856 |
Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2719512827 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 11553702 ps |
CPU time | 1.1 seconds |
Started | Aug 05 05:07:04 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-8c6eeb39-0a92-4fba-9fd3-ddaa1e40a23e |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719512827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2719512827 |
Directory | /workspace/22.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.427582813 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 14339614528 ps |
CPU time | 49.5 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:08:13 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-1a33aa27-8b91-490c-9e45-7e310add0664 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=427582813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.427582813 |
Directory | /workspace/22.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2760520198 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 6083697677 ps |
CPU time | 65.74 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-965ffcc5-b411-407e-a18a-84c40a8b4ff8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2760520198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2760520198 |
Directory | /workspace/22.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3592656511 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 4145951420 ps |
CPU time | 32.22 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-332a1db6-2589-4342-a89c-5b44f07a6493 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3592656511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3592656511 |
Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.694459796 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 3522563363 ps |
CPU time | 13.24 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-5b1ef31d-1f06-446f-aae9-cf1f35546ea2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=694459796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.694459796 |
Directory | /workspace/22.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.745773936 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 761268089 ps |
CPU time | 17.43 seconds |
Started | Aug 05 05:06:54 PM PDT 24 |
Finished | Aug 05 05:07:11 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-293ab01e-dd8b-40c6-a27e-4fd4b064cc46 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=745773936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.745773936 |
Directory | /workspace/23.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.363451794 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 36236561222 ps |
CPU time | 194.97 seconds |
Started | Aug 05 05:06:55 PM PDT 24 |
Finished | Aug 05 05:10:10 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-1e3020e0-177d-4726-86f0-ec498af249fd |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=363451794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo w_rsp.363451794 |
Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2426455659 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 628238670 ps |
CPU time | 6.32 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-e1ce4f5b-32bd-4fb9-9efa-a8e56110b05a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426455659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2426455659 |
Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2256101563 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 2822118930 ps |
CPU time | 7.78 seconds |
Started | Aug 05 05:06:58 PM PDT 24 |
Finished | Aug 05 05:07:06 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-fadc2a59-1372-4390-b47f-3c12a2257d52 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2256101563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2256101563 |
Directory | /workspace/23.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.428482634 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 466621159 ps |
CPU time | 7.15 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:24 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-82e7e636-ef27-44a6-b584-ebfd14a7c372 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428482634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.428482634 |
Directory | /workspace/23.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3397383286 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 5460959671 ps |
CPU time | 19.45 seconds |
Started | Aug 05 05:07:05 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 202300 kb |
Host | smart-45963d1c-e4c7-42a6-aff4-f21d8c9f2f18 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397383286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3397383286 |
Directory | /workspace/23.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.8719252 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 21116223909 ps |
CPU time | 125.82 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:09:06 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-5979f7fb-cc26-4a8e-bf90-78d7db59a64d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=8719252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.8719252 |
Directory | /workspace/23.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1677324277 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 26177811 ps |
CPU time | 3.91 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:07:10 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-8e444b84-6cb5-4b1b-beb4-78afac54507d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677324277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1677324277 |
Directory | /workspace/23.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.1022369442 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 38924706 ps |
CPU time | 4.12 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:06 PM PDT 24 |
Peak memory | 201900 kb |
Host | smart-99deb5f9-4307-4a87-821a-7c8261c138ef |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1022369442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1022369442 |
Directory | /workspace/23.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.3209196145 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 10352328 ps |
CPU time | 1.12 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-7e4a946f-e7e2-496f-845f-51297b768f48 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3209196145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3209196145 |
Directory | /workspace/23.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1187760226 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 2175346350 ps |
CPU time | 9.84 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:10 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-4aa34983-a044-44d0-abd5-3d067e6e6c7b |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187760226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1187760226 |
Directory | /workspace/23.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2828281658 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 1667816874 ps |
CPU time | 7.82 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:15 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-d513277c-416b-40b9-9cc2-08fbac97c999 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2828281658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2828281658 |
Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2175205885 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 17447729 ps |
CPU time | 1.16 seconds |
Started | Aug 05 05:06:52 PM PDT 24 |
Finished | Aug 05 05:06:54 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-35908964-7c53-4f5a-9d73-b0a90c982f42 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175205885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2175205885 |
Directory | /workspace/23.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.950241249 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 3826892931 ps |
CPU time | 56.87 seconds |
Started | Aug 05 05:07:08 PM PDT 24 |
Finished | Aug 05 05:08:05 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-76b502b0-2444-4ccc-9327-cf612f978963 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=950241249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.950241249 |
Directory | /workspace/23.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1480638673 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 2523983110 ps |
CPU time | 18.24 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-1289bac8-c1bb-42f5-91bd-9146a0c3b788 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1480638673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1480638673 |
Directory | /workspace/23.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3295601693 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 475833574 ps |
CPU time | 34.84 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:07:38 PM PDT 24 |
Peak memory | 204464 kb |
Host | smart-ec2431da-7bfb-4613-8069-8b09bd487b79 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3295601693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3295601693 |
Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.467786255 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 616330098 ps |
CPU time | 53.46 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 204456 kb |
Host | smart-137b7e15-eb5b-4942-bdaf-85f56b9f44e7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=467786255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.467786255 |
Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1036705538 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 1281148175 ps |
CPU time | 9.7 seconds |
Started | Aug 05 05:07:05 PM PDT 24 |
Finished | Aug 05 05:07:14 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-2f6bba9b-4f77-4d29-aa09-1bd5e4bbacc5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1036705538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1036705538 |
Directory | /workspace/23.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3801839479 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 47903597 ps |
CPU time | 9.34 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-414c7e9f-b966-48dc-9da5-aad8b068c23d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3801839479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3801839479 |
Directory | /workspace/24.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.587108401 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 44365009805 ps |
CPU time | 341.97 seconds |
Started | Aug 05 05:07:04 PM PDT 24 |
Finished | Aug 05 05:12:46 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-a8e055ae-3993-4d0f-8bb2-e53621afc9c3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=587108401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.587108401 |
Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2849181439 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 727772409 ps |
CPU time | 7.43 seconds |
Started | Aug 05 05:07:04 PM PDT 24 |
Finished | Aug 05 05:07:12 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-a6c4ef08-4779-4066-b2ae-eaee1b213e65 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2849181439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2849181439 |
Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.754026991 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 1586297132 ps |
CPU time | 6 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:09 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-ffece594-156f-4ed6-a365-68c7c937cd8f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=754026991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.754026991 |
Directory | /workspace/24.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.3908984729 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 574589586 ps |
CPU time | 2.94 seconds |
Started | Aug 05 05:07:08 PM PDT 24 |
Finished | Aug 05 05:07:16 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-dcb3adb2-f39c-4a3f-bced-3e9090707acf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3908984729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3908984729 |
Directory | /workspace/24.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.459703570 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 5624800343 ps |
CPU time | 18.18 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-f2b1ff33-bc00-4634-bdb3-60c66cd78db8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=459703570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.459703570 |
Directory | /workspace/24.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.558780295 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 35059290498 ps |
CPU time | 173.61 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:09:55 PM PDT 24 |
Peak memory | 202112 kb |
Host | smart-cddb5272-e010-46d8-b3d0-dc4b905f71f4 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=558780295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.558780295 |
Directory | /workspace/24.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.2690619453 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 10523706 ps |
CPU time | 1.41 seconds |
Started | Aug 05 05:07:11 PM PDT 24 |
Finished | Aug 05 05:07:12 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-d09830ca-ef27-400b-a97e-34a982e675e8 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690619453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2690619453 |
Directory | /workspace/24.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.4091292761 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 497598025 ps |
CPU time | 5.07 seconds |
Started | Aug 05 05:06:58 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-f03fc46a-4ca9-4c62-bac2-53343cd5c37e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091292761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4091292761 |
Directory | /workspace/24.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.2910688542 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 9630284 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:06:56 PM PDT 24 |
Finished | Aug 05 05:06:57 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-fd26ec3e-3f0b-4057-ae5c-8b6008996084 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2910688542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2910688542 |
Directory | /workspace/24.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2071255770 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 21044370274 ps |
CPU time | 11.18 seconds |
Started | Aug 05 05:07:15 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 202112 kb |
Host | smart-b10d550f-ff64-429a-8809-90497469f962 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071255770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2071255770 |
Directory | /workspace/24.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3970483909 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 1256402518 ps |
CPU time | 8.94 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:11 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-fe1a6c3c-6166-4584-b9e7-ea8316ca159e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3970483909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3970483909 |
Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3588910874 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 11081424 ps |
CPU time | 1.16 seconds |
Started | Aug 05 05:07:09 PM PDT 24 |
Finished | Aug 05 05:07:10 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-3104a484-bd4f-4f7f-a06b-aa1bd078836f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588910874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3588910874 |
Directory | /workspace/24.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.3177725442 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 69787117 ps |
CPU time | 1.72 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-643d8513-ac71-4184-bf78-b51509be3f20 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3177725442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3177725442 |
Directory | /workspace/24.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.226314973 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 4230902155 ps |
CPU time | 14.91 seconds |
Started | Aug 05 05:07:06 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-7f781f9b-98b5-4109-8831-978a2e038db4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=226314973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.226314973 |
Directory | /workspace/24.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.807599667 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 10853833916 ps |
CPU time | 176.12 seconds |
Started | Aug 05 05:07:16 PM PDT 24 |
Finished | Aug 05 05:10:12 PM PDT 24 |
Peak memory | 207052 kb |
Host | smart-4b648855-b3e1-4406-999a-a5cb011a99d6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=807599667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.807599667 |
Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3637972883 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 91187612 ps |
CPU time | 19.06 seconds |
Started | Aug 05 05:07:15 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-01c06615-2d9a-4755-9eab-35f7afddc294 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3637972883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3637972883 |
Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.843528652 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2224274552 ps |
CPU time | 9 seconds |
Started | Aug 05 05:07:11 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-ddbd0d9c-b08b-43ae-947e-180e4c3ab01b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=843528652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.843528652 |
Directory | /workspace/24.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3848331792 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 40604142 ps |
CPU time | 4.38 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-9215ceb1-dbe3-419e-aeb3-aa5653c9b12a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3848331792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3848331792 |
Directory | /workspace/25.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2910571483 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 4535244565 ps |
CPU time | 31.6 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-2eaa3167-368d-4b92-88c1-6a67f8764e2e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2910571483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2910571483 |
Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2168675704 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 70461316 ps |
CPU time | 6.17 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:13 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-ccbb8f2f-3416-4640-aeaf-68e2bc3b6ede |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2168675704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2168675704 |
Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2376455729 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 778191016 ps |
CPU time | 5.67 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:07:09 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-0c6dcae3-d439-430e-8e58-5376f7a67a23 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2376455729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2376455729 |
Directory | /workspace/25.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2182407982 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 50774183 ps |
CPU time | 4.72 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:19 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-2180846b-e3fd-47d9-bd1f-5e7583ca64a3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2182407982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2182407982 |
Directory | /workspace/25.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2339440674 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 33588638516 ps |
CPU time | 63.39 seconds |
Started | Aug 05 05:07:12 PM PDT 24 |
Finished | Aug 05 05:08:16 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-9dbe0d17-bf2a-4c30-b88e-5120e85e4909 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339440674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2339440674 |
Directory | /workspace/25.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1221826213 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 6555758736 ps |
CPU time | 39.97 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-0050d5d3-0893-471a-8d32-823545a3853c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1221826213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1221826213 |
Directory | /workspace/25.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2226114273 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 43397247 ps |
CPU time | 4.86 seconds |
Started | Aug 05 05:07:26 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-56100fa8-fd14-4e38-9eba-16d766cab521 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226114273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2226114273 |
Directory | /workspace/25.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2737623900 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 96539773 ps |
CPU time | 2.64 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-b64cb8c1-e193-4f7b-a3eb-17b2048e7145 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2737623900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2737623900 |
Directory | /workspace/25.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.2233811849 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 13725535 ps |
CPU time | 1.11 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:09 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-ec45d193-7e02-4a6d-a9a7-d47e461fa932 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2233811849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2233811849 |
Directory | /workspace/25.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2581461877 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 1905905539 ps |
CPU time | 9.31 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:10 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-d3600e69-3d0a-4584-92e5-5b4b19fb2afa |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581461877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2581461877 |
Directory | /workspace/25.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.877064415 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 611030988 ps |
CPU time | 5.06 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:06 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-b4ed6b6a-dd56-44b1-969a-b25086caa205 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=877064415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.877064415 |
Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1136505471 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 9160776 ps |
CPU time | 1.31 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-f34b3e67-5b69-439a-8592-f93dbb7134dd |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136505471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1136505471 |
Directory | /workspace/25.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2706937478 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 285677804 ps |
CPU time | 34.06 seconds |
Started | Aug 05 05:07:04 PM PDT 24 |
Finished | Aug 05 05:07:38 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-970dc41b-87e4-41eb-ab0c-132b0f0af4be |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2706937478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2706937478 |
Directory | /workspace/25.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2872693595 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 1202806015 ps |
CPU time | 12.82 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:13 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-c6316173-f3a0-4b88-a067-b507a85c08ea |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872693595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2872693595 |
Directory | /workspace/25.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1908086078 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 143437022 ps |
CPU time | 16.2 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:17 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-e2c541ac-693f-4514-8d3d-fe1ab76beca0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1908086078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1908086078 |
Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1376326036 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 2034803236 ps |
CPU time | 96.01 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:08:38 PM PDT 24 |
Peak memory | 206460 kb |
Host | smart-68ef7ce6-816f-41c4-ad58-81a626b3d6ae |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1376326036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1376326036 |
Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3504093932 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 99454097 ps |
CPU time | 7.62 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-671f54dc-be3a-4c41-acfa-cf64b859d5ad |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3504093932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3504093932 |
Directory | /workspace/25.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2979166202 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 48136022 ps |
CPU time | 9.25 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:26 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-f9c040cf-1960-45e0-aa3b-19f2c7b95fd2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979166202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2979166202 |
Directory | /workspace/26.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.11615515 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 45447403723 ps |
CPU time | 295.02 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:11:54 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-db30a203-4e91-4b16-b867-6564ff4efbc6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=11615515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow _rsp.11615515 |
Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2882471977 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 527102707 ps |
CPU time | 9.54 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:07:12 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-91b28021-3dd5-458d-ac75-c729bd0e0e10 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2882471977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2882471977 |
Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3552584754 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 80430643 ps |
CPU time | 1.75 seconds |
Started | Aug 05 05:07:01 PM PDT 24 |
Finished | Aug 05 05:07:03 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-1fe5de8e-5eee-45ec-bf24-ab9fb156beb7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3552584754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3552584754 |
Directory | /workspace/26.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.3128933460 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 468684523 ps |
CPU time | 7.11 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:07:35 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-cbeea08e-a313-4088-aded-091a6f284c9c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3128933460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3128933460 |
Directory | /workspace/26.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3623138667 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 9974890575 ps |
CPU time | 24.05 seconds |
Started | Aug 05 05:07:18 PM PDT 24 |
Finished | Aug 05 05:07:42 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-ac49c9f4-edff-405f-8e00-408800c4f99f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623138667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3623138667 |
Directory | /workspace/26.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1600009338 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 76610437060 ps |
CPU time | 105.49 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:08:49 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-ebdef6ef-706f-4049-ac6f-4b32d5cda76f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1600009338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1600009338 |
Directory | /workspace/26.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1131019083 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 33358648 ps |
CPU time | 3.81 seconds |
Started | Aug 05 05:07:19 PM PDT 24 |
Finished | Aug 05 05:07:23 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-39db08cf-3774-40f5-9c7d-ed8caa78daf0 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131019083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1131019083 |
Directory | /workspace/26.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.695141612 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 619235781 ps |
CPU time | 3.23 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-51aa50a9-f73c-4fd3-a9fa-2fd5c2b04fbf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695141612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.695141612 |
Directory | /workspace/26.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1070853560 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 10368166 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:07:05 PM PDT 24 |
Finished | Aug 05 05:07:06 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-e224c919-c592-494e-9aea-563443d56747 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1070853560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1070853560 |
Directory | /workspace/26.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1284377698 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 3211837299 ps |
CPU time | 9.71 seconds |
Started | Aug 05 05:07:10 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-c1c433c0-3b5b-4b6f-a16e-5af2ba37bbc7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284377698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1284377698 |
Directory | /workspace/26.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3089964346 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 1206890651 ps |
CPU time | 4.49 seconds |
Started | Aug 05 05:07:00 PM PDT 24 |
Finished | Aug 05 05:07:05 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-4bdd62b7-c05c-4452-845a-fc5263de96af |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3089964346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3089964346 |
Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.239118819 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 10778203 ps |
CPU time | 1.12 seconds |
Started | Aug 05 05:07:07 PM PDT 24 |
Finished | Aug 05 05:07:08 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-ea1cb255-fe8e-4c00-8737-8fe7610a1d3b |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239118819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.239118819 |
Directory | /workspace/26.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.4266034716 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 5528814028 ps |
CPU time | 96.48 seconds |
Started | Aug 05 05:07:04 PM PDT 24 |
Finished | Aug 05 05:08:41 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-2ebaeb0d-710a-462a-b302-2a3787d238b5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4266034716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.4266034716 |
Directory | /workspace/26.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2207601224 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 3918590007 ps |
CPU time | 25.33 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-6f3029f0-10dc-42c5-b34e-92f41b3dc435 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2207601224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2207601224 |
Directory | /workspace/26.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1611457741 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 2324394841 ps |
CPU time | 183.13 seconds |
Started | Aug 05 05:07:12 PM PDT 24 |
Finished | Aug 05 05:10:15 PM PDT 24 |
Peak memory | 206036 kb |
Host | smart-f730c0b2-d199-4a49-93fa-60e18a843041 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1611457741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1611457741 |
Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1351596292 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 658958196 ps |
CPU time | 68.84 seconds |
Started | Aug 05 05:07:16 PM PDT 24 |
Finished | Aug 05 05:08:25 PM PDT 24 |
Peak memory | 204320 kb |
Host | smart-fc072cc9-b3b8-4606-b9dc-d1b218ae4006 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351596292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1351596292 |
Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3227691375 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 41954438 ps |
CPU time | 4.52 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-d4d2d2f0-b2dc-48e4-bce5-66bcecc257de |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3227691375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3227691375 |
Directory | /workspace/26.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3682377771 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 96152726 ps |
CPU time | 13.55 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:28 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-9c5c1d77-27a7-4e32-a9a2-dfaddc0e3185 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3682377771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3682377771 |
Directory | /workspace/27.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.400148995 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 173469723614 ps |
CPU time | 305.86 seconds |
Started | Aug 05 05:07:02 PM PDT 24 |
Finished | Aug 05 05:12:08 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-4cf80019-833b-4f5f-921d-b149d64214d6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=400148995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.400148995 |
Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3687903327 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 53225015 ps |
CPU time | 4.96 seconds |
Started | Aug 05 05:07:15 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-9b4166a3-a3e6-4295-8d0c-0de3c0889fa8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3687903327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3687903327 |
Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.621789929 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 49298308 ps |
CPU time | 2.19 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-607a01f4-1bab-42f6-a36f-d213586af976 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=621789929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.621789929 |
Directory | /workspace/27.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.3130508471 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 105326540 ps |
CPU time | 4.84 seconds |
Started | Aug 05 05:06:59 PM PDT 24 |
Finished | Aug 05 05:07:04 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-2c5455cb-eee9-4e00-91b5-19e32396ede1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3130508471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3130508471 |
Directory | /workspace/27.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3402234986 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 53420649708 ps |
CPU time | 121.73 seconds |
Started | Aug 05 05:07:16 PM PDT 24 |
Finished | Aug 05 05:09:18 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-b21a55be-b820-411f-9f57-70f5e92e8529 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402234986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3402234986 |
Directory | /workspace/27.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1315054513 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 12578970819 ps |
CPU time | 91.33 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:08:48 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-57538193-ecfe-4283-a19e-d62539e9c3f8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1315054513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1315054513 |
Directory | /workspace/27.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2152583490 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 154349010 ps |
CPU time | 7.54 seconds |
Started | Aug 05 05:07:03 PM PDT 24 |
Finished | Aug 05 05:07:10 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-c88a79ab-0f04-476e-baab-42333267c97e |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152583490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2152583490 |
Directory | /workspace/27.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3314777552 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 52288065 ps |
CPU time | 5.11 seconds |
Started | Aug 05 05:07:09 PM PDT 24 |
Finished | Aug 05 05:07:14 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-adc05ac4-afd0-41a6-bbfc-3ff5ba17d3d0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314777552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3314777552 |
Directory | /workspace/27.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.333123 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 83213311 ps |
CPU time | 1.75 seconds |
Started | Aug 05 05:07:05 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-13a68594-a120-4e69-a62b-35fb5a47499d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=333123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.333123 |
Directory | /workspace/27.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3121576733 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 2618862171 ps |
CPU time | 10.98 seconds |
Started | Aug 05 05:07:08 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-c96ab26b-309d-416d-afa9-ae453eef532e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121576733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3121576733 |
Directory | /workspace/27.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3728452307 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 6345760207 ps |
CPU time | 16.13 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:30 PM PDT 24 |
Peak memory | 202056 kb |
Host | smart-3c1a8ca2-6bd2-4298-92ce-0b7ccccc8efc |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3728452307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3728452307 |
Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1621971928 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 15627003 ps |
CPU time | 1.03 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-2b2c6dbf-3fed-48b6-b71b-af3610768890 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621971928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1621971928 |
Directory | /workspace/27.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.4132008922 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 5197351518 ps |
CPU time | 56.57 seconds |
Started | Aug 05 05:07:11 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-ebe95981-47a2-47b1-a1dc-e89a34b1297c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4132008922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4132008922 |
Directory | /workspace/27.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3086157235 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 210022526 ps |
CPU time | 23.2 seconds |
Started | Aug 05 05:07:11 PM PDT 24 |
Finished | Aug 05 05:07:35 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-490034cb-99f8-44d2-9990-751f048e074e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3086157235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3086157235 |
Directory | /workspace/27.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.658185651 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 1032320475 ps |
CPU time | 122.75 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:09:20 PM PDT 24 |
Peak memory | 207732 kb |
Host | smart-890e49e2-081e-4838-b645-620d6ac48e90 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=658185651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.658185651 |
Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2027526071 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 492477022 ps |
CPU time | 66.61 seconds |
Started | Aug 05 05:07:16 PM PDT 24 |
Finished | Aug 05 05:08:22 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-cbe90fd3-d03c-4d78-8e49-90bdd2a19ffe |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2027526071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.2027526071 |
Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.892184817 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 320408566 ps |
CPU time | 5.66 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:19 PM PDT 24 |
Peak memory | 201844 kb |
Host | smart-65939bd7-caba-451e-8f30-d30947a6d2cc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=892184817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.892184817 |
Directory | /workspace/27.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.288374795 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 200398967 ps |
CPU time | 13.61 seconds |
Started | Aug 05 05:07:20 PM PDT 24 |
Finished | Aug 05 05:07:33 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-b8526649-e3f5-4e02-9afa-cd61749774c0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=288374795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.288374795 |
Directory | /workspace/28.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2941059144 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 96693898060 ps |
CPU time | 156.7 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:10:05 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-12f35883-8142-4a7f-ba89-66ea3dafb859 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2941059144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.2941059144 |
Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2914633515 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 4609347805 ps |
CPU time | 11.61 seconds |
Started | Aug 05 05:07:11 PM PDT 24 |
Finished | Aug 05 05:07:23 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-5fa606a3-cced-47b2-80ac-97cb3400a904 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2914633515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2914633515 |
Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.4121652250 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 123766598 ps |
CPU time | 6.05 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-90590bc1-a96c-4f34-8f0c-89a4c408a47d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4121652250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4121652250 |
Directory | /workspace/28.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.3615798810 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 757913588 ps |
CPU time | 10.09 seconds |
Started | Aug 05 05:07:11 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-2433683d-1113-4554-bd20-e6f2da374a97 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3615798810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3615798810 |
Directory | /workspace/28.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1862674127 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 51245470540 ps |
CPU time | 122.93 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:09:25 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-8e93b4d1-ea1a-4820-b29e-d9a5cef6d2b9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862674127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1862674127 |
Directory | /workspace/28.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2501543740 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 4701079853 ps |
CPU time | 4.95 seconds |
Started | Aug 05 05:07:16 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-7e79b9b5-2e65-4b10-8ff9-f621e29f90c3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2501543740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2501543740 |
Directory | /workspace/28.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.222054528 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 88054219 ps |
CPU time | 4.84 seconds |
Started | Aug 05 05:07:24 PM PDT 24 |
Finished | Aug 05 05:07:29 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-14a591fc-3af6-4db5-8f6c-400384b0b55c |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222054528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.222054528 |
Directory | /workspace/28.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1813562858 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 98351890 ps |
CPU time | 3.91 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-25fa2505-4427-494d-a1c9-149d48cf154e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1813562858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1813562858 |
Directory | /workspace/28.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.4242124929 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 51430250 ps |
CPU time | 1.35 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:15 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-e76be983-969e-4c9a-a71d-aca2482246bb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242124929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4242124929 |
Directory | /workspace/28.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3713172507 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 5247854905 ps |
CPU time | 8.06 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:22 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-7dacaa31-2a00-4fbf-8697-3d91f7129a6a |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713172507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3713172507 |
Directory | /workspace/28.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1899179069 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 8072564129 ps |
CPU time | 8.62 seconds |
Started | Aug 05 05:07:16 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-042b8565-e379-4eee-a031-f183968d7e07 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1899179069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1899179069 |
Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1840532360 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 8231910 ps |
CPU time | 1.12 seconds |
Started | Aug 05 05:07:15 PM PDT 24 |
Finished | Aug 05 05:07:17 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-c4505eb4-c3aa-443a-83bd-270b9d873dad |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840532360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1840532360 |
Directory | /workspace/28.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.901845928 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 302993952 ps |
CPU time | 14.03 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:41 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-fb8be485-530f-42a4-b14b-848f770294c3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=901845928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.901845928 |
Directory | /workspace/28.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1280826828 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 3271832238 ps |
CPU time | 34.03 seconds |
Started | Aug 05 05:07:12 PM PDT 24 |
Finished | Aug 05 05:07:46 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-3e40845f-5fdc-4147-a0fe-1d624fbad2d1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1280826828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1280826828 |
Directory | /workspace/28.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.287735421 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 458646364 ps |
CPU time | 50.16 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-1c0f7efa-69fa-4a31-9ee2-e640751070bc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=287735421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.287735421 |
Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4232282710 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 6542663963 ps |
CPU time | 186.39 seconds |
Started | Aug 05 05:07:09 PM PDT 24 |
Finished | Aug 05 05:10:15 PM PDT 24 |
Peak memory | 207100 kb |
Host | smart-c8d584eb-7386-41d2-abb4-4fc6febe5497 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4232282710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.4232282710 |
Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2460884915 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 2358089300 ps |
CPU time | 8.77 seconds |
Started | Aug 05 05:07:09 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-adf91a16-d7bc-4f75-ba6e-bdb0b60984f4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2460884915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2460884915 |
Directory | /workspace/28.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2999941650 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 22137429 ps |
CPU time | 3.59 seconds |
Started | Aug 05 05:07:10 PM PDT 24 |
Finished | Aug 05 05:07:14 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-27f25d78-71d9-4a07-9b79-2f602fc3fb2f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2999941650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2999941650 |
Directory | /workspace/29.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1999500104 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 20461255382 ps |
CPU time | 87.11 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:08:44 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-3adcf414-b028-4c2b-a268-834886326da5 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1999500104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1999500104 |
Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3278242027 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 685978335 ps |
CPU time | 10.48 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:24 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-b6d4fca6-7379-40fe-b1aa-fb10fce7e5d6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3278242027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3278242027 |
Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.3932431934 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 173683447 ps |
CPU time | 5.18 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:19 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-ac4eccce-b97b-410e-8c7a-1c8acc890c7d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3932431934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3932431934 |
Directory | /workspace/29.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.3637747251 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 19029403 ps |
CPU time | 2.12 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:19 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-81dcd1f5-24ed-4157-838d-a902a2156550 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3637747251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3637747251 |
Directory | /workspace/29.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1321605494 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 56866581447 ps |
CPU time | 83 seconds |
Started | Aug 05 05:07:21 PM PDT 24 |
Finished | Aug 05 05:08:44 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-745951bd-da96-49c2-81ec-2ef6fe7ed2f3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321605494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1321605494 |
Directory | /workspace/29.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2442719293 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 15867945567 ps |
CPU time | 81.8 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:08:45 PM PDT 24 |
Peak memory | 202124 kb |
Host | smart-3747a7eb-fa4d-4e6e-af85-71077235c103 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2442719293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2442719293 |
Directory | /workspace/29.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.191693823 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 228658604 ps |
CPU time | 10.12 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:07:32 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-4825edd3-caee-4667-92a4-9d6ec5eb78eb |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191693823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.191693823 |
Directory | /workspace/29.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.32170287 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 15562407 ps |
CPU time | 1.46 seconds |
Started | Aug 05 05:07:12 PM PDT 24 |
Finished | Aug 05 05:07:14 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-6335db3c-84d5-4239-9e5b-c4a72e6ff38b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=32170287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.32170287 |
Directory | /workspace/29.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3818138280 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 53629775 ps |
CPU time | 1.35 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:32 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-3dbf1d80-4811-46e6-a49d-e097ebe0e69a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3818138280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3818138280 |
Directory | /workspace/29.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1726781955 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 2571663832 ps |
CPU time | 9.5 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:23 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-1129a4b0-cb82-494f-a642-6075cc03b999 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726781955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1726781955 |
Directory | /workspace/29.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3887127923 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 576161806 ps |
CPU time | 5.07 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:07:29 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-6822a3a3-af1a-460c-b271-1218b36aa050 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3887127923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3887127923 |
Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3206130870 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 10150116 ps |
CPU time | 1.29 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:16 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-9f39f140-8682-4b50-91cc-a956d4054159 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206130870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3206130870 |
Directory | /workspace/29.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1082663186 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 740023587 ps |
CPU time | 32.14 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 204628 kb |
Host | smart-53547b38-97a9-4b93-b0bd-92819930f353 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1082663186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1082663186 |
Directory | /workspace/29.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3567568015 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 52578815961 ps |
CPU time | 90.28 seconds |
Started | Aug 05 05:07:26 PM PDT 24 |
Finished | Aug 05 05:08:57 PM PDT 24 |
Peak memory | 204120 kb |
Host | smart-cbd0b73b-a6d6-4fe6-aa6b-6eaa9a6ea69a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3567568015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3567568015 |
Directory | /workspace/29.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4022182448 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 545460069 ps |
CPU time | 41.43 seconds |
Started | Aug 05 05:07:21 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-368c208a-c0af-48d6-929c-15932d9996ec |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4022182448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.4022182448 |
Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1717875749 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 1452133940 ps |
CPU time | 80.96 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:08:35 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-de24b58d-45e9-4753-8a70-c9dbe201d20b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1717875749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.1717875749 |
Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.767167147 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 702550964 ps |
CPU time | 8.44 seconds |
Started | Aug 05 05:07:12 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-d455c41f-2ef5-40b9-88f9-186a5798ea75 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=767167147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.767167147 |
Directory | /workspace/29.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2981515151 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 390662170 ps |
CPU time | 2.64 seconds |
Started | Aug 05 05:06:15 PM PDT 24 |
Finished | Aug 05 05:06:23 PM PDT 24 |
Peak memory | 201276 kb |
Host | smart-dfd5b391-e079-4088-89e1-16e3d0ac38dd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2981515151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2981515151 |
Directory | /workspace/3.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1165654230 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 244365094215 ps |
CPU time | 341.99 seconds |
Started | Aug 05 05:06:15 PM PDT 24 |
Finished | Aug 05 05:11:57 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-e605c6ef-931f-4ac2-bf03-effa03563ba9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1165654230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1165654230 |
Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1438714097 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 607544243 ps |
CPU time | 8.85 seconds |
Started | Aug 05 05:06:21 PM PDT 24 |
Finished | Aug 05 05:06:30 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-e4a19d76-0aba-443d-812a-6dd97e34a34a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1438714097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1438714097 |
Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2590159381 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 103450947 ps |
CPU time | 8.12 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 201972 kb |
Host | smart-b0abf88f-fdd0-4e7a-9adc-082f13586090 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590159381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2590159381 |
Directory | /workspace/3.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3139902884 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 710709290 ps |
CPU time | 4.87 seconds |
Started | Aug 05 05:06:03 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-edd63798-0e94-42e1-a6b0-952de4471226 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3139902884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3139902884 |
Directory | /workspace/3.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.69236632 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 32361189315 ps |
CPU time | 144.25 seconds |
Started | Aug 05 05:06:12 PM PDT 24 |
Finished | Aug 05 05:08:37 PM PDT 24 |
Peak memory | 202108 kb |
Host | smart-0e8cbfd9-a0a0-4b42-83ff-6f8c8d01952f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=69236632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.69236632 |
Directory | /workspace/3.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1605368436 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 11991916489 ps |
CPU time | 65.03 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:07:41 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-754a1ce9-eee1-4c72-8a56-1a05c42f55f7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1605368436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1605368436 |
Directory | /workspace/3.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.952855664 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 124446484 ps |
CPU time | 6.25 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:06 PM PDT 24 |
Peak memory | 201968 kb |
Host | smart-3a2f7be1-dcbe-4c48-a0ad-9827d5cc4ee0 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952855664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.952855664 |
Directory | /workspace/3.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.2147784868 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 340824769 ps |
CPU time | 4.52 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:05 PM PDT 24 |
Peak memory | 201976 kb |
Host | smart-27aa1002-24bc-4880-aac7-68a943524dcc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2147784868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2147784868 |
Directory | /workspace/3.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1427445049 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 74871503 ps |
CPU time | 1.39 seconds |
Started | Aug 05 05:06:00 PM PDT 24 |
Finished | Aug 05 05:06:02 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-a10bfca8-09dc-4d47-bf3f-041df3ad29bc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1427445049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1427445049 |
Directory | /workspace/3.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3039036835 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 4556341619 ps |
CPU time | 8.74 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-bc387d53-3a85-4260-b8ef-176c6d8fe9b1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039036835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3039036835 |
Directory | /workspace/3.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.675001449 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1082899593 ps |
CPU time | 8.48 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-552025ba-15a6-4bae-95a8-54d893447aee |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=675001449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.675001449 |
Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2895634472 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 9765001 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:06:03 PM PDT 24 |
Finished | Aug 05 05:06:04 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-f545222b-3d92-499e-8167-46477d91424d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895634472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2895634472 |
Directory | /workspace/3.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3252877148 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 5418599205 ps |
CPU time | 90.03 seconds |
Started | Aug 05 05:06:08 PM PDT 24 |
Finished | Aug 05 05:07:38 PM PDT 24 |
Peak memory | 203092 kb |
Host | smart-707362db-6cb9-4abc-9032-f963228429dc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3252877148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3252877148 |
Directory | /workspace/3.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2457136454 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 3268890355 ps |
CPU time | 51.92 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-8d2ca03c-ad79-4050-aae4-eae28cfa42be |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2457136454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2457136454 |
Directory | /workspace/3.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2099824370 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 7971402933 ps |
CPU time | 149.76 seconds |
Started | Aug 05 05:06:06 PM PDT 24 |
Finished | Aug 05 05:08:36 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-a4ed942a-f391-4a9f-97e3-9996606577f3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2099824370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.2099824370 |
Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1987899104 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 5293901378 ps |
CPU time | 77.48 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 204220 kb |
Host | smart-a65218fb-7566-4f4b-b344-e087f046a174 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1987899104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1987899104 |
Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3570073072 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 331906652 ps |
CPU time | 3.04 seconds |
Started | Aug 05 05:06:19 PM PDT 24 |
Finished | Aug 05 05:06:28 PM PDT 24 |
Peak memory | 201884 kb |
Host | smart-9712334e-3261-4d73-9699-ce88f438a44e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3570073072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3570073072 |
Directory | /workspace/3.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1841568916 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 168945523 ps |
CPU time | 4.8 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:19 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-9c371dc2-88ad-47ab-8f4e-defd994f1bd6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841568916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1841568916 |
Directory | /workspace/30.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2522433532 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 7104178249 ps |
CPU time | 56.1 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:08:09 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-19dd6c0b-faf2-4e62-815c-4c321168e3c2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2522433532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2522433532 |
Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2675451518 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 23095803 ps |
CPU time | 2.45 seconds |
Started | Aug 05 05:07:33 PM PDT 24 |
Finished | Aug 05 05:07:36 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-26acffaf-d380-48be-8668-38b501c441ac |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2675451518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2675451518 |
Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.2731099811 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 425330066 ps |
CPU time | 3.66 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-f445fbca-7c15-414b-8352-dac4892740d1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2731099811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2731099811 |
Directory | /workspace/30.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.1528976761 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1924510562 ps |
CPU time | 11.7 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-af870621-64af-4533-8d58-077204a697c1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1528976761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1528976761 |
Directory | /workspace/30.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3645212128 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 15213024303 ps |
CPU time | 49.17 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-cb93bfd7-7bf1-4cb9-8d03-ff60cb3b7946 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645212128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3645212128 |
Directory | /workspace/30.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1794821449 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 15132905017 ps |
CPU time | 55.71 seconds |
Started | Aug 05 05:07:15 PM PDT 24 |
Finished | Aug 05 05:08:10 PM PDT 24 |
Peak memory | 202136 kb |
Host | smart-77bf921b-fdaf-4883-b9ed-caa018fc744e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1794821449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1794821449 |
Directory | /workspace/30.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2554588366 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 96579401 ps |
CPU time | 8.39 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:38 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-d7f379b0-60f6-4e83-a3ed-25d56eccb80b |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554588366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2554588366 |
Directory | /workspace/30.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1847406619 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 8801624167 ps |
CPU time | 13.07 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-665dbbc8-67ef-4a15-96d0-3ebd160e2b96 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847406619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1847406619 |
Directory | /workspace/30.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.779093144 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 8918342 ps |
CPU time | 1.04 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:16 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-fdaacb57-7d97-41cd-98f0-a2b7cd295e67 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=779093144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.779093144 |
Directory | /workspace/30.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2747167664 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 4274422058 ps |
CPU time | 8.4 seconds |
Started | Aug 05 05:07:18 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-162e3ebc-5292-4878-b70d-518012086d12 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747167664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2747167664 |
Directory | /workspace/30.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.976973734 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 2410392037 ps |
CPU time | 10.5 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-11fce7b1-e34d-48c0-9558-d2c0dc3f2bae |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=976973734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.976973734 |
Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.874610907 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 14731587 ps |
CPU time | 1.12 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:18 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-28ba0d69-038c-4237-b3bd-244669a99c79 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874610907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.874610907 |
Directory | /workspace/30.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3440470986 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 908469048 ps |
CPU time | 16.9 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:07:46 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-4e6dec9c-5f4f-443b-9abe-62c0016e20a8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440470986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3440470986 |
Directory | /workspace/30.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1928717439 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 1345194904 ps |
CPU time | 17.34 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:07:40 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-c0706e79-1566-452b-9de4-8909c673a462 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1928717439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1928717439 |
Directory | /workspace/30.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2833054581 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 364905494 ps |
CPU time | 54.34 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:08:23 PM PDT 24 |
Peak memory | 204148 kb |
Host | smart-c6000982-5500-48f3-b517-23a019937c73 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2833054581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2833054581 |
Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3921453858 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 160928585 ps |
CPU time | 15.83 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:07:45 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-d6bad668-2da2-4dce-848b-a3352994eabe |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3921453858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.3921453858 |
Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1425519276 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 50505354 ps |
CPU time | 5.12 seconds |
Started | Aug 05 05:07:21 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-3c253999-ec3c-4a5b-b74c-12b5f62e316c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1425519276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1425519276 |
Directory | /workspace/30.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1590099786 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 1581214431 ps |
CPU time | 8.4 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:26 PM PDT 24 |
Peak memory | 201900 kb |
Host | smart-6c316578-5fac-4ba9-9e59-2bcd4945bc06 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590099786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1590099786 |
Directory | /workspace/31.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2429248969 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 84523647498 ps |
CPU time | 182.4 seconds |
Started | Aug 05 05:07:33 PM PDT 24 |
Finished | Aug 05 05:10:36 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-9164978d-222f-4dbc-8a7d-5ed6f3d43830 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2429248969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2429248969 |
Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1908919177 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 142387065 ps |
CPU time | 3.22 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:20 PM PDT 24 |
Peak memory | 201968 kb |
Host | smart-5d331550-dcc4-45af-aa11-0562ebd35716 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1908919177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1908919177 |
Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3967033030 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 723821139 ps |
CPU time | 10.5 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-c39c3d72-6aa6-4adc-8f8a-f03dc9121ffe |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967033030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3967033030 |
Directory | /workspace/31.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.3515977046 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 851198362 ps |
CPU time | 5.98 seconds |
Started | Aug 05 05:07:17 PM PDT 24 |
Finished | Aug 05 05:07:23 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-3c4e0eaa-862e-451a-8081-64b86ecc8946 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3515977046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3515977046 |
Directory | /workspace/31.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1749311983 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 6535492896 ps |
CPU time | 32.21 seconds |
Started | Aug 05 05:07:14 PM PDT 24 |
Finished | Aug 05 05:07:46 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-c1ee318a-5e94-4010-9ea2-800fcef4b674 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749311983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1749311983 |
Directory | /workspace/31.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2031328493 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 25524690556 ps |
CPU time | 159.32 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:10:03 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-b798063f-b8b1-4195-81f2-a4d40eceb962 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2031328493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2031328493 |
Directory | /workspace/31.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3527272582 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 61590751 ps |
CPU time | 4.37 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:07:26 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-4744a006-285d-46ed-85a4-a3c0517801b3 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527272582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3527272582 |
Directory | /workspace/31.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.3011701391 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 1727198755 ps |
CPU time | 4.29 seconds |
Started | Aug 05 05:07:13 PM PDT 24 |
Finished | Aug 05 05:07:17 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-d765cb53-3af2-43bc-96a8-e3cb5c076c0e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3011701391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3011701391 |
Directory | /workspace/31.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.397528392 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 144390050 ps |
CPU time | 1.76 seconds |
Started | Aug 05 05:07:19 PM PDT 24 |
Finished | Aug 05 05:07:21 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-710cff2c-10f5-46cb-8693-ba3fa53b32bd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=397528392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.397528392 |
Directory | /workspace/31.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.924407004 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 2810671841 ps |
CPU time | 9.95 seconds |
Started | Aug 05 05:07:15 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-dfe4584a-b5e9-46f0-9022-addb3d413ae5 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=924407004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.924407004 |
Directory | /workspace/31.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.4052693649 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 3023932503 ps |
CPU time | 12.1 seconds |
Started | Aug 05 05:07:22 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-6a8d31f0-b3cc-4e2e-862c-5711366b29e7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4052693649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4052693649 |
Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1095815271 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 13767100 ps |
CPU time | 1.05 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:07:29 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-3d858e18-b1cd-493e-a174-b1f59f9dc3c4 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095815271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1095815271 |
Directory | /workspace/31.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.2073218813 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 404292620 ps |
CPU time | 7.56 seconds |
Started | Aug 05 05:07:24 PM PDT 24 |
Finished | Aug 05 05:07:32 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-3c0f71a4-9cd0-45cc-acfa-a5bcc3d8ec03 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073218813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2073218813 |
Directory | /workspace/31.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3199987120 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 721031896 ps |
CPU time | 10.92 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:07:42 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-b9231529-7ea5-4ade-8d6f-a25329e772c0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3199987120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3199987120 |
Directory | /workspace/31.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2324292558 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 720150614 ps |
CPU time | 136.41 seconds |
Started | Aug 05 05:07:25 PM PDT 24 |
Finished | Aug 05 05:09:41 PM PDT 24 |
Peak memory | 204476 kb |
Host | smart-591ba035-a217-44df-a2dc-ca66c61e3de6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2324292558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.2324292558 |
Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3514992053 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 1170199594 ps |
CPU time | 11.78 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-dc663927-b31a-4bac-bacf-773bab63313d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3514992053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3514992053 |
Directory | /workspace/31.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.238750720 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 13190050 ps |
CPU time | 1.88 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-3d7feb13-a4a3-4fcd-87a4-afcbcbcb7b4b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=238750720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.238750720 |
Directory | /workspace/32.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2471405371 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 55128984424 ps |
CPU time | 310.78 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:12:34 PM PDT 24 |
Peak memory | 203112 kb |
Host | smart-80a0c091-c8b6-43f1-89f3-0af287642ab3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2471405371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2471405371 |
Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2105850777 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 989700072 ps |
CPU time | 4.99 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-9ab811ab-0d77-48fe-9232-9c1b747d6c1d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2105850777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2105850777 |
Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.1534702050 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 424358066 ps |
CPU time | 7.93 seconds |
Started | Aug 05 05:07:25 PM PDT 24 |
Finished | Aug 05 05:07:33 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-f3a791ad-999e-4651-a15c-fb791035fca4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1534702050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1534702050 |
Directory | /workspace/32.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.1503873815 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 41362856 ps |
CPU time | 3.37 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:07:35 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-7dfc8743-5412-4f09-a0db-e78b3e7dad06 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1503873815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1503873815 |
Directory | /workspace/32.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3723525355 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 38131530641 ps |
CPU time | 131.98 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:09:43 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-fa169d60-96d9-445c-9c3a-8d6c020d62a4 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723525355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3723525355 |
Directory | /workspace/32.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3674689787 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 63122560833 ps |
CPU time | 162.46 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:10:10 PM PDT 24 |
Peak memory | 202108 kb |
Host | smart-2c3ca4a5-e294-4155-9761-0d335c167cb9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3674689787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3674689787 |
Directory | /workspace/32.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4245618002 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 353385315 ps |
CPU time | 6.38 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-86a6e7a0-8e18-4a38-8353-66bd426c1464 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245618002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4245618002 |
Directory | /workspace/32.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1822734840 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 4890117652 ps |
CPU time | 12.34 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:07:40 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-3c9867e8-ce93-4e81-9517-3a814ef957e0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822734840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1822734840 |
Directory | /workspace/32.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.273209655 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 23223864 ps |
CPU time | 1.25 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 201968 kb |
Host | smart-d6419f54-b661-4d10-b0ff-9d8e19fb655c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273209655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.273209655 |
Directory | /workspace/32.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3568224656 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 15083030690 ps |
CPU time | 9.24 seconds |
Started | Aug 05 05:07:23 PM PDT 24 |
Finished | Aug 05 05:07:32 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-c2e209bc-8b10-4b39-8601-9917a81e210c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568224656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3568224656 |
Directory | /workspace/32.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2356474949 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 3555389033 ps |
CPU time | 12.97 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-43e019cc-50b2-4f41-be7a-20e5a2dde383 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2356474949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2356474949 |
Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4152410728 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 10965773 ps |
CPU time | 1.17 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:07:32 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-8071c932-7124-4ef8-bc22-e043312c376a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152410728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4152410728 |
Directory | /workspace/32.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3291114156 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 2888820777 ps |
CPU time | 13.72 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:41 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-b74c40cf-d8ef-4bdb-afce-c51a437bf14d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3291114156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3291114156 |
Directory | /workspace/32.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1441503661 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 2638524888 ps |
CPU time | 31.36 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-461fa2b8-3513-45e5-890e-122da4bb19ff |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1441503661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1441503661 |
Directory | /workspace/32.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4216995466 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 6962760928 ps |
CPU time | 136.86 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:09:47 PM PDT 24 |
Peak memory | 207744 kb |
Host | smart-27fdc86c-cca6-4ea0-a9c5-8d65f5841f46 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4216995466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.4216995466 |
Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1042852708 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 6717144524 ps |
CPU time | 93.13 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:09:05 PM PDT 24 |
Peak memory | 205780 kb |
Host | smart-9d9e0779-2c7e-4cbf-8dbe-edbad4384989 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1042852708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1042852708 |
Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3486506507 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 72678901 ps |
CPU time | 8.13 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:35 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-ea521491-3f81-4d0a-90fa-6523a249824e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3486506507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3486506507 |
Directory | /workspace/32.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3117336844 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 1039542527 ps |
CPU time | 22.81 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-b8d179bd-5329-454a-bba9-e00b8a590dfd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3117336844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3117336844 |
Directory | /workspace/33.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2115570433 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 14970119271 ps |
CPU time | 106.07 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:09:20 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-14b6d5e5-58f4-4676-9a8f-0638a9283666 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2115570433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2115570433 |
Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2485378830 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 2091944074 ps |
CPU time | 5.14 seconds |
Started | Aug 05 05:07:40 PM PDT 24 |
Finished | Aug 05 05:07:45 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-18cfa615-2230-417c-a8ec-24b0e916311d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2485378830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2485378830 |
Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.1267339322 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 400122770 ps |
CPU time | 6.69 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:07:38 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-edf39932-cb4f-402b-a0a1-27c9758b656f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1267339322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1267339322 |
Directory | /workspace/33.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2344172069 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 300285904 ps |
CPU time | 6.6 seconds |
Started | Aug 05 05:07:26 PM PDT 24 |
Finished | Aug 05 05:07:33 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-0eeeb84f-0d2e-44e1-9c54-48d89708a269 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2344172069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2344172069 |
Directory | /workspace/33.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.365754016 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 33906814122 ps |
CPU time | 143.66 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:09:54 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-e7e46166-fce6-493d-8841-4140f4ac053c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=365754016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.365754016 |
Directory | /workspace/33.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.175866591 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 1314631818 ps |
CPU time | 4.26 seconds |
Started | Aug 05 05:07:26 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-7aaf65ec-bde7-40ed-96c9-8d68bc4d2744 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=175866591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.175866591 |
Directory | /workspace/33.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3781014429 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 137792564 ps |
CPU time | 3.42 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:07:33 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-47e5dc72-0fc7-4e1e-be7f-2f65e67169ee |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781014429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3781014429 |
Directory | /workspace/33.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.3255009969 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 86790168 ps |
CPU time | 6.12 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:07:36 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-140f5b4c-ed35-4ad9-b3dc-1660346c5a20 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3255009969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3255009969 |
Directory | /workspace/33.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2497710813 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 277997035 ps |
CPU time | 1.21 seconds |
Started | Aug 05 05:07:24 PM PDT 24 |
Finished | Aug 05 05:07:26 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-16ee1f13-3aca-494f-884c-1a7fe009ef65 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2497710813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2497710813 |
Directory | /workspace/33.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.926318483 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 15621835877 ps |
CPU time | 12.22 seconds |
Started | Aug 05 05:07:27 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-97b850d3-8fa4-4b5d-8134-51cfec3c9087 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=926318483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.926318483 |
Directory | /workspace/33.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.641969370 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 2485900713 ps |
CPU time | 7.56 seconds |
Started | Aug 05 05:07:21 PM PDT 24 |
Finished | Aug 05 05:07:29 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-b2ddd762-5b93-41e7-90e8-b942bc46ff52 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=641969370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.641969370 |
Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2363066092 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 12545519 ps |
CPU time | 1.3 seconds |
Started | Aug 05 05:07:24 PM PDT 24 |
Finished | Aug 05 05:07:26 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-9f9dbbca-0896-4b13-a554-d240cd3dc353 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363066092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2363066092 |
Directory | /workspace/33.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3740112598 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 9995404921 ps |
CPU time | 34.55 seconds |
Started | Aug 05 05:07:33 PM PDT 24 |
Finished | Aug 05 05:08:08 PM PDT 24 |
Peak memory | 204040 kb |
Host | smart-54b4ff01-3532-4486-b3b1-f1f56d32c00e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740112598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3740112598 |
Directory | /workspace/33.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.88825367 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 513081145 ps |
CPU time | 20.53 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:51 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-c2fd88bc-0ec1-4e1f-94fb-4c7b3b96c910 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=88825367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.88825367 |
Directory | /workspace/33.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3468732479 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 921006930 ps |
CPU time | 142.91 seconds |
Started | Aug 05 05:07:39 PM PDT 24 |
Finished | Aug 05 05:10:02 PM PDT 24 |
Peak memory | 205988 kb |
Host | smart-c1d5f5ef-5a7f-45a7-a80d-c4df89537241 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3468732479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3468732479 |
Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1831615147 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 543882444 ps |
CPU time | 74.49 seconds |
Started | Aug 05 05:07:33 PM PDT 24 |
Finished | Aug 05 05:08:47 PM PDT 24 |
Peak memory | 206812 kb |
Host | smart-d73f2eac-06f9-490e-994f-bb5475dd3c69 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1831615147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.1831615147 |
Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.4269924950 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 135043894 ps |
CPU time | 7.44 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-a777ead0-7042-4a3d-823a-21c7b98110e5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4269924950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4269924950 |
Directory | /workspace/33.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.690267027 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 206561149 ps |
CPU time | 3.69 seconds |
Started | Aug 05 05:07:41 PM PDT 24 |
Finished | Aug 05 05:07:45 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-c295de8d-37e6-41df-91ab-df1ffaecdf51 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690267027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.690267027 |
Directory | /workspace/34.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2270072515 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 76468778 ps |
CPU time | 6.63 seconds |
Started | Aug 05 05:07:33 PM PDT 24 |
Finished | Aug 05 05:07:40 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-a66c4404-e883-4a2e-b43c-725d142ae1d4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2270072515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2270072515 |
Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1670165430 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 955606628 ps |
CPU time | 8.82 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 201888 kb |
Host | smart-ceb50079-6047-4b5c-bf9d-913fed2f80cb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1670165430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1670165430 |
Directory | /workspace/34.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3111151222 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 494740012 ps |
CPU time | 7.73 seconds |
Started | Aug 05 05:07:38 PM PDT 24 |
Finished | Aug 05 05:07:46 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-95f9df25-c19d-4ce3-a295-f1c62812a91d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3111151222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3111151222 |
Directory | /workspace/34.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.494660372 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 28091542405 ps |
CPU time | 87.93 seconds |
Started | Aug 05 05:07:29 PM PDT 24 |
Finished | Aug 05 05:08:58 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-68e4b83c-e509-42f7-a3df-e3057eadef9c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=494660372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.494660372 |
Directory | /workspace/34.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.645858155 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 12932570521 ps |
CPU time | 70.29 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:08:41 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-92b1cbdf-40bc-4a50-b32e-55a8248b1ef2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=645858155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.645858155 |
Directory | /workspace/34.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3967227184 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 27048075 ps |
CPU time | 3.21 seconds |
Started | Aug 05 05:07:32 PM PDT 24 |
Finished | Aug 05 05:07:36 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-723e274f-6b88-40c6-9afa-8b0a2f68536d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967227184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3967227184 |
Directory | /workspace/34.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.4046837489 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 796659608 ps |
CPU time | 4.13 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:07:33 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-b29ca32f-911c-4628-b402-d2d2abc15b65 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4046837489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4046837489 |
Directory | /workspace/34.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.3622990581 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 98350070 ps |
CPU time | 1.74 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:32 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-fcdecd6d-df91-4d74-96f6-a81839dd0b7a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3622990581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3622990581 |
Directory | /workspace/34.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.215633934 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 2647915646 ps |
CPU time | 8.48 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:07:42 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-c372853f-1635-4bbd-b8f7-d59f31d9abab |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=215633934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.215633934 |
Directory | /workspace/34.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3970240309 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 1110801715 ps |
CPU time | 8.37 seconds |
Started | Aug 05 05:07:28 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-ad474899-82e1-41a0-8389-ac4132f2b2ce |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3970240309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3970240309 |
Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1974666007 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 10490970 ps |
CPU time | 1.06 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-6d6d476c-29c7-4c64-b34b-642e6cba1f99 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974666007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1974666007 |
Directory | /workspace/34.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.2897899821 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 547754032 ps |
CPU time | 31.16 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-c2098ffa-15c9-4832-b1f6-388e4bb950c8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2897899821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2897899821 |
Directory | /workspace/34.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3097175669 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 762917840 ps |
CPU time | 21.89 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-1da991ec-1beb-4a3e-aa79-5bf12e3abd81 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3097175669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3097175669 |
Directory | /workspace/34.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1700016364 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1288983672 ps |
CPU time | 92.59 seconds |
Started | Aug 05 05:07:35 PM PDT 24 |
Finished | Aug 05 05:09:07 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-4db07fff-dd0f-4932-88bb-8cc44fc0a5b8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1700016364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1700016364 |
Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1177502246 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 2929913205 ps |
CPU time | 87.34 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:08:57 PM PDT 24 |
Peak memory | 204272 kb |
Host | smart-f79a2bcb-95e3-4b9b-b0e4-88ef19d3acba |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1177502246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.1177502246 |
Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2305431738 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 10127709 ps |
CPU time | 1.29 seconds |
Started | Aug 05 05:07:52 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-7e8573db-a242-49a2-b3b6-14c61819fb5a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2305431738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2305431738 |
Directory | /workspace/34.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.940014032 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 443138549 ps |
CPU time | 5.49 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:36 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-d9f3faf4-1f21-4904-b7a3-483260b8c140 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=940014032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.940014032 |
Directory | /workspace/35.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.875505053 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 4768176225 ps |
CPU time | 22.29 seconds |
Started | Aug 05 05:07:32 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-397ea9eb-6793-4673-8810-10c9118e3111 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=875505053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.875505053 |
Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.452688412 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 129224539 ps |
CPU time | 1.26 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-e0d62fcd-559b-44f1-8b75-c370ab63dbe3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=452688412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.452688412 |
Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1840769303 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 90334638 ps |
CPU time | 6.13 seconds |
Started | Aug 05 05:07:32 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-d50133be-c75d-4bcf-bc06-c46aa9bc3260 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840769303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1840769303 |
Directory | /workspace/35.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.4087456175 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 326014821 ps |
CPU time | 7.53 seconds |
Started | Aug 05 05:07:31 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-843f7208-736f-4e9a-a305-594dbde4807e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4087456175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.4087456175 |
Directory | /workspace/35.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3893678198 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 33101428302 ps |
CPU time | 119.54 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:09:30 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-e6925fb6-e25f-4b80-9417-8e5736dfbda8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893678198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3893678198 |
Directory | /workspace/35.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.971102889 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 16630329489 ps |
CPU time | 99.95 seconds |
Started | Aug 05 05:07:32 PM PDT 24 |
Finished | Aug 05 05:09:12 PM PDT 24 |
Peak memory | 202348 kb |
Host | smart-0e1ca341-5a38-4fb7-a2f2-bca5d1f91ee7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=971102889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.971102889 |
Directory | /workspace/35.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1641440909 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 45328103 ps |
CPU time | 6.02 seconds |
Started | Aug 05 05:07:30 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-4d33e9e1-f737-4dc3-8747-6ddd117a0d0a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641440909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1641440909 |
Directory | /workspace/35.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3689649433 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 851139660 ps |
CPU time | 5.23 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-f98b4b24-659a-4f32-b929-259b1d4f9155 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3689649433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3689649433 |
Directory | /workspace/35.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.2987912828 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 55295610 ps |
CPU time | 1.55 seconds |
Started | Aug 05 05:07:51 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-55b19d11-81d4-466d-b779-cf9b55fc55fb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2987912828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2987912828 |
Directory | /workspace/35.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2642002770 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 4569498778 ps |
CPU time | 8.49 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:07:47 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-a2dc16ed-9145-45e9-9c96-aaf0688be35c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642002770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2642002770 |
Directory | /workspace/35.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.912669011 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 753149954 ps |
CPU time | 5.09 seconds |
Started | Aug 05 05:07:32 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-2138f50b-c93e-4080-991b-5577f85c64ab |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=912669011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.912669011 |
Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4174164889 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 11471828 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:07:33 PM PDT 24 |
Finished | Aug 05 05:07:34 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-06632257-64c8-4465-af62-71a0a9a5ed72 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174164889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4174164889 |
Directory | /workspace/35.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2847428684 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 697587080 ps |
CPU time | 12.94 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-5bb00ba6-7682-47b4-8350-ceda085a1fc6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2847428684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2847428684 |
Directory | /workspace/35.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4198019192 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 93791367 ps |
CPU time | 5.32 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-1e1b3717-1876-45e4-ad91-2d6539abb066 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4198019192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4198019192 |
Directory | /workspace/35.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1902005049 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1339988209 ps |
CPU time | 112.93 seconds |
Started | Aug 05 05:07:39 PM PDT 24 |
Finished | Aug 05 05:09:32 PM PDT 24 |
Peak memory | 204372 kb |
Host | smart-0db213e3-23de-49c1-a813-d79beabf30f4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1902005049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1902005049 |
Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.385252073 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 664855098 ps |
CPU time | 44.64 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:08:33 PM PDT 24 |
Peak memory | 204184 kb |
Host | smart-87a35959-df20-4382-a726-0572e0807175 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=385252073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_res et_error.385252073 |
Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3396686628 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 185769181 ps |
CPU time | 3.68 seconds |
Started | Aug 05 05:07:35 PM PDT 24 |
Finished | Aug 05 05:07:39 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-fc1a40ee-e34e-4828-90e6-eadd725c05db |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3396686628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3396686628 |
Directory | /workspace/35.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1616223742 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 44464415 ps |
CPU time | 5.47 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-1057e1b8-9b5a-47e9-bb29-4c35048f8195 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1616223742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1616223742 |
Directory | /workspace/36.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3126329980 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 29830026010 ps |
CPU time | 167.28 seconds |
Started | Aug 05 05:07:41 PM PDT 24 |
Finished | Aug 05 05:10:28 PM PDT 24 |
Peak memory | 203244 kb |
Host | smart-22f6584a-7f81-4844-85e8-583bef8caf6e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3126329980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.3126329980 |
Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2491847163 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 383129532 ps |
CPU time | 4.91 seconds |
Started | Aug 05 05:08:02 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-5396106f-24bf-412c-bf7f-b21118404adc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2491847163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2491847163 |
Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1388027995 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 115254613 ps |
CPU time | 4.4 seconds |
Started | Aug 05 05:07:49 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-031d4dca-7d2c-424f-91de-4a7d0778da78 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1388027995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1388027995 |
Directory | /workspace/36.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.437037598 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 30749631 ps |
CPU time | 4.13 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:08:01 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-7e4906a9-c300-4aaf-8c8d-60dca362a811 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=437037598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.437037598 |
Directory | /workspace/36.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.4123468615 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 9285559150 ps |
CPU time | 23.93 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-90fca537-a298-4194-8bb6-f5db90743421 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123468615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.4123468615 |
Directory | /workspace/36.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3104159575 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 54332086306 ps |
CPU time | 126.55 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:09:55 PM PDT 24 |
Peak memory | 202124 kb |
Host | smart-c5ac9ca0-7ba0-4729-9828-7ba3cc7ac479 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3104159575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3104159575 |
Directory | /workspace/36.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1755084863 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 51333801 ps |
CPU time | 5.51 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:42 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-a981ed0b-bee3-4746-9ddc-378306091fe1 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755084863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1755084863 |
Directory | /workspace/36.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2559498709 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 57031732 ps |
CPU time | 5.19 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:07:59 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-9f56af04-ecf8-466b-a841-6f44022adac4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2559498709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2559498709 |
Directory | /workspace/36.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2922791797 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 134869313 ps |
CPU time | 1.49 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-2d4a3edd-57da-4b2c-9e78-936963ad2e2b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2922791797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2922791797 |
Directory | /workspace/36.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1747699762 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 1680587895 ps |
CPU time | 7.16 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:07:51 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-93fb806f-efc6-495d-8f65-fa0f57fe910c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747699762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1747699762 |
Directory | /workspace/36.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3486613967 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 8273139334 ps |
CPU time | 11.58 seconds |
Started | Aug 05 05:07:35 PM PDT 24 |
Finished | Aug 05 05:07:47 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-311576cb-9a3c-4c97-89d3-58f2ed7552fb |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3486613967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3486613967 |
Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.702271521 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 7687925 ps |
CPU time | 1.04 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:07:48 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-88259870-6e93-49bd-85eb-d6f08478048f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702271521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.702271521 |
Directory | /workspace/36.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3878830732 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 209695032 ps |
CPU time | 20.51 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-5ea2b59e-61fd-44ba-8ac3-dfc540b72ab1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3878830732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3878830732 |
Directory | /workspace/36.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.378017161 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 1098702473 ps |
CPU time | 54.07 seconds |
Started | Aug 05 05:07:52 PM PDT 24 |
Finished | Aug 05 05:08:46 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-009bb642-9bd3-47f5-a543-1530e80362d6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=378017161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.378017161 |
Directory | /workspace/36.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2177766318 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 1176975878 ps |
CPU time | 21.22 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-d81b3415-93f6-4d13-8aec-97d469a2b316 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2177766318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2177766318 |
Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2155780635 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 213741849 ps |
CPU time | 20.21 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:56 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-530fba79-04d3-4c50-a76a-a5efe7f62da1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2155780635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2155780635 |
Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.484668968 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 340402091 ps |
CPU time | 6.34 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-c30f5b79-9ba6-47a9-a36f-c5e833db7f4b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=484668968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.484668968 |
Directory | /workspace/36.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3370123196 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 41714139 ps |
CPU time | 7.26 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:43 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-bd16c4a1-70d6-4be5-82e4-0163e297ef91 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3370123196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3370123196 |
Directory | /workspace/37.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.579794615 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 44770371 ps |
CPU time | 4.08 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-46d802e0-6528-4671-8989-a1b3bcdd8285 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579794615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.579794615 |
Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.487325758 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 2376398967 ps |
CPU time | 5.87 seconds |
Started | Aug 05 05:07:36 PM PDT 24 |
Finished | Aug 05 05:07:42 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-aa40bf59-ef7f-4c8a-aa6e-da008c10e945 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=487325758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.487325758 |
Directory | /workspace/37.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2629633173 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1066457678 ps |
CPU time | 11.9 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-a8962196-d2eb-4124-994e-483e1161255b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2629633173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2629633173 |
Directory | /workspace/37.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.255513789 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 122589733239 ps |
CPU time | 111.1 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:09:40 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-54f72d28-6381-4394-84d6-b5ceb2815bbe |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=255513789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.255513789 |
Directory | /workspace/37.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3040263357 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 24924914083 ps |
CPU time | 98.52 seconds |
Started | Aug 05 05:07:55 PM PDT 24 |
Finished | Aug 05 05:09:33 PM PDT 24 |
Peak memory | 202052 kb |
Host | smart-27f1eea2-928d-4112-aad1-aa0e948ead26 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3040263357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3040263357 |
Directory | /workspace/37.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.4141785170 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 21358498 ps |
CPU time | 1.1 seconds |
Started | Aug 05 05:07:51 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-8bf2bba5-1ddb-4550-9db2-030bd25ca080 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141785170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.4141785170 |
Directory | /workspace/37.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.3910937592 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 1297404892 ps |
CPU time | 13.16 seconds |
Started | Aug 05 05:07:53 PM PDT 24 |
Finished | Aug 05 05:08:06 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-8d431e8a-a52e-426f-b619-f037254d3b2e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3910937592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3910937592 |
Directory | /workspace/37.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2870487081 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 95588173 ps |
CPU time | 1.49 seconds |
Started | Aug 05 05:07:53 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-ae13cbd4-874c-45ab-aa98-eafd557e48a5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2870487081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2870487081 |
Directory | /workspace/37.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3050718231 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2775209781 ps |
CPU time | 13.75 seconds |
Started | Aug 05 05:07:46 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-b65f0cb1-1f79-42ec-ad46-562cf42e35b6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050718231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3050718231 |
Directory | /workspace/37.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1515793095 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 3253037407 ps |
CPU time | 5.07 seconds |
Started | Aug 05 05:07:39 PM PDT 24 |
Finished | Aug 05 05:07:44 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-89fcead5-cd04-472a-84a0-ae14890a3b79 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1515793095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1515793095 |
Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1539102473 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 8623721 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:07:35 PM PDT 24 |
Finished | Aug 05 05:07:37 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-0b80efd2-a6ad-451b-a531-95edb6cefbfa |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539102473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1539102473 |
Directory | /workspace/37.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.2583805843 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 9870547871 ps |
CPU time | 81.75 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:09:09 PM PDT 24 |
Peak memory | 204088 kb |
Host | smart-0d161c6d-720d-48cc-90e3-ecdcd05086e1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2583805843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2583805843 |
Directory | /workspace/37.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1320895686 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1056656092 ps |
CPU time | 36.29 seconds |
Started | Aug 05 05:07:38 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-da2bfd3d-98b6-4c3b-b67f-27304c55d6fa |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1320895686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1320895686 |
Directory | /workspace/37.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.285063760 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 21443416459 ps |
CPU time | 200.08 seconds |
Started | Aug 05 05:07:34 PM PDT 24 |
Finished | Aug 05 05:10:54 PM PDT 24 |
Peak memory | 206244 kb |
Host | smart-4580da3c-f074-48e4-9b00-aad609cd16f1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285063760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.285063760 |
Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1531081149 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 16106599870 ps |
CPU time | 148.74 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:10:11 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-1064bf70-cb1e-40c6-a65e-ce54b1ca7208 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1531081149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1531081149 |
Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1386274400 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 1580541462 ps |
CPU time | 8.59 seconds |
Started | Aug 05 05:07:41 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-74704a96-7ea6-4379-ac33-dc5ee1a5f027 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1386274400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1386274400 |
Directory | /workspace/37.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.4227027828 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 624703026 ps |
CPU time | 11.84 seconds |
Started | Aug 05 05:07:35 PM PDT 24 |
Finished | Aug 05 05:07:47 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-95e2a614-66eb-4811-ac63-71308dc6c618 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4227027828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.4227027828 |
Directory | /workspace/38.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1999894181 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 21635127315 ps |
CPU time | 158.15 seconds |
Started | Aug 05 05:07:49 PM PDT 24 |
Finished | Aug 05 05:10:27 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-a25035b4-4a68-425e-a174-860a703fadfc |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1999894181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1999894181 |
Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3745963335 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 166120649 ps |
CPU time | 3.97 seconds |
Started | Aug 05 05:07:45 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-20c9cca3-5418-4b96-a5d3-976300dc4fa5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745963335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3745963335 |
Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2138545566 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 1975310681 ps |
CPU time | 6.51 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-e06d6a81-829a-4050-a500-70d57d118862 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2138545566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2138545566 |
Directory | /workspace/38.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.1086288555 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 49570866 ps |
CPU time | 3.95 seconds |
Started | Aug 05 05:07:53 PM PDT 24 |
Finished | Aug 05 05:07:57 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-1c71b08e-6705-4205-87e4-5179bc37aa1d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1086288555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1086288555 |
Directory | /workspace/38.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.329132829 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 125213993343 ps |
CPU time | 96.07 seconds |
Started | Aug 05 05:07:53 PM PDT 24 |
Finished | Aug 05 05:09:29 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-0e071545-56b8-4b0f-8c20-b0330a08a353 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=329132829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.329132829 |
Directory | /workspace/38.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.279450237 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 34453053340 ps |
CPU time | 181.46 seconds |
Started | Aug 05 05:07:35 PM PDT 24 |
Finished | Aug 05 05:10:36 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-05c83226-da04-424d-a5d8-901d6bcb1590 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=279450237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.279450237 |
Directory | /workspace/38.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1781231665 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 91802291 ps |
CPU time | 4.09 seconds |
Started | Aug 05 05:07:52 PM PDT 24 |
Finished | Aug 05 05:07:56 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-c1e37c70-9d75-457a-b961-835155f8064a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781231665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1781231665 |
Directory | /workspace/38.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1894833349 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 772010842 ps |
CPU time | 9 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:05 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-84ade024-3a7e-4d0b-9ded-9da49f695cb9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1894833349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1894833349 |
Directory | /workspace/38.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.1548035079 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 13344108 ps |
CPU time | 1.06 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:07:48 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-5f2adf46-3c51-4581-8c20-b7295913eceb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1548035079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1548035079 |
Directory | /workspace/38.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1828927586 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 12191997074 ps |
CPU time | 11.29 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-4f0b41a3-a381-4331-9039-ec2bbeaaf628 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828927586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1828927586 |
Directory | /workspace/38.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.288637939 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 1654029630 ps |
CPU time | 6.72 seconds |
Started | Aug 05 05:07:38 PM PDT 24 |
Finished | Aug 05 05:07:45 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-84209c50-aa48-4792-b2b7-e2fc0cfb7290 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=288637939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.288637939 |
Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1012814280 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 8702501 ps |
CPU time | 1.08 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:50 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-f2c17db6-5d8b-4e13-b974-09bd596c95de |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012814280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1012814280 |
Directory | /workspace/38.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.718795033 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 4671539399 ps |
CPU time | 17.71 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-e5db714b-0655-4ee4-ac29-bbf0e0f72993 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=718795033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.718795033 |
Directory | /workspace/38.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1534676495 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 30665822603 ps |
CPU time | 130.56 seconds |
Started | Aug 05 05:07:55 PM PDT 24 |
Finished | Aug 05 05:10:05 PM PDT 24 |
Peak memory | 204008 kb |
Host | smart-43637c98-fe7a-4c4c-b709-358091527081 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1534676495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1534676495 |
Directory | /workspace/38.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1613634443 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 144728809 ps |
CPU time | 14.69 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:07:58 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-d2dbc71f-cacb-4562-9350-a02f113860c7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1613634443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1613634443 |
Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2427457912 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 788164041 ps |
CPU time | 74.29 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:09:11 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-adc91113-f173-4f4e-b66d-f412fe74a3a3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2427457912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2427457912 |
Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1094457322 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 2705650891 ps |
CPU time | 11.5 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 201976 kb |
Host | smart-cf1196a4-7475-4c8b-be0b-10f0aab9ad55 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1094457322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1094457322 |
Directory | /workspace/38.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3743852001 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 489914768 ps |
CPU time | 12.81 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:22 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-88d806bd-62ec-42f5-bb70-783fb4fb4b40 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3743852001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3743852001 |
Directory | /workspace/39.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.453711005 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 132851938313 ps |
CPU time | 152.58 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:10:29 PM PDT 24 |
Peak memory | 203084 kb |
Host | smart-e53b8459-2f3b-47d3-963e-9470ead84a86 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=453711005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo w_rsp.453711005 |
Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.4735529 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 1436169249 ps |
CPU time | 10.51 seconds |
Started | Aug 05 05:07:49 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-f9edde3c-1d08-4428-af40-df5435058583 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4735529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.4735529 |
Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3036488790 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 130265178 ps |
CPU time | 5.93 seconds |
Started | Aug 05 05:07:53 PM PDT 24 |
Finished | Aug 05 05:07:59 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-70cf409d-0456-4ae3-93fc-20610df508d8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3036488790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3036488790 |
Directory | /workspace/39.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.824367801 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 363434116 ps |
CPU time | 4.6 seconds |
Started | Aug 05 05:07:50 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-e8a0945e-69f3-41ff-b1d5-91135cc4b1d2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=824367801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.824367801 |
Directory | /workspace/39.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.225529627 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 8484952265 ps |
CPU time | 41.59 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:38 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-6cb32861-9da5-4710-baa5-4bd51c42d62d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=225529627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.225529627 |
Directory | /workspace/39.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3218547191 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 51074239046 ps |
CPU time | 103.64 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:09:26 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-d5e226d1-7ecd-461c-8ded-0c586c1c5274 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3218547191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3218547191 |
Directory | /workspace/39.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1323113615 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 32538514 ps |
CPU time | 4.62 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-f9ba2969-2f03-418e-9395-2fc63a470f9e |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323113615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1323113615 |
Directory | /workspace/39.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.2087556271 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 55817025 ps |
CPU time | 2.78 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:07:47 PM PDT 24 |
Peak memory | 201924 kb |
Host | smart-3c1b7400-e70f-4a4a-bcbe-180fa70e9858 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2087556271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2087556271 |
Directory | /workspace/39.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.3921197272 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 55265356 ps |
CPU time | 1.38 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:07:59 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-ee395fa0-aa46-4a07-b2fa-b9b1106237ab |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3921197272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3921197272 |
Directory | /workspace/39.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2525443440 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 2906755804 ps |
CPU time | 10.1 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-6417c5ab-9b1e-4c3c-b06d-0471a725418a |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525443440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2525443440 |
Directory | /workspace/39.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3854168690 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 6628386382 ps |
CPU time | 7.02 seconds |
Started | Aug 05 05:07:41 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-14391474-85d8-4114-acbf-27815ca81dba |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3854168690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3854168690 |
Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1548788619 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 9289730 ps |
CPU time | 1.14 seconds |
Started | Aug 05 05:08:03 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-811545ac-6bdb-4a4d-a268-148452c4a7c4 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548788619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1548788619 |
Directory | /workspace/39.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.193950438 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 5934719811 ps |
CPU time | 39.41 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:08:23 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-1d18a729-e01c-4c5a-8ace-2948dcebebf2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=193950438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.193950438 |
Directory | /workspace/39.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3286806786 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 4602908048 ps |
CPU time | 59.91 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:08:43 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-908a1b99-9892-4dd4-945f-d1877bc8f886 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3286806786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3286806786 |
Directory | /workspace/39.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3691942047 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 6428174147 ps |
CPU time | 195.17 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:11:11 PM PDT 24 |
Peak memory | 206192 kb |
Host | smart-958aa50c-d033-4974-a5a0-81210cb119e4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3691942047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3691942047 |
Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1239207525 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 143618787 ps |
CPU time | 22.03 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:08:05 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-90c49c43-e090-4aaf-85c8-3d6acc34228c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1239207525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1239207525 |
Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3992229187 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 38455187 ps |
CPU time | 2.38 seconds |
Started | Aug 05 05:07:50 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-308ed94a-6823-4cee-a69f-3115cf702566 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3992229187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3992229187 |
Directory | /workspace/39.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.808693700 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 38520858 ps |
CPU time | 5.97 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:06:42 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-f1657c2e-d107-4c76-93b4-ef04edf116e2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808693700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.808693700 |
Directory | /workspace/4.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2916529976 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 28739344567 ps |
CPU time | 171.08 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:09:20 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-1fb3a35f-62f1-4a0e-80a3-f6ed6f6fb2de |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2916529976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2916529976 |
Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1182016694 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 935861878 ps |
CPU time | 9.3 seconds |
Started | Aug 05 05:06:08 PM PDT 24 |
Finished | Aug 05 05:06:17 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-718b3740-15a3-4276-8004-3df464b1fc24 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1182016694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1182016694 |
Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.2608292817 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 303775105 ps |
CPU time | 5.27 seconds |
Started | Aug 05 05:06:05 PM PDT 24 |
Finished | Aug 05 05:06:11 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-dc3ac0ab-3ac7-4a3c-a202-e56359f9c46d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2608292817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2608292817 |
Directory | /workspace/4.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.2418883396 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 78861510 ps |
CPU time | 4.62 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:32 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-47c7792a-9e8f-4d58-95d4-c33c7ab99f07 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418883396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2418883396 |
Directory | /workspace/4.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3167163648 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 95792163642 ps |
CPU time | 120.13 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:08:21 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-668408c1-b893-4dce-9757-b1f50f2bb571 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167163648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3167163648 |
Directory | /workspace/4.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3414453185 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 31533037319 ps |
CPU time | 95.4 seconds |
Started | Aug 05 05:06:09 PM PDT 24 |
Finished | Aug 05 05:07:44 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-91401851-9874-426c-a90c-d0984abd28a0 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3414453185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3414453185 |
Directory | /workspace/4.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.974231091 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 64103314 ps |
CPU time | 2.83 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:06:10 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-4aba0f8a-aa53-4895-85b1-c78699efa6ec |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974231091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.974231091 |
Directory | /workspace/4.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.2299341929 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 1112760458 ps |
CPU time | 10.36 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:06:27 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-969995aa-b7ee-40eb-a939-d862151eeb5c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2299341929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2299341929 |
Directory | /workspace/4.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2422551006 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 139402294 ps |
CPU time | 1.82 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-61553c42-c042-4b98-a653-777a15e176c5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2422551006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2422551006 |
Directory | /workspace/4.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1875677390 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 6951803463 ps |
CPU time | 10.22 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-3f585999-16c2-4ab9-9b06-a19413a01304 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875677390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1875677390 |
Directory | /workspace/4.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.727458458 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 928929653 ps |
CPU time | 7.39 seconds |
Started | Aug 05 05:06:19 PM PDT 24 |
Finished | Aug 05 05:06:27 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-ec356ea6-8da1-46d0-b6a8-4a782627497c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727458458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.727458458 |
Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3832760251 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 13103997 ps |
CPU time | 1.15 seconds |
Started | Aug 05 05:06:05 PM PDT 24 |
Finished | Aug 05 05:06:06 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-915693bf-d174-4e29-b701-17b17beada9b |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832760251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3832760251 |
Directory | /workspace/4.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1260946166 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 286184603 ps |
CPU time | 5.85 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:06:29 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-81d98ac0-f641-491f-866b-e2da957a022d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1260946166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1260946166 |
Directory | /workspace/4.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2632798045 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 9990093286 ps |
CPU time | 57.13 seconds |
Started | Aug 05 05:06:07 PM PDT 24 |
Finished | Aug 05 05:07:04 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-4631a298-1b23-4d78-9839-addfada19124 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2632798045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2632798045 |
Directory | /workspace/4.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1347598888 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 619444520 ps |
CPU time | 79.58 seconds |
Started | Aug 05 05:06:05 PM PDT 24 |
Finished | Aug 05 05:07:25 PM PDT 24 |
Peak memory | 206352 kb |
Host | smart-f59b9156-29e9-4657-b836-30868d8a2d75 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1347598888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1347598888 |
Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2258701608 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 45010172 ps |
CPU time | 3.21 seconds |
Started | Aug 05 05:06:04 PM PDT 24 |
Finished | Aug 05 05:06:08 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-46e56f50-38d5-48e1-829a-47c1753b99ff |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2258701608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2258701608 |
Directory | /workspace/4.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.219407291 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 385815334 ps |
CPU time | 2.06 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:07:58 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-57487a0c-5fb9-4cd1-a0e5-b55d8878662f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=219407291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.219407291 |
Directory | /workspace/40.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.4023143682 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 60269758738 ps |
CPU time | 150.61 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:10:13 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-ffe6b017-6f52-4ca1-a4bb-26050d2cf2ca |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4023143682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.4023143682 |
Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2944732861 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 1007914742 ps |
CPU time | 9.53 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-ec8c4e10-59c9-478b-bc6e-a7063112a4d4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2944732861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2944732861 |
Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3727439167 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1467939430 ps |
CPU time | 11.75 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:08:06 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-751d41ec-2cd8-47d3-aeb0-e7558b7928d7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3727439167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3727439167 |
Directory | /workspace/40.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.2412321949 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 1170612013 ps |
CPU time | 13.57 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:07:57 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-a74457f2-d7f4-4122-a4db-e79716df33a1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2412321949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2412321949 |
Directory | /workspace/40.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.564221318 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 105007439768 ps |
CPU time | 162.59 seconds |
Started | Aug 05 05:07:45 PM PDT 24 |
Finished | Aug 05 05:10:28 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-4702a68f-6d10-474c-9dec-c9818d3897e2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=564221318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.564221318 |
Directory | /workspace/40.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1247361585 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 80655316898 ps |
CPU time | 77.2 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:09:04 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-7de95b61-74e3-4bec-88dd-b47e7fadace9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1247361585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1247361585 |
Directory | /workspace/40.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1839842893 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 104367174 ps |
CPU time | 4.99 seconds |
Started | Aug 05 05:07:42 PM PDT 24 |
Finished | Aug 05 05:07:47 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-7d0fc3c5-61af-418a-a4f7-1c6e8b7ec16f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839842893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1839842893 |
Directory | /workspace/40.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3335786743 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 629100395 ps |
CPU time | 8.62 seconds |
Started | Aug 05 05:07:55 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-a6023881-fffb-4cc8-97b0-bb6132ec10c4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3335786743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3335786743 |
Directory | /workspace/40.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2950934547 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 8684594 ps |
CPU time | 1.06 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:07:48 PM PDT 24 |
Peak memory | 202124 kb |
Host | smart-9fb2d02d-d07a-45af-8efb-91ee27147a77 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2950934547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2950934547 |
Directory | /workspace/40.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.321366355 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 8839322452 ps |
CPU time | 7.46 seconds |
Started | Aug 05 05:07:45 PM PDT 24 |
Finished | Aug 05 05:07:52 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-3de41a17-9658-48fc-8c30-00dcc6cb5f3d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=321366355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.321366355 |
Directory | /workspace/40.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3959091881 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 908451184 ps |
CPU time | 7.49 seconds |
Started | Aug 05 05:07:45 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-a920ca9a-2712-4f63-b311-c0a2474d34ae |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3959091881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3959091881 |
Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3972402324 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 8948209 ps |
CPU time | 1.22 seconds |
Started | Aug 05 05:08:04 PM PDT 24 |
Finished | Aug 05 05:08:05 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-86823bc4-a841-401e-a226-5b7280d94a3a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972402324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3972402324 |
Directory | /workspace/40.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3265917268 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 10616794037 ps |
CPU time | 66.8 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:08:50 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-f545b75e-cc60-4853-b45b-bc2ec4fd75b8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3265917268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3265917268 |
Directory | /workspace/40.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.370383575 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 100988101 ps |
CPU time | 8.14 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:08:16 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-2bbd01bc-96c1-4400-86c7-9cc14b9b7718 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=370383575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.370383575 |
Directory | /workspace/40.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1777888103 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 117240397 ps |
CPU time | 24.08 seconds |
Started | Aug 05 05:07:50 PM PDT 24 |
Finished | Aug 05 05:08:15 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-5b91ef3e-2dc8-440a-a9d2-17c60f4db664 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1777888103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1777888103 |
Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3121451310 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 74388682 ps |
CPU time | 5.58 seconds |
Started | Aug 05 05:07:44 PM PDT 24 |
Finished | Aug 05 05:07:50 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-af31065b-a9e2-40cf-89f5-0496fab51481 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3121451310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3121451310 |
Directory | /workspace/40.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3300945445 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 25489717 ps |
CPU time | 5.07 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-d38ac7ff-d22b-46f4-9ae1-cfc37c9b9241 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3300945445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3300945445 |
Directory | /workspace/41.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.456548161 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 680134627 ps |
CPU time | 5.04 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:08:02 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-f8688a3d-afa6-4f52-998c-f959320cbf6c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456548161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.456548161 |
Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.3982328098 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 20757181 ps |
CPU time | 2.87 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:51 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-746a2947-ef4c-4da9-9399-0a1d265f2df0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3982328098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3982328098 |
Directory | /workspace/41.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.981075503 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 674176744 ps |
CPU time | 3.47 seconds |
Started | Aug 05 05:07:53 PM PDT 24 |
Finished | Aug 05 05:07:57 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-1e16743e-afbc-4133-9041-ea04bd608991 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981075503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.981075503 |
Directory | /workspace/41.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2530928788 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 28067719477 ps |
CPU time | 124.73 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:09:52 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-994ec7eb-f7d1-4ac0-a136-2230033c8be1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530928788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2530928788 |
Directory | /workspace/41.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1401429803 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 28691981766 ps |
CPU time | 117.77 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:09:52 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-e2eab7c9-efb4-4212-b3cd-c6c98381e729 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1401429803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1401429803 |
Directory | /workspace/41.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3462288041 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 24576131 ps |
CPU time | 2.46 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:08:01 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-e713570d-f026-48f9-80fd-496affe738fa |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462288041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3462288041 |
Directory | /workspace/41.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.3360522548 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 2748153775 ps |
CPU time | 4.58 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:08:11 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-6f4724a9-7319-4c73-a853-c21401b38716 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3360522548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3360522548 |
Directory | /workspace/41.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2662768555 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 263132135 ps |
CPU time | 1.81 seconds |
Started | Aug 05 05:07:41 PM PDT 24 |
Finished | Aug 05 05:07:43 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-8b746495-47e4-4d58-8208-d957e6305678 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662768555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2662768555 |
Directory | /workspace/41.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1134176815 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 1861321806 ps |
CPU time | 7.42 seconds |
Started | Aug 05 05:07:59 PM PDT 24 |
Finished | Aug 05 05:08:06 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-a9635117-5c72-4b6a-81da-966b3e6d3661 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134176815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1134176815 |
Directory | /workspace/41.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2273064885 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1649317451 ps |
CPU time | 12.5 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-d3462876-f2d1-4a9d-965b-7bd54d431fe3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2273064885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2273064885 |
Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.949813471 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 19507491 ps |
CPU time | 1.34 seconds |
Started | Aug 05 05:07:43 PM PDT 24 |
Finished | Aug 05 05:07:44 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-85ecd70a-df41-4fef-81bc-2ca61246eb5f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949813471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.949813471 |
Directory | /workspace/41.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1267867741 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 359180980 ps |
CPU time | 19.65 seconds |
Started | Aug 05 05:08:03 PM PDT 24 |
Finished | Aug 05 05:08:23 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-c1126833-854c-4c55-af30-4470fb1a592b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1267867741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1267867741 |
Directory | /workspace/41.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3480233411 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 1485907186 ps |
CPU time | 25.45 seconds |
Started | Aug 05 05:07:50 PM PDT 24 |
Finished | Aug 05 05:08:16 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-65063058-5f14-455b-8a41-1328dbed8beb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3480233411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3480233411 |
Directory | /workspace/41.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.999862558 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1247704706 ps |
CPU time | 99.44 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:09:37 PM PDT 24 |
Peak memory | 204256 kb |
Host | smart-971f1ae9-efde-4675-b969-a4dd2b31f419 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=999862558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.999862558 |
Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3499585119 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 818775979 ps |
CPU time | 73.35 seconds |
Started | Aug 05 05:08:06 PM PDT 24 |
Finished | Aug 05 05:09:20 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-e9e15642-7531-46fe-8b54-76e7fe8200a3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499585119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.3499585119 |
Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3267246112 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 1971230163 ps |
CPU time | 8.42 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:57 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-37823fcf-c3fc-43c9-a2fd-b881dc93820e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3267246112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3267246112 |
Directory | /workspace/41.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2923115389 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 21182338 ps |
CPU time | 2.36 seconds |
Started | Aug 05 05:07:46 PM PDT 24 |
Finished | Aug 05 05:07:48 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-bc031fcd-2bf8-4ebc-bedc-c5bc19f03dda |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2923115389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2923115389 |
Directory | /workspace/42.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2961961677 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 190589035 ps |
CPU time | 5.14 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-c59c7490-df50-4c16-8ac7-cb81a83eba59 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2961961677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2961961677 |
Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.4129728926 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 405895585 ps |
CPU time | 5.09 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:54 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-2083a7c7-c6c9-4cad-af1f-fba58dd68bb0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4129728926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4129728926 |
Directory | /workspace/42.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.1351764522 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 275751226 ps |
CPU time | 4.15 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:07:51 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-dd3ee74d-1490-4a6c-b2e8-1e9222c73404 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351764522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1351764522 |
Directory | /workspace/42.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2630232920 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 31731057936 ps |
CPU time | 59.27 seconds |
Started | Aug 05 05:07:51 PM PDT 24 |
Finished | Aug 05 05:08:50 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-770550e1-b737-4682-8f12-3167c221e36d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630232920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2630232920 |
Directory | /workspace/42.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.725111830 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 14998556761 ps |
CPU time | 46.87 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:08:54 PM PDT 24 |
Peak memory | 202144 kb |
Host | smart-447d43f8-59b8-4f5f-b751-b517cac0bbde |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=725111830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.725111830 |
Directory | /workspace/42.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.549958010 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 54433950 ps |
CPU time | 5.16 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:53 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-1594ad0a-a5da-4ad7-b20a-c971be43bd84 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549958010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.549958010 |
Directory | /workspace/42.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.1316358625 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 214202815 ps |
CPU time | 1.84 seconds |
Started | Aug 05 05:07:47 PM PDT 24 |
Finished | Aug 05 05:07:49 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-4fb8f529-c553-4277-ad50-37c4cdb04bf1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1316358625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1316358625 |
Directory | /workspace/42.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.985971436 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 63287589 ps |
CPU time | 1.47 seconds |
Started | Aug 05 05:07:46 PM PDT 24 |
Finished | Aug 05 05:07:48 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-315d29d0-0044-47d3-a29f-0d9bbdab2fd7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=985971436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.985971436 |
Directory | /workspace/42.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2892521354 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 2117266956 ps |
CPU time | 8.36 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:57 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-3ca022dd-689e-4b08-8e63-d8ea81fa35ab |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892521354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2892521354 |
Directory | /workspace/42.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2416793442 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 5470134903 ps |
CPU time | 6.87 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:55 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-33710232-a63b-4bd8-90a3-109bc8a284db |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2416793442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2416793442 |
Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3614103744 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 17602080 ps |
CPU time | 1.26 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:07:59 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-7ee472f8-1df1-4d73-a3d6-44dcb1463d01 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614103744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3614103744 |
Directory | /workspace/42.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2112428624 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 3519768448 ps |
CPU time | 66.52 seconds |
Started | Aug 05 05:07:50 PM PDT 24 |
Finished | Aug 05 05:08:57 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-1403f305-b9f5-4f16-b602-dc13abe4a7e8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2112428624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2112428624 |
Directory | /workspace/42.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3258546772 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 5692824556 ps |
CPU time | 64.85 seconds |
Started | Aug 05 05:07:51 PM PDT 24 |
Finished | Aug 05 05:08:55 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-2aa04cbd-ac00-4c57-b92b-e9121111c074 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258546772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3258546772 |
Directory | /workspace/42.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2756566809 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 499426737 ps |
CPU time | 74.37 seconds |
Started | Aug 05 05:07:55 PM PDT 24 |
Finished | Aug 05 05:09:10 PM PDT 24 |
Peak memory | 204340 kb |
Host | smart-bc7ab693-5868-4ca0-be15-8a10ffbd44fe |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2756566809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.2756566809 |
Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1749788442 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 3742533564 ps |
CPU time | 54.39 seconds |
Started | Aug 05 05:07:51 PM PDT 24 |
Finished | Aug 05 05:08:46 PM PDT 24 |
Peak memory | 203152 kb |
Host | smart-0768a104-3a20-4a3f-921d-cc7369190166 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1749788442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.1749788442 |
Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.684920027 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 24785017 ps |
CPU time | 2.85 seconds |
Started | Aug 05 05:08:05 PM PDT 24 |
Finished | Aug 05 05:08:08 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-ed66c9d7-5f08-45ba-a892-1281bf531bb3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=684920027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.684920027 |
Directory | /workspace/42.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.217629606 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 788105728 ps |
CPU time | 13.99 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:08:25 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-3e376c30-224b-49db-8f45-9f2db38745b4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=217629606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.217629606 |
Directory | /workspace/43.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3748780345 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 30598094659 ps |
CPU time | 207.42 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:11:38 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-53e7d788-fb70-4dc1-b756-e641a1085625 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3748780345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3748780345 |
Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1887470214 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 330383109 ps |
CPU time | 6.04 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-369597a7-5c08-45a6-bc65-489f4c7358be |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1887470214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1887470214 |
Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.309838270 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 125375757 ps |
CPU time | 2.8 seconds |
Started | Aug 05 05:08:11 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-6d53949e-c745-4f9c-a715-b98f63702eb8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=309838270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.309838270 |
Directory | /workspace/43.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.2401638869 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 75263297 ps |
CPU time | 5.08 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:08:13 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-16f09c41-5737-4055-a586-e3e8fc47942c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2401638869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2401638869 |
Directory | /workspace/43.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.285397422 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 12258192538 ps |
CPU time | 42.4 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:08:37 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-8fda515a-5e43-405a-8bde-6be9c9b1a6c8 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=285397422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.285397422 |
Directory | /workspace/43.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.155273569 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 44345809012 ps |
CPU time | 113.8 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:09:50 PM PDT 24 |
Peak memory | 202152 kb |
Host | smart-0df05f57-0648-49cc-a8e3-e5569022f8dd |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=155273569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.155273569 |
Directory | /workspace/43.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3419438143 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 72765187 ps |
CPU time | 4.05 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:08:01 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-73697606-28a9-4b1b-bfcb-bf8b2f759a15 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419438143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3419438143 |
Directory | /workspace/43.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.3835212361 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 1270956619 ps |
CPU time | 8.61 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:08:17 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-ef996710-758f-4628-90d2-e9645584f6b0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3835212361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3835212361 |
Directory | /workspace/43.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3443923849 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 48872368 ps |
CPU time | 1.32 seconds |
Started | Aug 05 05:07:48 PM PDT 24 |
Finished | Aug 05 05:07:50 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-927b25bb-fcad-4dc3-b567-d223ef104679 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3443923849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3443923849 |
Directory | /workspace/43.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1394446329 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 5574064646 ps |
CPU time | 7.71 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:08:06 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-b5ff55d7-803f-4983-aaa2-dc31ef199ac1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394446329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1394446329 |
Directory | /workspace/43.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3548629206 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 4648031106 ps |
CPU time | 13.47 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:08:12 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-ac370505-6d0a-407f-ba18-03aa55095a64 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3548629206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3548629206 |
Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1305744795 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 20496916 ps |
CPU time | 1.35 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:07:56 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-16eeb32f-8234-40f0-ba61-704e5c7ec7dd |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305744795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1305744795 |
Directory | /workspace/43.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1610945503 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 446656560 ps |
CPU time | 55.23 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:08:53 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-e62d00a0-b5d0-44fb-a090-5c1260606593 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1610945503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1610945503 |
Directory | /workspace/43.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1950573144 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 13413205188 ps |
CPU time | 47.56 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:08:44 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-9cedb9fc-067a-41d1-9865-622c068608df |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1950573144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1950573144 |
Directory | /workspace/43.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3261680912 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 210843706 ps |
CPU time | 23.22 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:23 PM PDT 24 |
Peak memory | 203108 kb |
Host | smart-e434654f-0cde-4e4c-9ebe-a772db84da1a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261680912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.3261680912 |
Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2433431755 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 454686288 ps |
CPU time | 44.45 seconds |
Started | Aug 05 05:07:54 PM PDT 24 |
Finished | Aug 05 05:08:39 PM PDT 24 |
Peak memory | 204240 kb |
Host | smart-1ce235a5-c443-439c-a8ed-014a7aa62911 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2433431755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.2433431755 |
Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2303467151 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 570516864 ps |
CPU time | 9.78 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:10 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-af07aa5a-a017-48c9-b94a-428968cb9617 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2303467151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2303467151 |
Directory | /workspace/43.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3174966820 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 290411055 ps |
CPU time | 2.29 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-31891fc7-78a9-4251-87bb-982da945af72 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3174966820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3174966820 |
Directory | /workspace/44.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.936102802 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 46287406431 ps |
CPU time | 77.54 seconds |
Started | Aug 05 05:08:02 PM PDT 24 |
Finished | Aug 05 05:09:20 PM PDT 24 |
Peak memory | 202072 kb |
Host | smart-ea46de7d-d2f1-46ca-9179-f3c0feca079e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=936102802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.936102802 |
Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3692674110 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 278216829 ps |
CPU time | 2.92 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:08:00 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-52e48036-586e-473b-8f6d-38deef4d5afc |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3692674110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3692674110 |
Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.392640462 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 137575297 ps |
CPU time | 7.69 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 201900 kb |
Host | smart-02055c64-9262-40b9-89a0-eae50f520e68 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=392640462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.392640462 |
Directory | /workspace/44.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2333700316 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 714110809 ps |
CPU time | 13.2 seconds |
Started | Aug 05 05:07:58 PM PDT 24 |
Finished | Aug 05 05:08:11 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-697e6c27-affa-4a33-9b62-dd13bafbaa75 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2333700316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2333700316 |
Directory | /workspace/44.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2370631144 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 47365093741 ps |
CPU time | 137.4 seconds |
Started | Aug 05 05:08:18 PM PDT 24 |
Finished | Aug 05 05:10:35 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-c7718950-3de9-4f98-bf8c-db4f7e9aab27 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370631144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2370631144 |
Directory | /workspace/44.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.384887648 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 33192971401 ps |
CPU time | 92.5 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:09:45 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-754f8840-9983-4379-9c9f-61be72ccb0f7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=384887648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.384887648 |
Directory | /workspace/44.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.854400484 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 47320692 ps |
CPU time | 5.96 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:08:19 PM PDT 24 |
Peak memory | 201920 kb |
Host | smart-26068c5c-2371-4db5-ab7b-eef0a8924c4f |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854400484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.854400484 |
Directory | /workspace/44.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3516258016 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 38238667 ps |
CPU time | 3.75 seconds |
Started | Aug 05 05:07:57 PM PDT 24 |
Finished | Aug 05 05:08:01 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-29e9709c-910e-450b-bd79-5f753f90cb43 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3516258016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3516258016 |
Directory | /workspace/44.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.2769289808 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 163458715 ps |
CPU time | 1.47 seconds |
Started | Aug 05 05:08:14 PM PDT 24 |
Finished | Aug 05 05:08:21 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-726edddb-4386-4729-83cc-cbe310e40ed6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2769289808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2769289808 |
Directory | /workspace/44.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3704242989 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 1783523939 ps |
CPU time | 7.31 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-277b0735-7d5b-42c6-8557-17e27f3ae0c0 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704242989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3704242989 |
Directory | /workspace/44.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.749819410 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1104232589 ps |
CPU time | 6.54 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:08:20 PM PDT 24 |
Peak memory | 202128 kb |
Host | smart-646736df-ee77-468d-8f2d-add77402bd2d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=749819410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.749819410 |
Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2695317475 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 8974334 ps |
CPU time | 1.06 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:01 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-e5d42334-1235-42a5-a1ad-ce7554e57887 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695317475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2695317475 |
Directory | /workspace/44.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.872050154 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 6328087860 ps |
CPU time | 41.7 seconds |
Started | Aug 05 05:07:55 PM PDT 24 |
Finished | Aug 05 05:08:37 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-e241f5a1-9dba-4093-ac0f-a984f6e81902 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=872050154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.872050154 |
Directory | /workspace/44.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1729053790 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 495500253 ps |
CPU time | 7.96 seconds |
Started | Aug 05 05:07:56 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-8f00382d-8835-416a-96ad-6482a9f52084 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1729053790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1729053790 |
Directory | /workspace/44.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1371287720 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 638376346 ps |
CPU time | 84.2 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:09:41 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-8ace8afa-1550-4216-9895-deec03e05947 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1371287720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.1371287720 |
Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2318955188 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 601532852 ps |
CPU time | 103.68 seconds |
Started | Aug 05 05:08:06 PM PDT 24 |
Finished | Aug 05 05:09:50 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-e339f623-ac73-4c54-949f-8d9d7fd2351e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2318955188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2318955188 |
Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3693536406 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 97677596 ps |
CPU time | 2.05 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:08:10 PM PDT 24 |
Peak memory | 202040 kb |
Host | smart-627a447b-aaba-4d23-882e-414735fb7d07 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3693536406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3693536406 |
Directory | /workspace/44.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.210912258 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 103364528 ps |
CPU time | 9.97 seconds |
Started | Aug 05 05:08:23 PM PDT 24 |
Finished | Aug 05 05:08:33 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-d550cc5d-6b6a-46ee-b282-91dbb67cd392 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=210912258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.210912258 |
Directory | /workspace/45.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2897078935 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 127599590391 ps |
CPU time | 286.08 seconds |
Started | Aug 05 05:07:59 PM PDT 24 |
Finished | Aug 05 05:12:45 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-170bdfce-e1bd-4817-89ce-527a8f31d05f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2897078935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2897078935 |
Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3168795304 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 25680522 ps |
CPU time | 2.83 seconds |
Started | Aug 05 05:08:06 PM PDT 24 |
Finished | Aug 05 05:08:09 PM PDT 24 |
Peak memory | 202292 kb |
Host | smart-42915d7d-4876-4c3e-9110-9a908df151d0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3168795304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3168795304 |
Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.4062447580 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 79532831 ps |
CPU time | 8.71 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:08 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-4269143e-c70c-41e4-bdcd-9805ec43a021 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4062447580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.4062447580 |
Directory | /workspace/45.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.1682221348 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 40798288 ps |
CPU time | 4.97 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-58254864-aa3c-441b-ad95-121f7f52bcd2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1682221348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1682221348 |
Directory | /workspace/45.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3278343794 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 52820683045 ps |
CPU time | 124.28 seconds |
Started | Aug 05 05:07:59 PM PDT 24 |
Finished | Aug 05 05:10:03 PM PDT 24 |
Peak memory | 202104 kb |
Host | smart-3ad88380-15c1-40d2-a7b0-1373b7a5b476 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278343794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3278343794 |
Directory | /workspace/45.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3431543022 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 40754498402 ps |
CPU time | 183.74 seconds |
Started | Aug 05 05:08:06 PM PDT 24 |
Finished | Aug 05 05:11:10 PM PDT 24 |
Peak memory | 202128 kb |
Host | smart-6113bd87-a898-44e3-a183-a00c249f8692 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3431543022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3431543022 |
Directory | /workspace/45.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2990946167 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 30892077 ps |
CPU time | 2.25 seconds |
Started | Aug 05 05:08:20 PM PDT 24 |
Finished | Aug 05 05:08:22 PM PDT 24 |
Peak memory | 201932 kb |
Host | smart-33c5f77d-0c3d-422e-9b61-f0c8e2a9da03 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990946167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2990946167 |
Directory | /workspace/45.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1233522946 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 958476033 ps |
CPU time | 12.07 seconds |
Started | Aug 05 05:08:03 PM PDT 24 |
Finished | Aug 05 05:08:16 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-d44845fe-fc9e-4679-b3c8-cf7d49967c34 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1233522946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1233522946 |
Directory | /workspace/45.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.136425320 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 8504223 ps |
CPU time | 1.12 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:08:11 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-cb32383a-d008-4ce4-80ba-732fb8784c3e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=136425320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.136425320 |
Directory | /workspace/45.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2137702789 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 4296571830 ps |
CPU time | 11.86 seconds |
Started | Aug 05 05:08:12 PM PDT 24 |
Finished | Aug 05 05:08:24 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-3c76025e-6fca-4e63-8102-98cf3ceadf55 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137702789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2137702789 |
Directory | /workspace/45.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2480972471 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 1107676294 ps |
CPU time | 7.37 seconds |
Started | Aug 05 05:07:59 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-0e6411f3-a7cb-4ff9-8514-4df05dfb8f96 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2480972471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2480972471 |
Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1243406547 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 32718257 ps |
CPU time | 1.31 seconds |
Started | Aug 05 05:07:55 PM PDT 24 |
Finished | Aug 05 05:07:56 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-93269b9b-87b2-4607-954a-8c1316fa4331 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243406547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1243406547 |
Directory | /workspace/45.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3214785097 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 511900460 ps |
CPU time | 45.8 seconds |
Started | Aug 05 05:08:01 PM PDT 24 |
Finished | Aug 05 05:08:47 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-adccb50c-0c50-42b2-9228-75fe15846c48 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3214785097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3214785097 |
Directory | /workspace/45.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.41263618 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 3984091911 ps |
CPU time | 23.21 seconds |
Started | Aug 05 05:08:18 PM PDT 24 |
Finished | Aug 05 05:08:41 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-831dd9a2-1298-4227-a45f-a4b5162b860c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41263618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.41263618 |
Directory | /workspace/45.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.703374410 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 597517820 ps |
CPU time | 141.13 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:10:35 PM PDT 24 |
Peak memory | 207584 kb |
Host | smart-51aa44fa-a750-46e2-b636-fe2b1d5d09f6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=703374410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.703374410 |
Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3090903292 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2781273299 ps |
CPU time | 84.72 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:09:35 PM PDT 24 |
Peak memory | 204448 kb |
Host | smart-62152b85-980c-49b8-a141-4ecd3cb0c728 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3090903292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3090903292 |
Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1753506188 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 53756530 ps |
CPU time | 6.76 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:08:17 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-911c494b-06ff-41ac-b97e-78858fce428c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1753506188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1753506188 |
Directory | /workspace/45.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3018112424 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 302633844 ps |
CPU time | 6.04 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-20d86317-4a47-487a-8997-f2cd8bf75ce6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3018112424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3018112424 |
Directory | /workspace/46.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3274888354 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 69071848426 ps |
CPU time | 220.05 seconds |
Started | Aug 05 05:08:22 PM PDT 24 |
Finished | Aug 05 05:12:02 PM PDT 24 |
Peak memory | 203552 kb |
Host | smart-3ce97ac8-46e6-418b-8566-cc336d9add82 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3274888354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.3274888354 |
Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3282667514 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 73530477 ps |
CPU time | 6.18 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:06 PM PDT 24 |
Peak memory | 201984 kb |
Host | smart-006fa195-013c-4662-a975-19fd7a465ca8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3282667514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3282667514 |
Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.4036275443 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 4227300522 ps |
CPU time | 8.92 seconds |
Started | Aug 05 05:08:20 PM PDT 24 |
Finished | Aug 05 05:08:29 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-2366b8ab-13c9-4631-9d41-a7ad367072c4 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036275443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4036275443 |
Directory | /workspace/46.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3634403309 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 372742108 ps |
CPU time | 5.44 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:08:22 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-f7f09de4-9074-4376-9938-43bf33d4026a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3634403309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3634403309 |
Directory | /workspace/46.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.278643555 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 24386677465 ps |
CPU time | 103.14 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:09:50 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-408158a1-1eee-440b-9e85-f16da49a44c1 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=278643555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.278643555 |
Directory | /workspace/46.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2165177548 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 56498191697 ps |
CPU time | 106.36 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:09:55 PM PDT 24 |
Peak memory | 202132 kb |
Host | smart-ec3d3e8c-69db-465f-8453-f920a5452da9 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2165177548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2165177548 |
Directory | /workspace/46.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3221968666 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 44110691 ps |
CPU time | 5.34 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:08:29 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-5c090b44-2161-431d-b783-4bac10f792b9 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221968666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3221968666 |
Directory | /workspace/46.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.244840150 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 836103414 ps |
CPU time | 3.38 seconds |
Started | Aug 05 05:08:04 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-b9a5e848-0908-44e2-af2c-03999361ddbd |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=244840150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.244840150 |
Directory | /workspace/46.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3767488385 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 53177077 ps |
CPU time | 1.51 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:02 PM PDT 24 |
Peak memory | 201924 kb |
Host | smart-16586b9b-849a-4fcd-a469-659acc860fbf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3767488385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3767488385 |
Directory | /workspace/46.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3222150848 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 5795280350 ps |
CPU time | 9.05 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-7c578392-4f41-4f45-b435-89b7a2e6a6ee |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222150848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3222150848 |
Directory | /workspace/46.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.134199305 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 13108824985 ps |
CPU time | 10.73 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:08:27 PM PDT 24 |
Peak memory | 202132 kb |
Host | smart-fb6b1289-b14a-4fe2-8ecc-5410f45ce6bf |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=134199305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.134199305 |
Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3445591726 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 13447703 ps |
CPU time | 1.17 seconds |
Started | Aug 05 05:08:03 PM PDT 24 |
Finished | Aug 05 05:08:04 PM PDT 24 |
Peak memory | 201960 kb |
Host | smart-20d5f7b3-797b-40a2-850d-81bcedb724fc |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445591726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3445591726 |
Directory | /workspace/46.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3992955764 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 522918136 ps |
CPU time | 10.94 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:11 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-c9e963ce-59ab-4416-ad03-d5fab91f4bbf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3992955764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3992955764 |
Directory | /workspace/46.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2000913197 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 123163967 ps |
CPU time | 2.81 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:03 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-603c9299-c3e0-4362-9c71-ed20fe667e6b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2000913197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2000913197 |
Directory | /workspace/46.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1098914946 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 1238994490 ps |
CPU time | 161.96 seconds |
Started | Aug 05 05:08:17 PM PDT 24 |
Finished | Aug 05 05:10:59 PM PDT 24 |
Peak memory | 205736 kb |
Host | smart-8ac1496d-fdb4-4fea-9591-e45a81ac280d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1098914946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1098914946 |
Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.839659108 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 127330639 ps |
CPU time | 19.39 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:08:33 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-bf14e920-f163-4c0d-8cd3-0ca9623e1e6c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=839659108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.839659108 |
Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.622353494 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 182949187 ps |
CPU time | 4.2 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-45685741-06e0-4c0c-84f3-4fff228285f0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=622353494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.622353494 |
Directory | /workspace/46.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1028440404 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 290478472 ps |
CPU time | 4.06 seconds |
Started | Aug 05 05:08:26 PM PDT 24 |
Finished | Aug 05 05:08:30 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-acef5ce5-f7a4-4625-a4ad-40ddedfb23f5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028440404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1028440404 |
Directory | /workspace/47.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.305426563 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 232672336 ps |
CPU time | 4.02 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:13 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-7b367672-fc36-4b2b-95ee-1f706ca15ee3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=305426563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.305426563 |
Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.3157245476 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 56619980 ps |
CPU time | 3.85 seconds |
Started | Aug 05 05:08:23 PM PDT 24 |
Finished | Aug 05 05:08:27 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-9c8be826-06fc-4325-a363-79a7f3e52fe5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157245476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3157245476 |
Directory | /workspace/47.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.3521307048 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 2566277704 ps |
CPU time | 17.06 seconds |
Started | Aug 05 05:08:01 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-9dc39658-7839-4204-9eb2-4a0f6ddcb612 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3521307048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3521307048 |
Directory | /workspace/47.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2173205591 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 46883331061 ps |
CPU time | 73.66 seconds |
Started | Aug 05 05:08:01 PM PDT 24 |
Finished | Aug 05 05:09:14 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-a659f43b-7664-4cb9-b9a2-6e72bc6e84b3 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173205591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2173205591 |
Directory | /workspace/47.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4097353677 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 12637676706 ps |
CPU time | 79.73 seconds |
Started | Aug 05 05:08:15 PM PDT 24 |
Finished | Aug 05 05:09:35 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-a2e2200c-77a4-47cf-a5f5-6b175b865527 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4097353677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4097353677 |
Directory | /workspace/47.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3261395379 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 58920217 ps |
CPU time | 8.43 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-d546c081-6fb3-462e-bfe2-4e35076827d2 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261395379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3261395379 |
Directory | /workspace/47.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.1209787443 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 340476089 ps |
CPU time | 4.87 seconds |
Started | Aug 05 05:08:23 PM PDT 24 |
Finished | Aug 05 05:08:28 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-e40957bb-ecab-4947-90d0-188ba96fcfbe |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1209787443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1209787443 |
Directory | /workspace/47.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.4004254133 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 12846841 ps |
CPU time | 1.13 seconds |
Started | Aug 05 05:08:25 PM PDT 24 |
Finished | Aug 05 05:08:26 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-b8f1bf51-81bc-4a1d-8ef1-63721feb0ca1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4004254133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4004254133 |
Directory | /workspace/47.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1250330425 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 1625511820 ps |
CPU time | 6.46 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-4d09a0f5-f737-412a-aa7b-1bf70319c438 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250330425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1250330425 |
Directory | /workspace/47.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.740747591 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 3814271772 ps |
CPU time | 6.73 seconds |
Started | Aug 05 05:08:00 PM PDT 24 |
Finished | Aug 05 05:08:07 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-4d91e36f-5c05-46ec-ac46-1a0168bd996d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=740747591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.740747591 |
Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3552237776 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 9891594 ps |
CPU time | 1.21 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202004 kb |
Host | smart-f45d1dfb-ab36-47ec-b5b2-61a4b575e6f3 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552237776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3552237776 |
Directory | /workspace/47.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.574469790 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 557927790 ps |
CPU time | 39.63 seconds |
Started | Aug 05 05:08:20 PM PDT 24 |
Finished | Aug 05 05:09:00 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-873d55bd-610c-422a-9680-86230f4905ae |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=574469790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.574469790 |
Directory | /workspace/47.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.307339717 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 17598359420 ps |
CPU time | 92.66 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:09:41 PM PDT 24 |
Peak memory | 204148 kb |
Host | smart-e8d6241a-de70-4e82-a962-8a8ff06b5d21 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=307339717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.307339717 |
Directory | /workspace/47.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.187674857 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 132455345 ps |
CPU time | 21.71 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:08:29 PM PDT 24 |
Peak memory | 204004 kb |
Host | smart-f671f93c-6b6c-44f0-865e-eda23cb695f9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=187674857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand _reset.187674857 |
Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3573926534 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 424135505 ps |
CPU time | 29.13 seconds |
Started | Aug 05 05:08:06 PM PDT 24 |
Finished | Aug 05 05:08:35 PM PDT 24 |
Peak memory | 203776 kb |
Host | smart-1d8d65b9-5edd-432c-bdb4-3e7dcc9545b8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3573926534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3573926534 |
Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.4120197946 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 987226822 ps |
CPU time | 4.74 seconds |
Started | Aug 05 05:08:12 PM PDT 24 |
Finished | Aug 05 05:08:17 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-cfcb10db-0c9d-4051-82f3-2878c7edacb9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4120197946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4120197946 |
Directory | /workspace/47.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.466129168 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 97958361 ps |
CPU time | 10.28 seconds |
Started | Aug 05 05:08:14 PM PDT 24 |
Finished | Aug 05 05:08:25 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-95ca177e-f718-46b9-9008-d230f5709f54 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=466129168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.466129168 |
Directory | /workspace/48.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1949030211 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 19127071779 ps |
CPU time | 33.69 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:08:44 PM PDT 24 |
Peak memory | 202156 kb |
Host | smart-745820c6-f5d3-46b4-969d-5b69a7514962 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1949030211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1949030211 |
Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1286374919 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 544054785 ps |
CPU time | 7.58 seconds |
Started | Aug 05 05:08:11 PM PDT 24 |
Finished | Aug 05 05:08:19 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-28e3f2a4-ddf2-41ff-8e51-ba60d74a55c1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1286374919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1286374919 |
Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.2052481495 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 648601471 ps |
CPU time | 5.43 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:08:21 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-95c3fd30-2b33-42a9-afc5-4d1c49095c76 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2052481495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2052481495 |
Directory | /workspace/48.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1696813079 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1250828760 ps |
CPU time | 8.35 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:08:32 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-b4934788-2419-4287-bad5-55c86c6be54c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1696813079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1696813079 |
Directory | /workspace/48.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.4262332031 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2425875376 ps |
CPU time | 7.68 seconds |
Started | Aug 05 05:08:10 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-120595b3-0992-4fff-965f-58f492d9fb07 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262332031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.4262332031 |
Directory | /workspace/48.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.313633397 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 38067823038 ps |
CPU time | 116.36 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:10:04 PM PDT 24 |
Peak memory | 202116 kb |
Host | smart-4ef91b25-f8d6-4e18-8c81-c7c4c62e6108 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=313633397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.313633397 |
Directory | /workspace/48.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3753532784 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 31114838 ps |
CPU time | 2.17 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:08:09 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-16bb5c96-af9c-4d44-8125-1591b9743719 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753532784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3753532784 |
Directory | /workspace/48.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3193790577 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 600795843 ps |
CPU time | 8.98 seconds |
Started | Aug 05 05:08:06 PM PDT 24 |
Finished | Aug 05 05:08:15 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-90fb602b-9763-42f0-b06c-54b610f0a7f6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3193790577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3193790577 |
Directory | /workspace/48.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.3211110384 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 44710094 ps |
CPU time | 1.38 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:10 PM PDT 24 |
Peak memory | 201988 kb |
Host | smart-95d10eb0-5330-43f3-bc51-52c799a5f927 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3211110384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3211110384 |
Directory | /workspace/48.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2257185232 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 2377061821 ps |
CPU time | 8.1 seconds |
Started | Aug 05 05:08:19 PM PDT 24 |
Finished | Aug 05 05:08:27 PM PDT 24 |
Peak memory | 202096 kb |
Host | smart-aef8026c-45fd-412a-95a5-810a5bf4e3cc |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257185232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2257185232 |
Directory | /workspace/48.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3724761970 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 6175079135 ps |
CPU time | 7.81 seconds |
Started | Aug 05 05:08:17 PM PDT 24 |
Finished | Aug 05 05:08:25 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-206be8de-65dc-4cee-b959-3ca935c3effb |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3724761970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3724761970 |
Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.504657997 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 12583552 ps |
CPU time | 0.97 seconds |
Started | Aug 05 05:08:17 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-bcc881da-ea0f-423e-a81a-e628775570a8 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504657997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.504657997 |
Directory | /workspace/48.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.421181627 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 429697405 ps |
CPU time | 29.64 seconds |
Started | Aug 05 05:08:09 PM PDT 24 |
Finished | Aug 05 05:08:38 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-b56f3942-e25b-47c7-838c-2fc42bf3fd82 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=421181627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.421181627 |
Directory | /workspace/48.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.483004504 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 5580493156 ps |
CPU time | 36.88 seconds |
Started | Aug 05 05:08:21 PM PDT 24 |
Finished | Aug 05 05:08:58 PM PDT 24 |
Peak memory | 202092 kb |
Host | smart-4a2e1379-caf9-44e1-9df7-62a9fabe0e3e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=483004504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.483004504 |
Directory | /workspace/48.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1286931092 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 12084910278 ps |
CPU time | 70.43 seconds |
Started | Aug 05 05:08:21 PM PDT 24 |
Finished | Aug 05 05:09:32 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-3841c771-9a64-4f75-a6df-593a86fd3291 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1286931092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1286931092 |
Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1924220838 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 209359950 ps |
CPU time | 3.7 seconds |
Started | Aug 05 05:08:18 PM PDT 24 |
Finished | Aug 05 05:08:22 PM PDT 24 |
Peak memory | 201940 kb |
Host | smart-3ea0002e-8768-4f70-be9c-2587cd224728 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924220838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1924220838 |
Directory | /workspace/48.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.3948457721 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 138280125 ps |
CPU time | 3.84 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:08:28 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-565a3d4a-4b0d-4a82-a97d-4f908dda42b6 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3948457721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3948457721 |
Directory | /workspace/49.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.180623444 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 24979192048 ps |
CPU time | 131.77 seconds |
Started | Aug 05 05:08:15 PM PDT 24 |
Finished | Aug 05 05:10:27 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-b27eeb78-36e7-47af-947e-3f167d12c22f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=180623444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo w_rsp.180623444 |
Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.91729350 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 335774245 ps |
CPU time | 4.18 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:08:17 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-66429949-2a6b-4c38-811a-98313bfeb8f0 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=91729350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.91729350 |
Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.152987690 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 481026497 ps |
CPU time | 6.6 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:08:30 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-f988361d-1fcf-4a08-85d0-77c901fdfca2 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=152987690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.152987690 |
Directory | /workspace/49.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.381988985 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 91340474 ps |
CPU time | 2.42 seconds |
Started | Aug 05 05:08:07 PM PDT 24 |
Finished | Aug 05 05:08:09 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-1fb6413c-1684-433d-90c0-17d45cbd1cbf |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381988985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.381988985 |
Directory | /workspace/49.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2599877451 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 64014127779 ps |
CPU time | 97.87 seconds |
Started | Aug 05 05:08:22 PM PDT 24 |
Finished | Aug 05 05:10:00 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-8d783b51-43f8-47de-bdbe-3aafd0ddfde7 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599877451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2599877451 |
Directory | /workspace/49.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.848539650 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 18524255320 ps |
CPU time | 76.57 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:09:41 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-a051e193-8f74-462a-b6c4-8a939bea0e04 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=848539650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.848539650 |
Directory | /workspace/49.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.782970583 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 74868690 ps |
CPU time | 3.4 seconds |
Started | Aug 05 05:08:15 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-4ee397e8-3900-43c8-a59b-15f54726ac2a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782970583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.782970583 |
Directory | /workspace/49.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.4156668665 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 373269945 ps |
CPU time | 4.39 seconds |
Started | Aug 05 05:08:15 PM PDT 24 |
Finished | Aug 05 05:08:19 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-a758a802-7973-4de1-b8d1-d0fd7c07b694 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4156668665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4156668665 |
Directory | /workspace/49.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1162959152 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 174434082 ps |
CPU time | 1.52 seconds |
Started | Aug 05 05:08:13 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-40a0e07b-d56d-4725-bb41-a2a66d44018a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1162959152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1162959152 |
Directory | /workspace/49.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3109799367 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 8863479005 ps |
CPU time | 8.25 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:08:16 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-1eaf9d1d-d71f-431f-abd4-b355cf803e74 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109799367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3109799367 |
Directory | /workspace/49.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3088528671 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 856137795 ps |
CPU time | 6.53 seconds |
Started | Aug 05 05:08:08 PM PDT 24 |
Finished | Aug 05 05:08:14 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-2e5871e8-172f-4ce0-bcda-5452be833a3e |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3088528671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3088528671 |
Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.752797654 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 17499857 ps |
CPU time | 1.27 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:08:18 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-0bd7f7d6-17fe-4a9b-aaf4-cb976ab603aa |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752797654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.752797654 |
Directory | /workspace/49.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1642682403 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 3912330074 ps |
CPU time | 33.13 seconds |
Started | Aug 05 05:08:16 PM PDT 24 |
Finished | Aug 05 05:08:50 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-a78390b0-0ae9-4676-a30c-c70b49117374 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642682403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1642682403 |
Directory | /workspace/49.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1803959221 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 1973030760 ps |
CPU time | 101.94 seconds |
Started | Aug 05 05:08:14 PM PDT 24 |
Finished | Aug 05 05:09:56 PM PDT 24 |
Peak memory | 204204 kb |
Host | smart-cfdb5e78-c11c-4857-9aa7-99911709650e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1803959221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1803959221 |
Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2439083404 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 47771870 ps |
CPU time | 8.58 seconds |
Started | Aug 05 05:08:23 PM PDT 24 |
Finished | Aug 05 05:08:32 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-af3bd86f-39fb-4037-b4cf-e951bd3c6f74 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2439083404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.2439083404 |
Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.854939012 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 630967434 ps |
CPU time | 9.89 seconds |
Started | Aug 05 05:08:24 PM PDT 24 |
Finished | Aug 05 05:08:34 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-f1a12644-a1e6-4941-9810-86010ca6dae1 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=854939012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.854939012 |
Directory | /workspace/49.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1417000617 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 214903739 ps |
CPU time | 2.65 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-40fb2637-3616-4b59-a9fd-60e7b7c5f26d |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1417000617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1417000617 |
Directory | /workspace/5.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1340480245 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 6865197736 ps |
CPU time | 20.68 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:31 PM PDT 24 |
Peak memory | 202164 kb |
Host | smart-e8e7d0d2-b5b9-4ebd-96fa-5a99a10e77ad |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1340480245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.1340480245 |
Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1562843046 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 73049925 ps |
CPU time | 4.1 seconds |
Started | Aug 05 05:06:18 PM PDT 24 |
Finished | Aug 05 05:06:22 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-3e5f8c22-e329-4c9e-bd48-5b12834a22d8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1562843046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1562843046 |
Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2141354320 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 4144753744 ps |
CPU time | 8.63 seconds |
Started | Aug 05 05:06:23 PM PDT 24 |
Finished | Aug 05 05:06:32 PM PDT 24 |
Peak memory | 202084 kb |
Host | smart-11c1882b-2b45-40b0-bf26-fcd2c26388f3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2141354320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2141354320 |
Directory | /workspace/5.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.3788579819 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 588665338 ps |
CPU time | 6.61 seconds |
Started | Aug 05 05:06:06 PM PDT 24 |
Finished | Aug 05 05:06:13 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-32be927b-85fb-44a3-8bbc-277e2093b43b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788579819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3788579819 |
Directory | /workspace/5.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4015522223 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 130265302997 ps |
CPU time | 120.97 seconds |
Started | Aug 05 05:06:12 PM PDT 24 |
Finished | Aug 05 05:08:13 PM PDT 24 |
Peak memory | 202060 kb |
Host | smart-9a6180ba-d081-4b7d-a6a6-eb896c62461c |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015522223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4015522223 |
Directory | /workspace/5.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1702673 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 7044290204 ps |
CPU time | 47.35 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202160 kb |
Host | smart-9974a22c-55d7-47ce-8c25-e81133a3c9a6 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1702673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1702673 |
Directory | /workspace/5.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1889058833 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 72545507 ps |
CPU time | 7.75 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:06:18 PM PDT 24 |
Peak memory | 201996 kb |
Host | smart-fc89d2d0-661a-4ed2-ba58-d183ac7ee348 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889058833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1889058833 |
Directory | /workspace/5.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.3422785587 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 137290322 ps |
CPU time | 2.99 seconds |
Started | Aug 05 05:06:09 PM PDT 24 |
Finished | Aug 05 05:06:12 PM PDT 24 |
Peak memory | 201904 kb |
Host | smart-199a843c-4691-46af-b1ea-2351ca170957 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3422785587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3422785587 |
Directory | /workspace/5.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.3889094828 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 18784801 ps |
CPU time | 1.3 seconds |
Started | Aug 05 05:06:15 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-07951d06-c3a1-4868-a507-bc39e6f9439c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3889094828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3889094828 |
Directory | /workspace/5.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.104653577 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 4327299463 ps |
CPU time | 10.51 seconds |
Started | Aug 05 05:06:06 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 202056 kb |
Host | smart-39b1a388-8488-46a7-b05c-c8f4bb4c2028 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=104653577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.104653577 |
Directory | /workspace/5.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1523789832 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 1327079358 ps |
CPU time | 6.78 seconds |
Started | Aug 05 05:06:05 PM PDT 24 |
Finished | Aug 05 05:06:12 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-6c44ed47-77c6-4dac-806e-64de4b3b715f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1523789832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1523789832 |
Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3515616244 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 9617113 ps |
CPU time | 1.02 seconds |
Started | Aug 05 05:06:37 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-5bc7c89f-057e-4743-92b0-2e052c6fce0d |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515616244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3515616244 |
Directory | /workspace/5.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1970201022 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 592396084 ps |
CPU time | 27.9 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:06:44 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-e874a464-65b0-4293-a147-a091ec981932 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1970201022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1970201022 |
Directory | /workspace/5.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.366962065 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 16432439365 ps |
CPU time | 56.58 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:07:07 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-b831150d-1b77-4e4b-9329-f97db911de0f |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=366962065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.366962065 |
Directory | /workspace/5.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3187675498 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 616644809 ps |
CPU time | 91.14 seconds |
Started | Aug 05 05:06:38 PM PDT 24 |
Finished | Aug 05 05:08:09 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-efa4c5ea-6248-4bcc-a9be-8a8f7c79a3ae |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3187675498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3187675498 |
Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1707400015 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 561414697 ps |
CPU time | 86.73 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:07:44 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-40c87aa2-51c9-4283-913c-b694912ca691 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1707400015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1707400015 |
Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1988180075 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 478723548 ps |
CPU time | 5.82 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:37 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-c19d2448-aa97-41cc-8a82-cda55389e04e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1988180075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1988180075 |
Directory | /workspace/5.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3693738610 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 810072495 ps |
CPU time | 3.02 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:06:14 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-c2199daf-1950-4fa9-b63e-6782bad82208 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3693738610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3693738610 |
Directory | /workspace/6.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1231598334 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 5183046720 ps |
CPU time | 35.79 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:06:53 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-c4cfb2c4-23cb-4a1c-afde-04f7b72a34ed |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1231598334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1231598334 |
Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1266642802 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 308061710 ps |
CPU time | 6.88 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:06:20 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-ee7d359d-f89c-49c7-aa2d-c15c2988217b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1266642802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1266642802 |
Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.2603984805 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 104633625 ps |
CPU time | 2.16 seconds |
Started | Aug 05 05:06:25 PM PDT 24 |
Finished | Aug 05 05:06:28 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-5c6106b6-6a61-47c8-b1a6-a326d3ccf68b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2603984805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2603984805 |
Directory | /workspace/6.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.3180472099 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 239178324 ps |
CPU time | 6.25 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-280fe61b-bf07-428a-9d8b-eb9fc89f0b92 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180472099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3180472099 |
Directory | /workspace/6.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2426751661 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 168747137679 ps |
CPU time | 125.52 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:08:16 PM PDT 24 |
Peak memory | 202088 kb |
Host | smart-80574451-63ff-4704-ba06-acc4e47ffe75 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426751661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2426751661 |
Directory | /workspace/6.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.346690715 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 11148384682 ps |
CPU time | 53.84 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:07:27 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-5fc3a8f5-fb6c-4cb8-8047-00e2e95cd472 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=346690715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.346690715 |
Directory | /workspace/6.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2775917378 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 64623195 ps |
CPU time | 2.66 seconds |
Started | Aug 05 05:06:38 PM PDT 24 |
Finished | Aug 05 05:06:41 PM PDT 24 |
Peak memory | 202036 kb |
Host | smart-0a04fd95-60b1-4bee-ad71-872084fa03cb |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775917378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2775917378 |
Directory | /workspace/6.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.2316071856 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1068282199 ps |
CPU time | 6.85 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:06:24 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-7b83f4e8-f3c5-46f3-b4d1-5dc676758e4a |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2316071856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2316071856 |
Directory | /workspace/6.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.630554824 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 11156042 ps |
CPU time | 1.1 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:11 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-c496b129-ea6e-4fcd-a5ee-abcd1225def9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=630554824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.630554824 |
Directory | /workspace/6.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2783122767 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 8506663825 ps |
CPU time | 10.4 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:40 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-7b399803-66f2-4c7b-a370-bf2b97286b30 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783122767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2783122767 |
Directory | /workspace/6.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3442980379 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 1733486252 ps |
CPU time | 7.66 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:06:25 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-6300d490-bdd3-4060-8d5b-bc877a680d2d |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3442980379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3442980379 |
Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2783882504 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 9445930 ps |
CPU time | 1.1 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:06:12 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-83aae215-2426-4e49-a309-ac147afdf2a3 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783882504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2783882504 |
Directory | /workspace/6.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4052340257 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 522064906 ps |
CPU time | 47.52 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-1dbe45f2-6d38-4e6c-82de-3bff45ae4e50 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4052340257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4052340257 |
Directory | /workspace/6.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.373434533 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 2397398700 ps |
CPU time | 37.69 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 201992 kb |
Host | smart-820a254c-6de0-474f-9aa1-bead50483dae |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=373434533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.373434533 |
Directory | /workspace/6.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1250145007 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 357444466 ps |
CPU time | 37.58 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:06:55 PM PDT 24 |
Peak memory | 204280 kb |
Host | smart-6f1fe768-c36e-455f-8246-9d6b20433a4e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1250145007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1250145007 |
Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1213613495 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 165153168 ps |
CPU time | 4.95 seconds |
Started | Aug 05 05:06:10 PM PDT 24 |
Finished | Aug 05 05:06:15 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-5aa86567-56bb-4948-965f-255ee4d83df3 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1213613495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1213613495 |
Directory | /workspace/6.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.252410556 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 15559591 ps |
CPU time | 1.66 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:06:25 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-a585dcac-b552-4956-9592-c5a75ae9c18b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=252410556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.252410556 |
Directory | /workspace/7.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2488151803 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 17984211 ps |
CPU time | 1.83 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:06:15 PM PDT 24 |
Peak memory | 202048 kb |
Host | smart-bad25bb4-2c02-4bc7-8baf-c744a7ae6a99 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2488151803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2488151803 |
Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2810090669 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 26235959 ps |
CPU time | 2.75 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-54888ed2-2a70-432d-b7f8-cdb134d8c3e8 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2810090669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2810090669 |
Directory | /workspace/7.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.2044165852 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 45694279 ps |
CPU time | 1.98 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:06:13 PM PDT 24 |
Peak memory | 201952 kb |
Host | smart-20048279-8f0c-4bc2-ba15-8b320471a659 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2044165852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2044165852 |
Directory | /workspace/7.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.4191213170 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 30723859241 ps |
CPU time | 122.09 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:08:34 PM PDT 24 |
Peak memory | 202080 kb |
Host | smart-8b8dd87d-e0bf-45e3-a87f-b2046aab17e5 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191213170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4191213170 |
Directory | /workspace/7.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1546219269 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 19414245239 ps |
CPU time | 92.85 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:07:46 PM PDT 24 |
Peak memory | 202136 kb |
Host | smart-babefad0-787d-45b4-8612-67a7c6bf308f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1546219269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1546219269 |
Directory | /workspace/7.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.810859629 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 28180758 ps |
CPU time | 2.9 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:06:16 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-5362bc76-e948-404b-9df3-89d91b2a4a0a |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810859629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.810859629 |
Directory | /workspace/7.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.82805856 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 417434677 ps |
CPU time | 6.35 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:06:18 PM PDT 24 |
Peak memory | 201964 kb |
Host | smart-a7859f31-7ac2-4dda-bd82-f6bb3348306e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=82805856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.82805856 |
Directory | /workspace/7.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1385245823 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 59125079 ps |
CPU time | 1.48 seconds |
Started | Aug 05 05:06:33 PM PDT 24 |
Finished | Aug 05 05:06:35 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-994587d9-f6bb-4140-8364-65b0ad9d6626 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1385245823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1385245823 |
Directory | /workspace/7.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1512950486 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 2819366223 ps |
CPU time | 10.47 seconds |
Started | Aug 05 05:06:38 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202168 kb |
Host | smart-41d6b945-4c7c-4c91-bc58-7620279aa00f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512950486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1512950486 |
Directory | /workspace/7.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.100606549 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 4236074146 ps |
CPU time | 12.06 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:44 PM PDT 24 |
Peak memory | 202140 kb |
Host | smart-8b0cfab9-3975-4dea-ae3f-3d6fe572ce0f |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=100606549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.100606549 |
Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3315308230 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 26929752 ps |
CPU time | 1.06 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:31 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-d3815f69-8ba2-4ede-84ef-c7a50e99e297 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315308230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3315308230 |
Directory | /workspace/7.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.798846870 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 3546176469 ps |
CPU time | 43.34 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:06:59 PM PDT 24 |
Peak memory | 202112 kb |
Host | smart-e43abd0b-f13c-49e5-8f62-da8f7203fdf7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798846870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.798846870 |
Directory | /workspace/7.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3392162601 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 605030177 ps |
CPU time | 5.08 seconds |
Started | Aug 05 05:06:40 PM PDT 24 |
Finished | Aug 05 05:06:45 PM PDT 24 |
Peak memory | 202012 kb |
Host | smart-c4904723-dac4-4d17-9aa9-c33c43f37054 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3392162601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3392162601 |
Directory | /workspace/7.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.4160035309 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 1373216897 ps |
CPU time | 181.1 seconds |
Started | Aug 05 05:06:11 PM PDT 24 |
Finished | Aug 05 05:09:12 PM PDT 24 |
Peak memory | 204196 kb |
Host | smart-3b22b4bf-bef6-4c5f-bfb7-82ba6a5e84eb |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4160035309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.4160035309 |
Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3642899244 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1250573248 ps |
CPU time | 105.55 seconds |
Started | Aug 05 05:06:36 PM PDT 24 |
Finished | Aug 05 05:08:22 PM PDT 24 |
Peak memory | 207440 kb |
Host | smart-df322c0c-114d-41c2-be7a-3a2ab2a0d949 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3642899244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3642899244 |
Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2631648463 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 21419076 ps |
CPU time | 1.74 seconds |
Started | Aug 05 05:06:40 PM PDT 24 |
Finished | Aug 05 05:06:42 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-72334f95-7210-46d4-a1c4-8c0499a4f4ff |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631648463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2631648463 |
Directory | /workspace/7.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.838829592 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 151648459 ps |
CPU time | 9.7 seconds |
Started | Aug 05 05:06:16 PM PDT 24 |
Finished | Aug 05 05:06:26 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-329e25c8-040d-4b06-944e-59246b7102de |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=838829592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.838829592 |
Directory | /workspace/8.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3772936090 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 41845840222 ps |
CPU time | 125.66 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:08:30 PM PDT 24 |
Peak memory | 202148 kb |
Host | smart-3ab3e7d8-d10b-47dd-871d-2bc71c00ac06 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3772936090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3772936090 |
Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.2953415639 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 78368226 ps |
CPU time | 4.8 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:06:29 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-c5acff87-ffb7-46da-9eef-d40922668799 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953415639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.2953415639 |
Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.3381999769 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 13157582 ps |
CPU time | 1.48 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:29 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-a04b7fde-1a65-4f86-9a3a-5af6bb55f33e |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381999769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3381999769 |
Directory | /workspace/8.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.2576751520 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 149895434 ps |
CPU time | 7.99 seconds |
Started | Aug 05 05:06:22 PM PDT 24 |
Finished | Aug 05 05:06:30 PM PDT 24 |
Peak memory | 202044 kb |
Host | smart-71fd1505-826b-436e-893a-fa2fa33635b5 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2576751520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2576751520 |
Directory | /workspace/8.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2684347843 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 110347862303 ps |
CPU time | 77.9 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:07:31 PM PDT 24 |
Peak memory | 202008 kb |
Host | smart-bdf65c15-b09d-4422-a776-58ba84628828 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684347843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2684347843 |
Directory | /workspace/8.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3426932385 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 27997904870 ps |
CPU time | 129.89 seconds |
Started | Aug 05 05:06:18 PM PDT 24 |
Finished | Aug 05 05:08:28 PM PDT 24 |
Peak memory | 202168 kb |
Host | smart-735cc453-3e03-4c01-afac-adafa535b905 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3426932385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3426932385 |
Directory | /workspace/8.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.925683256 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 311305464 ps |
CPU time | 7.89 seconds |
Started | Aug 05 05:06:20 PM PDT 24 |
Finished | Aug 05 05:06:28 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-ef217553-2727-42e4-a6bd-ed762c314363 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925683256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.925683256 |
Directory | /workspace/8.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.831792620 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 39146942 ps |
CPU time | 4.11 seconds |
Started | Aug 05 05:06:45 PM PDT 24 |
Finished | Aug 05 05:06:49 PM PDT 24 |
Peak memory | 201936 kb |
Host | smart-729ed7b3-5b1a-4696-889e-ffb96cd45aab |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831792620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.831792620 |
Directory | /workspace/8.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.847455488 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 8593419 ps |
CPU time | 1.04 seconds |
Started | Aug 05 05:06:13 PM PDT 24 |
Finished | Aug 05 05:06:14 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-ba70e574-b3cf-4233-9d08-e0c95e1bdeba |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=847455488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.847455488 |
Directory | /workspace/8.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3701568928 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1616288522 ps |
CPU time | 7.59 seconds |
Started | Aug 05 05:06:17 PM PDT 24 |
Finished | Aug 05 05:06:24 PM PDT 24 |
Peak memory | 201980 kb |
Host | smart-53928c65-7af6-46a6-96d9-35ec8b2e6902 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701568928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3701568928 |
Directory | /workspace/8.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3557513103 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 2983747289 ps |
CPU time | 8.77 seconds |
Started | Aug 05 05:06:35 PM PDT 24 |
Finished | Aug 05 05:06:44 PM PDT 24 |
Peak memory | 202064 kb |
Host | smart-765addab-4198-4b39-b6cd-d92d41bbec62 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3557513103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3557513103 |
Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1170346762 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 14373719 ps |
CPU time | 1.17 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:06:32 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-46439e53-2db6-47e4-b971-b9025f0d3e29 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170346762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1170346762 |
Directory | /workspace/8.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1530419712 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 2368585207 ps |
CPU time | 16.15 seconds |
Started | Aug 05 05:06:31 PM PDT 24 |
Finished | Aug 05 05:06:47 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-e1bd4040-d35e-44da-84ed-4486abbfe1ba |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1530419712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1530419712 |
Directory | /workspace/8.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1703966708 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 10708310537 ps |
CPU time | 109.57 seconds |
Started | Aug 05 05:06:39 PM PDT 24 |
Finished | Aug 05 05:08:28 PM PDT 24 |
Peak memory | 203688 kb |
Host | smart-96f1fa73-298c-4400-8e62-4aa13122c2ea |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1703966708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1703966708 |
Directory | /workspace/8.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.410291176 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 2119582415 ps |
CPU time | 117.61 seconds |
Started | Aug 05 05:06:19 PM PDT 24 |
Finished | Aug 05 05:08:17 PM PDT 24 |
Peak memory | 204292 kb |
Host | smart-dd2f61fe-f4b6-4b65-96d8-aec36052ef84 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=410291176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_ reset.410291176 |
Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1337388927 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 4575869715 ps |
CPU time | 74.84 seconds |
Started | Aug 05 05:06:53 PM PDT 24 |
Finished | Aug 05 05:08:08 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-53e657cf-c797-45bc-833e-973ecfb868e9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337388927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1337388927 |
Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.242897285 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 37857321 ps |
CPU time | 1.32 seconds |
Started | Aug 05 05:06:46 PM PDT 24 |
Finished | Aug 05 05:06:48 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-1aed7307-8016-4503-a456-8e668143bc12 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=242897285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.242897285 |
Directory | /workspace/8.xbar_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1872503936 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 1762326064 ps |
CPU time | 7.12 seconds |
Started | Aug 05 05:06:26 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 201928 kb |
Host | smart-25cfa40a-b6af-49f9-b303-6e292339ab8c |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1872503936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1872503936 |
Directory | /workspace/9.xbar_access_same_device/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2310930715 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 37254540914 ps |
CPU time | 107.09 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:08:11 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-44a1a6a6-a518-4d7a-a1f2-c21645edeb45 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2310930715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2310930715 |
Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1366139346 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 84158396 ps |
CPU time | 4.1 seconds |
Started | Aug 05 05:06:43 PM PDT 24 |
Finished | Aug 05 05:06:47 PM PDT 24 |
Peak memory | 202000 kb |
Host | smart-b16223a0-4829-44fb-aa47-7ea0c8b8f566 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1366139346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1366139346 |
Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.720607177 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 646701725 ps |
CPU time | 6.22 seconds |
Started | Aug 05 05:06:33 PM PDT 24 |
Finished | Aug 05 05:06:39 PM PDT 24 |
Peak memory | 202028 kb |
Host | smart-20ae01fe-fa4c-4ba9-a38a-63c6192d0135 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=720607177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.720607177 |
Directory | /workspace/9.xbar_error_random/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.2940220422 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 864672204 ps |
CPU time | 14.2 seconds |
Started | Aug 05 05:06:29 PM PDT 24 |
Finished | Aug 05 05:06:44 PM PDT 24 |
Peak memory | 201944 kb |
Host | smart-87d579b9-546f-4213-b96d-48febc39f78b |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2940220422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2940220422 |
Directory | /workspace/9.xbar_random/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.712127220 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 18064262245 ps |
CPU time | 78.6 seconds |
Started | Aug 05 05:06:20 PM PDT 24 |
Finished | Aug 05 05:07:38 PM PDT 24 |
Peak memory | 201972 kb |
Host | smart-dcb7b1ef-e0eb-492c-ac48-12ff7a87aacd |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=712127220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.712127220 |
Directory | /workspace/9.xbar_random_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1478281839 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 8134438079 ps |
CPU time | 46.59 seconds |
Started | Aug 05 05:06:21 PM PDT 24 |
Finished | Aug 05 05:07:08 PM PDT 24 |
Peak memory | 202068 kb |
Host | smart-bd344f4f-aa2a-4d1a-8969-6e6165a41007 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1478281839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1478281839 |
Directory | /workspace/9.xbar_random_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2143920977 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 70980443 ps |
CPU time | 3.33 seconds |
Started | Aug 05 05:06:26 PM PDT 24 |
Finished | Aug 05 05:06:29 PM PDT 24 |
Peak memory | 202020 kb |
Host | smart-7646ca07-1cc4-42c9-b1a0-0c82e8a012d2 |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143920977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2143920977 |
Directory | /workspace/9.xbar_random_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1379888040 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 198635585 ps |
CPU time | 6.13 seconds |
Started | Aug 05 05:06:32 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 202032 kb |
Host | smart-35919c7b-d5cb-4e3b-b330-0f8057bd57f9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379888040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1379888040 |
Directory | /workspace/9.xbar_same_source/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3186643607 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 10981475 ps |
CPU time | 1.29 seconds |
Started | Aug 05 05:06:37 PM PDT 24 |
Finished | Aug 05 05:06:38 PM PDT 24 |
Peak memory | 201948 kb |
Host | smart-3af64550-8dc5-4cd5-984a-18426a5dec11 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3186643607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3186643607 |
Directory | /workspace/9.xbar_smoke/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.948500756 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 10935088387 ps |
CPU time | 12.37 seconds |
Started | Aug 05 05:06:26 PM PDT 24 |
Finished | Aug 05 05:06:39 PM PDT 24 |
Peak memory | 202108 kb |
Host | smart-25857085-7c0a-42b4-9a45-66bc2399c5ed |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=948500756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.948500756 |
Directory | /workspace/9.xbar_smoke_large_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1401496094 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 1228016047 ps |
CPU time | 7.66 seconds |
Started | Aug 05 05:06:26 PM PDT 24 |
Finished | Aug 05 05:06:34 PM PDT 24 |
Peak memory | 202016 kb |
Host | smart-d756b8bf-93c0-4d65-8783-1b4a7c6673a2 |
User | root |
Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1401496094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1401496094 |
Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1968672352 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 10028070 ps |
CPU time | 1.04 seconds |
Started | Aug 05 05:06:57 PM PDT 24 |
Finished | Aug 05 05:06:58 PM PDT 24 |
Peak memory | 202024 kb |
Host | smart-1b6415e4-6393-44c2-ab7b-83644dde5cfa |
User | root |
Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968672352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1968672352 |
Directory | /workspace/9.xbar_smoke_zero_delays/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2326477486 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 4925974611 ps |
CPU time | 32.57 seconds |
Started | Aug 05 05:06:28 PM PDT 24 |
Finished | Aug 05 05:07:00 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-5446e558-941e-4072-8de2-9a1f99549460 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2326477486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2326477486 |
Directory | /workspace/9.xbar_stress_all/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3767809848 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 5349265854 ps |
CPU time | 33.69 seconds |
Started | Aug 05 05:06:19 PM PDT 24 |
Finished | Aug 05 05:06:53 PM PDT 24 |
Peak memory | 202076 kb |
Host | smart-7210b528-6661-4f39-afc4-85bc70cad7f9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3767809848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3767809848 |
Directory | /workspace/9.xbar_stress_all_with_error/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.965384538 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 2030900509 ps |
CPU time | 73.48 seconds |
Started | Aug 05 05:06:30 PM PDT 24 |
Finished | Aug 05 05:07:44 PM PDT 24 |
Peak memory | 204492 kb |
Host | smart-25ab4d92-8114-414d-ad6d-60fc8650fcd9 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=965384538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.965384538 |
Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3063106718 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 266333708 ps |
CPU time | 37.1 seconds |
Started | Aug 05 05:06:24 PM PDT 24 |
Finished | Aug 05 05:07:01 PM PDT 24 |
Peak memory | 203536 kb |
Host | smart-4661c4f9-504e-41e2-8dd5-cc7552ec91de |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3063106718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.3063106718 |
Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1703228936 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 55341823 ps |
CPU time | 3.41 seconds |
Started | Aug 05 05:06:27 PM PDT 24 |
Finished | Aug 05 05:06:31 PM PDT 24 |
Peak memory | 201924 kb |
Host | smart-100810d2-daf9-47f2-a25d-a94594fd1fa7 |
User | root |
Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1703228936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1703228936 |
Directory | /workspace/9.xbar_unmapped_addr/latest |
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