Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	432	1			T1	6		T16	1		T12	5
all_values[1]	409	1			T1	5		T14	1		T16	1
all_values[2]	409	1			T1	9		T16	1		T21	1
all_values[3]	418	1			T1	10		T14	1		T16	1
all_values[4]	447	1			T1	2		T12	2		T45	4
all_values[5]	456	1			T1	9		T14	1		T21	1
all_values[6]	398	1			T1	8		T14	2		T12	1
all_values[7]	400	1			T1	6		T12	1		T45	6
all_values[8]	429	1			T1	7		T21	3		T12	4
all_values[9]	467	1			T1	7		T14	1		T21	3
all_values[10]	420	1			T1	9		T12	4		T111	1
all_values[11]	438	1			T1	2		T16	1		T21	1
all_values[12]	419	1			T1	3		T14	1		T12	1
all_values[13]	405	1			T1	4		T14	1		T12	2
all_values[14]	401	1			T1	4		T14	1		T51	1
all_values[15]	394	1			T1	3		T12	5		T44	1
all_values[16]	397	1			T1	7		T21	1		T12	2
all_values[17]	435	1			T1	7		T14	2		T12	4
all_values[18]	413	1			T1	5		T16	1		T12	2
all_values[19]	427	1			T1	4		T12	3		T111	1
all_values[20]	425	1			T1	10		T16	1		T12	2
all_values[21]	418	1			T1	6		T14	1		T16	1
all_values[22]	453	1			T1	7		T14	1		T12	1
all_values[23]	402	1			T1	4		T12	4		T45	6
all_values[24]	411	1			T1	7		T12	2		T56	1
all_values[25]	411	1			T1	2		T14	2		T16	2
all_values[26]	452	1			T1	5		T14	1		T12	2