Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	408	1			T16	6		T18	1		T204	5
all_values[1]	432	1			T16	4		T204	5		T71	1
all_values[2]	405	1			T5	1		T16	7		T40	2
all_values[3]	455	1			T5	1		T16	9		T40	2
all_values[4]	401	1			T16	6		T204	3		T39	1
all_values[5]	419	1			T16	3		T40	1		T204	2
all_values[6]	442	1			T5	1		T16	6		T18	2
all_values[7]	467	1			T16	8		T204	4		T60	3
all_values[8]	457	1			T5	2		T16	5		T18	1
all_values[9]	438	1			T16	9		T40	3		T204	10
all_values[10]	429	1			T16	8		T204	3		T39	2
all_values[11]	404	1			T16	6		T18	1		T40	1
all_values[12]	437	1			T5	1		T16	7		T204	4
all_values[13]	415	1			T5	1		T16	5		T18	1
all_values[14]	457	1			T5	1		T16	3		T18	1
all_values[15]	454	1			T5	1		T16	2		T40	1
all_values[16]	426	1			T5	1		T16	7		T204	9
all_values[17]	448	1			T16	10		T204	9		T60	1
all_values[18]	451	1			T5	1		T16	4		T40	1
all_values[19]	416	1			T5	3		T16	5		T204	6
all_values[20]	406	1			T5	1		T16	5		T204	6
all_values[21]	420	1			T16	8		T204	3		T84	3
all_values[22]	408	1			T5	1		T16	8		T204	3
all_values[23]	420	1			T16	11		T40	1		T204	8
all_values[24]	433	1			T5	2		T16	5		T204	5
all_values[25]	436	1			T5	2		T16	8		T40	1
all_values[26]	435	1			T16	10		T18	2		T40	1