Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	526	1			T19	2		T12	2		T45	8
all_values[1]	513	1			T1	1		T12	5		T45	9
all_values[2]	480	1			T5	1		T19	1		T12	3
all_values[3]	503	1			T5	2		T19	2		T12	7
all_values[4]	495	1			T12	10		T45	4		T31	7
all_values[5]	463	1			T5	2		T12	8		T45	6
all_values[6]	449	1			T19	3		T12	4		T45	5
all_values[7]	470	1			T1	1		T5	3		T19	1
all_values[8]	489	1			T5	3		T12	1		T45	8
all_values[9]	499	1			T5	1		T12	6		T45	2
all_values[10]	468	1			T12	2		T45	9		T31	6
all_values[11]	464	1			T12	5		T45	7		T31	9
all_values[12]	525	1			T19	1		T12	2		T45	8
all_values[13]	445	1			T12	3		T45	6		T31	5
all_values[14]	487	1			T19	1		T12	4		T45	8
all_values[15]	462	1			T1	2		T5	1		T19	1
all_values[16]	494	1			T12	7		T45	3		T31	8
all_values[17]	476	1			T12	2		T45	9		T31	8
all_values[18]	453	1			T1	1		T12	5		T45	8
all_values[19]	488	1			T5	1		T19	1		T12	7
all_values[20]	461	1			T12	2		T45	10		T31	7
all_values[21]	488	1			T19	1		T12	5		T45	3
all_values[22]	427	1			T5	1		T19	1		T12	7
all_values[23]	467	1			T19	2		T12	2		T45	7
all_values[24]	484	1			T5	1		T12	2		T45	10
all_values[25]	490	1			T12	2		T45	14		T31	5
all_values[26]	468	1			T12	4		T45	4		T31	9