Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	512	1			T4	7		T20	5		T26	3
all_values[1]	482	1			T4	5		T17	2		T19	1
all_values[2]	474	1			T4	7		T20	2		T32	1
all_values[3]	496	1			T4	4		T17	1		T19	1
all_values[4]	447	1			T4	5		T17	1		T19	1
all_values[5]	487	1			T4	5		T17	1		T19	3
all_values[6]	484	1			T4	3		T17	2		T19	2
all_values[7]	486	1			T4	5		T19	2		T20	2
all_values[8]	500	1			T4	7		T17	2		T20	3
all_values[9]	477	1			T4	1		T17	2		T19	1
all_values[10]	455	1			T4	4		T19	1		T20	2
all_values[11]	497	1			T4	4		T19	3		T20	2
all_values[12]	443	1			T4	4		T17	3		T20	5
all_values[13]	472	1			T4	3		T17	1		T20	4
all_values[14]	493	1			T4	3		T17	2		T19	1
all_values[15]	513	1			T4	4		T17	1		T20	4
all_values[16]	478	1			T4	7		T17	3		T20	3
all_values[17]	489	1			T4	4		T17	2		T19	1
all_values[18]	471	1			T4	9		T17	1		T19	1
all_values[19]	482	1			T4	7		T19	1		T20	4
all_values[20]	506	1			T4	2		T17	2		T20	7
all_values[21]	470	1			T4	2		T17	3		T20	7
all_values[22]	510	1			T4	7		T17	4		T20	8
all_values[23]	479	1			T4	2		T20	2		T26	1
all_values[24]	491	1			T4	5		T17	2		T20	9
all_values[25]	515	1			T4	4		T17	3		T20	4
all_values[26]	466	1			T4	2		T17	1		T20	5