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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 100.00 95.42 100.00 100.00 100.00 100.00


Total test records in report: 900
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T763 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2003288627 Aug 13 05:34:55 PM PDT 24 Aug 13 05:36:07 PM PDT 24 4146612721 ps
T764 /workspace/coverage/xbar_build_mode/4.xbar_same_source.862131965 Aug 13 05:32:49 PM PDT 24 Aug 13 05:32:52 PM PDT 24 30857818 ps
T765 /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1051469014 Aug 13 05:33:33 PM PDT 24 Aug 13 05:33:44 PM PDT 24 2830079880 ps
T766 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4048641996 Aug 13 05:35:02 PM PDT 24 Aug 13 05:35:09 PM PDT 24 639054320 ps
T767 /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2141262923 Aug 13 05:35:10 PM PDT 24 Aug 13 05:36:15 PM PDT 24 11487669301 ps
T768 /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2082103124 Aug 13 05:33:06 PM PDT 24 Aug 13 05:33:08 PM PDT 24 23219479 ps
T769 /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1285497864 Aug 13 05:33:12 PM PDT 24 Aug 13 05:33:20 PM PDT 24 48183054 ps
T770 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3381329690 Aug 13 05:33:37 PM PDT 24 Aug 13 05:33:43 PM PDT 24 132352359 ps
T771 /workspace/coverage/xbar_build_mode/41.xbar_error_random.1848607504 Aug 13 05:34:53 PM PDT 24 Aug 13 05:35:05 PM PDT 24 1240052340 ps
T772 /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1556899242 Aug 13 05:32:52 PM PDT 24 Aug 13 05:33:05 PM PDT 24 883055431 ps
T773 /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3916045246 Aug 13 05:34:02 PM PDT 24 Aug 13 05:34:09 PM PDT 24 108530631 ps
T774 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2378346839 Aug 13 05:32:46 PM PDT 24 Aug 13 05:32:47 PM PDT 24 9769696 ps
T203 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3871580185 Aug 13 05:34:35 PM PDT 24 Aug 13 05:36:31 PM PDT 24 87273067825 ps
T140 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2485726445 Aug 13 05:33:58 PM PDT 24 Aug 13 05:34:13 PM PDT 24 858002869 ps
T775 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2420362836 Aug 13 05:34:04 PM PDT 24 Aug 13 05:37:06 PM PDT 24 1064807306 ps
T184 /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3141572920 Aug 13 05:34:22 PM PDT 24 Aug 13 05:35:12 PM PDT 24 2966724476 ps
T776 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1367215111 Aug 13 05:34:01 PM PDT 24 Aug 13 05:37:54 PM PDT 24 202513929526 ps
T777 /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1024758640 Aug 13 05:34:38 PM PDT 24 Aug 13 05:34:52 PM PDT 24 130064645 ps
T778 /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2586715093 Aug 13 05:34:29 PM PDT 24 Aug 13 05:36:18 PM PDT 24 29355531547 ps
T779 /workspace/coverage/xbar_build_mode/30.xbar_error_random.298451585 Aug 13 05:34:15 PM PDT 24 Aug 13 05:34:26 PM PDT 24 732024935 ps
T780 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2092718454 Aug 13 05:33:50 PM PDT 24 Aug 13 05:33:53 PM PDT 24 39952353 ps
T128 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2431609508 Aug 13 05:33:46 PM PDT 24 Aug 13 05:36:24 PM PDT 24 4964322797 ps
T781 /workspace/coverage/xbar_build_mode/30.xbar_random.1656185060 Aug 13 05:34:14 PM PDT 24 Aug 13 05:34:25 PM PDT 24 71019509 ps
T782 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3010425585 Aug 13 05:35:08 PM PDT 24 Aug 13 05:35:16 PM PDT 24 303344004 ps
T783 /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4226777984 Aug 13 05:35:28 PM PDT 24 Aug 13 05:38:05 PM PDT 24 23800159100 ps
T784 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2233951118 Aug 13 05:33:29 PM PDT 24 Aug 13 05:34:36 PM PDT 24 2750027766 ps
T785 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2807766497 Aug 13 05:34:01 PM PDT 24 Aug 13 05:34:03 PM PDT 24 10776831 ps
T786 /workspace/coverage/xbar_build_mode/14.xbar_random.3092150020 Aug 13 05:33:28 PM PDT 24 Aug 13 05:33:32 PM PDT 24 212476598 ps
T174 /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2486326671 Aug 13 05:33:42 PM PDT 24 Aug 13 05:35:17 PM PDT 24 14083583226 ps
T787 /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1981479094 Aug 13 05:34:15 PM PDT 24 Aug 13 05:34:23 PM PDT 24 686340678 ps
T788 /workspace/coverage/xbar_build_mode/48.xbar_smoke.1226903162 Aug 13 05:35:15 PM PDT 24 Aug 13 05:35:17 PM PDT 24 60843422 ps
T217 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1908449902 Aug 13 05:33:08 PM PDT 24 Aug 13 05:36:48 PM PDT 24 87905554796 ps
T173 /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2385048731 Aug 13 05:33:20 PM PDT 24 Aug 13 05:34:52 PM PDT 24 106049211592 ps
T789 /workspace/coverage/xbar_build_mode/44.xbar_same_source.2804583477 Aug 13 05:35:02 PM PDT 24 Aug 13 05:35:14 PM PDT 24 1942110850 ps
T790 /workspace/coverage/xbar_build_mode/6.xbar_same_source.3310244356 Aug 13 05:33:02 PM PDT 24 Aug 13 05:33:07 PM PDT 24 53306668 ps
T791 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3538749004 Aug 13 05:34:07 PM PDT 24 Aug 13 05:34:14 PM PDT 24 2485996355 ps
T792 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1606761522 Aug 13 05:33:59 PM PDT 24 Aug 13 05:34:01 PM PDT 24 166180986 ps
T793 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2377636070 Aug 13 05:33:28 PM PDT 24 Aug 13 05:34:32 PM PDT 24 5396735048 ps
T794 /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1409127951 Aug 13 05:34:51 PM PDT 24 Aug 13 05:34:58 PM PDT 24 166545720 ps
T795 /workspace/coverage/xbar_build_mode/19.xbar_same_source.3345919738 Aug 13 05:33:41 PM PDT 24 Aug 13 05:33:48 PM PDT 24 1700699799 ps
T796 /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3118642176 Aug 13 05:33:34 PM PDT 24 Aug 13 05:33:43 PM PDT 24 5768872791 ps
T797 /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.497703581 Aug 13 05:33:02 PM PDT 24 Aug 13 05:33:03 PM PDT 24 13680294 ps
T798 /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.796814798 Aug 13 05:34:08 PM PDT 24 Aug 13 05:34:16 PM PDT 24 45811388 ps
T198 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3655571965 Aug 13 05:35:05 PM PDT 24 Aug 13 05:39:44 PM PDT 24 94781370143 ps
T799 /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4129700792 Aug 13 05:34:47 PM PDT 24 Aug 13 05:34:53 PM PDT 24 928239295 ps
T800 /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.724927674 Aug 13 05:32:58 PM PDT 24 Aug 13 05:33:05 PM PDT 24 3932075828 ps
T33 /workspace/coverage/xbar_build_mode/12.xbar_random.3170796476 Aug 13 05:33:20 PM PDT 24 Aug 13 05:33:34 PM PDT 24 632641188 ps
T801 /workspace/coverage/xbar_build_mode/18.xbar_smoke.923858222 Aug 13 05:33:32 PM PDT 24 Aug 13 05:33:34 PM PDT 24 138951532 ps
T213 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1060168924 Aug 13 05:33:32 PM PDT 24 Aug 13 05:36:33 PM PDT 24 73789755679 ps
T802 /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1395457038 Aug 13 05:33:02 PM PDT 24 Aug 13 05:33:04 PM PDT 24 199615724 ps
T803 /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1139219540 Aug 13 05:33:33 PM PDT 24 Aug 13 05:33:56 PM PDT 24 4774622330 ps
T804 /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4055568273 Aug 13 05:32:52 PM PDT 24 Aug 13 05:34:13 PM PDT 24 97626189460 ps
T805 /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1842317534 Aug 13 05:35:04 PM PDT 24 Aug 13 05:35:09 PM PDT 24 48242976 ps
T806 /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2808546214 Aug 13 05:34:14 PM PDT 24 Aug 13 05:36:04 PM PDT 24 5925432413 ps
T807 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2189268500 Aug 13 05:33:42 PM PDT 24 Aug 13 05:34:39 PM PDT 24 502117552 ps
T808 /workspace/coverage/xbar_build_mode/43.xbar_same_source.1847389145 Aug 13 05:34:54 PM PDT 24 Aug 13 05:34:58 PM PDT 24 35475708 ps
T809 /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.335052734 Aug 13 05:32:47 PM PDT 24 Aug 13 05:32:54 PM PDT 24 173970096 ps
T810 /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1004130278 Aug 13 05:33:32 PM PDT 24 Aug 13 05:33:44 PM PDT 24 3149511143 ps
T811 /workspace/coverage/xbar_build_mode/15.xbar_error_random.3898777024 Aug 13 05:33:30 PM PDT 24 Aug 13 05:33:31 PM PDT 24 52876292 ps
T812 /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.261634231 Aug 13 05:33:25 PM PDT 24 Aug 13 05:33:40 PM PDT 24 4810247502 ps
T813 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.317036875 Aug 13 05:33:48 PM PDT 24 Aug 13 05:34:36 PM PDT 24 222272576 ps
T814 /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3996694869 Aug 13 05:33:29 PM PDT 24 Aug 13 05:33:37 PM PDT 24 1410071900 ps
T815 /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.994909872 Aug 13 05:34:28 PM PDT 24 Aug 13 05:34:36 PM PDT 24 5776387588 ps
T816 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.720750718 Aug 13 05:33:07 PM PDT 24 Aug 13 05:36:02 PM PDT 24 1510202857 ps
T817 /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3007530342 Aug 13 05:32:49 PM PDT 24 Aug 13 05:33:03 PM PDT 24 1056307066 ps
T818 /workspace/coverage/xbar_build_mode/25.xbar_error_random.3295088091 Aug 13 05:33:59 PM PDT 24 Aug 13 05:34:02 PM PDT 24 368037417 ps
T819 /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2219903155 Aug 13 05:34:35 PM PDT 24 Aug 13 05:36:17 PM PDT 24 59476202326 ps
T820 /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.256623295 Aug 13 05:34:30 PM PDT 24 Aug 13 05:34:31 PM PDT 24 10915623 ps
T821 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4192011741 Aug 13 05:34:23 PM PDT 24 Aug 13 05:37:03 PM PDT 24 14766948905 ps
T822 /workspace/coverage/xbar_build_mode/13.xbar_smoke.3502791099 Aug 13 05:33:19 PM PDT 24 Aug 13 05:33:21 PM PDT 24 67399939 ps
T823 /workspace/coverage/xbar_build_mode/9.xbar_smoke.1343933760 Aug 13 05:33:08 PM PDT 24 Aug 13 05:33:09 PM PDT 24 12663081 ps
T824 /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3350363623 Aug 13 05:34:21 PM PDT 24 Aug 13 05:34:36 PM PDT 24 108752538 ps
T152 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.275228976 Aug 13 05:33:16 PM PDT 24 Aug 13 05:37:41 PM PDT 24 52506944111 ps
T825 /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1321227993 Aug 13 05:33:41 PM PDT 24 Aug 13 05:33:42 PM PDT 24 12798317 ps
T826 /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.58608012 Aug 13 05:34:14 PM PDT 24 Aug 13 05:34:16 PM PDT 24 23837178 ps
T150 /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3271441275 Aug 13 05:32:51 PM PDT 24 Aug 13 05:33:31 PM PDT 24 8605710475 ps
T827 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1961817675 Aug 13 05:35:03 PM PDT 24 Aug 13 05:37:27 PM PDT 24 8895952957 ps
T828 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2525104364 Aug 13 05:34:09 PM PDT 24 Aug 13 05:35:22 PM PDT 24 1116058141 ps
T829 /workspace/coverage/xbar_build_mode/45.xbar_random.55256500 Aug 13 05:35:05 PM PDT 24 Aug 13 05:35:09 PM PDT 24 40454711 ps
T830 /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.779750791 Aug 13 05:33:49 PM PDT 24 Aug 13 05:35:41 PM PDT 24 104579127018 ps
T831 /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1507210307 Aug 13 05:33:28 PM PDT 24 Aug 13 05:33:38 PM PDT 24 3096496754 ps
T832 /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1655805362 Aug 13 05:32:55 PM PDT 24 Aug 13 05:33:03 PM PDT 24 1258482135 ps
T833 /workspace/coverage/xbar_build_mode/22.xbar_error_random.2724906909 Aug 13 05:33:47 PM PDT 24 Aug 13 05:34:00 PM PDT 24 840439895 ps
T834 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2455283247 Aug 13 05:35:08 PM PDT 24 Aug 13 05:35:19 PM PDT 24 8915548013 ps
T835 /workspace/coverage/xbar_build_mode/27.xbar_error_random.96620561 Aug 13 05:34:07 PM PDT 24 Aug 13 05:34:17 PM PDT 24 640810322 ps
T836 /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1806549888 Aug 13 05:33:21 PM PDT 24 Aug 13 05:33:36 PM PDT 24 148235530 ps
T837 /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1927316834 Aug 13 05:35:08 PM PDT 24 Aug 13 05:35:17 PM PDT 24 9726385251 ps
T838 /workspace/coverage/xbar_build_mode/17.xbar_same_source.2030871649 Aug 13 05:33:34 PM PDT 24 Aug 13 05:33:47 PM PDT 24 874729155 ps
T839 /workspace/coverage/xbar_build_mode/28.xbar_smoke.849206186 Aug 13 05:34:05 PM PDT 24 Aug 13 05:34:07 PM PDT 24 19540366 ps
T840 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3639992531 Aug 13 05:33:15 PM PDT 24 Aug 13 05:34:20 PM PDT 24 6516530076 ps
T841 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2069415939 Aug 13 05:34:24 PM PDT 24 Aug 13 05:35:24 PM PDT 24 7001424573 ps
T842 /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4024204178 Aug 13 05:34:33 PM PDT 24 Aug 13 05:35:53 PM PDT 24 49675685081 ps
T843 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1270516160 Aug 13 05:34:47 PM PDT 24 Aug 13 05:35:34 PM PDT 24 212275797 ps
T844 /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1448850750 Aug 13 05:33:10 PM PDT 24 Aug 13 05:33:21 PM PDT 24 1295810609 ps
T845 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2353817163 Aug 13 05:34:17 PM PDT 24 Aug 13 05:36:43 PM PDT 24 1247895154 ps
T846 /workspace/coverage/xbar_build_mode/48.xbar_random.765743723 Aug 13 05:35:14 PM PDT 24 Aug 13 05:35:20 PM PDT 24 62514942 ps
T847 /workspace/coverage/xbar_build_mode/44.xbar_smoke.1886781247 Aug 13 05:35:01 PM PDT 24 Aug 13 05:35:03 PM PDT 24 507952861 ps
T848 /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3101508417 Aug 13 05:33:27 PM PDT 24 Aug 13 05:33:38 PM PDT 24 598851322 ps
T849 /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2176545811 Aug 13 05:33:07 PM PDT 24 Aug 13 05:33:11 PM PDT 24 48909233 ps
T850 /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.214027440 Aug 13 05:33:01 PM PDT 24 Aug 13 05:33:11 PM PDT 24 43902368 ps
T851 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3644556806 Aug 13 05:33:08 PM PDT 24 Aug 13 05:34:08 PM PDT 24 597593862 ps
T852 /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2840881637 Aug 13 05:34:31 PM PDT 24 Aug 13 05:35:42 PM PDT 24 3662548154 ps
T853 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.930104085 Aug 13 05:34:05 PM PDT 24 Aug 13 05:36:01 PM PDT 24 20790805778 ps
T854 /workspace/coverage/xbar_build_mode/23.xbar_smoke.3797514288 Aug 13 05:33:49 PM PDT 24 Aug 13 05:33:50 PM PDT 24 328898677 ps
T855 /workspace/coverage/xbar_build_mode/13.xbar_random.266014152 Aug 13 05:33:19 PM PDT 24 Aug 13 05:33:25 PM PDT 24 74393538 ps
T856 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1174075856 Aug 13 05:33:19 PM PDT 24 Aug 13 05:33:30 PM PDT 24 89954082 ps
T857 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1179067145 Aug 13 05:33:50 PM PDT 24 Aug 13 05:34:19 PM PDT 24 4017911757 ps
T858 /workspace/coverage/xbar_build_mode/13.xbar_error_random.682475079 Aug 13 05:33:27 PM PDT 24 Aug 13 05:33:31 PM PDT 24 127034045 ps
T859 /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2434961147 Aug 13 05:33:08 PM PDT 24 Aug 13 05:33:19 PM PDT 24 4199425535 ps
T860 /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.848408848 Aug 13 05:33:00 PM PDT 24 Aug 13 05:33:11 PM PDT 24 1420692402 ps
T861 /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3620543748 Aug 13 05:35:09 PM PDT 24 Aug 13 05:35:17 PM PDT 24 972076382 ps
T862 /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3010446058 Aug 13 05:33:06 PM PDT 24 Aug 13 05:33:07 PM PDT 24 10260336 ps
T863 /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3167322785 Aug 13 05:34:22 PM PDT 24 Aug 13 05:35:34 PM PDT 24 58874873729 ps
T864 /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2682295732 Aug 13 05:32:52 PM PDT 24 Aug 13 05:32:58 PM PDT 24 187420863 ps
T865 /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.657430237 Aug 13 05:34:16 PM PDT 24 Aug 13 05:34:17 PM PDT 24 10712266 ps
T866 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2913190720 Aug 13 05:34:16 PM PDT 24 Aug 13 05:35:36 PM PDT 24 5692089140 ps
T867 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2548817542 Aug 13 05:35:07 PM PDT 24 Aug 13 05:36:05 PM PDT 24 9694345165 ps
T868 /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3992726836 Aug 13 05:33:27 PM PDT 24 Aug 13 05:35:17 PM PDT 24 15854999220 ps
T869 /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3051295404 Aug 13 05:33:32 PM PDT 24 Aug 13 05:33:53 PM PDT 24 1054981583 ps
T870 /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.44445259 Aug 13 05:33:47 PM PDT 24 Aug 13 05:33:56 PM PDT 24 72085005 ps
T871 /workspace/coverage/xbar_build_mode/34.xbar_smoke.340853566 Aug 13 05:34:22 PM PDT 24 Aug 13 05:34:24 PM PDT 24 111051279 ps
T872 /workspace/coverage/xbar_build_mode/45.xbar_same_source.2307566755 Aug 13 05:35:06 PM PDT 24 Aug 13 05:35:09 PM PDT 24 182532769 ps
T873 /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1726424808 Aug 13 05:35:08 PM PDT 24 Aug 13 05:36:08 PM PDT 24 5237937186 ps
T874 /workspace/coverage/xbar_build_mode/10.xbar_error_random.4050185420 Aug 13 05:33:15 PM PDT 24 Aug 13 05:33:22 PM PDT 24 45753799 ps
T875 /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3558772372 Aug 13 05:34:36 PM PDT 24 Aug 13 05:34:43 PM PDT 24 4664710128 ps
T876 /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.628387922 Aug 13 05:33:26 PM PDT 24 Aug 13 05:33:31 PM PDT 24 56406587 ps
T877 /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3513440510 Aug 13 05:34:22 PM PDT 24 Aug 13 05:34:40 PM PDT 24 12082344604 ps
T878 /workspace/coverage/xbar_build_mode/47.xbar_smoke.3385737116 Aug 13 05:35:09 PM PDT 24 Aug 13 05:35:11 PM PDT 24 240935739 ps
T879 /workspace/coverage/xbar_build_mode/23.xbar_error_random.230920203 Aug 13 05:33:51 PM PDT 24 Aug 13 05:34:00 PM PDT 24 1011060611 ps
T880 /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1813389014 Aug 13 05:33:06 PM PDT 24 Aug 13 05:33:08 PM PDT 24 13104204 ps
T881 /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3333923767 Aug 13 05:32:48 PM PDT 24 Aug 13 05:32:57 PM PDT 24 1892585360 ps
T882 /workspace/coverage/xbar_build_mode/35.xbar_smoke.2590567662 Aug 13 05:34:30 PM PDT 24 Aug 13 05:34:32 PM PDT 24 69571520 ps
T883 /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1813831037 Aug 13 05:35:22 PM PDT 24 Aug 13 05:35:25 PM PDT 24 21030919 ps
T884 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2318894118 Aug 13 05:32:49 PM PDT 24 Aug 13 05:33:09 PM PDT 24 3236617023 ps
T885 /workspace/coverage/xbar_build_mode/11.xbar_smoke.3954767650 Aug 13 05:33:12 PM PDT 24 Aug 13 05:33:14 PM PDT 24 48217168 ps
T886 /workspace/coverage/xbar_build_mode/48.xbar_error_random.83536047 Aug 13 05:35:23 PM PDT 24 Aug 13 05:35:26 PM PDT 24 42832256 ps
T887 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1209642042 Aug 13 05:32:52 PM PDT 24 Aug 13 05:34:09 PM PDT 24 549496856 ps
T888 /workspace/coverage/xbar_build_mode/33.xbar_same_source.3909982194 Aug 13 05:34:20 PM PDT 24 Aug 13 05:34:29 PM PDT 24 3621104958 ps
T889 /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3678679292 Aug 13 05:33:49 PM PDT 24 Aug 13 05:34:06 PM PDT 24 71001377 ps
T890 /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.188340162 Aug 13 05:32:50 PM PDT 24 Aug 13 05:32:57 PM PDT 24 56137842 ps
T891 /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4236795097 Aug 13 05:33:03 PM PDT 24 Aug 13 05:33:06 PM PDT 24 40906638 ps
T892 /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2960507620 Aug 13 05:34:17 PM PDT 24 Aug 13 05:34:18 PM PDT 24 9564823 ps
T893 /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3947555001 Aug 13 05:34:32 PM PDT 24 Aug 13 05:34:38 PM PDT 24 68622054 ps
T894 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2779761347 Aug 13 05:33:19 PM PDT 24 Aug 13 05:34:34 PM PDT 24 10180838769 ps
T895 /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1663855081 Aug 13 05:34:02 PM PDT 24 Aug 13 05:34:53 PM PDT 24 3382537117 ps
T896 /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.793776935 Aug 13 05:33:29 PM PDT 24 Aug 13 05:33:30 PM PDT 24 14444810 ps
T897 /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3656949734 Aug 13 05:33:37 PM PDT 24 Aug 13 05:33:44 PM PDT 24 454863026 ps
T898 /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3225642149 Aug 13 05:33:34 PM PDT 24 Aug 13 05:33:36 PM PDT 24 25587842 ps
T899 /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2706892266 Aug 13 05:33:46 PM PDT 24 Aug 13 05:33:47 PM PDT 24 20661036 ps
T900 /workspace/coverage/xbar_build_mode/8.xbar_same_source.3435348387 Aug 13 05:33:05 PM PDT 24 Aug 13 05:33:10 PM PDT 24 437128105 ps

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.1404776965
Short name T4
Test name
Test status
Simulation time 1150081177 ps
CPU time 14.03 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:31 PM PDT 24
Peak memory 201620 kb
Host smart-9ec55e89-25c6-40bd-9152-e77eee5320b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404776965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1404776965
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.327154993
Short name T103
Test name
Test status
Simulation time 67289831264 ps
CPU time 333.2 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:39:56 PM PDT 24
Peak memory 204112 kb
Host smart-106d576a-4264-4327-8fab-d3b5745b62d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=327154993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo
w_rsp.327154993
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1767890454
Short name T97
Test name
Test status
Simulation time 106395827326 ps
CPU time 335.63 seconds
Started Aug 13 05:34:50 PM PDT 24
Finished Aug 13 05:40:26 PM PDT 24
Peak memory 203068 kb
Host smart-7f5f74da-c7bd-485f-b05d-cb2ad44574ee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1767890454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.1767890454
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.155385364
Short name T105
Test name
Test status
Simulation time 271577079877 ps
CPU time 306.34 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:40:20 PM PDT 24
Peak memory 203064 kb
Host smart-f9742ce7-af0c-4963-955b-cc3a7f16ded2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=155385364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo
w_rsp.155385364
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4088952624
Short name T8
Test name
Test status
Simulation time 2160505113 ps
CPU time 221.93 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:36:42 PM PDT 24
Peak memory 207888 kb
Host smart-06e1c255-3b6e-4881-a4f4-f6c822c0aed3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4088952624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.4088952624
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.4032591011
Short name T38
Test name
Test status
Simulation time 54281853272 ps
CPU time 268.93 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:37:17 PM PDT 24
Peak memory 202964 kb
Host smart-3f90f5f7-a391-448b-a684-8985c41f38af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4032591011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.4032591011
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1085363309
Short name T16
Test name
Test status
Simulation time 24957746044 ps
CPU time 160.98 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:35:29 PM PDT 24
Peak memory 202016 kb
Host smart-de6178f1-6dd8-4150-a8ae-03c558ba4a6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1085363309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1085363309
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1750636211
Short name T79
Test name
Test status
Simulation time 16726343872 ps
CPU time 248.91 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:37:08 PM PDT 24
Peak memory 206124 kb
Host smart-3c9470c9-a59e-4505-8eab-0e320c164d24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1750636211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.1750636211
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3875964805
Short name T200
Test name
Test status
Simulation time 47401901625 ps
CPU time 338.64 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:40:47 PM PDT 24
Peak memory 203064 kb
Host smart-ebb7a856-a246-4b7a-b59b-f4fa1a59d9fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3875964805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.3875964805
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2696798241
Short name T26
Test name
Test status
Simulation time 46124959546 ps
CPU time 119.58 seconds
Started Aug 13 05:34:56 PM PDT 24
Finished Aug 13 05:36:56 PM PDT 24
Peak memory 201892 kb
Host smart-c933d3f2-c027-40ba-9773-9fcb933d610c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696798241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2696798241
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2829924675
Short name T197
Test name
Test status
Simulation time 18590430149 ps
CPU time 144.29 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:37:11 PM PDT 24
Peak memory 202924 kb
Host smart-41d540ad-3277-41aa-852d-6853ce5c2c2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2829924675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl
ow_rsp.2829924675
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.216475196
Short name T10
Test name
Test status
Simulation time 2648937946 ps
CPU time 104.43 seconds
Started Aug 13 05:33:52 PM PDT 24
Finished Aug 13 05:35:37 PM PDT 24
Peak memory 204772 kb
Host smart-3f5e3763-7f0b-4df3-8028-27bc3852313a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=216475196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res
et_error.216475196
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.871753311
Short name T6
Test name
Test status
Simulation time 1200140170 ps
CPU time 209.86 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:37:30 PM PDT 24
Peak memory 207208 kb
Host smart-7bd04e5a-0ef9-44bf-a01a-7f830823f19e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=871753311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand
_reset.871753311
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2796133011
Short name T25
Test name
Test status
Simulation time 4985754333 ps
CPU time 182 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:37:32 PM PDT 24
Peak memory 205960 kb
Host smart-0c260f77-e25a-4f8c-ac6b-159795212584
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2796133011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.2796133011
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.1489461942
Short name T12
Test name
Test status
Simulation time 1121474223 ps
CPU time 11.29 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:59 PM PDT 24
Peak memory 201808 kb
Host smart-9b7bbd18-0046-4661-858d-4f9c02b220cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1489461942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1489461942
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1285471922
Short name T1
Test name
Test status
Simulation time 56838256118 ps
CPU time 137.39 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:36:42 PM PDT 24
Peak memory 202012 kb
Host smart-d1d008de-0c3f-4f49-8e5c-225bb7692e38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1285471922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1285471922
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.147165073
Short name T68
Test name
Test status
Simulation time 27100731099 ps
CPU time 107.53 seconds
Started Aug 13 05:34:46 PM PDT 24
Finished Aug 13 05:36:34 PM PDT 24
Peak memory 202128 kb
Host smart-53d46978-f564-426e-8871-e12871a5cc74
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=147165073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.147165073
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1709734666
Short name T154
Test name
Test status
Simulation time 4612909565 ps
CPU time 94.92 seconds
Started Aug 13 05:33:20 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 204876 kb
Host smart-d7aa8ba2-a6f1-42c6-b7ef-be9c45c36f88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1709734666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.1709734666
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3594550737
Short name T212
Test name
Test status
Simulation time 7330026347 ps
CPU time 202.38 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:36:10 PM PDT 24
Peak memory 209296 kb
Host smart-2a0749ee-c9f5-437a-962f-7f5fece0ce2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3594550737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.3594550737
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.8143854
Short name T196
Test name
Test status
Simulation time 65696589998 ps
CPU time 273.48 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:38:33 PM PDT 24
Peak memory 202980 kb
Host smart-79afc1fe-6fca-4bc2-8837-eff23b59b06b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=8143854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.8143854
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1301216083
Short name T758
Test name
Test status
Simulation time 2925858662 ps
CPU time 32.4 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:39 PM PDT 24
Peak memory 203152 kb
Host smart-fc96c416-75a9-455e-9990-6f86b9c3eced
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1301216083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.1301216083
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.150401684
Short name T67
Test name
Test status
Simulation time 37582630017 ps
CPU time 164.37 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 203028 kb
Host smart-81a7fa66-1630-4248-96b0-db752a84e16e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=150401684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo
w_rsp.150401684
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.4239340464
Short name T320
Test name
Test status
Simulation time 204210684 ps
CPU time 18.24 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201928 kb
Host smart-2e7789e5-594b-4f9f-b7fc-a704ce61d8ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4239340464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4239340464
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1173586877
Short name T402
Test name
Test status
Simulation time 10154374139 ps
CPU time 37.77 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:33:24 PM PDT 24
Peak memory 202032 kb
Host smart-a1718167-6339-4fef-9001-eceb9a262fe8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1173586877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.1173586877
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.335052734
Short name T809
Test name
Test status
Simulation time 173970096 ps
CPU time 7.06 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:54 PM PDT 24
Peak memory 201964 kb
Host smart-23782084-3fec-462e-b520-a482bbea3213
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=335052734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.335052734
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.3365869824
Short name T694
Test name
Test status
Simulation time 1548443043 ps
CPU time 11.35 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:58 PM PDT 24
Peak memory 201880 kb
Host smart-5a0cf37d-4a79-44f3-9ab1-8bc78d01dcab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3365869824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3365869824
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.240296454
Short name T274
Test name
Test status
Simulation time 571861622 ps
CPU time 11.2 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:33:01 PM PDT 24
Peak memory 201912 kb
Host smart-33b40ea4-dba1-4f43-aa88-49afab6fa83e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=240296454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.240296454
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1552451739
Short name T593
Test name
Test status
Simulation time 67648020731 ps
CPU time 165.87 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:35:32 PM PDT 24
Peak memory 201888 kb
Host smart-97054e4e-c9ba-44d3-ae6c-4187e6bf4003
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552451739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1552451739
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.371088782
Short name T612
Test name
Test status
Simulation time 59278242 ps
CPU time 5.93 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:52 PM PDT 24
Peak memory 201956 kb
Host smart-6d8f596b-36e0-488a-8d45-165302d70278
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371088782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.371088782
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.368757613
Short name T160
Test name
Test status
Simulation time 202584461 ps
CPU time 2.73 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:32:53 PM PDT 24
Peak memory 201976 kb
Host smart-ffaa5c42-3d2f-4bf7-a98d-75bef2b028db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=368757613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.368757613
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2214649044
Short name T430
Test name
Test status
Simulation time 438157865 ps
CPU time 2 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:48 PM PDT 24
Peak memory 201920 kb
Host smart-b2a1c373-9b61-4319-879f-c06d000bbd41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2214649044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2214649044
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2319629634
Short name T732
Test name
Test status
Simulation time 1532813064 ps
CPU time 7.56 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:55 PM PDT 24
Peak memory 201920 kb
Host smart-c8d88277-15f7-4547-834e-3a42c7867c29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319629634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2319629634
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3629949565
Short name T375
Test name
Test status
Simulation time 2244523396 ps
CPU time 7.98 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:55 PM PDT 24
Peak memory 202032 kb
Host smart-e83760d5-cf7b-46e4-82f0-ba638775b2a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3629949565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3629949565
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2106339590
Short name T725
Test name
Test status
Simulation time 10339111 ps
CPU time 1.15 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:47 PM PDT 24
Peak memory 201956 kb
Host smart-82dee100-8030-4366-a56c-6622e090d28b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106339590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2106339590
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.1510147263
Short name T287
Test name
Test status
Simulation time 4846965414 ps
CPU time 81.55 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 204400 kb
Host smart-be3850bd-2942-4515-867b-5c9f8b87ab28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1510147263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1510147263
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.857907797
Short name T268
Test name
Test status
Simulation time 5801765848 ps
CPU time 82.18 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 203060 kb
Host smart-7277a202-4867-4674-b339-434b5852ea52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=857907797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.857907797
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1146311260
Short name T229
Test name
Test status
Simulation time 1286854830 ps
CPU time 84.74 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 204188 kb
Host smart-498a5ae0-a096-4b56-940f-a82e9a13837d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1146311260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.1146311260
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.565130324
Short name T558
Test name
Test status
Simulation time 4840430572 ps
CPU time 15.15 seconds
Started Aug 13 05:32:44 PM PDT 24
Finished Aug 13 05:32:59 PM PDT 24
Peak memory 201884 kb
Host smart-ecf36093-ea4a-4ae3-9672-7df55f4fbfb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=565130324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.565130324
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.636579984
Short name T486
Test name
Test status
Simulation time 686458758 ps
CPU time 8.47 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:57 PM PDT 24
Peak memory 201880 kb
Host smart-af117367-a841-4073-97e1-a4d904b97d6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=636579984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.636579984
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2270630224
Short name T113
Test name
Test status
Simulation time 474289707 ps
CPU time 2.43 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:49 PM PDT 24
Peak memory 201872 kb
Host smart-be4df396-3601-475a-b23c-3bd0ae506f2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2270630224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2270630224
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.357186877
Short name T633
Test name
Test status
Simulation time 1438966806 ps
CPU time 5.46 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:52 PM PDT 24
Peak memory 201880 kb
Host smart-93a04140-db31-4aab-a066-b2a3cff1f1f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=357186877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.357186877
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3130644159
Short name T477
Test name
Test status
Simulation time 9281496298 ps
CPU time 37.82 seconds
Started Aug 13 05:32:45 PM PDT 24
Finished Aug 13 05:33:23 PM PDT 24
Peak memory 201836 kb
Host smart-dae829bb-613b-4bf5-b7f8-084a6a208f78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130644159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3130644159
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2318894118
Short name T884
Test name
Test status
Simulation time 3236617023 ps
CPU time 20.66 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:33:09 PM PDT 24
Peak memory 201928 kb
Host smart-ed71385c-1c3a-4d6d-8ee6-0c0a4446b868
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2318894118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2318894118
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.552683949
Short name T473
Test name
Test status
Simulation time 147017643 ps
CPU time 4.92 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:32:54 PM PDT 24
Peak memory 201956 kb
Host smart-10b9bbf5-25be-4744-9bc9-d742bd64f6cc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552683949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.552683949
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.3478696548
Short name T142
Test name
Test status
Simulation time 602772578 ps
CPU time 6.08 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:54 PM PDT 24
Peak memory 201860 kb
Host smart-07cdc70c-f485-432b-989d-0ad56dfdb2b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478696548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3478696548
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.2587508506
Short name T244
Test name
Test status
Simulation time 11661792 ps
CPU time 1.47 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:50 PM PDT 24
Peak memory 201888 kb
Host smart-73a797d2-b629-43d6-8e34-dd118bd29485
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2587508506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2587508506
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.7360745
Short name T513
Test name
Test status
Simulation time 3243264086 ps
CPU time 8.69 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:56 PM PDT 24
Peak memory 201884 kb
Host smart-09be4ea6-95a9-4bb9-840d-4b8d3b5a7a16
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=7360745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.7360745
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1833348850
Short name T601
Test name
Test status
Simulation time 7944562729 ps
CPU time 7.07 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:53 PM PDT 24
Peak memory 202036 kb
Host smart-2a0f0400-49c4-409e-a507-7d1a1622ffff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1833348850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1833348850
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1746648190
Short name T470
Test name
Test status
Simulation time 9566807 ps
CPU time 1.24 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:49 PM PDT 24
Peak memory 201984 kb
Host smart-eaf45fc7-c94a-4120-83de-82bd7e29e2f6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746648190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1746648190
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1637793826
Short name T77
Test name
Test status
Simulation time 6607704291 ps
CPU time 50.49 seconds
Started Aug 13 05:33:02 PM PDT 24
Finished Aug 13 05:33:53 PM PDT 24
Peak memory 203048 kb
Host smart-c7f8beac-198d-42f5-b394-5796bfd06552
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1637793826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1637793826
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.417822049
Short name T246
Test name
Test status
Simulation time 2772641864 ps
CPU time 31.47 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:33:21 PM PDT 24
Peak memory 202024 kb
Host smart-9e8abda8-2d7e-431e-80c5-37312ee6e9ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=417822049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.417822049
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.137386751
Short name T760
Test name
Test status
Simulation time 580919010 ps
CPU time 105.02 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 205876 kb
Host smart-7e603aaa-9509-46b8-8230-684808502078
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=137386751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_
reset.137386751
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3398161324
Short name T226
Test name
Test status
Simulation time 386647047 ps
CPU time 71.52 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:33:58 PM PDT 24
Peak memory 205392 kb
Host smart-7a7dbb29-6ce8-4b2b-a3f7-c3a9178cf045
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3398161324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.3398161324
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.197089614
Short name T698
Test name
Test status
Simulation time 1046111284 ps
CPU time 9.98 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:58 PM PDT 24
Peak memory 201872 kb
Host smart-51053afc-7cbe-4a31-bb09-a75f97edd98b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=197089614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.197089614
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3082855838
Short name T474
Test name
Test status
Simulation time 398199123 ps
CPU time 3.52 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:33:16 PM PDT 24
Peak memory 201920 kb
Host smart-c5afe3e2-76b4-4f34-9121-38cf1a3d13eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3082855838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3082855838
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1244957649
Short name T207
Test name
Test status
Simulation time 29233444824 ps
CPU time 185.8 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 202908 kb
Host smart-0562aa37-0b5e-417f-a28b-8fb6189a8303
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1244957649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.1244957649
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2644429421
Short name T408
Test name
Test status
Simulation time 2029819886 ps
CPU time 9.26 seconds
Started Aug 13 05:33:11 PM PDT 24
Finished Aug 13 05:33:21 PM PDT 24
Peak memory 201916 kb
Host smart-ddb59491-82f5-44a2-9923-0338dada276f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2644429421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2644429421
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.4050185420
Short name T874
Test name
Test status
Simulation time 45753799 ps
CPU time 6.53 seconds
Started Aug 13 05:33:15 PM PDT 24
Finished Aug 13 05:33:22 PM PDT 24
Peak memory 201960 kb
Host smart-4b34ed1a-0c47-4f61-9994-8f1fb23b870a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4050185420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4050185420
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.16783993
Short name T313
Test name
Test status
Simulation time 79270544 ps
CPU time 3.07 seconds
Started Aug 13 05:33:16 PM PDT 24
Finished Aug 13 05:33:19 PM PDT 24
Peak memory 201816 kb
Host smart-89f0e4d1-b690-453b-a645-8a6419c84f27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16783993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.16783993
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1744977520
Short name T536
Test name
Test status
Simulation time 35232052529 ps
CPU time 60.31 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:34:19 PM PDT 24
Peak memory 201968 kb
Host smart-20c6b5b7-726e-4b60-bac0-87be74404a69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744977520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1744977520
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.91082875
Short name T306
Test name
Test status
Simulation time 6987683571 ps
CPU time 42.36 seconds
Started Aug 13 05:33:14 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 202032 kb
Host smart-3d7c435b-8cb4-43c4-82d8-d9c85662af3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=91082875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.91082875
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1285497864
Short name T769
Test name
Test status
Simulation time 48183054 ps
CPU time 7.44 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:33:20 PM PDT 24
Peak memory 201872 kb
Host smart-84bec632-85b8-4c33-9513-459527459cc9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285497864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1285497864
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.3171656010
Short name T583
Test name
Test status
Simulation time 24689223 ps
CPU time 2.53 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:33:19 PM PDT 24
Peak memory 201916 kb
Host smart-05eccf72-2edc-4668-b085-4814d52176d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3171656010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3171656010
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.43617741
Short name T167
Test name
Test status
Simulation time 23265258 ps
CPU time 1.52 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:33:14 PM PDT 24
Peak memory 201836 kb
Host smart-d2c65e18-4443-4e40-ac07-8d7a9e695efd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43617741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.43617741
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1504435367
Short name T312
Test name
Test status
Simulation time 16906593345 ps
CPU time 10.58 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:33:23 PM PDT 24
Peak memory 201940 kb
Host smart-9f5e0408-6451-4b1e-a680-d80ff3f75392
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504435367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1504435367
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1313144079
Short name T567
Test name
Test status
Simulation time 6398733681 ps
CPU time 9.82 seconds
Started Aug 13 05:33:26 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201940 kb
Host smart-f0a12a48-77ef-4877-a396-6b17934fc79c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1313144079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1313144079
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3494273586
Short name T483
Test name
Test status
Simulation time 16722083 ps
CPU time 1.23 seconds
Started Aug 13 05:33:14 PM PDT 24
Finished Aug 13 05:33:15 PM PDT 24
Peak memory 201956 kb
Host smart-62702bef-a572-4fc0-a3bb-37373568ed30
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494273586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3494273586
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.4270142481
Short name T462
Test name
Test status
Simulation time 3879519863 ps
CPU time 31.14 seconds
Started Aug 13 05:33:18 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 204044 kb
Host smart-de05c5d6-9723-4dcf-afd9-bbfa732cb3c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4270142481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4270142481
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3639992531
Short name T840
Test name
Test status
Simulation time 6516530076 ps
CPU time 64.36 seconds
Started Aug 13 05:33:15 PM PDT 24
Finished Aug 13 05:34:20 PM PDT 24
Peak memory 203060 kb
Host smart-408db47d-9174-4a13-936f-662b080d2ab0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3639992531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3639992531
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2735257584
Short name T374
Test name
Test status
Simulation time 2260089016 ps
CPU time 89.01 seconds
Started Aug 13 05:33:11 PM PDT 24
Finished Aug 13 05:34:41 PM PDT 24
Peak memory 205368 kb
Host smart-9ce58c27-bad3-41c4-b41d-f5e89b05f212
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2735257584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.2735257584
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2779761347
Short name T894
Test name
Test status
Simulation time 10180838769 ps
CPU time 75.25 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:34:34 PM PDT 24
Peak memory 204324 kb
Host smart-7602c032-81ae-42ad-89dd-9620a7d97b20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779761347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.2779761347
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.596575162
Short name T358
Test name
Test status
Simulation time 523167631 ps
CPU time 9.72 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 201860 kb
Host smart-4e231a22-e24f-423e-9300-68992038d869
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=596575162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.596575162
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3424571203
Short name T389
Test name
Test status
Simulation time 1114516818 ps
CPU time 18.07 seconds
Started Aug 13 05:33:14 PM PDT 24
Finished Aug 13 05:33:32 PM PDT 24
Peak memory 201952 kb
Host smart-200b8af5-135c-4b7f-8911-fbca2039066e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3424571203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3424571203
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.275228976
Short name T152
Test name
Test status
Simulation time 52506944111 ps
CPU time 264.91 seconds
Started Aug 13 05:33:16 PM PDT 24
Finished Aug 13 05:37:41 PM PDT 24
Peak memory 203076 kb
Host smart-e4f9f2a0-29a1-4f15-8fd0-268a010de882
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=275228976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.275228976
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1448850750
Short name T844
Test name
Test status
Simulation time 1295810609 ps
CPU time 10.71 seconds
Started Aug 13 05:33:10 PM PDT 24
Finished Aug 13 05:33:21 PM PDT 24
Peak memory 201912 kb
Host smart-18da9dc2-c5a3-468f-9ae0-20d7f9cd15fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448850750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1448850750
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.4251909844
Short name T449
Test name
Test status
Simulation time 693470946 ps
CPU time 5.72 seconds
Started Aug 13 05:33:11 PM PDT 24
Finished Aug 13 05:33:17 PM PDT 24
Peak memory 201968 kb
Host smart-300240f2-373f-48b8-93c5-098cfeef84b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4251909844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.4251909844
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.3000610327
Short name T293
Test name
Test status
Simulation time 282206696 ps
CPU time 6.76 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:26 PM PDT 24
Peak memory 201856 kb
Host smart-01b2b2de-e7cb-44e3-b151-0fb17837eca7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3000610327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3000610327
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1210130406
Short name T410
Test name
Test status
Simulation time 27567831560 ps
CPU time 98.95 seconds
Started Aug 13 05:33:18 PM PDT 24
Finished Aug 13 05:34:57 PM PDT 24
Peak memory 201928 kb
Host smart-9bb78e02-baf3-42f2-8bb7-18207ba44476
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210130406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1210130406
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3469525930
Short name T323
Test name
Test status
Simulation time 4504388519 ps
CPU time 33.94 seconds
Started Aug 13 05:33:11 PM PDT 24
Finished Aug 13 05:33:45 PM PDT 24
Peak memory 201884 kb
Host smart-13c10ac0-def8-4152-a0a9-2cdaa73715d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3469525930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3469525930
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2068189150
Short name T680
Test name
Test status
Simulation time 64842591 ps
CPU time 8.73 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201872 kb
Host smart-bc72b098-b432-47d2-b5e0-70b56887c1a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068189150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2068189150
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.3305449603
Short name T693
Test name
Test status
Simulation time 776719307 ps
CPU time 8.81 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:28 PM PDT 24
Peak memory 201824 kb
Host smart-106afad4-f585-462c-a0e5-9da6d9831c92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3305449603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3305449603
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.3954767650
Short name T885
Test name
Test status
Simulation time 48217168 ps
CPU time 1.46 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:33:14 PM PDT 24
Peak memory 201904 kb
Host smart-f229a9d8-6375-43b1-b67c-8e0814da8479
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3954767650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3954767650
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.261634231
Short name T812
Test name
Test status
Simulation time 4810247502 ps
CPU time 14.97 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:40 PM PDT 24
Peak memory 201904 kb
Host smart-121b2563-b08b-4da1-b5f2-43aa2f295b97
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=261634231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.261634231
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3378266306
Short name T418
Test name
Test status
Simulation time 1197711733 ps
CPU time 7.25 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201880 kb
Host smart-eab122fd-f053-4b05-a462-feec330695a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3378266306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3378266306
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2348815746
Short name T550
Test name
Test status
Simulation time 9721623 ps
CPU time 1.22 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:26 PM PDT 24
Peak memory 201892 kb
Host smart-837dd4d7-a74b-45e3-993a-8b9c2079f573
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348815746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2348815746
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.735461137
Short name T250
Test name
Test status
Simulation time 9815122929 ps
CPU time 32.87 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201932 kb
Host smart-0942561f-3dd2-493c-9f3e-9cef21b717a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=735461137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.735461137
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1604738729
Short name T604
Test name
Test status
Simulation time 159871516 ps
CPU time 5.91 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:25 PM PDT 24
Peak memory 201956 kb
Host smart-3fb98579-7db2-4338-88cc-d2f0ecdb0ddf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604738729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1604738729
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.529280421
Short name T69
Test name
Test status
Simulation time 10701536213 ps
CPU time 117.34 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 207168 kb
Host smart-1b935f18-5c2e-406b-86f9-f4ce188cdc86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=529280421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand
_reset.529280421
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.4172189174
Short name T186
Test name
Test status
Simulation time 183465604 ps
CPU time 11.13 seconds
Started Aug 13 05:33:22 PM PDT 24
Finished Aug 13 05:33:33 PM PDT 24
Peak memory 201864 kb
Host smart-f2b88f1a-a2e3-4378-951d-11cad94b9720
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4172189174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.4172189174
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3739714812
Short name T661
Test name
Test status
Simulation time 22171647 ps
CPU time 2.65 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:22 PM PDT 24
Peak memory 201964 kb
Host smart-528e9d53-f3c4-48bc-a106-85581ac7d57c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3739714812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3739714812
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1806549888
Short name T836
Test name
Test status
Simulation time 148235530 ps
CPU time 14.72 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201968 kb
Host smart-bdddd88a-d719-4baf-aac9-5fc7a6a694b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1806549888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1806549888
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2072581377
Short name T373
Test name
Test status
Simulation time 537855631 ps
CPU time 4.45 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:25 PM PDT 24
Peak memory 201964 kb
Host smart-efaa3a20-23b3-4541-9500-1f29bfacc782
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2072581377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2072581377
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1350395736
Short name T654
Test name
Test status
Simulation time 1612794051 ps
CPU time 10.23 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201928 kb
Host smart-5834fd99-65ab-46a7-b168-8e02fda451e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1350395736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1350395736
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.3170796476
Short name T33
Test name
Test status
Simulation time 632641188 ps
CPU time 13.29 seconds
Started Aug 13 05:33:20 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201816 kb
Host smart-95353181-49a8-4c69-b604-63751af8d12d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3170796476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3170796476
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2385048731
Short name T173
Test name
Test status
Simulation time 106049211592 ps
CPU time 92.14 seconds
Started Aug 13 05:33:20 PM PDT 24
Finished Aug 13 05:34:52 PM PDT 24
Peak memory 201928 kb
Host smart-978e8462-2a69-4468-a6a4-7b004d4e79ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385048731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2385048731
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3172090683
Short name T666
Test name
Test status
Simulation time 6581565617 ps
CPU time 26.54 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:46 PM PDT 24
Peak memory 202008 kb
Host smart-1f00ff3f-7ebe-44dc-b878-e47db63a0eac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3172090683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3172090683
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3571347468
Short name T527
Test name
Test status
Simulation time 84891878 ps
CPU time 4.54 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:26 PM PDT 24
Peak memory 201868 kb
Host smart-a863678b-fe4e-45aa-abf8-7167b011be82
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571347468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3571347468
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.293636079
Short name T348
Test name
Test status
Simulation time 21193079 ps
CPU time 1.28 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:21 PM PDT 24
Peak memory 201972 kb
Host smart-b02d93b1-5fae-44c7-952e-944dca1d0268
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=293636079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.293636079
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.355337957
Short name T28
Test name
Test status
Simulation time 97417027 ps
CPU time 1.81 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:33:19 PM PDT 24
Peak memory 201788 kb
Host smart-d076eb96-1282-4d40-9f09-2d9ae75b4084
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=355337957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.355337957
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3344433733
Short name T488
Test name
Test status
Simulation time 2610309451 ps
CPU time 9.54 seconds
Started Aug 13 05:33:20 PM PDT 24
Finished Aug 13 05:33:30 PM PDT 24
Peak memory 201948 kb
Host smart-cf89f97a-62e4-4f86-b6d8-ee7a16c449d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344433733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3344433733
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3311085267
Short name T451
Test name
Test status
Simulation time 15663247271 ps
CPU time 13.38 seconds
Started Aug 13 05:33:22 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 201996 kb
Host smart-e59bc725-6e55-4b04-a285-4b53f07b6725
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3311085267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3311085267
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.567792631
Short name T504
Test name
Test status
Simulation time 8831331 ps
CPU time 1.11 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:20 PM PDT 24
Peak memory 201868 kb
Host smart-853aa588-fd6f-4d36-9977-49dbb7d59629
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567792631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.567792631
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2666570271
Short name T569
Test name
Test status
Simulation time 10232628984 ps
CPU time 74.22 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:34:31 PM PDT 24
Peak memory 203008 kb
Host smart-7dd87a5e-31a9-4d43-bd64-7b05b775e38f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2666570271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2666570271
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1196421712
Short name T170
Test name
Test status
Simulation time 2611558998 ps
CPU time 44.95 seconds
Started Aug 13 05:33:18 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 202032 kb
Host smart-e8035939-8895-4b0b-8845-10461f6eb942
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196421712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1196421712
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.149896738
Short name T761
Test name
Test status
Simulation time 5297814318 ps
CPU time 89.88 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 206520 kb
Host smart-5e7b7bb6-b060-499a-a342-7766ff35198b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=149896738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res
et_error.149896738
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.716174274
Short name T708
Test name
Test status
Simulation time 96432286 ps
CPU time 3.32 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201964 kb
Host smart-2b7cffb1-a991-4f2d-bac2-3c4032df3406
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=716174274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.716174274
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3364903067
Short name T294
Test name
Test status
Simulation time 32215602 ps
CPU time 3.47 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201960 kb
Host smart-5ac1ef1a-4101-453a-89c8-5cce81c16319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364903067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3364903067
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3071690162
Short name T172
Test name
Test status
Simulation time 13107362751 ps
CPU time 91.3 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 202036 kb
Host smart-2ac8cd79-c19f-4cd7-9caa-1de55a9b2760
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3071690162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3071690162
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.766016936
Short name T431
Test name
Test status
Simulation time 152960135 ps
CPU time 2.67 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201964 kb
Host smart-c14e56d0-c059-4d72-9dfb-33a9e6b0420d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=766016936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.766016936
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.682475079
Short name T858
Test name
Test status
Simulation time 127034045 ps
CPU time 4.53 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201968 kb
Host smart-7318944f-e361-4cae-a0f9-2b7d297b7bbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682475079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.682475079
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.266014152
Short name T855
Test name
Test status
Simulation time 74393538 ps
CPU time 6.22 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:25 PM PDT 24
Peak memory 201756 kb
Host smart-e0be82e4-9456-4822-87fd-a6e3b4ec7f32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=266014152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.266014152
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.564695181
Short name T597
Test name
Test status
Simulation time 40411479325 ps
CPU time 150.25 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 201936 kb
Host smart-cace45fb-2d82-4d5e-a253-23694fc7e07d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=564695181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.564695181
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1025258746
Short name T648
Test name
Test status
Simulation time 9243380014 ps
CPU time 50.61 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:34:10 PM PDT 24
Peak memory 201960 kb
Host smart-bbefad34-ceea-4e6b-930d-6a21c97ee876
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1025258746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1025258746
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.4213179072
Short name T689
Test name
Test status
Simulation time 20618897 ps
CPU time 1.98 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:29 PM PDT 24
Peak memory 201872 kb
Host smart-be35a822-bee9-4a4b-bd52-98e8f4a15be8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213179072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.4213179072
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.4096048262
Short name T502
Test name
Test status
Simulation time 843384494 ps
CPU time 7.47 seconds
Started Aug 13 05:33:20 PM PDT 24
Finished Aug 13 05:33:28 PM PDT 24
Peak memory 201900 kb
Host smart-83b0b6e4-bab3-4ac3-9b41-d14c52ab1def
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4096048262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4096048262
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.3502791099
Short name T822
Test name
Test status
Simulation time 67399939 ps
CPU time 1.61 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:21 PM PDT 24
Peak memory 201840 kb
Host smart-eadc0c3f-ab0a-45d1-9185-dd0935260256
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3502791099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3502791099
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3577005474
Short name T270
Test name
Test status
Simulation time 2983105329 ps
CPU time 8.53 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:30 PM PDT 24
Peak memory 201976 kb
Host smart-00b5dca5-cce4-4455-9e3b-f41c97c7cb03
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577005474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3577005474
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1927388708
Short name T161
Test name
Test status
Simulation time 1925760578 ps
CPU time 11.09 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:30 PM PDT 24
Peak memory 201944 kb
Host smart-fb50c233-5b9e-4051-ac4f-3be01864572b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1927388708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1927388708
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.143544450
Short name T417
Test name
Test status
Simulation time 8068321 ps
CPU time 1.05 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:22 PM PDT 24
Peak memory 201864 kb
Host smart-5ccc8c9f-94e3-4893-a2a3-469f7e275a0b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143544450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.143544450
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.4376545
Short name T335
Test name
Test status
Simulation time 3094939839 ps
CPU time 38.1 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 202880 kb
Host smart-40044abf-b99b-4bb5-a7f8-d161201df3c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4376545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.4376545
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2615747460
Short name T743
Test name
Test status
Simulation time 13230918736 ps
CPU time 82.89 seconds
Started Aug 13 05:33:23 PM PDT 24
Finished Aug 13 05:34:46 PM PDT 24
Peak memory 201940 kb
Host smart-f459c0a2-c89f-4376-a418-4d062c67e00c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2615747460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2615747460
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.916922504
Short name T107
Test name
Test status
Simulation time 8272647577 ps
CPU time 120.22 seconds
Started Aug 13 05:33:18 PM PDT 24
Finished Aug 13 05:35:18 PM PDT 24
Peak memory 206332 kb
Host smart-33489584-d07f-43b8-af41-b6782ea0df55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=916922504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand
_reset.916922504
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1174075856
Short name T856
Test name
Test status
Simulation time 89954082 ps
CPU time 10.68 seconds
Started Aug 13 05:33:19 PM PDT 24
Finished Aug 13 05:33:30 PM PDT 24
Peak memory 201880 kb
Host smart-1993c93e-76c6-4b43-a2f9-037c105d7bf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174075856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.1174075856
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3566597864
Short name T528
Test name
Test status
Simulation time 61891822 ps
CPU time 3.45 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:30 PM PDT 24
Peak memory 201968 kb
Host smart-71cf224d-9157-4a32-889e-9b33c52fa2cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3566597864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3566597864
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3051295404
Short name T869
Test name
Test status
Simulation time 1054981583 ps
CPU time 20.7 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:53 PM PDT 24
Peak memory 201956 kb
Host smart-904f85cb-0611-4301-b82d-d036cd1c06a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3051295404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3051295404
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1235670989
Short name T106
Test name
Test status
Simulation time 126246791496 ps
CPU time 161 seconds
Started Aug 13 05:33:23 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 203024 kb
Host smart-82c66c91-cd19-4326-9cd1-388c40a3caa8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1235670989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.1235670989
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2868436178
Short name T555
Test name
Test status
Simulation time 53971896 ps
CPU time 4.12 seconds
Started Aug 13 05:33:31 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 201952 kb
Host smart-7a8b2bb2-a3bf-4321-9567-a2a8ace420bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2868436178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2868436178
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.298333812
Short name T592
Test name
Test status
Simulation time 1161293655 ps
CPU time 8.44 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201960 kb
Host smart-e70440fe-b968-42d5-8b48-29501beec528
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=298333812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.298333812
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.3092150020
Short name T786
Test name
Test status
Simulation time 212476598 ps
CPU time 4 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:33:32 PM PDT 24
Peak memory 201880 kb
Host smart-48f2eb15-94bc-4cd1-a35c-fc66bf4ca896
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3092150020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3092150020
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1876059025
Short name T277
Test name
Test status
Simulation time 3144315582 ps
CPU time 15.36 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:40 PM PDT 24
Peak memory 201940 kb
Host smart-48f1d5a3-deca-42a0-8d55-233e380ea362
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876059025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1876059025
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.119025430
Short name T572
Test name
Test status
Simulation time 3718915122 ps
CPU time 24.91 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 202012 kb
Host smart-90fafcc8-7d94-45ee-afc1-86bd84ab73a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=119025430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.119025430
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.628387922
Short name T876
Test name
Test status
Simulation time 56406587 ps
CPU time 5.47 seconds
Started Aug 13 05:33:26 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201956 kb
Host smart-2c7ec833-7a36-4dcf-8137-7489baf9f0f1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628387922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.628387922
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.17270199
Short name T520
Test name
Test status
Simulation time 119212025 ps
CPU time 6.07 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:40 PM PDT 24
Peak memory 201856 kb
Host smart-ef9366a6-4a3c-45b8-b9c2-133968db1192
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17270199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.17270199
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.3956793375
Short name T40
Test name
Test status
Simulation time 13189257 ps
CPU time 1.02 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 201800 kb
Host smart-a25803f7-2a7a-4302-8ca1-36e48d991f45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3956793375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3956793375
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3955833498
Short name T330
Test name
Test status
Simulation time 7798652668 ps
CPU time 7.72 seconds
Started Aug 13 05:33:24 PM PDT 24
Finished Aug 13 05:33:32 PM PDT 24
Peak memory 201840 kb
Host smart-a3a9b006-db3d-415c-a9ab-5bb197f3cd92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955833498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3955833498
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1088641665
Short name T500
Test name
Test status
Simulation time 1250306817 ps
CPU time 8.45 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201884 kb
Host smart-8db41e2b-12f6-429c-bfd7-59a67c3e4b20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1088641665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1088641665
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4130522140
Short name T22
Test name
Test status
Simulation time 10291769 ps
CPU time 1.12 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:28 PM PDT 24
Peak memory 201892 kb
Host smart-7cdc0bb6-a7a4-4f3e-bc02-d35f4e393d60
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130522140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4130522140
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.1950493305
Short name T192
Test name
Test status
Simulation time 9292567 ps
CPU time 1.18 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201924 kb
Host smart-6c61d274-ad78-4f1b-8682-21b76ffce8ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1950493305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1950493305
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2377636070
Short name T793
Test name
Test status
Simulation time 5396735048 ps
CPU time 63.45 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 204004 kb
Host smart-22bd4997-d027-40c8-96e7-d4324459e4e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2377636070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2377636070
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4266171583
Short name T223
Test name
Test status
Simulation time 6267159498 ps
CPU time 68.21 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 205016 kb
Host smart-e7581f5e-8dc0-4969-bd06-34ea7ef72e44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4266171583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.4266171583
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1013941367
Short name T621
Test name
Test status
Simulation time 7283333571 ps
CPU time 37.76 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 201904 kb
Host smart-696bbb9f-b085-4fba-9b7a-3471d6929d7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1013941367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.1013941367
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1067249330
Short name T187
Test name
Test status
Simulation time 1117382099 ps
CPU time 8.7 seconds
Started Aug 13 05:33:24 PM PDT 24
Finished Aug 13 05:33:32 PM PDT 24
Peak memory 201932 kb
Host smart-c886eaeb-d117-4cd1-8d1e-0ff0ea55f2e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067249330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1067249330
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3214104500
Short name T435
Test name
Test status
Simulation time 1373232922 ps
CPU time 22.52 seconds
Started Aug 13 05:33:31 PM PDT 24
Finished Aug 13 05:33:54 PM PDT 24
Peak memory 201440 kb
Host smart-121b4fb6-c943-4a37-96e1-cb0301c06bfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3214104500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3214104500
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1102404073
Short name T175
Test name
Test status
Simulation time 2603950019 ps
CPU time 16.23 seconds
Started Aug 13 05:33:26 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 202044 kb
Host smart-7cc6c881-258a-48e4-9a36-6beb675f2db4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1102404073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1102404073
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3996694869
Short name T814
Test name
Test status
Simulation time 1410071900 ps
CPU time 7.88 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:33:37 PM PDT 24
Peak memory 201912 kb
Host smart-c55392f0-e22d-47ba-b21e-faf06aa284f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3996694869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3996694869
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.3898777024
Short name T811
Test name
Test status
Simulation time 52876292 ps
CPU time 1.55 seconds
Started Aug 13 05:33:30 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201972 kb
Host smart-1219f9d1-4984-46d2-a1a6-04f438ddb020
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3898777024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3898777024
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.2909468049
Short name T468
Test name
Test status
Simulation time 753345489 ps
CPU time 8.58 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:33:37 PM PDT 24
Peak memory 201896 kb
Host smart-4295cdcb-e337-482c-9089-425cc6dd5565
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2909468049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2909468049
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1347057508
Short name T512
Test name
Test status
Simulation time 24078291209 ps
CPU time 104.57 seconds
Started Aug 13 05:33:30 PM PDT 24
Finished Aug 13 05:35:14 PM PDT 24
Peak memory 201924 kb
Host smart-9b7d3917-8764-4a93-85a1-1cf58875c82d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347057508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1347057508
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3992726836
Short name T868
Test name
Test status
Simulation time 15854999220 ps
CPU time 110.79 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:35:17 PM PDT 24
Peak memory 202024 kb
Host smart-8a55c0c5-50f2-4a70-84d5-06b922dd0fbc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3992726836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3992726836
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.538522719
Short name T588
Test name
Test status
Simulation time 84482589 ps
CPU time 3.64 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:33:33 PM PDT 24
Peak memory 201908 kb
Host smart-f49b0d78-109c-4520-910b-bb1a7c2da9e7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538522719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.538522719
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.1645331777
Short name T728
Test name
Test status
Simulation time 1949691491 ps
CPU time 11.91 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:33:40 PM PDT 24
Peak memory 201884 kb
Host smart-4a2f3074-9e39-4eb7-8545-d7897a8acbac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1645331777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1645331777
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.3532510523
Short name T304
Test name
Test status
Simulation time 151847648 ps
CPU time 1.5 seconds
Started Aug 13 05:33:26 PM PDT 24
Finished Aug 13 05:33:27 PM PDT 24
Peak memory 201860 kb
Host smart-625d8b0e-c61a-4e3f-a750-9452d08198c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3532510523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3532510523
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1507210307
Short name T831
Test name
Test status
Simulation time 3096496754 ps
CPU time 9.62 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:33:38 PM PDT 24
Peak memory 201932 kb
Host smart-b6d8794f-5189-4e4d-939e-13895bb9722a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507210307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1507210307
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2308982486
Short name T757
Test name
Test status
Simulation time 3422954828 ps
CPU time 12.72 seconds
Started Aug 13 05:33:26 PM PDT 24
Finished Aug 13 05:33:39 PM PDT 24
Peak memory 202004 kb
Host smart-123bc115-91b3-407a-8f9f-6a132f02321a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2308982486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2308982486
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1501238068
Short name T720
Test name
Test status
Simulation time 12244167 ps
CPU time 1.25 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201848 kb
Host smart-132f7ee5-5de6-431a-8aa8-8252eea45ef8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501238068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1501238068
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.224922587
Short name T120
Test name
Test status
Simulation time 684186894 ps
CPU time 15.74 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:33:45 PM PDT 24
Peak memory 201988 kb
Host smart-551f301a-13e7-4b17-b6f0-98082fd3b8a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=224922587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.224922587
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.843520074
Short name T383
Test name
Test status
Simulation time 191020730 ps
CPU time 23.94 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:49 PM PDT 24
Peak memory 201876 kb
Host smart-e998cba5-b9a2-43e3-9bd5-3ae32a129117
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=843520074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.843520074
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.25691401
Short name T538
Test name
Test status
Simulation time 78231021 ps
CPU time 14.06 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 201956 kb
Host smart-dc2b5e10-3ebc-44b4-9f0e-851ca6674c10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25691401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_
reset.25691401
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3732648362
Short name T448
Test name
Test status
Simulation time 1222299599 ps
CPU time 48.83 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:34:17 PM PDT 24
Peak memory 204256 kb
Host smart-5c77f952-aea7-44f3-89e9-efc4b447a546
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3732648362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.3732648362
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3675580224
Short name T543
Test name
Test status
Simulation time 35042907 ps
CPU time 3.93 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:29 PM PDT 24
Peak memory 202124 kb
Host smart-6696103e-d853-44b7-a979-3e2ac30af235
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3675580224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3675580224
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2385856782
Short name T746
Test name
Test status
Simulation time 2436366062 ps
CPU time 8.5 seconds
Started Aug 13 05:33:28 PM PDT 24
Finished Aug 13 05:33:37 PM PDT 24
Peak memory 202004 kb
Host smart-9d7c7b70-1ee6-42db-be58-b26c8d159ddf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2385856782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2385856782
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3835869710
Short name T104
Test name
Test status
Simulation time 30000482162 ps
CPU time 164.08 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:36:09 PM PDT 24
Peak memory 203060 kb
Host smart-38aacf8f-0df0-4388-abe0-5b98c3165e67
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3835869710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3835869710
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2730415619
Short name T437
Test name
Test status
Simulation time 59370739 ps
CPU time 6.07 seconds
Started Aug 13 05:33:31 PM PDT 24
Finished Aug 13 05:33:37 PM PDT 24
Peak memory 201496 kb
Host smart-d5cbad5c-bbbd-4068-ab42-e2004d46cca6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2730415619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2730415619
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.2915440196
Short name T321
Test name
Test status
Simulation time 153146682 ps
CPU time 1.84 seconds
Started Aug 13 05:33:38 PM PDT 24
Finished Aug 13 05:33:40 PM PDT 24
Peak memory 201844 kb
Host smart-75efa878-514b-4740-a345-daea9e1af6fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2915440196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2915440196
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.3269551940
Short name T534
Test name
Test status
Simulation time 459048253 ps
CPU time 8.95 seconds
Started Aug 13 05:33:31 PM PDT 24
Finished Aug 13 05:33:40 PM PDT 24
Peak memory 201908 kb
Host smart-1e768195-3a61-4281-b778-9326fd2efccf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3269551940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3269551940
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.270416401
Short name T305
Test name
Test status
Simulation time 29641056721 ps
CPU time 97.72 seconds
Started Aug 13 05:33:26 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 201944 kb
Host smart-19aff679-9717-4281-9a03-6c937c5d557c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=270416401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.270416401
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2963499894
Short name T387
Test name
Test status
Simulation time 36528056750 ps
CPU time 113.73 seconds
Started Aug 13 05:33:30 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 201992 kb
Host smart-fbfe9c87-a1b3-4517-8bd0-604a8745a064
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2963499894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2963499894
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3791363790
Short name T563
Test name
Test status
Simulation time 119715375 ps
CPU time 2.95 seconds
Started Aug 13 05:33:30 PM PDT 24
Finished Aug 13 05:33:33 PM PDT 24
Peak memory 201908 kb
Host smart-eed2bc2f-f733-4929-8c50-2792990165e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791363790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3791363790
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.2464248728
Short name T251
Test name
Test status
Simulation time 4201525793 ps
CPU time 11.72 seconds
Started Aug 13 05:33:25 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201888 kb
Host smart-38f0d46b-7eed-4494-9416-0d8d9dac31ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2464248728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2464248728
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.4164186081
Short name T43
Test name
Test status
Simulation time 12567945 ps
CPU time 1.19 seconds
Started Aug 13 05:33:30 PM PDT 24
Finished Aug 13 05:33:32 PM PDT 24
Peak memory 201864 kb
Host smart-83c8683e-fc30-4a72-ab8b-7b88745f7bec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4164186081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4164186081
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.541700173
Short name T642
Test name
Test status
Simulation time 2283601186 ps
CPU time 8.95 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 201980 kb
Host smart-fe33bc85-fb16-4f49-b676-3cf41f3936e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=541700173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.541700173
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1747926511
Short name T384
Test name
Test status
Simulation time 2456956427 ps
CPU time 7.43 seconds
Started Aug 13 05:33:21 PM PDT 24
Finished Aug 13 05:33:29 PM PDT 24
Peak memory 201948 kb
Host smart-4ba884d6-4506-4100-94b6-1fb490f331d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1747926511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1747926511
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.793776935
Short name T896
Test name
Test status
Simulation time 14444810 ps
CPU time 1.37 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:33:30 PM PDT 24
Peak memory 201956 kb
Host smart-b402586a-63f3-4555-94db-22c96fb06d51
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793776935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.793776935
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.4115869051
Short name T100
Test name
Test status
Simulation time 25720595971 ps
CPU time 148.92 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 205880 kb
Host smart-f07619a1-40fc-4b84-bad5-fb1b9f6c6d1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115869051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4115869051
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.4039612145
Short name T388
Test name
Test status
Simulation time 114922317 ps
CPU time 9.21 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201856 kb
Host smart-36dd9c2d-2a15-4fda-8a26-783c552dd1e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4039612145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.4039612145
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2233951118
Short name T784
Test name
Test status
Simulation time 2750027766 ps
CPU time 67.06 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 204220 kb
Host smart-e0efe33a-5a24-4b0a-91f9-7655076a200d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2233951118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.2233951118
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1188418628
Short name T58
Test name
Test status
Simulation time 1076097405 ps
CPU time 108.6 seconds
Started Aug 13 05:33:29 PM PDT 24
Finished Aug 13 05:35:18 PM PDT 24
Peak memory 205776 kb
Host smart-7a7f26f6-6e75-45fe-9b21-e3a5bfa367cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1188418628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.1188418628
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3101508417
Short name T848
Test name
Test status
Simulation time 598851322 ps
CPU time 10.65 seconds
Started Aug 13 05:33:27 PM PDT 24
Finished Aug 13 05:33:38 PM PDT 24
Peak memory 201952 kb
Host smart-843d4a44-4b43-4c75-8ca5-3814bf9e1e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3101508417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3101508417
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.4150281981
Short name T347
Test name
Test status
Simulation time 366103177 ps
CPU time 11 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 201968 kb
Host smart-1ee96147-45d4-42c3-a033-645339580ef0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4150281981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.4150281981
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1060168924
Short name T213
Test name
Test status
Simulation time 73789755679 ps
CPU time 180.66 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:36:33 PM PDT 24
Peak memory 203032 kb
Host smart-b08d8b20-f5b2-4d95-ac60-6e9cc5129b24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1060168924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.1060168924
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3225642149
Short name T898
Test name
Test status
Simulation time 25587842 ps
CPU time 2.52 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201920 kb
Host smart-6519ce25-662a-4217-89f2-6dd54b731551
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3225642149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3225642149
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.851822311
Short name T242
Test name
Test status
Simulation time 287190039 ps
CPU time 2.5 seconds
Started Aug 13 05:33:35 PM PDT 24
Finished Aug 13 05:33:38 PM PDT 24
Peak memory 201980 kb
Host smart-a6e088a9-9650-40a3-9da0-7cd170bd89c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=851822311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.851822311
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.1300869177
Short name T438
Test name
Test status
Simulation time 3483399167 ps
CPU time 12.71 seconds
Started Aug 13 05:33:31 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201964 kb
Host smart-9a10a267-dca2-4061-ab0d-ed66a9d26870
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1300869177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1300869177
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1139219540
Short name T803
Test name
Test status
Simulation time 4774622330 ps
CPU time 23.68 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 201980 kb
Host smart-77bc09e5-9668-4909-99b3-99fb49a2688a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139219540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1139219540
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3835801288
Short name T482
Test name
Test status
Simulation time 9875315723 ps
CPU time 49.59 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:34:24 PM PDT 24
Peak memory 202040 kb
Host smart-2087f7ba-eedd-4908-8902-bc20d78a2b82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3835801288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3835801288
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2434178803
Short name T672
Test name
Test status
Simulation time 56595378 ps
CPU time 4.62 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:38 PM PDT 24
Peak memory 201956 kb
Host smart-ce0afd04-ae7b-4b78-9e0f-399bd08828c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434178803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2434178803
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2030871649
Short name T838
Test name
Test status
Simulation time 874729155 ps
CPU time 13.25 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201880 kb
Host smart-59e19906-829b-4a4c-9a95-12868328a428
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2030871649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2030871649
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2418404153
Short name T90
Test name
Test status
Simulation time 21236839 ps
CPU time 1.17 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201804 kb
Host smart-d272b888-0faa-47e8-adc4-791af0b6d5ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2418404153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2418404153
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3118642176
Short name T796
Test name
Test status
Simulation time 5768872791 ps
CPU time 9.3 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 201924 kb
Host smart-4e591fa5-c983-45b1-b2fc-ab7a0dfe3489
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118642176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3118642176
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3323759210
Short name T279
Test name
Test status
Simulation time 3094894767 ps
CPU time 7.41 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 202028 kb
Host smart-e679e502-edf5-44a7-a1d6-441ef81db3a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3323759210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3323759210
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2682061044
Short name T19
Test name
Test status
Simulation time 8510878 ps
CPU time 1.1 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201956 kb
Host smart-675f8bbc-50b8-416e-8517-8cc2bf2d3923
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682061044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2682061044
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3943542070
Short name T367
Test name
Test status
Simulation time 9759913749 ps
CPU time 19.29 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:52 PM PDT 24
Peak memory 201996 kb
Host smart-0635dfbb-e32d-4b92-9566-f8de0ed54637
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3943542070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3943542070
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3380276312
Short name T324
Test name
Test status
Simulation time 415445597 ps
CPU time 32.61 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:34:05 PM PDT 24
Peak memory 201964 kb
Host smart-d5e3f194-2407-4d47-844f-64098899d105
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3380276312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3380276312
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2092401486
Short name T620
Test name
Test status
Simulation time 491348284 ps
CPU time 81.31 seconds
Started Aug 13 05:33:35 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 204572 kb
Host smart-859c0312-979e-48f4-bf13-d0a16749e1c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2092401486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.2092401486
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4118506567
Short name T751
Test name
Test status
Simulation time 56719786 ps
CPU time 7.47 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 201988 kb
Host smart-1c41fd68-c551-4bcc-b3a9-3df713f99a0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4118506567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.4118506567
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1412902932
Short name T252
Test name
Test status
Simulation time 357058426 ps
CPU time 3.64 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 202120 kb
Host smart-5e3930b7-0abd-43bd-b02a-5c4ee6d61033
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1412902932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1412902932
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.4128528226
Short name T400
Test name
Test status
Simulation time 15824407 ps
CPU time 2.29 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 201916 kb
Host smart-9fc86387-34ca-409c-af71-7a7852dc1410
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4128528226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.4128528226
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4073295838
Short name T650
Test name
Test status
Simulation time 56652953696 ps
CPU time 96.79 seconds
Started Aug 13 05:33:35 PM PDT 24
Finished Aug 13 05:35:12 PM PDT 24
Peak memory 201880 kb
Host smart-a0bb802f-f211-4e18-8042-2d0c45040650
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4073295838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.4073295838
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3656949734
Short name T897
Test name
Test status
Simulation time 454863026 ps
CPU time 7.07 seconds
Started Aug 13 05:33:37 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201992 kb
Host smart-bfda0f4a-71fe-491b-b1d6-e378f4c34d5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3656949734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3656949734
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.849762647
Short name T272
Test name
Test status
Simulation time 203163325 ps
CPU time 2.29 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:35 PM PDT 24
Peak memory 201972 kb
Host smart-f4322c4e-5889-43cc-bb45-a2f4a2621740
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=849762647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.849762647
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.1632556737
Short name T145
Test name
Test status
Simulation time 514978672 ps
CPU time 6.2 seconds
Started Aug 13 05:33:37 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 201916 kb
Host smart-24f2b5a3-32b3-4f9e-9917-f59a675c6dfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1632556737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1632556737
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3045598807
Short name T95
Test name
Test status
Simulation time 169893359644 ps
CPU time 167.36 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:36:21 PM PDT 24
Peak memory 201892 kb
Host smart-c46c26ee-e67c-4e3b-b7f9-65b31cd3959e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045598807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3045598807
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1646977896
Short name T331
Test name
Test status
Simulation time 54333979089 ps
CPU time 62.69 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 201808 kb
Host smart-123eabb8-e1b9-4dd8-a940-79749e581cea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1646977896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1646977896
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.365025322
Short name T395
Test name
Test status
Simulation time 343211334 ps
CPU time 6.65 seconds
Started Aug 13 05:33:35 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 201964 kb
Host smart-f4458ff6-8b2c-42c9-84ef-867e7bf6df37
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365025322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.365025322
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.2093396522
Short name T439
Test name
Test status
Simulation time 1038783233 ps
CPU time 8.68 seconds
Started Aug 13 05:33:34 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 201880 kb
Host smart-aee623cf-6f8a-4aa4-96d2-17767972ce6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2093396522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2093396522
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.923858222
Short name T801
Test name
Test status
Simulation time 138951532 ps
CPU time 1.35 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201836 kb
Host smart-30e90e87-dc42-4848-a7a3-82d035d60de8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=923858222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.923858222
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1051469014
Short name T765
Test name
Test status
Simulation time 2830079880 ps
CPU time 10.37 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201980 kb
Host smart-1527c054-82f2-4bc0-822e-57e0d4f1288e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051469014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1051469014
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2859843350
Short name T83
Test name
Test status
Simulation time 3174531267 ps
CPU time 9.24 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 201988 kb
Host smart-3e45a127-22b9-4320-811f-30bfc209dcf7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2859843350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2859843350
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4130296303
Short name T475
Test name
Test status
Simulation time 13827281 ps
CPU time 1.28 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 201648 kb
Host smart-af575b62-d988-4143-a0a0-48377c0ebf6b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130296303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4130296303
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3896514411
Short name T166
Test name
Test status
Simulation time 158945073 ps
CPU time 7.34 seconds
Started Aug 13 05:33:35 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 201876 kb
Host smart-bdbe3670-8a62-4a87-867f-9c4a90525323
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3896514411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3896514411
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1317462166
Short name T485
Test name
Test status
Simulation time 186905131 ps
CPU time 17.37 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:49 PM PDT 24
Peak memory 201976 kb
Host smart-0067cd62-1103-4c10-ab71-c4b10d474989
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1317462166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1317462166
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1417678681
Short name T490
Test name
Test status
Simulation time 167084419 ps
CPU time 47.11 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:34:19 PM PDT 24
Peak memory 204340 kb
Host smart-74596003-33d8-46d0-a296-f89a16958020
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1417678681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.1417678681
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.558346298
Short name T653
Test name
Test status
Simulation time 239972253 ps
CPU time 32.88 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 203000 kb
Host smart-ab80b9e1-2336-4cc1-9c16-60ba03efbc64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=558346298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res
et_error.558346298
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1657950367
Short name T255
Test name
Test status
Simulation time 13009409 ps
CPU time 1.45 seconds
Started Aug 13 05:33:37 PM PDT 24
Finished Aug 13 05:33:38 PM PDT 24
Peak memory 201976 kb
Host smart-5c725598-547a-4e9c-9e25-f59a8e69152b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1657950367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1657950367
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1711143830
Short name T96
Test name
Test status
Simulation time 881367287 ps
CPU time 21.01 seconds
Started Aug 13 05:33:38 PM PDT 24
Finished Aug 13 05:33:59 PM PDT 24
Peak memory 201812 kb
Host smart-1753611d-9fcd-41b8-a691-d2fa0125e9cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1711143830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1711143830
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2048876888
Short name T110
Test name
Test status
Simulation time 64721091811 ps
CPU time 317.96 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:38:59 PM PDT 24
Peak memory 203600 kb
Host smart-bf75ab31-7e06-4839-82d7-ebe32be81e44
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2048876888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.2048876888
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.693596304
Short name T62
Test name
Test status
Simulation time 378675140 ps
CPU time 1.83 seconds
Started Aug 13 05:33:40 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 201872 kb
Host smart-73359f42-78b4-4de3-a1d3-ab9913f3a757
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=693596304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.693596304
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.671144540
Short name T733
Test name
Test status
Simulation time 44717126 ps
CPU time 2.95 seconds
Started Aug 13 05:33:38 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 202104 kb
Host smart-0885bbdd-ebef-43e6-a884-e53a28116a41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=671144540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.671144540
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.330130497
Short name T282
Test name
Test status
Simulation time 28459517 ps
CPU time 3.09 seconds
Started Aug 13 05:33:38 PM PDT 24
Finished Aug 13 05:33:41 PM PDT 24
Peak memory 201928 kb
Host smart-70df4d11-8658-4310-9ea4-9abc61c135c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=330130497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.330130497
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.291052507
Short name T149
Test name
Test status
Simulation time 5024250547 ps
CPU time 17.9 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:59 PM PDT 24
Peak memory 201888 kb
Host smart-7cbf6a1d-e4b5-4da9-9c8e-6c8fd571a406
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=291052507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.291052507
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2195540349
Short name T132
Test name
Test status
Simulation time 223203775573 ps
CPU time 208.59 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:37:10 PM PDT 24
Peak memory 201908 kb
Host smart-0fd323d7-ebef-404b-9850-e4a27fb11068
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2195540349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2195540349
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1406154746
Short name T119
Test name
Test status
Simulation time 98516854 ps
CPU time 5.14 seconds
Started Aug 13 05:33:38 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201948 kb
Host smart-9e640da2-e634-44fd-91a7-12e732f17678
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406154746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1406154746
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.3345919738
Short name T795
Test name
Test status
Simulation time 1700699799 ps
CPU time 6.67 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:48 PM PDT 24
Peak memory 201864 kb
Host smart-cadf1e2a-7589-4dea-90ee-85dbf41af5b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3345919738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3345919738
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2165333893
Short name T269
Test name
Test status
Simulation time 42018191 ps
CPU time 1.45 seconds
Started Aug 13 05:33:35 PM PDT 24
Finished Aug 13 05:33:36 PM PDT 24
Peak memory 201916 kb
Host smart-c24b697f-778b-42d9-8487-fb8235ee0c5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2165333893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2165333893
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1004130278
Short name T810
Test name
Test status
Simulation time 3149511143 ps
CPU time 12.4 seconds
Started Aug 13 05:33:32 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201952 kb
Host smart-68e441a3-1be2-4ebe-8572-e6f7b8c60694
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004130278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1004130278
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1130915736
Short name T704
Test name
Test status
Simulation time 9223375075 ps
CPU time 8.93 seconds
Started Aug 13 05:33:33 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 202044 kb
Host smart-3785a334-d915-46d8-9e01-0d104084fbc2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1130915736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1130915736
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1628434063
Short name T495
Test name
Test status
Simulation time 10366462 ps
CPU time 1.1 seconds
Started Aug 13 05:33:36 PM PDT 24
Finished Aug 13 05:33:37 PM PDT 24
Peak memory 201868 kb
Host smart-de087d59-47de-4ae3-8c42-378afb75740f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628434063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1628434063
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1574078608
Short name T118
Test name
Test status
Simulation time 12804946660 ps
CPU time 78.32 seconds
Started Aug 13 05:33:40 PM PDT 24
Finished Aug 13 05:34:59 PM PDT 24
Peak memory 203012 kb
Host smart-193b58d8-f8a4-4193-9171-4840a2beaf14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1574078608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1574078608
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1411825830
Short name T345
Test name
Test status
Simulation time 178586070 ps
CPU time 21.68 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 201964 kb
Host smart-dbb18b5d-28e1-4da3-a670-700391036053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1411825830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1411825830
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2189268500
Short name T807
Test name
Test status
Simulation time 502117552 ps
CPU time 57.06 seconds
Started Aug 13 05:33:42 PM PDT 24
Finished Aug 13 05:34:39 PM PDT 24
Peak memory 204308 kb
Host smart-cda6f20f-f1b6-47ef-aa47-4dbe32060432
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2189268500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.2189268500
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2949348826
Short name T625
Test name
Test status
Simulation time 200940850 ps
CPU time 15.19 seconds
Started Aug 13 05:33:39 PM PDT 24
Finished Aug 13 05:33:55 PM PDT 24
Peak memory 201920 kb
Host smart-73585013-cc75-415a-9786-8067e294773c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2949348826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.2949348826
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3381329690
Short name T770
Test name
Test status
Simulation time 132352359 ps
CPU time 6.16 seconds
Started Aug 13 05:33:37 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 201832 kb
Host smart-1e00a4d1-ff88-4649-8993-fb6066b76934
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3381329690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3381329690
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3007530342
Short name T817
Test name
Test status
Simulation time 1056307066 ps
CPU time 13.85 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201860 kb
Host smart-8cb8d24f-4a3c-4dde-907f-8ce1742ec8c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3007530342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3007530342
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1845569559
Short name T46
Test name
Test status
Simulation time 53729400230 ps
CPU time 110.04 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 202044 kb
Host smart-35e1419f-0b1b-499c-b5c0-3f8241462a45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1845569559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.1845569559
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4003583008
Short name T72
Test name
Test status
Simulation time 567406367 ps
CPU time 11.09 seconds
Started Aug 13 05:32:53 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201872 kb
Host smart-fb414e50-4990-46e9-b62e-6b61d37c95c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003583008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4003583008
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.1528313959
Short name T664
Test name
Test status
Simulation time 39370171 ps
CPU time 3.9 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:32:56 PM PDT 24
Peak memory 201964 kb
Host smart-52bb01a2-d769-40d6-beee-46debbf70cbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1528313959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1528313959
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.2350385486
Short name T529
Test name
Test status
Simulation time 50619620 ps
CPU time 5.16 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:32:55 PM PDT 24
Peak memory 201904 kb
Host smart-31e2dc73-8330-46be-9771-743d8d9d2102
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2350385486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2350385486
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3952315385
Short name T638
Test name
Test status
Simulation time 14476518409 ps
CPU time 37.97 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:29 PM PDT 24
Peak memory 201884 kb
Host smart-60552801-3f79-46af-8ba2-88d3d71736e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952315385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3952315385
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2471682516
Short name T506
Test name
Test status
Simulation time 19076408771 ps
CPU time 118.85 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:34:48 PM PDT 24
Peak memory 202012 kb
Host smart-114bcc0c-2d38-4fe3-95fd-47753b37ab35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2471682516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2471682516
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3828767980
Short name T652
Test name
Test status
Simulation time 17358151 ps
CPU time 1.93 seconds
Started Aug 13 05:32:54 PM PDT 24
Finished Aug 13 05:32:56 PM PDT 24
Peak memory 201904 kb
Host smart-d208375d-4ab5-4919-967c-5445271329b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828767980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3828767980
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.1815431227
Short name T670
Test name
Test status
Simulation time 2176766546 ps
CPU time 9.96 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:01 PM PDT 24
Peak memory 202012 kb
Host smart-7aa17369-df39-4fdc-a80f-4f35c3302f91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1815431227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1815431227
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.2230728364
Short name T259
Test name
Test status
Simulation time 133735460 ps
CPU time 1.91 seconds
Started Aug 13 05:32:47 PM PDT 24
Finished Aug 13 05:32:49 PM PDT 24
Peak memory 201932 kb
Host smart-a1ca85ec-ef7e-464c-9b4f-786949160028
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2230728364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2230728364
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2122111279
Short name T114
Test name
Test status
Simulation time 1364338261 ps
CPU time 7.33 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:33:06 PM PDT 24
Peak memory 201916 kb
Host smart-be5db139-c502-4416-bd3e-9fe83c4cb3d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122111279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2122111279
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3969102359
Short name T143
Test name
Test status
Simulation time 1252105906 ps
CPU time 6.91 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:32:58 PM PDT 24
Peak memory 201876 kb
Host smart-27f9e9d0-2f91-45a7-8c3c-4c52953449cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3969102359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3969102359
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2378346839
Short name T774
Test name
Test status
Simulation time 9769696 ps
CPU time 1.22 seconds
Started Aug 13 05:32:46 PM PDT 24
Finished Aug 13 05:32:47 PM PDT 24
Peak memory 201876 kb
Host smart-e6209dbf-785b-4899-b7ad-e8551cbdc904
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378346839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2378346839
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.346194407
Short name T365
Test name
Test status
Simulation time 397459165 ps
CPU time 33.35 seconds
Started Aug 13 05:32:54 PM PDT 24
Finished Aug 13 05:33:27 PM PDT 24
Peak memory 201876 kb
Host smart-eefd7dbe-2bb6-4039-b674-e09204c09b81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=346194407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.346194407
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1912165892
Short name T537
Test name
Test status
Simulation time 431800629 ps
CPU time 35.73 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:27 PM PDT 24
Peak memory 201928 kb
Host smart-ecbc688f-3267-4cfa-9810-daeaebf6417f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1912165892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1912165892
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2518081521
Short name T224
Test name
Test status
Simulation time 681867478 ps
CPU time 132.18 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:35:03 PM PDT 24
Peak memory 205904 kb
Host smart-5e3d7ca1-c7f6-4978-b46f-371a8c71cb5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2518081521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.2518081521
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1009730223
Short name T489
Test name
Test status
Simulation time 112676672 ps
CPU time 19.58 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:11 PM PDT 24
Peak memory 201932 kb
Host smart-1db48b50-6b46-40b0-b31b-b3fdd9d7555a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1009730223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res
et_error.1009730223
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1556899242
Short name T772
Test name
Test status
Simulation time 883055431 ps
CPU time 12.89 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:33:05 PM PDT 24
Peak memory 201944 kb
Host smart-ae6858f3-ef3e-4656-a090-c1d961075952
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1556899242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1556899242
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2367456943
Short name T338
Test name
Test status
Simulation time 127384475 ps
CPU time 2.97 seconds
Started Aug 13 05:33:44 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201844 kb
Host smart-5219737d-3e9b-4767-ad29-31e352e28107
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2367456943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2367456943
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3680963522
Short name T194
Test name
Test status
Simulation time 10747946415 ps
CPU time 77.27 seconds
Started Aug 13 05:33:39 PM PDT 24
Finished Aug 13 05:34:57 PM PDT 24
Peak memory 201996 kb
Host smart-f164a498-34dd-48e5-838b-4fbe3e31503f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3680963522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.3680963522
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.868626202
Short name T275
Test name
Test status
Simulation time 34921312 ps
CPU time 3.13 seconds
Started Aug 13 05:33:39 PM PDT 24
Finished Aug 13 05:33:43 PM PDT 24
Peak memory 201876 kb
Host smart-a343fef1-f614-46ae-8014-d6e6cd23b6df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=868626202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.868626202
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.3681648647
Short name T551
Test name
Test status
Simulation time 46467400 ps
CPU time 3.51 seconds
Started Aug 13 05:33:40 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 201964 kb
Host smart-13fee3ea-e81e-4a3a-ad62-caf68bd11f1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3681648647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3681648647
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.1744076733
Short name T517
Test name
Test status
Simulation time 796615601 ps
CPU time 5.94 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201860 kb
Host smart-a4f3c04d-f6a4-496c-8ca6-edf323de99ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744076733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1744076733
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3956850007
Short name T5
Test name
Test status
Simulation time 16134703194 ps
CPU time 70.01 seconds
Started Aug 13 05:33:45 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 201972 kb
Host smart-f677f662-b6ad-4cf4-a6d1-a0af00c0f3aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956850007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3956850007
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2486326671
Short name T174
Test name
Test status
Simulation time 14083583226 ps
CPU time 94.9 seconds
Started Aug 13 05:33:42 PM PDT 24
Finished Aug 13 05:35:17 PM PDT 24
Peak memory 201984 kb
Host smart-e8a7a658-8c43-49eb-8dfd-297bc957c70b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2486326671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2486326671
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2566416232
Short name T281
Test name
Test status
Simulation time 72149763 ps
CPU time 4.84 seconds
Started Aug 13 05:33:42 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201800 kb
Host smart-be926882-5985-4dd4-9933-631c3c984b5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566416232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2566416232
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.1978943991
Short name T542
Test name
Test status
Simulation time 102409519 ps
CPU time 6.49 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:48 PM PDT 24
Peak memory 201864 kb
Host smart-a1145286-dd1a-4075-bc90-af6689ded6ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1978943991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1978943991
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.1368415981
Short name T702
Test name
Test status
Simulation time 343865658 ps
CPU time 1.55 seconds
Started Aug 13 05:33:44 PM PDT 24
Finished Aug 13 05:33:45 PM PDT 24
Peak memory 201800 kb
Host smart-8be0338c-7241-4ba3-9442-bb0c01f5e9f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1368415981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1368415981
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2846106601
Short name T491
Test name
Test status
Simulation time 6015634254 ps
CPU time 10.35 seconds
Started Aug 13 05:33:38 PM PDT 24
Finished Aug 13 05:33:49 PM PDT 24
Peak memory 201952 kb
Host smart-cb1e8cc1-42bf-4499-85db-23846a878bd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846106601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2846106601
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.964906188
Short name T376
Test name
Test status
Simulation time 2088214839 ps
CPU time 11.76 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:53 PM PDT 24
Peak memory 201976 kb
Host smart-c446ffdd-fd49-4bde-8535-c852a1304199
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=964906188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.964906188
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1321227993
Short name T825
Test name
Test status
Simulation time 12798317 ps
CPU time 0.97 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 201980 kb
Host smart-991dff3c-4d22-412f-88a1-540d390acce8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321227993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1321227993
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2057656898
Short name T626
Test name
Test status
Simulation time 127309632 ps
CPU time 2.93 seconds
Started Aug 13 05:33:39 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 201964 kb
Host smart-cca086f4-7ab3-4e57-b5d8-5be148655e44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2057656898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2057656898
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3342407662
Short name T406
Test name
Test status
Simulation time 59431689 ps
CPU time 5.38 seconds
Started Aug 13 05:33:40 PM PDT 24
Finished Aug 13 05:33:45 PM PDT 24
Peak memory 201928 kb
Host smart-37fa55ab-1c19-4005-9ed9-bd5ebd608878
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3342407662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3342407662
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.4280377541
Short name T116
Test name
Test status
Simulation time 8590493347 ps
CPU time 74.35 seconds
Started Aug 13 05:33:39 PM PDT 24
Finished Aug 13 05:34:54 PM PDT 24
Peak memory 204192 kb
Host smart-a287a669-4111-4c2b-85d6-b18f3fd414b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4280377541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.4280377541
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1365632565
Short name T547
Test name
Test status
Simulation time 243077694 ps
CPU time 27.83 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 201920 kb
Host smart-270d1bc4-7db3-4996-a082-1801689fb55b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1365632565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1365632565
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2169607020
Short name T422
Test name
Test status
Simulation time 214796585 ps
CPU time 4.62 seconds
Started Aug 13 05:33:42 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201880 kb
Host smart-2332f67a-b004-4bd5-b750-8c7515ce2492
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2169607020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2169607020
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.4232853588
Short name T662
Test name
Test status
Simulation time 3026083536 ps
CPU time 13.92 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:34:04 PM PDT 24
Peak memory 202008 kb
Host smart-749a59f2-fa0f-4d6d-b78d-be492481084e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4232853588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.4232853588
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2830778357
Short name T101
Test name
Test status
Simulation time 92875062197 ps
CPU time 337.49 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:39:24 PM PDT 24
Peak memory 203060 kb
Host smart-85dfd176-068f-4c57-81d3-3cfba2fc7067
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2830778357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.2830778357
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1721039908
Short name T624
Test name
Test status
Simulation time 81734985 ps
CPU time 3.08 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:33:49 PM PDT 24
Peak memory 201876 kb
Host smart-b6579387-ac5e-4e06-94a3-241e742d4fdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1721039908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1721039908
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.98094669
Short name T454
Test name
Test status
Simulation time 128960718 ps
CPU time 1.95 seconds
Started Aug 13 05:33:44 PM PDT 24
Finished Aug 13 05:33:46 PM PDT 24
Peak memory 201968 kb
Host smart-0a67ec1d-68af-4268-99dc-c828d9d385be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98094669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.98094669
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.302217879
Short name T426
Test name
Test status
Simulation time 91596566 ps
CPU time 4.64 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:33:52 PM PDT 24
Peak memory 201912 kb
Host smart-5ba8ab28-da33-4165-8442-5989093efb39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=302217879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.302217879
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1849233797
Short name T521
Test name
Test status
Simulation time 1241947769 ps
CPU time 5.96 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:33:53 PM PDT 24
Peak memory 201924 kb
Host smart-1b2a27aa-96e8-4ac6-8fd0-5c9a8f157050
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849233797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1849233797
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.223448195
Short name T590
Test name
Test status
Simulation time 34455308433 ps
CPU time 183.11 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 201972 kb
Host smart-4e57b416-fb8c-4ba4-9351-3feb1598aaf1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=223448195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.223448195
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1400545103
Short name T403
Test name
Test status
Simulation time 121542351 ps
CPU time 2.75 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201912 kb
Host smart-45b2c49b-a0f0-4903-87e4-35d6a5652dc1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400545103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1400545103
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.1255318530
Short name T478
Test name
Test status
Simulation time 1076613266 ps
CPU time 10.61 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:34:00 PM PDT 24
Peak memory 201956 kb
Host smart-d3d43032-6c50-40ca-a612-24915a2f47b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1255318530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1255318530
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.2301191881
Short name T3
Test name
Test status
Simulation time 9050960 ps
CPU time 1.13 seconds
Started Aug 13 05:33:41 PM PDT 24
Finished Aug 13 05:33:42 PM PDT 24
Peak memory 201840 kb
Host smart-36d27be9-1a31-469f-bf28-5a6b69066ddb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301191881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2301191881
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3620100031
Short name T425
Test name
Test status
Simulation time 2014440521 ps
CPU time 8.97 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:33:59 PM PDT 24
Peak memory 201764 kb
Host smart-aa44011c-b160-481a-a94a-cb110b52cce1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620100031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3620100031
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2837493639
Short name T582
Test name
Test status
Simulation time 1241319987 ps
CPU time 6.31 seconds
Started Aug 13 05:33:44 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201932 kb
Host smart-20e0131d-a4dd-444b-9e38-8a271a5cc85d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2837493639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2837493639
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2514473485
Short name T599
Test name
Test status
Simulation time 7888689 ps
CPU time 1.04 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:33:48 PM PDT 24
Peak memory 201932 kb
Host smart-3920dd49-1275-453d-a16b-637530fd9de4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514473485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2514473485
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.4006456469
Short name T607
Test name
Test status
Simulation time 320469889 ps
CPU time 17.32 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:34:04 PM PDT 24
Peak memory 201872 kb
Host smart-a14863c5-0c83-43d9-8e16-2d4c6a12e5b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4006456469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4006456469
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2644835925
Short name T88
Test name
Test status
Simulation time 330338358 ps
CPU time 3.59 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:33:51 PM PDT 24
Peak memory 201844 kb
Host smart-8fa1a0c3-c720-45de-a8d8-378674266a3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2644835925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2644835925
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2431609508
Short name T128
Test name
Test status
Simulation time 4964322797 ps
CPU time 158.18 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 204916 kb
Host smart-a5fb5702-aaeb-4d0a-a634-43884a629f66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2431609508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.2431609508
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3136199791
Short name T222
Test name
Test status
Simulation time 1326747804 ps
CPU time 132.16 seconds
Started Aug 13 05:33:45 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 205992 kb
Host smart-d7edd4df-6e53-449e-bd0e-bdc991b94670
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3136199791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.3136199791
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1580413072
Short name T671
Test name
Test status
Simulation time 297002873 ps
CPU time 5.69 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 201948 kb
Host smart-4ef9bf71-a4c0-4463-9a0a-b76afa8d5652
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1580413072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1580413072
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.851603660
Short name T156
Test name
Test status
Simulation time 605755769 ps
CPU time 10.97 seconds
Started Aug 13 05:33:45 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 201956 kb
Host smart-55bc0e21-b2a5-4e55-bdbf-8de14fb5164b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=851603660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.851603660
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2741815933
Short name T98
Test name
Test status
Simulation time 31020256620 ps
CPU time 175.87 seconds
Started Aug 13 05:33:45 PM PDT 24
Finished Aug 13 05:36:41 PM PDT 24
Peak memory 202980 kb
Host smart-46f7a5eb-4fa5-4e4a-bfb9-0a1cbd505f6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2741815933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.2741815933
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2124430485
Short name T631
Test name
Test status
Simulation time 17216253 ps
CPU time 1.47 seconds
Started Aug 13 05:33:49 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201952 kb
Host smart-03e6e78d-f6e9-4d5f-8cab-5ef1ef2c7b18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2124430485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2124430485
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.2724906909
Short name T833
Test name
Test status
Simulation time 840439895 ps
CPU time 13.11 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:34:00 PM PDT 24
Peak memory 201952 kb
Host smart-817cbd3b-ea5a-495b-826f-dd92cc2fa7b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2724906909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2724906909
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.2151524848
Short name T397
Test name
Test status
Simulation time 1746276272 ps
CPU time 7.18 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:33:53 PM PDT 24
Peak memory 201852 kb
Host smart-130ca542-1ad5-4c94-949b-ecdd0ca49db7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2151524848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2151524848
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.779750791
Short name T830
Test name
Test status
Simulation time 104579127018 ps
CPU time 112.06 seconds
Started Aug 13 05:33:49 PM PDT 24
Finished Aug 13 05:35:41 PM PDT 24
Peak memory 201908 kb
Host smart-e536d0f4-2453-469e-9b5c-cdbdc78f369c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=779750791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.779750791
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1097832127
Short name T608
Test name
Test status
Simulation time 15031051295 ps
CPU time 109.46 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:35:37 PM PDT 24
Peak memory 202028 kb
Host smart-93ab35c6-3c09-40ac-9a08-b45478681a5f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1097832127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1097832127
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.44445259
Short name T870
Test name
Test status
Simulation time 72085005 ps
CPU time 9.46 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 201928 kb
Host smart-21bfb91c-1d77-4765-a3e6-67f59a808580
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44445259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.44445259
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.2976817447
Short name T699
Test name
Test status
Simulation time 711486687 ps
CPU time 4.45 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201872 kb
Host smart-ef8034c3-bd77-4da7-86a6-e5463de0fa35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2976817447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2976817447
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.1973789674
Short name T501
Test name
Test status
Simulation time 10707047 ps
CPU time 1.22 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201876 kb
Host smart-fec021f8-cea0-4499-822f-a732986267d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1973789674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1973789674
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3112567620
Short name T158
Test name
Test status
Simulation time 1322851936 ps
CPU time 6.98 seconds
Started Aug 13 05:33:44 PM PDT 24
Finished Aug 13 05:33:51 PM PDT 24
Peak memory 201828 kb
Host smart-bacbccd6-024b-4dd8-ad38-6a25ec2127f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112567620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3112567620
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3010702443
Short name T730
Test name
Test status
Simulation time 2328250529 ps
CPU time 7.06 seconds
Started Aug 13 05:33:49 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 202016 kb
Host smart-8a2db457-5a75-40cc-9845-2f780b56e0db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3010702443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3010702443
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1469818287
Short name T645
Test name
Test status
Simulation time 9456297 ps
CPU time 1.44 seconds
Started Aug 13 05:33:45 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201836 kb
Host smart-9c5c4db7-9af7-4033-a111-499c8c967436
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469818287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1469818287
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1707971662
Short name T286
Test name
Test status
Simulation time 18615484995 ps
CPU time 66.55 seconds
Started Aug 13 05:33:49 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 202972 kb
Host smart-c2dd18e6-5b17-40c3-8818-f6b8c786adcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1707971662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1707971662
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1179067145
Short name T857
Test name
Test status
Simulation time 4017911757 ps
CPU time 28.94 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:34:19 PM PDT 24
Peak memory 202028 kb
Host smart-aa22177a-989d-41b5-9201-d3bd97e7b8cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1179067145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1179067145
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.317036875
Short name T813
Test name
Test status
Simulation time 222272576 ps
CPU time 48.14 seconds
Started Aug 13 05:33:48 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 204320 kb
Host smart-138e0f9b-1000-4420-9401-6de1e2c09b47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=317036875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand
_reset.317036875
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3678679292
Short name T889
Test name
Test status
Simulation time 71001377 ps
CPU time 16.75 seconds
Started Aug 13 05:33:49 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 202820 kb
Host smart-0b26bc5a-51a4-46df-b762-c3dd02c23e13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3678679292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.3678679292
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1458976676
Short name T682
Test name
Test status
Simulation time 154110889 ps
CPU time 3.43 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201920 kb
Host smart-76f4ee16-8f0a-40df-aa71-cb7d84558acc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1458976676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1458976676
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.2092718454
Short name T780
Test name
Test status
Simulation time 39952353 ps
CPU time 3.43 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:33:53 PM PDT 24
Peak memory 201916 kb
Host smart-39633070-f145-4d9e-a099-51d2c011d326
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2092718454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2092718454
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2485812430
Short name T134
Test name
Test status
Simulation time 85613166627 ps
CPU time 214.89 seconds
Started Aug 13 05:33:55 PM PDT 24
Finished Aug 13 05:37:30 PM PDT 24
Peak memory 203428 kb
Host smart-c370c713-421a-451c-a811-ee764e2745b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2485812430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.2485812430
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2107442834
Short name T675
Test name
Test status
Simulation time 59309777 ps
CPU time 5.08 seconds
Started Aug 13 05:33:52 PM PDT 24
Finished Aug 13 05:33:57 PM PDT 24
Peak memory 201956 kb
Host smart-2e44310d-7385-44ec-81ec-e7c29b7c901e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2107442834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2107442834
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.230920203
Short name T879
Test name
Test status
Simulation time 1011060611 ps
CPU time 9.06 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:34:00 PM PDT 24
Peak memory 201920 kb
Host smart-677d1856-4d05-4dfe-b66a-cfe0ce54d3da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=230920203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.230920203
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1259331384
Short name T505
Test name
Test status
Simulation time 1421318202 ps
CPU time 13.8 seconds
Started Aug 13 05:33:47 PM PDT 24
Finished Aug 13 05:34:01 PM PDT 24
Peak memory 201908 kb
Host smart-9ef5417f-92a7-4043-b69f-e39e190807cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1259331384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1259331384
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2900671735
Short name T668
Test name
Test status
Simulation time 5614937046 ps
CPU time 16.18 seconds
Started Aug 13 05:33:53 PM PDT 24
Finished Aug 13 05:34:10 PM PDT 24
Peak memory 201904 kb
Host smart-3b28ec07-b2a6-4a79-891a-0c75e9037c0c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900671735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2900671735
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3257562573
Short name T210
Test name
Test status
Simulation time 69186992517 ps
CPU time 104.98 seconds
Started Aug 13 05:33:52 PM PDT 24
Finished Aug 13 05:35:37 PM PDT 24
Peak memory 201956 kb
Host smart-0cc14651-681f-4639-9a5f-fecee7d2624d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3257562573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3257562573
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1102506771
Short name T553
Test name
Test status
Simulation time 48633831 ps
CPU time 7.59 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:33:59 PM PDT 24
Peak memory 201924 kb
Host smart-1ecff030-56c8-44b2-b059-1642a444cf95
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102506771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1102506771
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.2085445761
Short name T289
Test name
Test status
Simulation time 4526439782 ps
CPU time 14.62 seconds
Started Aug 13 05:33:53 PM PDT 24
Finished Aug 13 05:34:08 PM PDT 24
Peak memory 201856 kb
Host smart-d33d3207-ba9b-4199-891a-696d7ae05838
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2085445761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2085445761
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.3797514288
Short name T854
Test name
Test status
Simulation time 328898677 ps
CPU time 1.43 seconds
Started Aug 13 05:33:49 PM PDT 24
Finished Aug 13 05:33:50 PM PDT 24
Peak memory 201836 kb
Host smart-99a86690-254e-42e0-9b86-e1c879bb3de0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3797514288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3797514288
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.661812957
Short name T443
Test name
Test status
Simulation time 12154400515 ps
CPU time 7.63 seconds
Started Aug 13 05:33:48 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 201916 kb
Host smart-6ed36542-34fa-48e5-af51-395bf17f7e71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=661812957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.661812957
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.381228635
Short name T359
Test name
Test status
Simulation time 2821510489 ps
CPU time 6.65 seconds
Started Aug 13 05:33:48 PM PDT 24
Finished Aug 13 05:33:55 PM PDT 24
Peak memory 202044 kb
Host smart-31be2f2d-5f3d-4ea6-8599-b4b708069267
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=381228635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.381228635
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2706892266
Short name T899
Test name
Test status
Simulation time 20661036 ps
CPU time 1.21 seconds
Started Aug 13 05:33:46 PM PDT 24
Finished Aug 13 05:33:47 PM PDT 24
Peak memory 201928 kb
Host smart-d906f364-fa6b-4548-a6ed-91595edaffb2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706892266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2706892266
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2392892643
Short name T411
Test name
Test status
Simulation time 18716256902 ps
CPU time 72.35 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:35:03 PM PDT 24
Peak memory 204260 kb
Host smart-5990ed68-5ff5-47dd-8402-504f4e6b0629
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2392892643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2392892643
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2637593218
Short name T598
Test name
Test status
Simulation time 4096049847 ps
CPU time 36.73 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 202036 kb
Host smart-dbc2e2f8-3d86-42fa-a24f-e317a9c0c962
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2637593218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2637593218
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1422172311
Short name T284
Test name
Test status
Simulation time 4336138398 ps
CPU time 80.67 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:35:11 PM PDT 24
Peak memory 205056 kb
Host smart-dd1ac356-3ae8-4c7b-b9d2-574a81e28a4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1422172311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.1422172311
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.436468075
Short name T11
Test name
Test status
Simulation time 1036640836 ps
CPU time 141.94 seconds
Started Aug 13 05:33:54 PM PDT 24
Finished Aug 13 05:36:16 PM PDT 24
Peak memory 208168 kb
Host smart-829c870e-c665-402d-8dc3-690368d39010
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=436468075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res
et_error.436468075
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1452546588
Short name T78
Test name
Test status
Simulation time 911101934 ps
CPU time 13.04 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 201960 kb
Host smart-c72ba04d-5490-4f5e-9ccc-b67c0750f423
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1452546588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1452546588
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2807766497
Short name T785
Test name
Test status
Simulation time 10776831 ps
CPU time 1.66 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 201956 kb
Host smart-fc8c80d4-a48b-4c34-b06e-556db4be9191
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2807766497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2807766497
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1367215111
Short name T776
Test name
Test status
Simulation time 202513929526 ps
CPU time 232.61 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:37:54 PM PDT 24
Peak memory 203056 kb
Host smart-ee50b54a-d163-417a-965d-bd2cdc0ab2ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1367215111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.1367215111
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1837037362
Short name T519
Test name
Test status
Simulation time 115607866 ps
CPU time 3.53 seconds
Started Aug 13 05:33:53 PM PDT 24
Finished Aug 13 05:33:57 PM PDT 24
Peak memory 201864 kb
Host smart-83fd015b-3392-41c9-bc22-bce163e42c2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1837037362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1837037362
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1869944038
Short name T322
Test name
Test status
Simulation time 27557084 ps
CPU time 2.36 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:33:54 PM PDT 24
Peak memory 201948 kb
Host smart-3d4abc38-ab67-405f-8ed2-8600ede1b382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1869944038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1869944038
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.115575169
Short name T523
Test name
Test status
Simulation time 1451768035 ps
CPU time 18.1 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 201896 kb
Host smart-02f18f1f-9715-47bb-a45f-78c01aaf513b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115575169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.115575169
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3196374460
Short name T576
Test name
Test status
Simulation time 14711447808 ps
CPU time 61.48 seconds
Started Aug 13 05:33:52 PM PDT 24
Finished Aug 13 05:34:54 PM PDT 24
Peak memory 201872 kb
Host smart-a876d531-a138-46b1-b0a7-0bedf5295abf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196374460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3196374460
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1923617073
Short name T729
Test name
Test status
Simulation time 10770744154 ps
CPU time 65.27 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 202012 kb
Host smart-61ebdf22-838c-4a3d-b76c-8295279bc39a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1923617073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1923617073
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3188831983
Short name T628
Test name
Test status
Simulation time 47139901 ps
CPU time 1.69 seconds
Started Aug 13 05:33:50 PM PDT 24
Finished Aug 13 05:33:52 PM PDT 24
Peak memory 201948 kb
Host smart-4c09e2b3-6cf3-451f-9144-c1636b244094
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188831983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3188831983
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3371583455
Short name T545
Test name
Test status
Simulation time 2277385031 ps
CPU time 12.03 seconds
Started Aug 13 05:33:54 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 202012 kb
Host smart-38bfdbba-6b85-4c11-adfb-785cc91b52af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3371583455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3371583455
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.2140724726
Short name T298
Test name
Test status
Simulation time 17588954 ps
CPU time 1.18 seconds
Started Aug 13 05:33:53 PM PDT 24
Finished Aug 13 05:33:55 PM PDT 24
Peak memory 201820 kb
Host smart-c5ab1769-9bf7-4601-9e96-652dd8146002
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2140724726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2140724726
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1377275152
Short name T273
Test name
Test status
Simulation time 1934162570 ps
CPU time 6.9 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:33:58 PM PDT 24
Peak memory 201892 kb
Host smart-83c708ea-b8d1-4c56-8d61-ef49d71e8393
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377275152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1377275152
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.4015587285
Short name T49
Test name
Test status
Simulation time 1614718616 ps
CPU time 9.92 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:34:01 PM PDT 24
Peak memory 201880 kb
Host smart-a4420e60-3c2e-48d3-ba28-066168177587
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4015587285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.4015587285
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.4019520710
Short name T516
Test name
Test status
Simulation time 8349783 ps
CPU time 1.16 seconds
Started Aug 13 05:33:53 PM PDT 24
Finished Aug 13 05:33:54 PM PDT 24
Peak memory 201956 kb
Host smart-5c230ac3-e676-4bfa-97e1-0a2e2cac0c80
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019520710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.4019520710
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.3816220138
Short name T94
Test name
Test status
Simulation time 3555410246 ps
CPU time 37.56 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:34:29 PM PDT 24
Peak memory 202028 kb
Host smart-7d50a46c-6a3a-4e75-b821-89e3896fa319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3816220138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3816220138
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3621072267
Short name T674
Test name
Test status
Simulation time 6003220848 ps
CPU time 55.04 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:34:46 PM PDT 24
Peak memory 202000 kb
Host smart-c54d6a5a-1c38-4754-8081-cc88b5821309
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3621072267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3621072267
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1512489605
Short name T377
Test name
Test status
Simulation time 95946069 ps
CPU time 19.26 seconds
Started Aug 13 05:33:51 PM PDT 24
Finished Aug 13 05:34:10 PM PDT 24
Peak memory 203980 kb
Host smart-a77af8e8-76a9-40fe-8dfc-42271f525a0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1512489605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran
d_reset.1512489605
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2316795220
Short name T525
Test name
Test status
Simulation time 432460668 ps
CPU time 7.6 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 201964 kb
Host smart-67e7e51a-8d5d-460e-baea-58d0ba35f2e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2316795220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2316795220
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2485726445
Short name T140
Test name
Test status
Simulation time 858002869 ps
CPU time 14.85 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:13 PM PDT 24
Peak memory 201956 kb
Host smart-11cc7de6-2cd3-42e3-9816-4039f19a5f84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2485726445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2485726445
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.203603244
Short name T649
Test name
Test status
Simulation time 17138009505 ps
CPU time 82.09 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 201932 kb
Host smart-f6b3e604-0658-4861-b779-3898a0be9011
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=203603244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.203603244
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1606761522
Short name T792
Test name
Test status
Simulation time 166180986 ps
CPU time 1.99 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:01 PM PDT 24
Peak memory 201928 kb
Host smart-e3918f41-fb21-4d99-ac91-e33ae2d735a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1606761522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1606761522
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.3295088091
Short name T818
Test name
Test status
Simulation time 368037417 ps
CPU time 2.86 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:02 PM PDT 24
Peak memory 201956 kb
Host smart-9063526e-d71a-48b5-8a8f-61a36cf7cb60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3295088091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3295088091
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.945009442
Short name T295
Test name
Test status
Simulation time 208618279 ps
CPU time 3.97 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:34:04 PM PDT 24
Peak memory 201868 kb
Host smart-66b020e5-f371-4a13-89b1-33c8490a3540
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=945009442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.945009442
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.958736176
Short name T749
Test name
Test status
Simulation time 5449706374 ps
CPU time 23.07 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:22 PM PDT 24
Peak memory 201988 kb
Host smart-f8685096-bf08-43a9-a798-dbb1912100d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=958736176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.958736176
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.793487627
Short name T147
Test name
Test status
Simulation time 35701483466 ps
CPU time 167.49 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 202012 kb
Host smart-ec4d3d95-9494-4f58-9109-20fa5d6a1499
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=793487627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.793487627
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3187115621
Short name T130
Test name
Test status
Simulation time 35990447 ps
CPU time 3.03 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:02 PM PDT 24
Peak memory 201968 kb
Host smart-8d16ccce-5860-46f9-b248-ffdb45f466a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187115621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3187115621
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.2739708671
Short name T51
Test name
Test status
Simulation time 720739773 ps
CPU time 9.75 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:34:11 PM PDT 24
Peak memory 201884 kb
Host smart-fbf9e3f9-8190-4f99-a9b1-b3591cf4e953
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739708671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2739708671
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.2015164514
Short name T685
Test name
Test status
Simulation time 77113584 ps
CPU time 1.62 seconds
Started Aug 13 05:33:56 PM PDT 24
Finished Aug 13 05:33:58 PM PDT 24
Peak memory 201792 kb
Host smart-c95e9250-1ba9-4c7b-8df5-c4336dc3d668
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2015164514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2015164514
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.688778841
Short name T456
Test name
Test status
Simulation time 1960202784 ps
CPU time 10.05 seconds
Started Aug 13 05:34:02 PM PDT 24
Finished Aug 13 05:34:12 PM PDT 24
Peak memory 201916 kb
Host smart-c9ec1e15-575a-4369-8595-7691d545ae78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=688778841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.688778841
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1703524186
Short name T440
Test name
Test status
Simulation time 1242953254 ps
CPU time 9.7 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:08 PM PDT 24
Peak memory 201968 kb
Host smart-9876dcfb-cf68-4cc1-87c7-11065214d0f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1703524186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1703524186
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.4016614360
Short name T524
Test name
Test status
Simulation time 21349591 ps
CPU time 1.11 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:01 PM PDT 24
Peak memory 201984 kb
Host smart-4e10d455-b596-46ad-9abc-4fc276bd3279
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016614360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.4016614360
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1663855081
Short name T895
Test name
Test status
Simulation time 3382537117 ps
CPU time 50.88 seconds
Started Aug 13 05:34:02 PM PDT 24
Finished Aug 13 05:34:53 PM PDT 24
Peak memory 202956 kb
Host smart-6f854068-51b2-4f23-a177-fb1db996c74a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663855081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1663855081
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1231900839
Short name T169
Test name
Test status
Simulation time 172202687 ps
CPU time 3.65 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:02 PM PDT 24
Peak memory 201884 kb
Host smart-406d74b4-2077-4131-bbd7-58543d9cd809
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1231900839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1231900839
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2207109753
Short name T554
Test name
Test status
Simulation time 1746526366 ps
CPU time 76.19 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 204128 kb
Host smart-af9ef15c-c376-48ce-afc1-4c9342c43c41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2207109753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.2207109753
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3916045246
Short name T773
Test name
Test status
Simulation time 108530631 ps
CPU time 6.8 seconds
Started Aug 13 05:34:02 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 201968 kb
Host smart-06a1c695-40af-414d-b04d-4dcc92f8d484
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3916045246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3916045246
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4245409707
Short name T337
Test name
Test status
Simulation time 303906081 ps
CPU time 9.41 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 201872 kb
Host smart-b249d449-8159-469d-ad8e-7b55c66772b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4245409707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4245409707
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.668654887
Short name T177
Test name
Test status
Simulation time 15086333 ps
CPU time 1.71 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 201860 kb
Host smart-8e338ffe-1df2-460c-b7ce-a4c21bb09b56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=668654887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.668654887
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.3384938950
Short name T577
Test name
Test status
Simulation time 66527797 ps
CPU time 1.81 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:00 PM PDT 24
Peak memory 201964 kb
Host smart-9470c5c2-754b-432c-b416-ed25a261ee50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3384938950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3384938950
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3622371053
Short name T264
Test name
Test status
Simulation time 98965154 ps
CPU time 9.2 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:07 PM PDT 24
Peak memory 201856 kb
Host smart-e3f41830-7a03-4cfe-85bb-70122afb490b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3622371053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3622371053
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3581605094
Short name T753
Test name
Test status
Simulation time 19744667058 ps
CPU time 49.36 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201888 kb
Host smart-6e06b6b1-a15f-446f-b53e-e8ddc1cbb459
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581605094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3581605094
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2792100139
Short name T427
Test name
Test status
Simulation time 6386521337 ps
CPU time 38.28 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 202040 kb
Host smart-cecd9841-4879-4748-a13a-052cee983713
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2792100139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2792100139
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.943075922
Short name T752
Test name
Test status
Simulation time 8290533 ps
CPU time 1.27 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:33:59 PM PDT 24
Peak memory 201956 kb
Host smart-9b99b168-d9db-4882-92ed-d65da0acd78c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943075922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.943075922
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.3922095200
Short name T48
Test name
Test status
Simulation time 1283006827 ps
CPU time 4.5 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 201952 kb
Host smart-c904cc10-938f-4826-8419-020da16ac8d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3922095200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3922095200
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.172537901
Short name T696
Test name
Test status
Simulation time 18827062 ps
CPU time 1.08 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:34:01 PM PDT 24
Peak memory 201852 kb
Host smart-9a1cf85f-f19b-4ba7-83f5-0e370aaa5c45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=172537901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.172537901
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.348465708
Short name T446
Test name
Test status
Simulation time 3880931404 ps
CPU time 12.11 seconds
Started Aug 13 05:33:58 PM PDT 24
Finished Aug 13 05:34:10 PM PDT 24
Peak memory 201944 kb
Host smart-35bb2328-fdc2-41b4-b7db-be8034b1adf7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=348465708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.348465708
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.213871600
Short name T541
Test name
Test status
Simulation time 2420319558 ps
CPU time 7.07 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 201924 kb
Host smart-d646d9dd-fe86-4a06-a21b-64c198b0af52
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=213871600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.213871600
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4277820505
Short name T76
Test name
Test status
Simulation time 14432684 ps
CPU time 1.25 seconds
Started Aug 13 05:33:59 PM PDT 24
Finished Aug 13 05:34:00 PM PDT 24
Peak memory 201988 kb
Host smart-c3583c63-e460-478b-bd14-b64dbfe81472
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277820505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4277820505
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2586013388
Short name T611
Test name
Test status
Simulation time 5693929662 ps
CPU time 67 seconds
Started Aug 13 05:34:00 PM PDT 24
Finished Aug 13 05:35:07 PM PDT 24
Peak memory 204360 kb
Host smart-c1fee870-d57a-401f-9a18-07598ac637d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2586013388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2586013388
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.727286693
Short name T433
Test name
Test status
Simulation time 62134479 ps
CPU time 8.74 seconds
Started Aug 13 05:34:04 PM PDT 24
Finished Aug 13 05:34:13 PM PDT 24
Peak memory 201820 kb
Host smart-5e14c23e-357f-4b47-a9ab-2a3201e7f0e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=727286693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.727286693
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2420362836
Short name T775
Test name
Test status
Simulation time 1064807306 ps
CPU time 181.87 seconds
Started Aug 13 05:34:04 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 204772 kb
Host smart-83490ba8-ba9b-4be3-8e54-793ad88c3acc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2420362836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.2420362836
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2525104364
Short name T828
Test name
Test status
Simulation time 1116058141 ps
CPU time 72.79 seconds
Started Aug 13 05:34:09 PM PDT 24
Finished Aug 13 05:35:22 PM PDT 24
Peak memory 204948 kb
Host smart-38b97e44-60fc-410f-95c7-56118b0f4792
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2525104364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.2525104364
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2813988821
Short name T27
Test name
Test status
Simulation time 1010126334 ps
CPU time 5.61 seconds
Started Aug 13 05:34:01 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 201948 kb
Host smart-7bf89f1b-0152-43e1-b7f4-dcd2de630250
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2813988821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2813988821
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.796814798
Short name T798
Test name
Test status
Simulation time 45811388 ps
CPU time 7.93 seconds
Started Aug 13 05:34:08 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 201956 kb
Host smart-3be2f683-1265-4fe7-8cf8-5d1efa8f5d47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=796814798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.796814798
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1073854077
Short name T205
Test name
Test status
Simulation time 32571223357 ps
CPU time 115.91 seconds
Started Aug 13 05:34:08 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 203060 kb
Host smart-bbed9e85-4e76-46f2-8602-31fe6c5b0af8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1073854077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.1073854077
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.959607697
Short name T581
Test name
Test status
Simulation time 526403830 ps
CPU time 10.26 seconds
Started Aug 13 05:34:05 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 201932 kb
Host smart-87d07b58-9e20-4bef-a029-855e38e99e19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=959607697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.959607697
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.96620561
Short name T835
Test name
Test status
Simulation time 640810322 ps
CPU time 10.66 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:17 PM PDT 24
Peak memory 201924 kb
Host smart-93ddb734-980c-43c2-8957-23b225d963a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96620561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.96620561
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.413142590
Short name T163
Test name
Test status
Simulation time 317460209 ps
CPU time 5.15 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:13 PM PDT 24
Peak memory 201788 kb
Host smart-45a30cd7-7d5f-476a-9a81-b1a107c4eb6f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=413142590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.413142590
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1297425093
Short name T371
Test name
Test status
Simulation time 46884644608 ps
CPU time 92.57 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:35:40 PM PDT 24
Peak memory 201884 kb
Host smart-fbefcaf4-2762-482d-9962-cb1c78fd0073
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297425093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1297425093
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.163833363
Short name T339
Test name
Test status
Simulation time 13307993271 ps
CPU time 42.59 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201996 kb
Host smart-ccb2ec51-e2b6-4c79-99a7-43c411b5818c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=163833363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.163833363
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3977615676
Short name T368
Test name
Test status
Simulation time 185765435 ps
CPU time 8.21 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 201872 kb
Host smart-3c994fce-27e0-4f86-a5e0-08dd12ab936d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977615676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3977615676
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.277638345
Short name T314
Test name
Test status
Simulation time 755877186 ps
CPU time 9.05 seconds
Started Aug 13 05:34:08 PM PDT 24
Finished Aug 13 05:34:17 PM PDT 24
Peak memory 201804 kb
Host smart-1bc5adce-7af3-465e-9c3f-ad5a5680907e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277638345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.277638345
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.4248712651
Short name T713
Test name
Test status
Simulation time 11817933 ps
CPU time 1.19 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 201928 kb
Host smart-a67ed33d-bf97-40f1-8816-c07b1d9cb560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4248712651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.4248712651
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3538749004
Short name T791
Test name
Test status
Simulation time 2485996355 ps
CPU time 6.83 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:14 PM PDT 24
Peak memory 201884 kb
Host smart-da904822-fdd1-4b53-b646-23c327bda971
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538749004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3538749004
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3793400114
Short name T370
Test name
Test status
Simulation time 8066372241 ps
CPU time 7.54 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:14 PM PDT 24
Peak memory 201988 kb
Host smart-58753b2c-d8b7-4069-b5ce-764ebfc62244
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3793400114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3793400114
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1099758347
Short name T379
Test name
Test status
Simulation time 13992160 ps
CPU time 1.12 seconds
Started Aug 13 05:34:05 PM PDT 24
Finished Aug 13 05:34:06 PM PDT 24
Peak memory 201928 kb
Host smart-2a3ae410-f027-409b-a98c-4119d0b38bf3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099758347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1099758347
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.1861609865
Short name T687
Test name
Test status
Simulation time 2648755289 ps
CPU time 29.5 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 203040 kb
Host smart-591b00f0-2699-4260-842b-b4c14dae3389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1861609865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1861609865
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.75741153
Short name T707
Test name
Test status
Simulation time 5585565404 ps
CPU time 46.66 seconds
Started Aug 13 05:34:05 PM PDT 24
Finished Aug 13 05:34:52 PM PDT 24
Peak memory 201920 kb
Host smart-cebd2d87-36ef-42cb-912a-654df8c6b454
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75741153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.75741153
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.4043643072
Short name T755
Test name
Test status
Simulation time 351010102 ps
CPU time 48.85 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 203980 kb
Host smart-b1cfa23b-aab8-412c-ba60-16e292be16f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4043643072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran
d_reset.4043643072
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.898459691
Short name T568
Test name
Test status
Simulation time 7553735544 ps
CPU time 33.15 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:39 PM PDT 24
Peak memory 203276 kb
Host smart-30ce715c-6465-4715-9276-bab95b26f12d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=898459691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res
et_error.898459691
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.200509297
Short name T739
Test name
Test status
Simulation time 990997491 ps
CPU time 10.9 seconds
Started Aug 13 05:34:05 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 201956 kb
Host smart-8de712fa-09e3-4873-a445-c4eb9080b628
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=200509297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.200509297
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.653556601
Short name T679
Test name
Test status
Simulation time 1304592752 ps
CPU time 18.21 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:25 PM PDT 24
Peak memory 201872 kb
Host smart-fe7c39be-a463-4004-88e2-41be11c82753
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=653556601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.653556601
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.930104085
Short name T853
Test name
Test status
Simulation time 20790805778 ps
CPU time 116.08 seconds
Started Aug 13 05:34:05 PM PDT 24
Finished Aug 13 05:36:01 PM PDT 24
Peak memory 203112 kb
Host smart-3b48d079-5e58-4432-995d-873db5b84a7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=930104085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo
w_rsp.930104085
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1648571062
Short name T459
Test name
Test status
Simulation time 51817442 ps
CPU time 5.49 seconds
Started Aug 13 05:34:18 PM PDT 24
Finished Aug 13 05:34:23 PM PDT 24
Peak memory 201916 kb
Host smart-577c9bec-a17d-4ec2-abe9-e6236f3bc486
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1648571062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1648571062
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.3740987196
Short name T63
Test name
Test status
Simulation time 2256967503 ps
CPU time 11.49 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:18 PM PDT 24
Peak memory 202008 kb
Host smart-8cef45b2-71a4-474d-92be-5cfae8e08188
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3740987196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3740987196
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.4280126410
Short name T595
Test name
Test status
Simulation time 870470165 ps
CPU time 14.36 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201872 kb
Host smart-34ce9dc7-4309-40f2-ae04-e3b46d4a82cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4280126410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4280126410
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.405796919
Short name T124
Test name
Test status
Simulation time 22809681663 ps
CPU time 76.52 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 201904 kb
Host smart-a6aed7fa-a600-43fe-9e3b-ca3f464fb452
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=405796919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.405796919
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2465727643
Short name T734
Test name
Test status
Simulation time 5735414083 ps
CPU time 31.43 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:39 PM PDT 24
Peak memory 201944 kb
Host smart-35bffa3d-88cc-4d35-9712-e32b9204f6aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2465727643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2465727643
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3053102164
Short name T193
Test name
Test status
Simulation time 68689951 ps
CPU time 6.81 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:13 PM PDT 24
Peak memory 201872 kb
Host smart-ea974725-6368-49a5-b595-d7abbef11cd5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053102164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3053102164
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.1008190905
Short name T452
Test name
Test status
Simulation time 2742014776 ps
CPU time 8.73 seconds
Started Aug 13 05:34:06 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 201976 kb
Host smart-efb383cc-dcb5-43e7-8507-e6206ebb0645
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1008190905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1008190905
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.849206186
Short name T839
Test name
Test status
Simulation time 19540366 ps
CPU time 1.09 seconds
Started Aug 13 05:34:05 PM PDT 24
Finished Aug 13 05:34:07 PM PDT 24
Peak memory 201916 kb
Host smart-6124fbc4-bf6c-4023-a200-dcb30d7e1174
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=849206186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.849206186
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2701602286
Short name T176
Test name
Test status
Simulation time 5131235137 ps
CPU time 8.56 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 201988 kb
Host smart-21bf1524-98ba-47a3-9c9f-9763740d2671
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701602286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2701602286
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3738926012
Short name T352
Test name
Test status
Simulation time 1606338245 ps
CPU time 8.41 seconds
Started Aug 13 05:34:08 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 201936 kb
Host smart-90358c8f-3580-493d-a81e-82c4019b90af
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3738926012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3738926012
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3463078267
Short name T92
Test name
Test status
Simulation time 8953489 ps
CPU time 1.05 seconds
Started Aug 13 05:34:07 PM PDT 24
Finished Aug 13 05:34:08 PM PDT 24
Peak memory 201796 kb
Host smart-b85ac267-3ce1-4472-849a-6e39a3ecd0e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463078267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3463078267
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1065685579
Short name T71
Test name
Test status
Simulation time 16121362721 ps
CPU time 82.88 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:35:38 PM PDT 24
Peak memory 204216 kb
Host smart-fa65d470-7cbb-42d7-ad32-facb2b9de729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1065685579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1065685579
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3307058331
Short name T171
Test name
Test status
Simulation time 287992658 ps
CPU time 32.51 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201936 kb
Host smart-83a45289-2a92-47a9-84c7-ecf2b0135ed6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3307058331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3307058331
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3745891923
Short name T102
Test name
Test status
Simulation time 4197722970 ps
CPU time 86.48 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:35:44 PM PDT 24
Peak memory 204332 kb
Host smart-43d5ace2-685c-47d0-ad30-8a48ae3f98f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3745891923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.3745891923
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4223639554
Short name T225
Test name
Test status
Simulation time 420795646 ps
CPU time 27.66 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 203088 kb
Host smart-7021c987-cd60-4f5b-9187-f4c20b575f21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4223639554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.4223639554
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.381264207
Short name T522
Test name
Test status
Simulation time 586021946 ps
CPU time 4 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201872 kb
Host smart-5e2df70b-15fb-47bc-8099-383da491971d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=381264207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.381264207
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2372835400
Short name T215
Test name
Test status
Simulation time 1923797471 ps
CPU time 22.15 seconds
Started Aug 13 05:34:13 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 201820 kb
Host smart-e8168fbf-8ba4-405c-afcd-4fa78da37340
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2372835400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2372835400
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3816868393
Short name T201
Test name
Test status
Simulation time 171308257223 ps
CPU time 141.29 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:36:36 PM PDT 24
Peak memory 203060 kb
Host smart-1b256d40-e81d-4442-8495-d3b1720946f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3816868393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.3816868393
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1878985960
Short name T469
Test name
Test status
Simulation time 46152756 ps
CPU time 5.14 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:20 PM PDT 24
Peak memory 201952 kb
Host smart-0bf6b8c8-4b74-474c-b443-88a41f7a2479
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1878985960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1878985960
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.1690785115
Short name T644
Test name
Test status
Simulation time 105208813 ps
CPU time 1.56 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 201892 kb
Host smart-dd33f27f-05a4-40ad-8df0-304f8ef90884
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690785115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1690785115
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.818825233
Short name T442
Test name
Test status
Simulation time 18605697018 ps
CPU time 41.42 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:59 PM PDT 24
Peak memory 201864 kb
Host smart-89af8dd3-79e7-49d2-ac1d-591ad8db0805
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=818825233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.818825233
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3178751632
Short name T351
Test name
Test status
Simulation time 8059256798 ps
CPU time 55.22 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:35:10 PM PDT 24
Peak memory 201876 kb
Host smart-c7fff875-a861-4443-9f3b-71781450be8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3178751632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3178751632
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3240614079
Short name T574
Test name
Test status
Simulation time 45026558 ps
CPU time 5.21 seconds
Started Aug 13 05:34:18 PM PDT 24
Finished Aug 13 05:34:23 PM PDT 24
Peak memory 201916 kb
Host smart-6be0ce0d-5071-44e2-afb9-edafaa4ca950
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240614079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3240614079
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1360183104
Short name T476
Test name
Test status
Simulation time 1532907076 ps
CPU time 10.62 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:34:26 PM PDT 24
Peak memory 201952 kb
Host smart-ff7c75fc-c805-4786-9c62-8fdf920359dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1360183104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1360183104
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.4252589150
Short name T254
Test name
Test status
Simulation time 55603921 ps
CPU time 1.52 seconds
Started Aug 13 05:34:13 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 201884 kb
Host smart-b0add6c6-6356-4518-a528-6c8df587c0f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4252589150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4252589150
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2001439012
Short name T444
Test name
Test status
Simulation time 4031097022 ps
CPU time 8.29 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:26 PM PDT 24
Peak memory 201888 kb
Host smart-d4fd9f90-3330-4fc9-8881-c33e7d2dbc57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001439012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2001439012
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4110321736
Short name T390
Test name
Test status
Simulation time 6178159243 ps
CPU time 10.98 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:28 PM PDT 24
Peak memory 201940 kb
Host smart-16f9c74a-d9b6-4ff9-86d5-29779949c1e9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4110321736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4110321736
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.657430237
Short name T865
Test name
Test status
Simulation time 10712266 ps
CPU time 1.2 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:34:17 PM PDT 24
Peak memory 201884 kb
Host smart-50f25bd7-0230-4782-938f-792272e7fa7d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657430237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.657430237
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3219536054
Short name T137
Test name
Test status
Simulation time 4676521535 ps
CPU time 85.41 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:35:42 PM PDT 24
Peak memory 203028 kb
Host smart-7d2d53b1-6666-4740-b6f6-6df8ff4c2b9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3219536054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3219536054
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3463121364
Short name T556
Test name
Test status
Simulation time 110302056 ps
CPU time 7.16 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201976 kb
Host smart-e4f744f4-1e04-43b1-91a2-4eca094ae24c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3463121364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3463121364
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1781396476
Short name T262
Test name
Test status
Simulation time 2362143103 ps
CPU time 242.23 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:38:19 PM PDT 24
Peak memory 208780 kb
Host smart-3c496951-19cb-4c8b-a01f-31b80e863d3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1781396476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1781396476
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1027734524
Short name T9
Test name
Test status
Simulation time 9766423843 ps
CPU time 107.1 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204840 kb
Host smart-0f9e2b62-b353-46b9-b1b7-3524a444d340
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1027734524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1027734524
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.1086363136
Short name T87
Test name
Test status
Simulation time 292443681 ps
CPU time 5.93 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:20 PM PDT 24
Peak memory 201912 kb
Host smart-9ec1bdac-e3d2-4ff7-b1e7-8707b8412567
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1086363136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1086363136
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1525132276
Short name T178
Test name
Test status
Simulation time 1658107048 ps
CPU time 13.54 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:14 PM PDT 24
Peak memory 201956 kb
Host smart-be32cc17-853d-4dc6-a4ae-a2bbf318fb88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1525132276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1525132276
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3404443987
Short name T204
Test name
Test status
Simulation time 3685985793 ps
CPU time 17.52 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:33:06 PM PDT 24
Peak memory 202016 kb
Host smart-ad24496a-c248-467d-a3d9-6fda8ba7415e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3404443987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.3404443987
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1215504471
Short name T658
Test name
Test status
Simulation time 9168612 ps
CPU time 1.16 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:32:54 PM PDT 24
Peak memory 201916 kb
Host smart-3a8b725e-6ee8-46da-b8fd-a722e344093b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1215504471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1215504471
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.2995379341
Short name T640
Test name
Test status
Simulation time 51161760 ps
CPU time 5.47 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:32:54 PM PDT 24
Peak memory 201920 kb
Host smart-922c2913-30e5-4992-9ba7-d803889e17df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2995379341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2995379341
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.3077894403
Short name T419
Test name
Test status
Simulation time 74036571 ps
CPU time 6.44 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201908 kb
Host smart-c48314c2-638a-4015-a95e-5091bcdf0ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3077894403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3077894403
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2778908032
Short name T372
Test name
Test status
Simulation time 71582799917 ps
CPU time 65.44 seconds
Started Aug 13 05:32:53 PM PDT 24
Finished Aug 13 05:33:59 PM PDT 24
Peak memory 201976 kb
Host smart-cfd20c05-439a-4be3-9953-2ed1852b0969
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778908032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2778908032
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4055568273
Short name T804
Test name
Test status
Simulation time 97626189460 ps
CPU time 81.32 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:34:13 PM PDT 24
Peak memory 202012 kb
Host smart-bbe9d209-0fc5-475c-8b78-da5d82fc6a2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4055568273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4055568273
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.188340162
Short name T890
Test name
Test status
Simulation time 56137842 ps
CPU time 6.44 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:32:57 PM PDT 24
Peak memory 201884 kb
Host smart-88179915-35b1-480d-8879-0c207d8da688
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188340162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.188340162
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.1698154020
Short name T82
Test name
Test status
Simulation time 464970933 ps
CPU time 6.42 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:32:58 PM PDT 24
Peak memory 201932 kb
Host smart-b298ef4d-b85d-4ab7-aa91-c5374c7dc6e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698154020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1698154020
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.77591361
Short name T398
Test name
Test status
Simulation time 12148278 ps
CPU time 1.58 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:32:52 PM PDT 24
Peak memory 201836 kb
Host smart-a853f6cc-7eeb-477a-8b63-783876dd41d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77591361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.77591361
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3333923767
Short name T881
Test name
Test status
Simulation time 1892585360 ps
CPU time 8.52 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:57 PM PDT 24
Peak memory 201924 kb
Host smart-39fdb9eb-9323-4f1b-a3e1-35e1758cd6c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333923767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3333923767
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1655805362
Short name T832
Test name
Test status
Simulation time 1258482135 ps
CPU time 8.34 seconds
Started Aug 13 05:32:55 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201972 kb
Host smart-1c051153-5896-41b5-b840-bf34908049ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1655805362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1655805362
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1970143061
Short name T445
Test name
Test status
Simulation time 10878324 ps
CPU time 1.16 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:32:52 PM PDT 24
Peak memory 201968 kb
Host smart-fa8d787b-b81b-49f3-a29e-f814977c2c26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970143061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1970143061
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2159917918
Short name T148
Test name
Test status
Simulation time 5962373585 ps
CPU time 100.18 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 203000 kb
Host smart-7ab149b1-f4bc-47f1-a894-f213e7a64584
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2159917918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2159917918
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2424725374
Short name T218
Test name
Test status
Simulation time 7131493427 ps
CPU time 81.68 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 203040 kb
Host smart-69d27294-cb6c-4f53-a001-f348217613b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2424725374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2424725374
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2438152305
Short name T623
Test name
Test status
Simulation time 4462249228 ps
CPU time 103.02 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:34:42 PM PDT 24
Peak memory 204732 kb
Host smart-8c2306cb-05fd-417f-8764-4ca818fb2a86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2438152305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.2438152305
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1209642042
Short name T887
Test name
Test status
Simulation time 549496856 ps
CPU time 76.5 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:34:09 PM PDT 24
Peak memory 206476 kb
Host smart-2d141b59-41be-4280-91f3-9ae01fbbeeda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1209642042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1209642042
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3847689182
Short name T718
Test name
Test status
Simulation time 113735605 ps
CPU time 3.24 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201956 kb
Host smart-f70885c2-26e8-4791-bb97-29093a0ffddc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3847689182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3847689182
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2358475486
Short name T85
Test name
Test status
Simulation time 3075575304 ps
CPU time 19.59 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 201932 kb
Host smart-1f85c2ba-7890-492a-bd1f-fd51eb367176
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2358475486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2358475486
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3900099099
Short name T750
Test name
Test status
Simulation time 15045851438 ps
CPU time 20.58 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 202008 kb
Host smart-a24fdc4b-55f0-4e52-b788-18542c3b46c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3900099099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.3900099099
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1981479094
Short name T787
Test name
Test status
Simulation time 686340678 ps
CPU time 8.45 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:23 PM PDT 24
Peak memory 201992 kb
Host smart-a2df5235-93c6-4d7d-8a50-21142db8a1aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1981479094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1981479094
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.298451585
Short name T779
Test name
Test status
Simulation time 732024935 ps
CPU time 11.04 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:26 PM PDT 24
Peak memory 201960 kb
Host smart-76a250f7-4352-427e-8505-78058a3684e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=298451585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.298451585
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.1656185060
Short name T781
Test name
Test status
Simulation time 71019509 ps
CPU time 10.68 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:25 PM PDT 24
Peak memory 201844 kb
Host smart-b3b3a8fe-4453-4ffa-9500-0a4679470492
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1656185060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1656185060
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3356629129
Short name T355
Test name
Test status
Simulation time 9019114339 ps
CPU time 39.1 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 201836 kb
Host smart-64190c8c-4627-4ee9-817e-f07558e6faa3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356629129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3356629129
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1144462418
Short name T414
Test name
Test status
Simulation time 53239342432 ps
CPU time 91.07 seconds
Started Aug 13 05:34:18 PM PDT 24
Finished Aug 13 05:35:49 PM PDT 24
Peak memory 201976 kb
Host smart-5d6035ad-883a-48e7-aa8e-1fc4f2f9ed28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1144462418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1144462418
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.370449254
Short name T635
Test name
Test status
Simulation time 28354064 ps
CPU time 3.26 seconds
Started Aug 13 05:34:18 PM PDT 24
Finished Aug 13 05:34:22 PM PDT 24
Peak memory 201916 kb
Host smart-0d7afd41-3041-458c-82c5-0fb97683bad8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370449254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.370449254
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.4150229113
Short name T341
Test name
Test status
Simulation time 156778828 ps
CPU time 3.57 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201880 kb
Host smart-a6fd2507-88b5-46b9-877f-c62711df75c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4150229113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4150229113
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.100598195
Short name T253
Test name
Test status
Simulation time 206136892 ps
CPU time 1.41 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 201836 kb
Host smart-c8f069f3-1010-4d5b-ab44-fa1822faf7df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100598195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.100598195
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2350956032
Short name T432
Test name
Test status
Simulation time 4318224597 ps
CPU time 13.66 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:34:29 PM PDT 24
Peak memory 201892 kb
Host smart-8062cc21-0f69-464c-b837-3895f7b305a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350956032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2350956032
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3426302042
Short name T309
Test name
Test status
Simulation time 7395852851 ps
CPU time 12.86 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:27 PM PDT 24
Peak memory 201984 kb
Host smart-9ff4dc4a-23b4-4283-9c49-176518c7f8a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3426302042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3426302042
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2960507620
Short name T892
Test name
Test status
Simulation time 9564823 ps
CPU time 1.24 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:18 PM PDT 24
Peak memory 201960 kb
Host smart-4e0f651a-8f4b-48ae-9c8a-1543669cb9a3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960507620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2960507620
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2808546214
Short name T806
Test name
Test status
Simulation time 5925432413 ps
CPU time 109.94 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:36:04 PM PDT 24
Peak memory 204068 kb
Host smart-db2c384d-6d18-415e-8e53-1435ae7ae21a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2808546214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2808546214
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.14514629
Short name T646
Test name
Test status
Simulation time 1787685079 ps
CPU time 30.34 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:47 PM PDT 24
Peak memory 201952 kb
Host smart-be30dfe6-bad5-4eaa-b966-f355df44f736
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14514629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.14514629
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2353817163
Short name T845
Test name
Test status
Simulation time 1247895154 ps
CPU time 145.89 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:36:43 PM PDT 24
Peak memory 206832 kb
Host smart-e15941c5-f047-4ebb-a3f8-ee8d3728657e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2353817163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.2353817163
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2913190720
Short name T866
Test name
Test status
Simulation time 5692089140 ps
CPU time 80.22 seconds
Started Aug 13 05:34:16 PM PDT 24
Finished Aug 13 05:35:36 PM PDT 24
Peak memory 206164 kb
Host smart-1e76c509-8bd3-4594-a0ae-1703293f8828
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2913190720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.2913190720
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.897272753
Short name T34
Test name
Test status
Simulation time 1116558026 ps
CPU time 7.52 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:23 PM PDT 24
Peak memory 201916 kb
Host smart-a4818d0e-d9c7-4fda-b652-70f645f0a07f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=897272753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.897272753
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2491267552
Short name T681
Test name
Test status
Simulation time 773491714 ps
CPU time 16.32 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 201960 kb
Host smart-a9a7b581-46bb-4138-9da6-109fcb55ff22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2491267552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2491267552
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.236947282
Short name T393
Test name
Test status
Simulation time 813738507 ps
CPU time 10.44 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:34 PM PDT 24
Peak memory 201952 kb
Host smart-af9023a7-5fd3-4f3a-a4bd-646bc41558b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=236947282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.236947282
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.1725337904
Short name T511
Test name
Test status
Simulation time 728480657 ps
CPU time 9.73 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 201960 kb
Host smart-abb25049-a96d-447a-aefb-dcb6f5c459ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1725337904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1725337904
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.607490684
Short name T632
Test name
Test status
Simulation time 95476031 ps
CPU time 4.61 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:20 PM PDT 24
Peak memory 201912 kb
Host smart-733a94db-b2a9-4d2b-8be2-ea346eab7437
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=607490684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.607490684
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1795688704
Short name T239
Test name
Test status
Simulation time 22977450958 ps
CPU time 104.62 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 201888 kb
Host smart-d291fcca-4ac1-40a8-b5a5-39e1b4cec693
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795688704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1795688704
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3846207836
Short name T127
Test name
Test status
Simulation time 31222370376 ps
CPU time 138.28 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:36:43 PM PDT 24
Peak memory 202028 kb
Host smart-97d4be89-5ca1-4d95-a971-40e0367a4246
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3846207836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3846207836
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1373032465
Short name T245
Test name
Test status
Simulation time 154336770 ps
CPU time 7.7 seconds
Started Aug 13 05:34:13 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201876 kb
Host smart-8655b459-77e5-4536-a27c-f803699854fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373032465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1373032465
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.3194507477
Short name T629
Test name
Test status
Simulation time 505241045 ps
CPU time 3.39 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:27 PM PDT 24
Peak memory 201964 kb
Host smart-162047bf-ae4a-469c-85dd-87d06ffe8618
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3194507477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3194507477
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.452020078
Short name T412
Test name
Test status
Simulation time 13306438 ps
CPU time 1.1 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:15 PM PDT 24
Peak memory 201820 kb
Host smart-a25c3758-0d68-44b3-836a-23d7693ae447
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=452020078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.452020078
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2662220557
Short name T686
Test name
Test status
Simulation time 2383196291 ps
CPU time 7.41 seconds
Started Aug 13 05:34:17 PM PDT 24
Finished Aug 13 05:34:25 PM PDT 24
Peak memory 201976 kb
Host smart-da4016e3-67c8-4645-8543-d4b2fbd0a227
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662220557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2662220557
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.202065668
Short name T530
Test name
Test status
Simulation time 1046977947 ps
CPU time 8.52 seconds
Started Aug 13 05:34:15 PM PDT 24
Finished Aug 13 05:34:23 PM PDT 24
Peak memory 201900 kb
Host smart-8578d5b6-0282-4b9b-a10e-4a531b28c2b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=202065668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.202065668
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.58608012
Short name T826
Test name
Test status
Simulation time 23837178 ps
CPU time 1.19 seconds
Started Aug 13 05:34:14 PM PDT 24
Finished Aug 13 05:34:16 PM PDT 24
Peak memory 201856 kb
Host smart-bc88ad4e-bc6b-4e66-8b49-6cb4ebcebdcd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58608012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.58608012
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3141572920
Short name T184
Test name
Test status
Simulation time 2966724476 ps
CPU time 49.75 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:35:12 PM PDT 24
Peak memory 202984 kb
Host smart-2696011e-a3d4-4e33-b424-34a62342228b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3141572920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3141572920
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2501373304
Short name T441
Test name
Test status
Simulation time 436627325 ps
CPU time 6.86 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:34:29 PM PDT 24
Peak memory 201972 kb
Host smart-3874bb33-aeb3-4bc8-9ba1-5bd4b69f5b96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2501373304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2501373304
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1303684326
Short name T566
Test name
Test status
Simulation time 948346125 ps
CPU time 79.37 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:35:41 PM PDT 24
Peak memory 204536 kb
Host smart-8c8e9bca-642b-496e-8e5d-d7c57ca1eae2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1303684326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.1303684326
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3203468267
Short name T584
Test name
Test status
Simulation time 464897096 ps
CPU time 86.19 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:35:51 PM PDT 24
Peak memory 206004 kb
Host smart-43cd087d-9a27-4a8b-901c-0e0088b7b51e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3203468267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.3203468267
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2040299140
Short name T709
Test name
Test status
Simulation time 718119913 ps
CPU time 9.78 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 201952 kb
Host smart-ab71f48c-1f25-4f54-9c8c-c9efc7f98d7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2040299140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2040299140
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2093360429
Short name T311
Test name
Test status
Simulation time 942185108 ps
CPU time 16.99 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:34:41 PM PDT 24
Peak memory 201872 kb
Host smart-3e249979-f2ba-48f6-9559-344d559f5039
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2093360429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2093360429
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3372287106
Short name T747
Test name
Test status
Simulation time 32553171821 ps
CPU time 33.46 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 202000 kb
Host smart-3dfa7252-4fca-4df8-8c5c-25adc40fbee1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3372287106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.3372287106
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.623173977
Short name T610
Test name
Test status
Simulation time 603025700 ps
CPU time 5.67 seconds
Started Aug 13 05:34:27 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201036 kb
Host smart-014b0f8a-ed03-4fb8-a1b8-fe293ce2eae4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=623173977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.623173977
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.4169636578
Short name T248
Test name
Test status
Simulation time 86064972 ps
CPU time 5.42 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:34:27 PM PDT 24
Peak memory 201964 kb
Host smart-de3807e7-41e0-454d-9866-ba963d288bf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4169636578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4169636578
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.2622213143
Short name T596
Test name
Test status
Simulation time 210480253 ps
CPU time 8.91 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201884 kb
Host smart-26eaa474-61b8-4155-ad71-da18b84cf80e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622213143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2622213143
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3291901821
Short name T691
Test name
Test status
Simulation time 18779440142 ps
CPU time 62.1 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 201988 kb
Host smart-0243d881-d479-4363-a5fa-d941501e258f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291901821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3291901821
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3513440510
Short name T877
Test name
Test status
Simulation time 12082344604 ps
CPU time 17.97 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:34:40 PM PDT 24
Peak memory 202032 kb
Host smart-1d833634-dc11-4a6e-9e22-5fdb639da072
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3513440510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3513440510
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.630279322
Short name T181
Test name
Test status
Simulation time 48439252 ps
CPU time 5.59 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:27 PM PDT 24
Peak memory 201968 kb
Host smart-98848001-768f-411d-b46c-8f61a55691f2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630279322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.630279322
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.2488679460
Short name T236
Test name
Test status
Simulation time 44210247 ps
CPU time 4.39 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:25 PM PDT 24
Peak memory 202120 kb
Host smart-3672b6ed-bdb9-48d9-85b6-3adafb22e267
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2488679460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2488679460
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.4148567540
Short name T613
Test name
Test status
Simulation time 14967522 ps
CPU time 1.29 seconds
Started Aug 13 05:34:27 PM PDT 24
Finished Aug 13 05:34:29 PM PDT 24
Peak memory 201796 kb
Host smart-48501110-98ec-4d64-be8c-b34c33050b88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4148567540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4148567540
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2847546697
Short name T50
Test name
Test status
Simulation time 4672084567 ps
CPU time 7.68 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:27 PM PDT 24
Peak memory 201988 kb
Host smart-2c570977-8064-4d59-aeb0-7076216a0e40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847546697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2847546697
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.994909872
Short name T815
Test name
Test status
Simulation time 5776387588 ps
CPU time 8.4 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 202008 kb
Host smart-510ad14b-7c38-415b-bc0e-23de16d1197b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=994909872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.994909872
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3157103980
Short name T531
Test name
Test status
Simulation time 8686096 ps
CPU time 1.11 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201936 kb
Host smart-625afbc2-31fd-4fb9-8bad-7a973e72a6a8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157103980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3157103980
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1937009721
Short name T381
Test name
Test status
Simulation time 3362971748 ps
CPU time 28.36 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:50 PM PDT 24
Peak memory 201932 kb
Host smart-49e403ef-5e2d-4fe7-ab51-f988b6c20fdd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937009721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1937009721
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2069415939
Short name T841
Test name
Test status
Simulation time 7001424573 ps
CPU time 59.64 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 201948 kb
Host smart-d23229d4-73c6-4eb2-bd2a-5ac6359364ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2069415939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2069415939
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1954219631
Short name T111
Test name
Test status
Simulation time 6147482853 ps
CPU time 144.59 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 207228 kb
Host smart-00399715-c752-4470-b828-f791f9dd8b53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954219631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.1954219631
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2374486609
Short name T737
Test name
Test status
Simulation time 1875323087 ps
CPU time 77.12 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:35:39 PM PDT 24
Peak memory 204332 kb
Host smart-185febe6-5876-444e-84e5-2bb282cf0701
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2374486609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2374486609
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2242774542
Short name T302
Test name
Test status
Simulation time 2171388565 ps
CPU time 9.96 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:34:34 PM PDT 24
Peak memory 202008 kb
Host smart-f86ee90e-0d1b-4c81-86ce-db2c2c7bee1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2242774542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2242774542
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3982397782
Short name T267
Test name
Test status
Simulation time 113875528 ps
CPU time 12.47 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 201872 kb
Host smart-84605961-fd7b-441d-b05a-ec45dd8dd054
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3982397782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3982397782
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2297110176
Short name T301
Test name
Test status
Simulation time 2167897098 ps
CPU time 7.28 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:31 PM PDT 24
Peak memory 202044 kb
Host smart-f0e2999f-6971-4082-9fe6-901fd6eafa41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2297110176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2297110176
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.1751447256
Short name T479
Test name
Test status
Simulation time 950941437 ps
CPU time 15.9 seconds
Started Aug 13 05:34:27 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 201152 kb
Host smart-b13b9a23-3494-436f-b75e-b1ee3730899e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1751447256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1751447256
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.977818382
Short name T138
Test name
Test status
Simulation time 3456558871 ps
CPU time 15.13 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:37 PM PDT 24
Peak memory 201988 kb
Host smart-5f5d584d-3788-4bf8-ab57-8d03557e3b80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=977818382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.977818382
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2930878093
Short name T47
Test name
Test status
Simulation time 14130706588 ps
CPU time 28.08 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201932 kb
Host smart-75e5dfc3-89eb-4b9c-8792-b0d8ef2851f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930878093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2930878093
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3167322785
Short name T863
Test name
Test status
Simulation time 58874873729 ps
CPU time 71.65 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:35:34 PM PDT 24
Peak memory 201884 kb
Host smart-0d781b02-aada-41f7-a918-08adb3623ee8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3167322785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3167322785
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.5953963
Short name T382
Test name
Test status
Simulation time 59008159 ps
CPU time 2.44 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:34:27 PM PDT 24
Peak memory 201956 kb
Host smart-4af2ceed-02e1-43d9-8d9e-013b6929fa5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5953963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.5953963
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.3909982194
Short name T888
Test name
Test status
Simulation time 3621104958 ps
CPU time 8.92 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:29 PM PDT 24
Peak memory 201996 kb
Host smart-955a5861-1a73-47f7-99bd-fc0a94ff8338
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3909982194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3909982194
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.3184251490
Short name T726
Test name
Test status
Simulation time 72839735 ps
CPU time 1.35 seconds
Started Aug 13 05:34:27 PM PDT 24
Finished Aug 13 05:34:28 PM PDT 24
Peak memory 201880 kb
Host smart-96799084-0587-46f1-8cd6-3c876946ac07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3184251490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3184251490
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.212660985
Short name T741
Test name
Test status
Simulation time 3081770419 ps
CPU time 8.9 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201876 kb
Host smart-591a49d1-1254-4608-b757-98bc7c1f93fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=212660985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.212660985
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2282477211
Short name T509
Test name
Test status
Simulation time 4331256614 ps
CPU time 14.09 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 202040 kb
Host smart-7458c92f-b4e3-4cca-853e-52ffa735630c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2282477211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2282477211
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1064048151
Short name T647
Test name
Test status
Simulation time 10303728 ps
CPU time 1.14 seconds
Started Aug 13 05:34:24 PM PDT 24
Finished Aug 13 05:34:25 PM PDT 24
Peak memory 201956 kb
Host smart-4a18af4f-46f7-4960-87e3-84daa25815ab
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064048151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1064048151
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3350363623
Short name T824
Test name
Test status
Simulation time 108752538 ps
CPU time 15.33 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 202720 kb
Host smart-7246ab93-d08c-416b-a97a-4dc4bf9fbeff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3350363623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3350363623
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1028705083
Short name T354
Test name
Test status
Simulation time 24743586682 ps
CPU time 42.97 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:35:06 PM PDT 24
Peak memory 201996 kb
Host smart-c5ce74c3-9660-45d2-b599-f7cfdc403f9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1028705083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1028705083
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2707702186
Short name T453
Test name
Test status
Simulation time 3549334286 ps
CPU time 42.84 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:35:10 PM PDT 24
Peak memory 204380 kb
Host smart-17266d1e-b83a-4242-bb90-7f059a36c1f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2707702186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.2707702186
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4192011741
Short name T821
Test name
Test status
Simulation time 14766948905 ps
CPU time 159.85 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:37:03 PM PDT 24
Peak memory 206320 kb
Host smart-10c59a5e-b391-4f87-af3a-ecb4e9acb056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4192011741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.4192011741
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3037699141
Short name T467
Test name
Test status
Simulation time 47100787 ps
CPU time 5.13 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:28 PM PDT 24
Peak memory 201964 kb
Host smart-8d35db75-fb11-4e20-9669-8c9a94aae52a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037699141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3037699141
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.4086197792
Short name T135
Test name
Test status
Simulation time 546486461 ps
CPU time 11.19 seconds
Started Aug 13 05:34:32 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 201916 kb
Host smart-1c37a2ff-e238-48af-9c92-3115efb63acc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4086197792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.4086197792
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.929964915
Short name T199
Test name
Test status
Simulation time 36279317560 ps
CPU time 251.63 seconds
Started Aug 13 05:34:33 PM PDT 24
Finished Aug 13 05:38:45 PM PDT 24
Peak memory 203064 kb
Host smart-93196ac8-5051-4933-bb7a-aed50871a341
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=929964915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo
w_rsp.929964915
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2382919000
Short name T688
Test name
Test status
Simulation time 571357109 ps
CPU time 2.9 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 201980 kb
Host smart-3a8e1175-d005-44e9-9d36-bc291896f93e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2382919000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2382919000
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.3766597767
Short name T735
Test name
Test status
Simulation time 659553237 ps
CPU time 9.64 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:40 PM PDT 24
Peak memory 201800 kb
Host smart-68a64c8d-c831-45aa-9a7f-dc1c6d40da96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3766597767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3766597767
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.4123135026
Short name T32
Test name
Test status
Simulation time 1380868747 ps
CPU time 8.07 seconds
Started Aug 13 05:34:19 PM PDT 24
Finished Aug 13 05:34:28 PM PDT 24
Peak memory 201864 kb
Host smart-704b97f8-b9d8-4a71-a5a6-c502dccce4e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4123135026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.4123135026
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4024204178
Short name T842
Test name
Test status
Simulation time 49675685081 ps
CPU time 80.42 seconds
Started Aug 13 05:34:33 PM PDT 24
Finished Aug 13 05:35:53 PM PDT 24
Peak memory 201984 kb
Host smart-43f04ffb-d6e8-454b-8ab6-fe6d457ef504
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024204178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4024204178
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2518720664
Short name T721
Test name
Test status
Simulation time 50036325761 ps
CPU time 119.76 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:36:29 PM PDT 24
Peak memory 201928 kb
Host smart-b41cc621-a358-490a-9920-ab460f4793c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2518720664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2518720664
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1574204406
Short name T641
Test name
Test status
Simulation time 66986663 ps
CPU time 6.46 seconds
Started Aug 13 05:34:23 PM PDT 24
Finished Aug 13 05:34:30 PM PDT 24
Peak memory 201956 kb
Host smart-bd1d5d45-a52a-4b40-81dc-c17450ff5270
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574204406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1574204406
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.2442674652
Short name T484
Test name
Test status
Simulation time 67331024 ps
CPU time 4.11 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 201920 kb
Host smart-ff219cd0-684b-4903-9966-846badedbaed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2442674652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2442674652
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.340853566
Short name T871
Test name
Test status
Simulation time 111051279 ps
CPU time 1.75 seconds
Started Aug 13 05:34:22 PM PDT 24
Finished Aug 13 05:34:24 PM PDT 24
Peak memory 201920 kb
Host smart-c7a41b97-8a76-4233-b519-0c349316d1a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=340853566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.340853566
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.562135936
Short name T480
Test name
Test status
Simulation time 2960557865 ps
CPU time 7.53 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:28 PM PDT 24
Peak memory 201980 kb
Host smart-b6ba08f9-8fab-4f92-99c1-90a62186ccd4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=562135936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.562135936
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1084689270
Short name T276
Test name
Test status
Simulation time 2717335725 ps
CPU time 11.45 seconds
Started Aug 13 05:34:21 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 201992 kb
Host smart-e42636e3-3641-47ae-b670-f5ba4fe58136
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1084689270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1084689270
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3992596693
Short name T539
Test name
Test status
Simulation time 9434896 ps
CPU time 1.29 seconds
Started Aug 13 05:34:20 PM PDT 24
Finished Aug 13 05:34:21 PM PDT 24
Peak memory 201956 kb
Host smart-a29de912-89e9-4fa9-88b1-09970d28ae45
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992596693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3992596693
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3437015903
Short name T594
Test name
Test status
Simulation time 426509818 ps
CPU time 37.74 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:35:06 PM PDT 24
Peak memory 202900 kb
Host smart-979f94aa-95ba-4df2-9fee-bbdb91f6b3c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437015903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3437015903
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3134897562
Short name T565
Test name
Test status
Simulation time 120968476 ps
CPU time 12.5 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:42 PM PDT 24
Peak memory 201968 kb
Host smart-1a2bc8b7-fecd-451c-98e3-c7ee57f1d26f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3134897562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3134897562
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2286836437
Short name T481
Test name
Test status
Simulation time 1509108545 ps
CPU time 70.62 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:35:41 PM PDT 24
Peak memory 204564 kb
Host smart-f64f7b7c-565b-45c9-a5d6-c61e117fc0f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2286836437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.2286836437
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3860873145
Short name T112
Test name
Test status
Simulation time 31976191 ps
CPU time 6.96 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 201976 kb
Host smart-f0dc77ee-46d1-4c71-8a5d-799ad0c5d0ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3860873145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.3860873145
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.338218640
Short name T288
Test name
Test status
Simulation time 67606341 ps
CPU time 1.71 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201948 kb
Host smart-7bab5703-499d-4ac6-ab15-1d06c3b1afec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=338218640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.338218640
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2455800756
Short name T416
Test name
Test status
Simulation time 165524908 ps
CPU time 1.93 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 201904 kb
Host smart-055113ae-275e-4d0b-b462-0db929949558
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2455800756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2455800756
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2698824425
Short name T211
Test name
Test status
Simulation time 13387200495 ps
CPU time 92.25 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 201956 kb
Host smart-a270f577-d76d-4a16-b7c7-56e2ab680e1d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2698824425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.2698824425
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1592615957
Short name T544
Test name
Test status
Simulation time 71260164 ps
CPU time 4.01 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201912 kb
Host smart-fcc807bc-96d5-4d61-ab0a-8e5e41dfe9fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1592615957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1592615957
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.1434734659
Short name T162
Test name
Test status
Simulation time 182958903 ps
CPU time 4.84 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 201876 kb
Host smart-e7fe967c-c6e3-4314-8a94-dd813965d5b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1434734659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1434734659
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.1673945333
Short name T319
Test name
Test status
Simulation time 216637711 ps
CPU time 4.43 seconds
Started Aug 13 05:34:32 PM PDT 24
Finished Aug 13 05:34:37 PM PDT 24
Peak memory 201912 kb
Host smart-a9dfb9da-0337-4dbe-a15a-b4d63ec13864
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1673945333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1673945333
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.4141253477
Short name T66
Test name
Test status
Simulation time 13762565354 ps
CPU time 51.41 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:35:21 PM PDT 24
Peak memory 201948 kb
Host smart-1d86a16d-8eca-4cf6-93d0-6de48c981c2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141253477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.4141253477
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3631906051
Short name T386
Test name
Test status
Simulation time 4435920920 ps
CPU time 30.69 seconds
Started Aug 13 05:34:27 PM PDT 24
Finished Aug 13 05:34:58 PM PDT 24
Peak memory 201928 kb
Host smart-09318228-40dd-4381-8cf9-d8adeb421607
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3631906051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3631906051
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1970392729
Short name T369
Test name
Test status
Simulation time 48987311 ps
CPU time 3.56 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201844 kb
Host smart-8b649bf7-ce76-495b-a116-48f0eaf0ead9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970392729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1970392729
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3135929827
Short name T159
Test name
Test status
Simulation time 115155563 ps
CPU time 5.31 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 201872 kb
Host smart-5cedd798-6d47-486a-bda0-11851984ec3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3135929827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3135929827
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.2590567662
Short name T882
Test name
Test status
Simulation time 69571520 ps
CPU time 1.38 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201804 kb
Host smart-78fa8e6a-ef98-47ff-aae8-aa020a123aaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2590567662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2590567662
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.4029764140
Short name T332
Test name
Test status
Simulation time 4034407799 ps
CPU time 7.53 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:34:36 PM PDT 24
Peak memory 201968 kb
Host smart-d2699426-aa47-4ca0-ba8c-3163c83be03d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029764140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4029764140
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3037903647
Short name T357
Test name
Test status
Simulation time 1191781351 ps
CPU time 5.76 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:34:40 PM PDT 24
Peak memory 201860 kb
Host smart-b2f5d31e-7ba3-4242-9abd-2ef16802b6ab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3037903647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3037903647
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.256623295
Short name T820
Test name
Test status
Simulation time 10915623 ps
CPU time 1.28 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:31 PM PDT 24
Peak memory 201960 kb
Host smart-7ea885c9-e070-4616-a0b9-105a8792b465
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256623295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.256623295
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3833710007
Short name T585
Test name
Test status
Simulation time 234641969 ps
CPU time 17.71 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201936 kb
Host smart-624c83f7-e3ee-4c24-aa55-5959251810af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3833710007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3833710007
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1945487601
Short name T343
Test name
Test status
Simulation time 673033617 ps
CPU time 50.57 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:35:19 PM PDT 24
Peak memory 202988 kb
Host smart-5a2ad1e2-7f45-48f5-a954-929664b3c003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1945487601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1945487601
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2722425448
Short name T221
Test name
Test status
Simulation time 336795614 ps
CPU time 67.16 seconds
Started Aug 13 05:34:33 PM PDT 24
Finished Aug 13 05:35:40 PM PDT 24
Peak memory 204248 kb
Host smart-348222e1-5998-4dc0-b549-48ad74b166e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2722425448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.2722425448
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2537047838
Short name T656
Test name
Test status
Simulation time 652508024 ps
CPU time 63.59 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:35:38 PM PDT 24
Peak memory 203832 kb
Host smart-daced306-740d-4f61-8a61-5ae6d32764ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2537047838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.2537047838
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4147445729
Short name T280
Test name
Test status
Simulation time 140059675 ps
CPU time 3.43 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:34:32 PM PDT 24
Peak memory 201912 kb
Host smart-87ea631e-4b9d-4dfd-be23-fa9358c41d6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4147445729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4147445729
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.229641773
Short name T677
Test name
Test status
Simulation time 33391311 ps
CPU time 4.71 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:34:34 PM PDT 24
Peak memory 201864 kb
Host smart-97cba17a-e1e7-4600-bb92-29d44a867fd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=229641773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.229641773
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.198611206
Short name T618
Test name
Test status
Simulation time 22017277458 ps
CPU time 88.76 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:35:57 PM PDT 24
Peak memory 202008 kb
Host smart-0bb0f5ca-09a9-4d53-8a39-b1bfb8d062d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=198611206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo
w_rsp.198611206
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3947555001
Short name T893
Test name
Test status
Simulation time 68622054 ps
CPU time 5.51 seconds
Started Aug 13 05:34:32 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201936 kb
Host smart-ab4df7ec-77cc-45a2-ad3a-c63433476339
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3947555001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3947555001
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.3561522818
Short name T700
Test name
Test status
Simulation time 46792169 ps
CPU time 4.48 seconds
Started Aug 13 05:34:33 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201960 kb
Host smart-d4c95b61-5eaf-4dde-8b87-71b137976673
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3561522818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3561522818
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.2658477797
Short name T564
Test name
Test status
Simulation time 381053886 ps
CPU time 6.94 seconds
Started Aug 13 05:34:28 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 201832 kb
Host smart-7b0eef39-1e53-4197-81f1-d5754f7cfe17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2658477797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2658477797
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2586715093
Short name T778
Test name
Test status
Simulation time 29355531547 ps
CPU time 108.45 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:36:18 PM PDT 24
Peak memory 201948 kb
Host smart-e49c2233-714f-4446-a624-822b1f885dd1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586715093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2586715093
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3646488259
Short name T84
Test name
Test status
Simulation time 21874896721 ps
CPU time 131.45 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:36:41 PM PDT 24
Peak memory 202044 kb
Host smart-e29968ce-4b2c-4a6b-ad22-9544893c3810
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3646488259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3646488259
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.376929481
Short name T39
Test name
Test status
Simulation time 84733346 ps
CPU time 3.22 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201848 kb
Host smart-fb6c9ab9-98b5-4a99-a265-171caa659b4d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376929481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.376929481
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.2619595004
Short name T74
Test name
Test status
Simulation time 4040927325 ps
CPU time 6.65 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:37 PM PDT 24
Peak memory 201980 kb
Host smart-c9458807-f316-4652-b998-de978813eeec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2619595004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2619595004
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.2389918194
Short name T123
Test name
Test status
Simulation time 76054680 ps
CPU time 1.75 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:34:31 PM PDT 24
Peak memory 201924 kb
Host smart-7f34dcdd-23ac-402f-be70-ae74ff556b6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2389918194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2389918194
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.676658189
Short name T586
Test name
Test status
Simulation time 1261116502 ps
CPU time 6.54 seconds
Started Aug 13 05:34:33 PM PDT 24
Finished Aug 13 05:34:40 PM PDT 24
Peak memory 201916 kb
Host smart-f2d7b8e8-83bf-45f0-94d3-8f2146c4b838
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=676658189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.676658189
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3310909385
Short name T30
Test name
Test status
Simulation time 1454654295 ps
CPU time 6.62 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201876 kb
Host smart-74c6e62f-f6d5-48e4-a586-e36ebe2ddb82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3310909385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3310909385
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1132711393
Short name T701
Test name
Test status
Simulation time 8507392 ps
CPU time 1.16 seconds
Started Aug 13 05:34:30 PM PDT 24
Finished Aug 13 05:34:31 PM PDT 24
Peak memory 201936 kb
Host smart-2e1cdf2c-7178-48ac-9465-ef1350013af0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132711393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1132711393
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2840881637
Short name T852
Test name
Test status
Simulation time 3662548154 ps
CPU time 71.34 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:35:42 PM PDT 24
Peak memory 203020 kb
Host smart-a61401b6-7dc0-47d5-a9c4-ee7b75aa47b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2840881637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2840881637
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1101982575
Short name T450
Test name
Test status
Simulation time 3672115610 ps
CPU time 38.03 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:35:07 PM PDT 24
Peak memory 202016 kb
Host smart-1fdcbc18-da34-4e7c-abcb-8ba7e5b374e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1101982575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1101982575
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2429014295
Short name T220
Test name
Test status
Simulation time 2116952419 ps
CPU time 75.83 seconds
Started Aug 13 05:34:29 PM PDT 24
Finished Aug 13 05:35:45 PM PDT 24
Peak memory 204500 kb
Host smart-fdc829ed-efb8-4702-b91e-d7daeaa2203b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2429014295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.2429014295
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.4236123352
Short name T363
Test name
Test status
Simulation time 524278452 ps
CPU time 8.9 seconds
Started Aug 13 05:34:31 PM PDT 24
Finished Aug 13 05:34:40 PM PDT 24
Peak memory 201948 kb
Host smart-49ba5182-cd30-4bd3-ab6a-87792a4ae028
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236123352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4236123352
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2017047402
Short name T54
Test name
Test status
Simulation time 963717099 ps
CPU time 13.54 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201916 kb
Host smart-d443f48e-94b1-4a7d-a127-b76940eb971d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2017047402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2017047402
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.885522769
Short name T139
Test name
Test status
Simulation time 6797736546 ps
CPU time 44.7 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:35:21 PM PDT 24
Peak memory 202040 kb
Host smart-03ce9466-f697-4475-9d75-e504cfc4d4a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=885522769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo
w_rsp.885522769
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.856824674
Short name T575
Test name
Test status
Simulation time 48134812 ps
CPU time 2.68 seconds
Started Aug 13 05:34:39 PM PDT 24
Finished Aug 13 05:34:42 PM PDT 24
Peak memory 201948 kb
Host smart-229c4e93-4bc7-4d94-91df-a2d9fc86bfa4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856824674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.856824674
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.4172171555
Short name T191
Test name
Test status
Simulation time 70915031 ps
CPU time 6.77 seconds
Started Aug 13 05:34:40 PM PDT 24
Finished Aug 13 05:34:47 PM PDT 24
Peak memory 201872 kb
Host smart-77cadab5-b925-4923-8595-78e4cb099b79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4172171555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.4172171555
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.1932258808
Short name T303
Test name
Test status
Simulation time 899652198 ps
CPU time 5.17 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 201908 kb
Host smart-0d55bf13-5151-4c5c-ab19-21acf36ff114
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1932258808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1932258808
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1090464697
Short name T727
Test name
Test status
Simulation time 44020093436 ps
CPU time 81.67 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 201972 kb
Host smart-c617535b-9cb5-4254-85b9-4fece6878b4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090464697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1090464697
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2016606321
Short name T738
Test name
Test status
Simulation time 12139899426 ps
CPU time 76.5 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:35:52 PM PDT 24
Peak memory 202032 kb
Host smart-42dfbb40-3a80-4469-b348-5b772aa2c570
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2016606321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2016606321
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.757932963
Short name T499
Test name
Test status
Simulation time 107952055 ps
CPU time 11.43 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:34:47 PM PDT 24
Peak memory 201920 kb
Host smart-ee4ab6f7-0e5c-4393-9997-47792124685e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757932963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.757932963
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.1228220562
Short name T263
Test name
Test status
Simulation time 50195844 ps
CPU time 5.65 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:44 PM PDT 24
Peak memory 201884 kb
Host smart-ca241f57-cebb-4c90-941c-c5851e103a0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1228220562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1228220562
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.1960785946
Short name T361
Test name
Test status
Simulation time 11639783 ps
CPU time 1.49 seconds
Started Aug 13 05:34:34 PM PDT 24
Finished Aug 13 05:34:35 PM PDT 24
Peak memory 201900 kb
Host smart-476276fc-acd3-4275-ba4a-d3a170ffe21e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1960785946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1960785946
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.659787120
Short name T684
Test name
Test status
Simulation time 3032923411 ps
CPU time 8.67 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:46 PM PDT 24
Peak memory 201876 kb
Host smart-a10737be-7ada-44ca-bbdb-26d4e4967f81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=659787120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.659787120
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1915995756
Short name T182
Test name
Test status
Simulation time 1865933744 ps
CPU time 10.74 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:48 PM PDT 24
Peak memory 201972 kb
Host smart-45cf8053-111c-4314-bdda-7395e6e83a0d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1915995756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1915995756
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.958612757
Short name T89
Test name
Test status
Simulation time 10507656 ps
CPU time 1.18 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201956 kb
Host smart-2d89cfc3-4bc3-4e3a-a17d-31a17f1e861b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958612757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.958612757
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1024758640
Short name T777
Test name
Test status
Simulation time 130064645 ps
CPU time 13.85 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:52 PM PDT 24
Peak memory 201856 kb
Host smart-fcaabdd0-5bde-441a-becd-f775995dcbff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1024758640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1024758640
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.497243484
Short name T714
Test name
Test status
Simulation time 1505444336 ps
CPU time 25.87 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:35:01 PM PDT 24
Peak memory 201932 kb
Host smart-f17296ec-e28a-4086-833a-1622f2a8a014
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=497243484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.497243484
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1329690167
Short name T697
Test name
Test status
Simulation time 20387866 ps
CPU time 11.29 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201952 kb
Host smart-1634741a-6902-480c-9e47-fbd85ec72ecf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1329690167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.1329690167
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2000007574
Short name T471
Test name
Test status
Simulation time 605722082 ps
CPU time 81.63 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 203276 kb
Host smart-1ee779cb-4afc-4e7f-a096-bb78fcc3750b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2000007574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2000007574
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.269399911
Short name T740
Test name
Test status
Simulation time 84644282 ps
CPU time 6.77 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 201960 kb
Host smart-54ce83e0-4ac1-4b7c-816a-d11e18674564
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=269399911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.269399911
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1824355575
Short name T209
Test name
Test status
Simulation time 1691714880 ps
CPU time 16.13 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:53 PM PDT 24
Peak memory 201952 kb
Host smart-8a6f8682-0d6f-4782-bf41-a1b08af8b7a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1824355575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1824355575
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3871580185
Short name T203
Test name
Test status
Simulation time 87273067825 ps
CPU time 115.91 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:36:31 PM PDT 24
Peak memory 202564 kb
Host smart-740716c7-9a83-4989-bb75-1c7e7235e19c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3871580185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3871580185
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.450149316
Short name T93
Test name
Test status
Simulation time 85154372 ps
CPU time 4.17 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:41 PM PDT 24
Peak memory 201872 kb
Host smart-40457d4a-b182-4a3f-ab81-a8357b1867aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=450149316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.450149316
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.200055240
Short name T257
Test name
Test status
Simulation time 1032677702 ps
CPU time 8.01 seconds
Started Aug 13 05:34:39 PM PDT 24
Finished Aug 13 05:34:47 PM PDT 24
Peak memory 201964 kb
Host smart-0b5881a0-5d18-416f-9620-9ee199d148fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=200055240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.200055240
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3032969609
Short name T271
Test name
Test status
Simulation time 49808689 ps
CPU time 7.05 seconds
Started Aug 13 05:34:40 PM PDT 24
Finished Aug 13 05:34:47 PM PDT 24
Peak memory 201880 kb
Host smart-7a1814bb-cb3d-4570-9634-1f01a8a4e569
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3032969609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3032969609
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2219903155
Short name T819
Test name
Test status
Simulation time 59476202326 ps
CPU time 102.01 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:36:17 PM PDT 24
Peak memory 201980 kb
Host smart-8d1006c0-68bc-4899-ba6b-3e376dfb9064
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219903155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2219903155
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.934519650
Short name T290
Test name
Test status
Simulation time 1705550780 ps
CPU time 5.36 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 201968 kb
Host smart-442ac8bb-8d47-4257-97b5-3ca34a11de51
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=934519650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.934519650
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1778295380
Short name T616
Test name
Test status
Simulation time 92030480 ps
CPU time 5.57 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:34:42 PM PDT 24
Peak memory 201868 kb
Host smart-3b7fbd4a-8d2b-4322-857f-93d35247c342
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778295380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1778295380
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.2956774721
Short name T362
Test name
Test status
Simulation time 257987909 ps
CPU time 2.6 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:41 PM PDT 24
Peak memory 201944 kb
Host smart-ea355c32-84c6-47d1-a036-f69f37a6a274
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2956774721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2956774721
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.208086546
Short name T232
Test name
Test status
Simulation time 10753690 ps
CPU time 1.2 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:39 PM PDT 24
Peak memory 201884 kb
Host smart-d75675ed-8a59-4524-987e-72ffaadbd7c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=208086546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.208086546
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1804731636
Short name T91
Test name
Test status
Simulation time 8694640867 ps
CPU time 6.68 seconds
Started Aug 13 05:34:41 PM PDT 24
Finished Aug 13 05:34:47 PM PDT 24
Peak memory 201980 kb
Host smart-7dfa9e96-7fe9-42a0-8131-7b52de976bc6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804731636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1804731636
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2731881887
Short name T333
Test name
Test status
Simulation time 2388077046 ps
CPU time 9.39 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:46 PM PDT 24
Peak memory 202024 kb
Host smart-ecea179f-3cf6-4037-9d25-f9e5d8e34f6f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2731881887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2731881887
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.834829281
Short name T703
Test name
Test status
Simulation time 14814715 ps
CPU time 1.03 seconds
Started Aug 13 05:34:38 PM PDT 24
Finished Aug 13 05:34:39 PM PDT 24
Peak memory 201796 kb
Host smart-31975e98-f94a-4f90-8da6-46ca3937dcc7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834829281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.834829281
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.4028411655
Short name T17
Test name
Test status
Simulation time 330350447 ps
CPU time 26.59 seconds
Started Aug 13 05:34:40 PM PDT 24
Finished Aug 13 05:35:07 PM PDT 24
Peak memory 203268 kb
Host smart-bc4feeb9-29a1-484c-9969-e2993feff456
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4028411655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.4028411655
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.404757867
Short name T122
Test name
Test status
Simulation time 3793593566 ps
CPU time 21.13 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:34:57 PM PDT 24
Peak memory 201992 kb
Host smart-10245be9-b777-4225-8401-b53d37b97866
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=404757867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.404757867
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2129549263
Short name T180
Test name
Test status
Simulation time 15669117258 ps
CPU time 81.45 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 204636 kb
Host smart-9478cef5-822a-49be-b4c0-13c57fe39f81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2129549263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2129549263
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1983744510
Short name T637
Test name
Test status
Simulation time 667360452 ps
CPU time 111.11 seconds
Started Aug 13 05:34:39 PM PDT 24
Finished Aug 13 05:36:31 PM PDT 24
Peak memory 205564 kb
Host smart-c7d8a49a-b55c-4cb4-9198-98345624f630
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1983744510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.1983744510
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1037758453
Short name T580
Test name
Test status
Simulation time 111667967 ps
CPU time 2.63 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201912 kb
Host smart-273be9b7-02a6-4974-96fa-ffbfd389455d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1037758453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1037758453
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2069794715
Short name T421
Test name
Test status
Simulation time 876765165 ps
CPU time 22.37 seconds
Started Aug 13 05:34:46 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201968 kb
Host smart-adaf7774-f7ee-4136-93fb-f59253e3c83a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2069794715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2069794715
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1409127951
Short name T794
Test name
Test status
Simulation time 166545720 ps
CPU time 6.99 seconds
Started Aug 13 05:34:51 PM PDT 24
Finished Aug 13 05:34:58 PM PDT 24
Peak memory 201952 kb
Host smart-0bd99df8-ad9c-4304-8357-46fb405e4e5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1409127951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1409127951
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.3113632881
Short name T146
Test name
Test status
Simulation time 366773677 ps
CPU time 2.78 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 201968 kb
Host smart-c0bf775b-36de-4a6a-92d0-1f57cec8ef9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3113632881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3113632881
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.2014002354
Short name T692
Test name
Test status
Simulation time 69824501 ps
CPU time 9.23 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 201820 kb
Host smart-dd7a9bda-7fad-4069-bb13-57f987d8ccf9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2014002354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2014002354
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2671620673
Short name T602
Test name
Test status
Simulation time 65711483817 ps
CPU time 141.51 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:37:09 PM PDT 24
Peak memory 201984 kb
Host smart-e1c86c64-66ed-4eed-8b8b-8b927ee5f34f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671620673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2671620673
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3399478225
Short name T510
Test name
Test status
Simulation time 6986023766 ps
CPU time 41.56 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:35:29 PM PDT 24
Peak memory 201928 kb
Host smart-5b549c40-4f64-4294-ad85-878622263ef2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3399478225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3399478225
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3322339245
Short name T579
Test name
Test status
Simulation time 11926414 ps
CPU time 1.65 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:49 PM PDT 24
Peak memory 201968 kb
Host smart-8c9f8566-f08f-45b1-ab9e-7c1885925ccf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322339245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3322339245
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.1912078242
Short name T80
Test name
Test status
Simulation time 517093198 ps
CPU time 3.68 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 201980 kb
Host smart-5fa37414-9c99-4189-9949-0c9416d65c6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1912078242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1912078242
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.1690620409
Short name T55
Test name
Test status
Simulation time 55772555 ps
CPU time 1.71 seconds
Started Aug 13 05:34:35 PM PDT 24
Finished Aug 13 05:34:37 PM PDT 24
Peak memory 201880 kb
Host smart-89485ef3-20b9-4dd1-9f33-cabd89f2353b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690620409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1690620409
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3558772372
Short name T875
Test name
Test status
Simulation time 4664710128 ps
CPU time 6.84 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:34:43 PM PDT 24
Peak memory 201992 kb
Host smart-b4768dff-4489-4b98-bf8e-f46d3b0a44e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558772372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3558772372
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.335310732
Short name T492
Test name
Test status
Simulation time 1653450466 ps
CPU time 9.16 seconds
Started Aug 13 05:34:36 PM PDT 24
Finished Aug 13 05:34:45 PM PDT 24
Peak memory 201984 kb
Host smart-cdeebffd-68be-4812-a181-ba1d45148ad7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=335310732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.335310732
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3749590428
Short name T614
Test name
Test status
Simulation time 14342284 ps
CPU time 1.12 seconds
Started Aug 13 05:34:37 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201920 kb
Host smart-bcedc89f-00aa-4de3-967b-adcae2a8cdbf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749590428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3749590428
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3478084822
Short name T665
Test name
Test status
Simulation time 5541898016 ps
CPU time 62.84 seconds
Started Aug 13 05:34:45 PM PDT 24
Finished Aug 13 05:35:48 PM PDT 24
Peak memory 203196 kb
Host smart-5a5f6988-b3fd-477f-927f-376ce0fa3395
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478084822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3478084822
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2249659875
Short name T208
Test name
Test status
Simulation time 2618308694 ps
CPU time 45.59 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:35:33 PM PDT 24
Peak memory 202024 kb
Host smart-fd372d63-3bd5-4400-a239-8d887acf1961
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2249659875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2249659875
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2912550836
Short name T136
Test name
Test status
Simulation time 11950148649 ps
CPU time 130.59 seconds
Started Aug 13 05:34:49 PM PDT 24
Finished Aug 13 05:36:59 PM PDT 24
Peak memory 206492 kb
Host smart-dd953360-5ee8-424f-a018-2586923ecaf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2912550836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.2912550836
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1270516160
Short name T843
Test name
Test status
Simulation time 212275797 ps
CPU time 47.59 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:35:34 PM PDT 24
Peak memory 203300 kb
Host smart-24de34f6-edc1-4c07-83d9-1fb3156cfbac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1270516160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.1270516160
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.155956690
Short name T603
Test name
Test status
Simulation time 31319585 ps
CPU time 3.52 seconds
Started Aug 13 05:34:49 PM PDT 24
Finished Aug 13 05:34:53 PM PDT 24
Peak memory 201944 kb
Host smart-b267ce1e-0c46-4534-914e-e6ca17e56b27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=155956690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.155956690
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2682295732
Short name T864
Test name
Test status
Simulation time 187420863 ps
CPU time 6.34 seconds
Started Aug 13 05:32:52 PM PDT 24
Finished Aug 13 05:32:58 PM PDT 24
Peak memory 201932 kb
Host smart-9c1d6879-6daa-40bd-8418-c24881104d1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2682295732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2682295732
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3271441275
Short name T150
Test name
Test status
Simulation time 8605710475 ps
CPU time 39.95 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 202000 kb
Host smart-fe050f05-2a42-483d-9d67-8537a255c1c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3271441275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3271441275
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2139382052
Short name T562
Test name
Test status
Simulation time 499607436 ps
CPU time 4.33 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:32:56 PM PDT 24
Peak memory 201908 kb
Host smart-27310b98-08d2-49a2-8635-1d5342c06d1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2139382052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2139382052
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3829967487
Short name T458
Test name
Test status
Simulation time 758702840 ps
CPU time 12.61 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201804 kb
Host smart-eb97fb07-a374-4d5f-9a1c-ec06f71f7951
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3829967487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3829967487
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2038927419
Short name T465
Test name
Test status
Simulation time 16750115 ps
CPU time 1.7 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:50 PM PDT 24
Peak memory 202076 kb
Host smart-a8c68ef1-a164-4039-bf98-25cc20a77cae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2038927419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2038927419
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1558871909
Short name T609
Test name
Test status
Simulation time 7525566975 ps
CPU time 10.3 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:33:02 PM PDT 24
Peak memory 201924 kb
Host smart-389557fb-0274-4a37-a82b-f21860abe9d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558871909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1558871909
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2499629785
Short name T546
Test name
Test status
Simulation time 32079860931 ps
CPU time 65.05 seconds
Started Aug 13 05:32:50 PM PDT 24
Finished Aug 13 05:33:56 PM PDT 24
Peak memory 202028 kb
Host smart-0185ebf7-d5d8-485b-bb6f-5dfb7009e15c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2499629785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2499629785
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2387625219
Short name T238
Test name
Test status
Simulation time 41749004 ps
CPU time 5.16 seconds
Started Aug 13 05:32:53 PM PDT 24
Finished Aug 13 05:32:59 PM PDT 24
Peak memory 201964 kb
Host smart-e7ad0e9b-3885-48e7-b4ea-9526c395f700
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387625219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2387625219
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.862131965
Short name T764
Test name
Test status
Simulation time 30857818 ps
CPU time 3.17 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:32:52 PM PDT 24
Peak memory 201948 kb
Host smart-661ab876-c5c3-417a-8a69-91ddab155ea1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862131965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.862131965
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1149061063
Short name T360
Test name
Test status
Simulation time 8987449 ps
CPU time 1.18 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:01 PM PDT 24
Peak memory 201912 kb
Host smart-2764eeaf-b943-4f35-b143-37ec1a7bc047
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1149061063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1149061063
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2590079757
Short name T676
Test name
Test status
Simulation time 4429967667 ps
CPU time 9.69 seconds
Started Aug 13 05:32:48 PM PDT 24
Finished Aug 13 05:32:57 PM PDT 24
Peak memory 201896 kb
Host smart-bd9077b8-724e-4cc8-a58c-0a079317debe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590079757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2590079757
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.738778215
Short name T429
Test name
Test status
Simulation time 1383390658 ps
CPU time 4.27 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:32:56 PM PDT 24
Peak memory 201984 kb
Host smart-5cc5b49a-5f49-4f4c-ae44-e191fd3e0c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=738778215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.738778215
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.348476475
Short name T249
Test name
Test status
Simulation time 15019917 ps
CPU time 1.42 seconds
Started Aug 13 05:32:51 PM PDT 24
Finished Aug 13 05:32:53 PM PDT 24
Peak memory 201800 kb
Host smart-046ac655-9cff-4f37-9f87-498857355b6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348476475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.348476475
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2714069840
Short name T168
Test name
Test status
Simulation time 5632860148 ps
CPU time 17.2 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:33:14 PM PDT 24
Peak memory 201976 kb
Host smart-4051b661-0ffe-4f8a-b1df-3c3a0e2cae15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2714069840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2714069840
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3507708437
Short name T125
Test name
Test status
Simulation time 210144709 ps
CPU time 34.13 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:32 PM PDT 24
Peak memory 201884 kb
Host smart-5d193b8a-8f3c-401d-8405-a6eee7e79aa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3507708437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3507708437
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4173069938
Short name T619
Test name
Test status
Simulation time 9553101620 ps
CPU time 189.85 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:36:08 PM PDT 24
Peak memory 205068 kb
Host smart-1ac1757c-11ad-4d90-ae62-dfb86b40b29c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4173069938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.4173069938
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3578374923
Short name T659
Test name
Test status
Simulation time 158812599 ps
CPU time 5.97 seconds
Started Aug 13 05:32:49 PM PDT 24
Finished Aug 13 05:32:55 PM PDT 24
Peak memory 201836 kb
Host smart-2ae4cef0-45f9-494f-a39b-aa97097ea5e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3578374923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3578374923
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3370980522
Short name T155
Test name
Test status
Simulation time 377632074 ps
CPU time 3.52 seconds
Started Aug 13 05:34:51 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 201956 kb
Host smart-1c81a85e-53cd-480c-9761-0d52e288b0e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3370980522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3370980522
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4129700792
Short name T799
Test name
Test status
Simulation time 928239295 ps
CPU time 6.41 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:53 PM PDT 24
Peak memory 201848 kb
Host smart-f908c0d1-17c8-4df6-af5b-abee120a1d9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4129700792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4129700792
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2421321619
Short name T15
Test name
Test status
Simulation time 492046842 ps
CPU time 4.84 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:53 PM PDT 24
Peak memory 201916 kb
Host smart-59b647a5-d1ad-40d1-843d-cc180a51ac8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2421321619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2421321619
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.2936384632
Short name T261
Test name
Test status
Simulation time 102307057 ps
CPU time 5.6 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:54 PM PDT 24
Peak memory 201756 kb
Host smart-f2e38cfc-c006-444e-8eba-c79e889e94fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2936384632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2936384632
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.4037824807
Short name T349
Test name
Test status
Simulation time 35132002191 ps
CPU time 63.47 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:35:50 PM PDT 24
Peak memory 202000 kb
Host smart-74c04e10-3633-43be-ab6c-fcba8b5b751f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4037824807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4037824807
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2852948525
Short name T533
Test name
Test status
Simulation time 275244959 ps
CPU time 9.36 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 201968 kb
Host smart-071174ad-2877-46b1-8113-84846093745a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852948525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2852948525
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.3742135736
Short name T344
Test name
Test status
Simulation time 65332358 ps
CPU time 3.4 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 201916 kb
Host smart-5c131eed-8eee-4fc0-b09a-93d9f3306696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3742135736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3742135736
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.1766995181
Short name T557
Test name
Test status
Simulation time 188329591 ps
CPU time 1.59 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:48 PM PDT 24
Peak memory 201928 kb
Host smart-7642e3e3-b8c4-42ed-ae59-8bd98a62eaab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1766995181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1766995181
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.891155026
Short name T498
Test name
Test status
Simulation time 8874744008 ps
CPU time 9.21 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:57 PM PDT 24
Peak memory 201980 kb
Host smart-c51ffe6a-03fc-4550-b43a-0b120e4741db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=891155026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.891155026
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3083479146
Short name T712
Test name
Test status
Simulation time 5629547777 ps
CPU time 7.12 seconds
Started Aug 13 05:34:51 PM PDT 24
Finished Aug 13 05:34:58 PM PDT 24
Peak memory 202032 kb
Host smart-43ec1318-43b7-4a7a-9146-c157c7d1c70a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3083479146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3083479146
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2799505998
Short name T667
Test name
Test status
Simulation time 13435778 ps
CPU time 1.42 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:50 PM PDT 24
Peak memory 201976 kb
Host smart-5a94f2eb-9644-4c45-91dc-1ffda6429dd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799505998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2799505998
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1039113305
Short name T285
Test name
Test status
Simulation time 7658789235 ps
CPU time 46.49 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:35:35 PM PDT 24
Peak memory 202048 kb
Host smart-4fe26c5b-d643-489c-a0d1-76655e8e7f86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1039113305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1039113305
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2366957821
Short name T394
Test name
Test status
Simulation time 4961947970 ps
CPU time 54.91 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:35:43 PM PDT 24
Peak memory 202000 kb
Host smart-e3c40440-eed9-4673-a701-9b3cb9853299
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2366957821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2366957821
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2452836754
Short name T234
Test name
Test status
Simulation time 142646640 ps
CPU time 14.72 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:35:02 PM PDT 24
Peak memory 202976 kb
Host smart-96765e65-4af2-4d34-8100-529320f46240
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2452836754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.2452836754
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1901960652
Short name T57
Test name
Test status
Simulation time 4183354615 ps
CPU time 111.97 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:36:40 PM PDT 24
Peak memory 205092 kb
Host smart-207659ff-0a65-4833-84fd-8df147e5e796
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1901960652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.1901960652
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3833795126
Short name T366
Test name
Test status
Simulation time 151265114 ps
CPU time 3.12 seconds
Started Aug 13 05:34:49 PM PDT 24
Finished Aug 13 05:34:52 PM PDT 24
Peak memory 201796 kb
Host smart-b823736c-5339-4fcf-87ee-f4d1874db2d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3833795126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3833795126
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3975422051
Short name T706
Test name
Test status
Simulation time 53940754 ps
CPU time 11.42 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:34:59 PM PDT 24
Peak memory 201908 kb
Host smart-e21b081d-024d-4f2b-9d97-d6be35ab4c22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3975422051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3975422051
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1150152964
Short name T673
Test name
Test status
Simulation time 14286981767 ps
CPU time 24.1 seconds
Started Aug 13 05:34:45 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201988 kb
Host smart-6c3141b6-13f7-4623-8c30-4da4ef538791
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1150152964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.1150152964
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1828995774
Short name T627
Test name
Test status
Simulation time 1419404852 ps
CPU time 7.07 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:35:02 PM PDT 24
Peak memory 201960 kb
Host smart-6c85e4bf-3455-411d-8ff1-06f9c0d937b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828995774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1828995774
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.1848607504
Short name T771
Test name
Test status
Simulation time 1240052340 ps
CPU time 11.8 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 201924 kb
Host smart-0b057793-9d1e-4e0f-983c-15e106ab880b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1848607504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1848607504
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.3406846836
Short name T493
Test name
Test status
Simulation time 5968585487 ps
CPU time 12.37 seconds
Started Aug 13 05:34:49 PM PDT 24
Finished Aug 13 05:35:01 PM PDT 24
Peak memory 201812 kb
Host smart-f8c98cf3-77eb-4bf6-9bb4-a24c07078936
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3406846836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3406846836
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2955233843
Short name T81
Test name
Test status
Simulation time 151354692883 ps
CPU time 129.11 seconds
Started Aug 13 05:34:49 PM PDT 24
Finished Aug 13 05:36:58 PM PDT 24
Peak memory 201924 kb
Host smart-4e8a77d7-fd98-42d3-8160-c541856fe8bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955233843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2955233843
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.843446576
Short name T615
Test name
Test status
Simulation time 12638360442 ps
CPU time 58.74 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:35:47 PM PDT 24
Peak memory 202012 kb
Host smart-3bea1f45-c85b-44a2-8d0c-61469f9049b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=843446576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.843446576
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3463891689
Short name T717
Test name
Test status
Simulation time 21524955 ps
CPU time 3.32 seconds
Started Aug 13 05:34:47 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 201968 kb
Host smart-019b8c06-1b7d-4a2b-92fa-ada6fee2d662
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463891689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3463891689
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.2778717430
Short name T424
Test name
Test status
Simulation time 677294434 ps
CPU time 6.96 seconds
Started Aug 13 05:35:04 PM PDT 24
Finished Aug 13 05:35:11 PM PDT 24
Peak memory 201860 kb
Host smart-fc1fd387-ad9b-4d50-82b6-2a67c3248d03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2778717430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2778717430
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.2438436545
Short name T260
Test name
Test status
Simulation time 16913316 ps
CPU time 1.1 seconds
Started Aug 13 05:34:50 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 201908 kb
Host smart-7b0277ec-7567-4721-b9ee-c496938cd25e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2438436545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2438436545
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3043408705
Short name T695
Test name
Test status
Simulation time 8083324333 ps
CPU time 11.8 seconds
Started Aug 13 05:34:48 PM PDT 24
Finished Aug 13 05:35:00 PM PDT 24
Peak memory 201956 kb
Host smart-d092b5a3-6c8b-4c63-8107-1c263380a50a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043408705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3043408705
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.858264182
Short name T356
Test name
Test status
Simulation time 1295663505 ps
CPU time 6.2 seconds
Started Aug 13 05:34:49 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 201948 kb
Host smart-384b2d9a-eb82-452e-8f19-eac3e390e87c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=858264182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.858264182
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4199014105
Short name T423
Test name
Test status
Simulation time 12557316 ps
CPU time 1.25 seconds
Started Aug 13 05:34:50 PM PDT 24
Finished Aug 13 05:34:52 PM PDT 24
Peak memory 201956 kb
Host smart-cc3188f1-3f31-4d11-8029-13db22d08e7b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199014105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4199014105
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1029077204
Short name T600
Test name
Test status
Simulation time 3555189001 ps
CPU time 60.73 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:35:56 PM PDT 24
Peak memory 203028 kb
Host smart-e5400560-ae0c-4982-9923-54711ade058f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1029077204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1029077204
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2749186431
Short name T457
Test name
Test status
Simulation time 2590719433 ps
CPU time 11.09 seconds
Started Aug 13 05:35:04 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201932 kb
Host smart-f6bc7e5b-dfb9-4afd-a9a5-bf1d732fb4ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2749186431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2749186431
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2678906173
Short name T420
Test name
Test status
Simulation time 314641360 ps
CPU time 85.64 seconds
Started Aug 13 05:34:58 PM PDT 24
Finished Aug 13 05:36:24 PM PDT 24
Peak memory 204236 kb
Host smart-dc2d07f3-3b09-40dc-9900-f049c5f09f86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2678906173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.2678906173
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2778371659
Short name T578
Test name
Test status
Simulation time 6062330949 ps
CPU time 110.94 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:36:47 PM PDT 24
Peak memory 206368 kb
Host smart-371cab29-93b4-41af-a96a-d5479737c344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2778371659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2778371659
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3798895608
Short name T188
Test name
Test status
Simulation time 931366694 ps
CPU time 11.92 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 201812 kb
Host smart-d33cedd2-9d15-4c32-8ab9-6904f404155c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3798895608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3798895608
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2552606791
Short name T121
Test name
Test status
Simulation time 806995824 ps
CPU time 12.19 seconds
Started Aug 13 05:34:56 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201868 kb
Host smart-aa3a4381-d526-4728-b585-73b997d0be84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2552606791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2552606791
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3375960886
Short name T214
Test name
Test status
Simulation time 56686566170 ps
CPU time 179.57 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:37:52 PM PDT 24
Peak memory 202960 kb
Host smart-6afb723b-bcd0-426f-b75b-2f4bdf218d08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3375960886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.3375960886
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2687765142
Short name T2
Test name
Test status
Simulation time 414192841 ps
CPU time 1.78 seconds
Started Aug 13 05:35:04 PM PDT 24
Finished Aug 13 05:35:06 PM PDT 24
Peak memory 201856 kb
Host smart-422e87ee-76cd-4428-ade2-8bd7f4c3c5c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2687765142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2687765142
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.1676232832
Short name T75
Test name
Test status
Simulation time 65439843 ps
CPU time 3.43 seconds
Started Aug 13 05:34:59 PM PDT 24
Finished Aug 13 05:35:02 PM PDT 24
Peak memory 201968 kb
Host smart-d42e8813-3736-4635-9aec-6ce0cf8da02b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1676232832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1676232832
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2727461967
Short name T308
Test name
Test status
Simulation time 10140210 ps
CPU time 1.14 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 201916 kb
Host smart-0dd3eb04-a12c-43c6-b0a2-def19ade04d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2727461967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2727461967
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.994684192
Short name T189
Test name
Test status
Simulation time 22261894078 ps
CPU time 149.25 seconds
Started Aug 13 05:34:52 PM PDT 24
Finished Aug 13 05:37:21 PM PDT 24
Peak memory 201992 kb
Host smart-c8ab9484-19f0-4c26-9795-45acbe041ad1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=994684192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.994684192
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1416842715
Short name T514
Test name
Test status
Simulation time 120325105 ps
CPU time 5.76 seconds
Started Aug 13 05:34:52 PM PDT 24
Finished Aug 13 05:34:58 PM PDT 24
Peak memory 201912 kb
Host smart-65d6f0fe-c850-4675-9c47-c2155ec05e33
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416842715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1416842715
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2337502814
Short name T61
Test name
Test status
Simulation time 26305262 ps
CPU time 2.14 seconds
Started Aug 13 05:34:58 PM PDT 24
Finished Aug 13 05:35:00 PM PDT 24
Peak memory 201948 kb
Host smart-072299ef-e12f-40bf-a578-2119b8b80524
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2337502814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2337502814
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.476336471
Short name T340
Test name
Test status
Simulation time 8667264 ps
CPU time 1.03 seconds
Started Aug 13 05:34:54 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 201920 kb
Host smart-1b7490f9-b38c-4da3-a7fd-310e621e7c20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=476336471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.476336471
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1472878977
Short name T235
Test name
Test status
Simulation time 2964430446 ps
CPU time 9.59 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 201952 kb
Host smart-9fbed2a3-d30e-4f78-bead-1f0f7d81c581
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472878977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1472878977
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.4236796380
Short name T460
Test name
Test status
Simulation time 5126520805 ps
CPU time 11.13 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 202016 kb
Host smart-b37a3938-1b1b-4a28-ad78-a710be09e305
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4236796380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4236796380
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3664180852
Short name T508
Test name
Test status
Simulation time 14850317 ps
CPU time 1.36 seconds
Started Aug 13 05:34:58 PM PDT 24
Finished Aug 13 05:34:59 PM PDT 24
Peak memory 201924 kb
Host smart-f2c9963a-f3de-4a0a-9b05-c43db09d91bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664180852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3664180852
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1238736574
Short name T283
Test name
Test status
Simulation time 4306024730 ps
CPU time 29.85 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 202036 kb
Host smart-ce5298f5-9d50-4a39-b8d6-7c91f2a8684b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1238736574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1238736574
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3038489975
Short name T639
Test name
Test status
Simulation time 42983826 ps
CPU time 6.85 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:35:00 PM PDT 24
Peak memory 201968 kb
Host smart-7af841a9-a1fd-4337-b74b-45292f42d3bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3038489975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3038489975
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2003288627
Short name T763
Test name
Test status
Simulation time 4146612721 ps
CPU time 71.32 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:36:07 PM PDT 24
Peak memory 204256 kb
Host smart-c0ac120b-aec9-49ae-bef6-f9ca4bf9301d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2003288627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.2003288627
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2946855258
Short name T745
Test name
Test status
Simulation time 231465734 ps
CPU time 29.45 seconds
Started Aug 13 05:34:58 PM PDT 24
Finished Aug 13 05:35:27 PM PDT 24
Peak memory 202992 kb
Host smart-4d5793c8-0f6a-4e08-9382-31eab21d3871
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2946855258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2946855258
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2219415471
Short name T292
Test name
Test status
Simulation time 9031151 ps
CPU time 1.08 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:06 PM PDT 24
Peak memory 201860 kb
Host smart-282a3bca-1446-4db2-96c1-60f43c559386
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219415471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2219415471
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1469034172
Short name T318
Test name
Test status
Simulation time 385926278 ps
CPU time 11.17 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 201860 kb
Host smart-9a673270-5a54-4619-9fae-76365738dbfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1469034172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1469034172
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3928544846
Short name T202
Test name
Test status
Simulation time 140465910930 ps
CPU time 165.12 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:37:48 PM PDT 24
Peak memory 202968 kb
Host smart-65f12913-6aed-4d82-b75a-faf7f226b20d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3928544846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.3928544846
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1828738230
Short name T409
Test name
Test status
Simulation time 52973829 ps
CPU time 1.37 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 201892 kb
Host smart-a5ae431f-9fa6-4c25-b689-c8c32c62dc99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828738230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1828738230
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1215984839
Short name T342
Test name
Test status
Simulation time 1321514052 ps
CPU time 13.4 seconds
Started Aug 13 05:34:56 PM PDT 24
Finished Aug 13 05:35:10 PM PDT 24
Peak memory 201880 kb
Host smart-0ce9545e-66d7-4899-8fba-373ea2aa9ba0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1215984839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1215984839
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.3467980547
Short name T41
Test name
Test status
Simulation time 26899407 ps
CPU time 3.05 seconds
Started Aug 13 05:34:54 PM PDT 24
Finished Aug 13 05:34:57 PM PDT 24
Peak memory 201904 kb
Host smart-21107174-0a80-4407-abe2-2701a344eda4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3467980547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3467980547
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2722648598
Short name T744
Test name
Test status
Simulation time 2636787516 ps
CPU time 10.23 seconds
Started Aug 13 05:34:59 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201988 kb
Host smart-4a024121-10eb-405a-8b3e-17c678d7a53f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722648598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2722648598
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.510466094
Short name T20
Test name
Test status
Simulation time 44732044438 ps
CPU time 104.3 seconds
Started Aug 13 05:34:54 PM PDT 24
Finished Aug 13 05:36:39 PM PDT 24
Peak memory 201932 kb
Host smart-bad9ab11-c44a-4194-b61a-cf0fb58ff29b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=510466094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.510466094
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2104243195
Short name T131
Test name
Test status
Simulation time 18727432 ps
CPU time 2.5 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 201860 kb
Host smart-7e0d70fe-f432-482f-ae5b-b08edcf73f98
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104243195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2104243195
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.1847389145
Short name T808
Test name
Test status
Simulation time 35475708 ps
CPU time 3.65 seconds
Started Aug 13 05:34:54 PM PDT 24
Finished Aug 13 05:34:58 PM PDT 24
Peak memory 201960 kb
Host smart-a2f76bfd-b333-4fe5-99cc-ccc7d83171ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1847389145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1847389145
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.2411799986
Short name T44
Test name
Test status
Simulation time 347530575 ps
CPU time 1.84 seconds
Started Aug 13 05:34:57 PM PDT 24
Finished Aug 13 05:34:59 PM PDT 24
Peak memory 201908 kb
Host smart-a9eb9983-9ee0-4a9b-9597-91feb3fd4981
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2411799986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2411799986
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1997475088
Short name T52
Test name
Test status
Simulation time 1682609601 ps
CPU time 6.6 seconds
Started Aug 13 05:34:53 PM PDT 24
Finished Aug 13 05:35:00 PM PDT 24
Peak memory 201888 kb
Host smart-6db44d1e-2dd4-4aa0-97e0-4773e22f19a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997475088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1997475088
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2960388421
Short name T494
Test name
Test status
Simulation time 1205138728 ps
CPU time 6.38 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:35:02 PM PDT 24
Peak memory 201932 kb
Host smart-fa3bb64e-fe18-4d30-9a6d-5ecbb4056470
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2960388421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2960388421
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.272433452
Short name T325
Test name
Test status
Simulation time 8334863 ps
CPU time 1.3 seconds
Started Aug 13 05:34:55 PM PDT 24
Finished Aug 13 05:34:56 PM PDT 24
Peak memory 201952 kb
Host smart-6dea8e26-89c7-45bf-8c6e-23324be6f8a2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272433452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.272433452
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2185323283
Short name T651
Test name
Test status
Simulation time 25310678466 ps
CPU time 59.95 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 203080 kb
Host smart-289b835e-9f80-4504-8ea8-a8885869b629
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2185323283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2185323283
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1379432336
Short name T535
Test name
Test status
Simulation time 506363829 ps
CPU time 32.26 seconds
Started Aug 13 05:35:01 PM PDT 24
Finished Aug 13 05:35:34 PM PDT 24
Peak memory 201944 kb
Host smart-bfb956ba-cfa9-417c-ba71-d4b9dcfb24af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1379432336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1379432336
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4284466097
Short name T526
Test name
Test status
Simulation time 746481247 ps
CPU time 121.1 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:37:06 PM PDT 24
Peak memory 204880 kb
Host smart-68a6eb3d-a291-4faf-a2d4-46a545cecc8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4284466097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.4284466097
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.494220019
Short name T573
Test name
Test status
Simulation time 4842161955 ps
CPU time 48.7 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 203500 kb
Host smart-680e5fde-de59-4a0a-b312-c1f9312e32d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=494220019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res
et_error.494220019
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3494777674
Short name T126
Test name
Test status
Simulation time 259631781 ps
CPU time 5.93 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201936 kb
Host smart-7539a4ad-9fd5-413c-a4b3-ac40a92cfadc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3494777674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3494777674
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.862215687
Short name T14
Test name
Test status
Simulation time 4324589545 ps
CPU time 13.41 seconds
Started Aug 13 05:35:00 PM PDT 24
Finished Aug 13 05:35:14 PM PDT 24
Peak memory 201976 kb
Host smart-1a78b115-5745-4207-af99-671dacb5a490
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862215687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.862215687
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1164895245
Short name T206
Test name
Test status
Simulation time 4656885924 ps
CPU time 30.67 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:37 PM PDT 24
Peak memory 202036 kb
Host smart-36054d65-0d7f-421c-8a90-8367d6e368fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1164895245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.1164895245
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1385728697
Short name T515
Test name
Test status
Simulation time 123393736 ps
CPU time 5.75 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:08 PM PDT 24
Peak memory 201936 kb
Host smart-a9a803e1-6a3b-4e79-94f9-8814364e2497
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1385728697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1385728697
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.1416955087
Short name T326
Test name
Test status
Simulation time 11266528 ps
CPU time 1.07 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:03 PM PDT 24
Peak memory 201968 kb
Host smart-117c8517-8d14-473c-b895-e81d82920c1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1416955087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1416955087
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.2587212122
Short name T144
Test name
Test status
Simulation time 648032827 ps
CPU time 9.92 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:13 PM PDT 24
Peak memory 201880 kb
Host smart-1ef073c3-1e72-4206-8bbd-3acd7a1dcbd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2587212122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2587212122
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2278697297
Short name T660
Test name
Test status
Simulation time 7165987600 ps
CPU time 23.41 seconds
Started Aug 13 05:35:00 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 201968 kb
Host smart-69f3d317-6453-48c8-9ca4-ef13a8663b82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278697297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2278697297
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2451677652
Short name T266
Test name
Test status
Simulation time 25918681211 ps
CPU time 104.48 seconds
Started Aug 13 05:35:01 PM PDT 24
Finished Aug 13 05:36:46 PM PDT 24
Peak memory 202028 kb
Host smart-59041499-59a5-43e8-8fe5-47a53aed49d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2451677652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2451677652
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3287924797
Short name T291
Test name
Test status
Simulation time 30925612 ps
CPU time 2.83 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:06 PM PDT 24
Peak memory 201920 kb
Host smart-28bba140-a691-4f4f-8aa0-748ec461e16d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287924797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3287924797
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.2804583477
Short name T789
Test name
Test status
Simulation time 1942110850 ps
CPU time 12.42 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:14 PM PDT 24
Peak memory 201912 kb
Host smart-104084c8-a21b-4b3b-81cd-90e3eb08041b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2804583477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2804583477
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.1886781247
Short name T847
Test name
Test status
Simulation time 507952861 ps
CPU time 1.87 seconds
Started Aug 13 05:35:01 PM PDT 24
Finished Aug 13 05:35:03 PM PDT 24
Peak memory 201876 kb
Host smart-5afcdaf4-a685-44a7-a476-8781a57c8ccc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1886781247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1886781247
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1031793740
Short name T327
Test name
Test status
Simulation time 7155195927 ps
CPU time 10.47 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:12 PM PDT 24
Peak memory 201980 kb
Host smart-e537afac-b215-4f38-9764-5fe9a4796e82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031793740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1031793740
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.749991111
Short name T165
Test name
Test status
Simulation time 2592003860 ps
CPU time 11.99 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:19 PM PDT 24
Peak memory 201916 kb
Host smart-c20aeea1-715d-41e0-a391-86574729f242
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=749991111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.749991111
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.783211780
Short name T434
Test name
Test status
Simulation time 9982581 ps
CPU time 1.46 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 201968 kb
Host smart-4031f762-73cb-49cc-8777-e056bf849b52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783211780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.783211780
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1094735900
Short name T724
Test name
Test status
Simulation time 46939084 ps
CPU time 3.87 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:07 PM PDT 24
Peak memory 201928 kb
Host smart-6224d011-8e32-4f49-b078-ef99a3532032
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1094735900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1094735900
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.4048641996
Short name T766
Test name
Test status
Simulation time 639054320 ps
CPU time 6.29 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201884 kb
Host smart-a72b7460-af0c-4ab2-9d67-7150e1d04503
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048641996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4048641996
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1961817675
Short name T827
Test name
Test status
Simulation time 8895952957 ps
CPU time 144.31 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 204544 kb
Host smart-9cdc43cf-e557-4788-9eaa-ee777d93ca99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1961817675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.1961817675
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4218600231
Short name T227
Test name
Test status
Simulation time 392822615 ps
CPU time 75.67 seconds
Started Aug 13 05:35:04 PM PDT 24
Finished Aug 13 05:36:20 PM PDT 24
Peak memory 205552 kb
Host smart-e17dea05-3e14-477d-9c64-4adc9dda2552
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4218600231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.4218600231
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.796564143
Short name T455
Test name
Test status
Simulation time 91889476 ps
CPU time 7.94 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:13 PM PDT 24
Peak memory 201968 kb
Host smart-d28204b9-5096-4340-9336-7d55360892cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=796564143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.796564143
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3961516750
Short name T109
Test name
Test status
Simulation time 1345300061 ps
CPU time 21.3 seconds
Started Aug 13 05:35:00 PM PDT 24
Finished Aug 13 05:35:22 PM PDT 24
Peak memory 201956 kb
Host smart-8db904e4-cc25-42ed-a156-6f1be56b6764
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3961516750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3961516750
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3655571965
Short name T198
Test name
Test status
Simulation time 94781370143 ps
CPU time 278.66 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:39:44 PM PDT 24
Peak memory 202960 kb
Host smart-bc27f68f-18d0-4d56-aed3-8729d91057f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3655571965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.3655571965
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.511156772
Short name T230
Test name
Test status
Simulation time 119256167 ps
CPU time 4.98 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:08 PM PDT 24
Peak memory 201956 kb
Host smart-c1e20f01-7416-4736-ba67-3ed12eacc20e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=511156772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.511156772
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.1736753943
Short name T683
Test name
Test status
Simulation time 600650543 ps
CPU time 9.9 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:13 PM PDT 24
Peak memory 201880 kb
Host smart-ff90fccd-3485-48bd-b294-3bd134859320
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1736753943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1736753943
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.55256500
Short name T829
Test name
Test status
Simulation time 40454711 ps
CPU time 3.49 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201756 kb
Host smart-b22421ed-1bb1-4a79-8a72-7d6d91855e91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55256500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.55256500
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2748038193
Short name T328
Test name
Test status
Simulation time 39391855557 ps
CPU time 70.82 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:36:14 PM PDT 24
Peak memory 201976 kb
Host smart-407d3066-01a6-4028-9f64-b0a32899441e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748038193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2748038193
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3994698348
Short name T241
Test name
Test status
Simulation time 3619743714 ps
CPU time 20.1 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:22 PM PDT 24
Peak memory 201976 kb
Host smart-3d3df9f2-14f4-4c61-9b6a-d3212e1e4093
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3994698348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3994698348
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1842317534
Short name T805
Test name
Test status
Simulation time 48242976 ps
CPU time 4.51 seconds
Started Aug 13 05:35:04 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201920 kb
Host smart-c5ad6788-c430-4f97-a559-2577c88175f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842317534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1842317534
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.2307566755
Short name T872
Test name
Test status
Simulation time 182532769 ps
CPU time 2.88 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201900 kb
Host smart-a8550779-448f-47bc-a3a7-2a14dadc0e45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2307566755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2307566755
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.1647254806
Short name T29
Test name
Test status
Simulation time 57878849 ps
CPU time 1.52 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 202068 kb
Host smart-a67a5a24-ab54-458b-ba02-30a9f16cc488
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1647254806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1647254806
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3412924415
Short name T549
Test name
Test status
Simulation time 1552311350 ps
CPU time 7.43 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201828 kb
Host smart-b9851803-8198-4267-8657-4e889c584dbb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412924415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3412924415
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1473577763
Short name T754
Test name
Test status
Simulation time 598438147 ps
CPU time 5.4 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201936 kb
Host smart-017dc4aa-b494-4c91-989d-632b48a25607
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1473577763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1473577763
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1227352891
Short name T472
Test name
Test status
Simulation time 9412700 ps
CPU time 1.24 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:07 PM PDT 24
Peak memory 201872 kb
Host smart-4c88e0ee-1c94-4a99-b382-f2a7db85d737
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227352891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1227352891
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1923791324
Short name T300
Test name
Test status
Simulation time 1254997260 ps
CPU time 25.23 seconds
Started Aug 13 05:35:01 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 201944 kb
Host smart-241b58e9-433a-4d26-81c3-cf9c1afc3748
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1923791324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1923791324
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1570603983
Short name T60
Test name
Test status
Simulation time 3554353454 ps
CPU time 61.65 seconds
Started Aug 13 05:35:12 PM PDT 24
Finished Aug 13 05:36:14 PM PDT 24
Peak memory 201948 kb
Host smart-4b1b4a8e-147d-4e1c-82d8-5f1d0da32216
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1570603983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1570603983
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1658058217
Short name T53
Test name
Test status
Simulation time 2370800797 ps
CPU time 83.71 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:36:25 PM PDT 24
Peak memory 205300 kb
Host smart-a4cdbcda-0c26-479e-8e96-c409c9926fb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658058217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1658058217
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1913761162
Short name T571
Test name
Test status
Simulation time 7251019 ps
CPU time 0.9 seconds
Started Aug 13 05:35:03 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 201900 kb
Host smart-a6ebcddf-76bf-4211-8979-262c50bbb068
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1913761162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.1913761162
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1468468038
Short name T561
Test name
Test status
Simulation time 14455223 ps
CPU time 1.45 seconds
Started Aug 13 05:35:01 PM PDT 24
Finished Aug 13 05:35:03 PM PDT 24
Peak memory 201868 kb
Host smart-59857fca-37a3-49a7-98a0-c901bd9bbfff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468468038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1468468038
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2750275808
Short name T151
Test name
Test status
Simulation time 181147097 ps
CPU time 3.07 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201852 kb
Host smart-f0ec46ed-ed6e-4c58-9f78-1788befde885
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2750275808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2750275808
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1490251176
Short name T722
Test name
Test status
Simulation time 83936866839 ps
CPU time 232.43 seconds
Started Aug 13 05:35:07 PM PDT 24
Finished Aug 13 05:38:59 PM PDT 24
Peak memory 203064 kb
Host smart-81263fe5-eaf0-4c98-a692-b81c11841725
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1490251176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.1490251176
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1044449219
Short name T64
Test name
Test status
Simulation time 10194016 ps
CPU time 1.17 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:35:14 PM PDT 24
Peak memory 201892 kb
Host smart-8182c913-fb55-4c0f-b9c2-6e573f49267b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1044449219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1044449219
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.284470289
Short name T86
Test name
Test status
Simulation time 52682573 ps
CPU time 1.63 seconds
Started Aug 13 05:35:10 PM PDT 24
Finished Aug 13 05:35:11 PM PDT 24
Peak memory 201880 kb
Host smart-445002cb-41d3-4a35-b34d-acb6d7fcb80e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284470289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.284470289
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.3183029688
Short name T316
Test name
Test status
Simulation time 406200140 ps
CPU time 2.59 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:04 PM PDT 24
Peak memory 201916 kb
Host smart-27e3330a-6efd-4b6c-816c-0bc7ea7eec91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3183029688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3183029688
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2283790667
Short name T133
Test name
Test status
Simulation time 4823035839 ps
CPU time 17 seconds
Started Aug 13 05:35:02 PM PDT 24
Finished Aug 13 05:35:19 PM PDT 24
Peak memory 201984 kb
Host smart-cf99a56c-bd7a-4df3-97fa-16a08b0cfbb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283790667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2283790667
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3104271588
Short name T711
Test name
Test status
Simulation time 4910687556 ps
CPU time 9.9 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201912 kb
Host smart-1939b7b9-2006-4e38-8415-d004a1a88a7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3104271588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3104271588
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3631668028
Short name T385
Test name
Test status
Simulation time 32126472 ps
CPU time 4.93 seconds
Started Aug 13 05:35:07 PM PDT 24
Finished Aug 13 05:35:12 PM PDT 24
Peak memory 201956 kb
Host smart-9fa1df9a-fff8-4f93-b0a3-f4b9f08279d9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631668028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3631668028
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3507964899
Short name T605
Test name
Test status
Simulation time 61842504 ps
CPU time 5.55 seconds
Started Aug 13 05:35:10 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201952 kb
Host smart-6d9084e4-f1eb-4367-9526-1b9d52be04fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3507964899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3507964899
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.2235434434
Short name T589
Test name
Test status
Simulation time 14519382 ps
CPU time 1.02 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:08 PM PDT 24
Peak memory 201904 kb
Host smart-536489e0-dca7-4184-b2d5-6cdf38b02f67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2235434434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2235434434
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1893574241
Short name T552
Test name
Test status
Simulation time 1887900910 ps
CPU time 9.08 seconds
Started Aug 13 05:35:06 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201916 kb
Host smart-dec29558-d231-4cde-9fc5-bdee1fe86c01
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893574241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1893574241
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3491991969
Short name T463
Test name
Test status
Simulation time 834533596 ps
CPU time 6.77 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:12 PM PDT 24
Peak memory 201900 kb
Host smart-e70b6a5d-e326-4c8c-95ee-bb41084a784b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3491991969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3491991969
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.453672128
Short name T428
Test name
Test status
Simulation time 15929607 ps
CPU time 1.31 seconds
Started Aug 13 05:35:04 PM PDT 24
Finished Aug 13 05:35:05 PM PDT 24
Peak memory 201884 kb
Host smart-c3496dfd-56f0-4d0d-8717-62e29b48c8b5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453672128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.453672128
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.3884862774
Short name T24
Test name
Test status
Simulation time 4046077049 ps
CPU time 65.01 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:36:13 PM PDT 24
Peak memory 203000 kb
Host smart-f98fd6cf-f16b-4de8-8678-75997abeb960
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3884862774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3884862774
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1726424808
Short name T873
Test name
Test status
Simulation time 5237937186 ps
CPU time 59.68 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:36:08 PM PDT 24
Peak memory 202032 kb
Host smart-162bf88b-3567-4613-8871-103a9bcfd97b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1726424808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1726424808
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.771923617
Short name T719
Test name
Test status
Simulation time 1047593676 ps
CPU time 138.59 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:37:27 PM PDT 24
Peak memory 204600 kb
Host smart-4b74c496-89ea-413a-bd0f-abbc69ca5dfb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=771923617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand
_reset.771923617
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2627976944
Short name T228
Test name
Test status
Simulation time 678335091 ps
CPU time 96.6 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:36:45 PM PDT 24
Peak memory 204184 kb
Host smart-1de89386-71f7-4950-bbfb-d646409f6076
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2627976944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.2627976944
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4211823342
Short name T336
Test name
Test status
Simulation time 427621520 ps
CPU time 7.74 seconds
Started Aug 13 05:35:07 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 202120 kb
Host smart-9eb63cf5-827f-4989-bd0e-52ec518eb2f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4211823342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4211823342
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3683785641
Short name T404
Test name
Test status
Simulation time 24346096 ps
CPU time 4.78 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:35:18 PM PDT 24
Peak memory 201872 kb
Host smart-4b7c2bd6-c31a-428e-b8d7-8399a9ba7053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3683785641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3683785641
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4185909927
Short name T59
Test name
Test status
Simulation time 23045447 ps
CPU time 1.03 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:09 PM PDT 24
Peak memory 201960 kb
Host smart-2efe7963-520e-4ff1-9720-851121404ef4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4185909927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4185909927
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2123875952
Short name T466
Test name
Test status
Simulation time 475225246 ps
CPU time 3.62 seconds
Started Aug 13 05:35:07 PM PDT 24
Finished Aug 13 05:35:11 PM PDT 24
Peak memory 201936 kb
Host smart-7f50425b-23e7-4b27-b841-8265b79de6ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2123875952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2123875952
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.223245625
Short name T185
Test name
Test status
Simulation time 70229868 ps
CPU time 1.94 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 201844 kb
Host smart-81e216e9-3979-4806-bcc8-a9340a84540d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223245625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.223245625
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3193908027
Short name T407
Test name
Test status
Simulation time 30299598240 ps
CPU time 99.82 seconds
Started Aug 13 05:35:10 PM PDT 24
Finished Aug 13 05:36:50 PM PDT 24
Peak memory 201972 kb
Host smart-a9ff0b09-7187-41ee-b511-00fee0df3c59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193908027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3193908027
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2141262923
Short name T767
Test name
Test status
Simulation time 11487669301 ps
CPU time 65.47 seconds
Started Aug 13 05:35:10 PM PDT 24
Finished Aug 13 05:36:15 PM PDT 24
Peak memory 202016 kb
Host smart-30bae73e-eafb-4a0e-a34d-6e5ffc3532b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2141262923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2141262923
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.4117945775
Short name T710
Test name
Test status
Simulation time 38468607 ps
CPU time 4.59 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:35:18 PM PDT 24
Peak memory 201872 kb
Host smart-32b322f9-6222-4db4-8859-fdb866a56e3b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117945775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4117945775
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.2559392390
Short name T21
Test name
Test status
Simulation time 1772116635 ps
CPU time 11 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:35:24 PM PDT 24
Peak memory 201884 kb
Host smart-1813bc7e-7c33-435b-badc-71d20bdeb63b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2559392390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2559392390
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.3385737116
Short name T878
Test name
Test status
Simulation time 240935739 ps
CPU time 1.65 seconds
Started Aug 13 05:35:09 PM PDT 24
Finished Aug 13 05:35:11 PM PDT 24
Peak memory 201916 kb
Host smart-352674c6-fe85-4906-8077-fbb08fa02a9b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3385737116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3385737116
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1371010057
Short name T334
Test name
Test status
Simulation time 3081726013 ps
CPU time 7.26 seconds
Started Aug 13 05:35:05 PM PDT 24
Finished Aug 13 05:35:13 PM PDT 24
Peak memory 201868 kb
Host smart-500a8d8e-2e2e-4d9c-bcc5-70d4b1a9ebfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371010057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1371010057
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3620543748
Short name T861
Test name
Test status
Simulation time 972076382 ps
CPU time 7.96 seconds
Started Aug 13 05:35:09 PM PDT 24
Finished Aug 13 05:35:17 PM PDT 24
Peak memory 201916 kb
Host smart-d09c1c34-6a1c-4a86-b53b-c67f712a28f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3620543748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3620543748
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2039085937
Short name T315
Test name
Test status
Simulation time 8845096 ps
CPU time 1.26 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:10 PM PDT 24
Peak memory 201964 kb
Host smart-0f3f50aa-1a40-4a76-aac5-1c462565aa0a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039085937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2039085937
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2095716903
Short name T18
Test name
Test status
Simulation time 5441260563 ps
CPU time 73.6 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:36:28 PM PDT 24
Peak memory 204420 kb
Host smart-64afe934-38ad-4482-81f5-6469579f9718
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2095716903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2095716903
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2548817542
Short name T867
Test name
Test status
Simulation time 9694345165 ps
CPU time 57.65 seconds
Started Aug 13 05:35:07 PM PDT 24
Finished Aug 13 05:36:05 PM PDT 24
Peak memory 203052 kb
Host smart-18a40f6d-ad24-4ed6-9be6-e2bee3481510
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2548817542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2548817542
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3926333390
Short name T179
Test name
Test status
Simulation time 344068980 ps
CPU time 33.93 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:42 PM PDT 24
Peak memory 203048 kb
Host smart-f646f4d2-ca81-4a02-9eac-942a8382483f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3926333390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.3926333390
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.4136362833
Short name T7
Test name
Test status
Simulation time 288623342 ps
CPU time 49.77 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 203112 kb
Host smart-b77d987a-2f7c-4e60-a475-9d58ae9ace1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4136362833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.4136362833
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3010425585
Short name T782
Test name
Test status
Simulation time 303344004 ps
CPU time 7.4 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 201904 kb
Host smart-8a3bc4ee-03e6-4a67-a87f-92f3fd765d4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3010425585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3010425585
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2019478865
Short name T436
Test name
Test status
Simulation time 203491520 ps
CPU time 4.55 seconds
Started Aug 13 05:35:09 PM PDT 24
Finished Aug 13 05:35:14 PM PDT 24
Peak memory 201964 kb
Host smart-e7eb0cd3-b17c-49f4-9b9c-ebf0b00b1f95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2019478865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2019478865
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4226777984
Short name T783
Test name
Test status
Simulation time 23800159100 ps
CPU time 156.04 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:38:05 PM PDT 24
Peak memory 203060 kb
Host smart-de69e77a-f7d3-4995-bc8f-de053f6ff2da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4226777984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.4226777984
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1775720557
Short name T392
Test name
Test status
Simulation time 131543108 ps
CPU time 2.23 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:35:23 PM PDT 24
Peak memory 201980 kb
Host smart-931f7e77-ebc1-4f01-8cbd-23d6549bbde6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1775720557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1775720557
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.83536047
Short name T886
Test name
Test status
Simulation time 42832256 ps
CPU time 3.73 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 201884 kb
Host smart-b4d8dd20-631c-4740-aa9f-26647943aa3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83536047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.83536047
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.765743723
Short name T846
Test name
Test status
Simulation time 62514942 ps
CPU time 6.06 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:20 PM PDT 24
Peak memory 201840 kb
Host smart-847ef96a-521e-4316-9b59-551c151bc5df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=765743723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.765743723
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2357934139
Short name T310
Test name
Test status
Simulation time 4421619814 ps
CPU time 8.13 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:16 PM PDT 24
Peak memory 201984 kb
Host smart-852441b2-f6bf-4858-a19f-e476a6ba1cb5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357934139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2357934139
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3160153795
Short name T503
Test name
Test status
Simulation time 35145189628 ps
CPU time 100.77 seconds
Started Aug 13 05:35:09 PM PDT 24
Finished Aug 13 05:36:50 PM PDT 24
Peak memory 202032 kb
Host smart-1d095373-deae-4839-80b7-84e1f3343680
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3160153795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3160153795
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3248899201
Short name T237
Test name
Test status
Simulation time 71816919 ps
CPU time 7.53 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201928 kb
Host smart-d9c9d2db-cc97-4ff7-b293-12cf240eb1d7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248899201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3248899201
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.2023437416
Short name T634
Test name
Test status
Simulation time 29789274 ps
CPU time 1.63 seconds
Started Aug 13 05:35:24 PM PDT 24
Finished Aug 13 05:35:25 PM PDT 24
Peak memory 201980 kb
Host smart-18bcc258-4597-4d03-bc4d-b524416d036b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2023437416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2023437416
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.1226903162
Short name T788
Test name
Test status
Simulation time 60843422 ps
CPU time 1.93 seconds
Started Aug 13 05:35:15 PM PDT 24
Finished Aug 13 05:35:17 PM PDT 24
Peak memory 201836 kb
Host smart-b656faac-dad2-4647-8efa-d4bf342caa52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1226903162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1226903162
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2455283247
Short name T834
Test name
Test status
Simulation time 8915548013 ps
CPU time 11.27 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:19 PM PDT 24
Peak memory 201992 kb
Host smart-753b92af-832f-4f2c-a97c-f54deca9ab23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455283247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2455283247
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1927316834
Short name T837
Test name
Test status
Simulation time 9726385251 ps
CPU time 8.91 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:17 PM PDT 24
Peak memory 202032 kb
Host smart-6140a0f6-2514-4f40-830b-aa9840821a51
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1927316834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1927316834
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3878541502
Short name T657
Test name
Test status
Simulation time 9881185 ps
CPU time 1.36 seconds
Started Aug 13 05:35:08 PM PDT 24
Finished Aug 13 05:35:10 PM PDT 24
Peak memory 201948 kb
Host smart-aeaf5664-c494-4acf-8d2e-95683e73f78a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878541502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3878541502
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3822321760
Short name T42
Test name
Test status
Simulation time 311455058 ps
CPU time 47.24 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 204740 kb
Host smart-0a913ce8-afc7-4f3d-971b-cdf53a66cb79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3822321760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3822321760
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.273062519
Short name T748
Test name
Test status
Simulation time 11990998980 ps
CPU time 70.63 seconds
Started Aug 13 05:35:15 PM PDT 24
Finished Aug 13 05:36:26 PM PDT 24
Peak memory 203136 kb
Host smart-93583300-3523-4fe3-93cb-b0ca66deaae2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273062519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.273062519
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.975988049
Short name T36
Test name
Test status
Simulation time 1789313853 ps
CPU time 115.98 seconds
Started Aug 13 05:35:24 PM PDT 24
Finished Aug 13 05:37:20 PM PDT 24
Peak memory 205560 kb
Host smart-9c5ca219-7e14-4da3-b694-15c704e4ad67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=975988049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand
_reset.975988049
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2473450875
Short name T265
Test name
Test status
Simulation time 193012716 ps
CPU time 31 seconds
Started Aug 13 05:35:15 PM PDT 24
Finished Aug 13 05:35:46 PM PDT 24
Peak memory 204084 kb
Host smart-50d23a0b-b4c1-4f77-bd6e-989b819ddd48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2473450875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.2473450875
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1494949216
Short name T317
Test name
Test status
Simulation time 17979856 ps
CPU time 1.38 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201872 kb
Host smart-d60ba0b6-828a-403d-86ef-184c345f4ee8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1494949216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1494949216
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1813831037
Short name T883
Test name
Test status
Simulation time 21030919 ps
CPU time 3.02 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:25 PM PDT 24
Peak memory 201952 kb
Host smart-9d64467a-7dd9-4b85-b0f9-a797ec008e09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1813831037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1813831037
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2079802597
Short name T548
Test name
Test status
Simulation time 741324868 ps
CPU time 3.61 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:32 PM PDT 24
Peak memory 201284 kb
Host smart-bc4605f9-dd0f-4d4b-9036-46687deb618b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2079802597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2079802597
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2652900125
Short name T299
Test name
Test status
Simulation time 195652045 ps
CPU time 3.95 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:18 PM PDT 24
Peak memory 201976 kb
Host smart-2f9af4b5-c2bf-45e9-b355-bffb5fac615b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2652900125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2652900125
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.600963147
Short name T606
Test name
Test status
Simulation time 67379630 ps
CPU time 2.38 seconds
Started Aug 13 05:35:28 PM PDT 24
Finished Aug 13 05:35:31 PM PDT 24
Peak memory 201136 kb
Host smart-4cb72dec-dfa3-40a6-87f4-762fb9325052
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=600963147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.600963147
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.832446902
Short name T65
Test name
Test status
Simulation time 33701538370 ps
CPU time 86.79 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:36:49 PM PDT 24
Peak memory 201952 kb
Host smart-ed65afba-87f9-4f35-8026-23980f03cdb1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=832446902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.832446902
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1793687453
Short name T31
Test name
Test status
Simulation time 60207034795 ps
CPU time 129.36 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:37:31 PM PDT 24
Peak memory 201948 kb
Host smart-1bf33b9d-635a-4b47-85ad-43d16a667539
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1793687453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1793687453
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1661121758
Short name T233
Test name
Test status
Simulation time 89902750 ps
CPU time 3.78 seconds
Started Aug 13 05:35:15 PM PDT 24
Finished Aug 13 05:35:19 PM PDT 24
Peak memory 201952 kb
Host smart-479e7ed0-8bd5-4872-bf3d-aec7f43b124e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661121758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1661121758
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.814812620
Short name T329
Test name
Test status
Simulation time 826736969 ps
CPU time 9.06 seconds
Started Aug 13 05:35:23 PM PDT 24
Finished Aug 13 05:35:32 PM PDT 24
Peak memory 201892 kb
Host smart-0fe3822e-5aca-450a-9881-603ccf30e519
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=814812620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.814812620
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.312027168
Short name T415
Test name
Test status
Simulation time 21389783 ps
CPU time 1.16 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:15 PM PDT 24
Peak memory 201904 kb
Host smart-ede62f7e-6286-410c-b0c9-9171a180cc23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=312027168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.312027168
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2813521252
Short name T378
Test name
Test status
Simulation time 2052149354 ps
CPU time 10.18 seconds
Started Aug 13 05:35:22 PM PDT 24
Finished Aug 13 05:35:32 PM PDT 24
Peak memory 201828 kb
Host smart-5c8e4852-8b3c-4b0c-8a7b-c4a34b1f630d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813521252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2813521252
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.92690897
Short name T705
Test name
Test status
Simulation time 1403581621 ps
CPU time 8.03 seconds
Started Aug 13 05:35:34 PM PDT 24
Finished Aug 13 05:35:43 PM PDT 24
Peak memory 201880 kb
Host smart-fcb3f1ad-e99d-4b76-ba0c-e5b3ab4ee7dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=92690897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.92690897
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2910421935
Short name T759
Test name
Test status
Simulation time 9270272 ps
CPU time 1.25 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:26 PM PDT 24
Peak memory 201892 kb
Host smart-3b362f9b-c881-4c6f-ac8b-f43c0f2e1df6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910421935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2910421935
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1572352558
Short name T183
Test name
Test status
Simulation time 13815086230 ps
CPU time 80.13 seconds
Started Aug 13 05:35:21 PM PDT 24
Finished Aug 13 05:36:41 PM PDT 24
Peak memory 204396 kb
Host smart-ee1bb655-5440-41cc-ae89-406e24949f24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1572352558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1572352558
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3503099689
Short name T296
Test name
Test status
Simulation time 2953983559 ps
CPU time 39.67 seconds
Started Aug 13 05:35:14 PM PDT 24
Finished Aug 13 05:35:54 PM PDT 24
Peak memory 201996 kb
Host smart-bd591306-c199-4034-8bd5-b83da04d8334
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3503099689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3503099689
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4152977712
Short name T129
Test name
Test status
Simulation time 709006587 ps
CPU time 68.62 seconds
Started Aug 13 05:35:13 PM PDT 24
Finished Aug 13 05:36:22 PM PDT 24
Peak memory 204748 kb
Host smart-22ec2f0c-8a83-4c99-bffa-d7c5bb657241
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4152977712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.4152977712
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2773918371
Short name T464
Test name
Test status
Simulation time 103426792 ps
CPU time 12.57 seconds
Started Aug 13 05:35:25 PM PDT 24
Finished Aug 13 05:35:38 PM PDT 24
Peak memory 201888 kb
Host smart-2f2e132d-ff50-4baf-be56-874f2f64b96e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2773918371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.2773918371
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3140152353
Short name T45
Test name
Test status
Simulation time 565148910 ps
CPU time 4.77 seconds
Started Aug 13 05:35:15 PM PDT 24
Finished Aug 13 05:35:20 PM PDT 24
Peak memory 201928 kb
Host smart-40556d2f-d5db-412a-9cd3-10b814437ec7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3140152353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3140152353
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3325757354
Short name T117
Test name
Test status
Simulation time 643717637 ps
CPU time 9.18 seconds
Started Aug 13 05:33:04 PM PDT 24
Finished Aug 13 05:33:13 PM PDT 24
Peak memory 201956 kb
Host smart-d4790241-4d6b-42c2-ba89-aa7184d1097f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3325757354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3325757354
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3055137322
Short name T216
Test name
Test status
Simulation time 37201912956 ps
CPU time 130.38 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:35:11 PM PDT 24
Peak memory 203020 kb
Host smart-9fbaab61-5bb3-4f1e-b68c-52f5f55fa46e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3055137322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3055137322
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4236795097
Short name T891
Test name
Test status
Simulation time 40906638 ps
CPU time 2.92 seconds
Started Aug 13 05:33:03 PM PDT 24
Finished Aug 13 05:33:06 PM PDT 24
Peak memory 201956 kb
Host smart-8f41adb0-eaea-4caf-94b4-f78ee347c8f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236795097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4236795097
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.3037612410
Short name T497
Test name
Test status
Simulation time 8949443 ps
CPU time 1.35 seconds
Started Aug 13 05:33:02 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201924 kb
Host smart-3fe7029c-8153-46d7-afe6-6d5f5dd66ebe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037612410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3037612410
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.2224877582
Short name T532
Test name
Test status
Simulation time 153388708 ps
CPU time 2.84 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201904 kb
Host smart-92945b63-51d7-4e8a-aab7-5e83cda83b0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2224877582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2224877582
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.504919087
Short name T157
Test name
Test status
Simulation time 55800368949 ps
CPU time 96.76 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:34:38 PM PDT 24
Peak memory 201980 kb
Host smart-dab7daac-8815-44ee-87ab-0f6071f1acc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=504919087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.504919087
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2951870500
Short name T413
Test name
Test status
Simulation time 2872199515 ps
CPU time 14.77 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:15 PM PDT 24
Peak memory 202028 kb
Host smart-a35050ae-286d-4da9-a350-41854d0680ac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2951870500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2951870500
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2067955215
Short name T496
Test name
Test status
Simulation time 13867198 ps
CPU time 1.51 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:32:58 PM PDT 24
Peak memory 202120 kb
Host smart-42a38757-1850-4ad5-be55-9390c744a404
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067955215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2067955215
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.3959500238
Short name T518
Test name
Test status
Simulation time 17073852 ps
CPU time 2.3 seconds
Started Aug 13 05:33:02 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201936 kb
Host smart-400de54c-6481-4d86-89d9-3b1641073a5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3959500238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3959500238
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.224397900
Short name T560
Test name
Test status
Simulation time 9148499 ps
CPU time 1.29 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:02 PM PDT 24
Peak memory 201808 kb
Host smart-b7af6644-eebe-447e-ad61-6c27b18e9e46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=224397900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.224397900
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3574478846
Short name T353
Test name
Test status
Simulation time 4409305884 ps
CPU time 13.75 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:12 PM PDT 24
Peak memory 201976 kb
Host smart-3bb07b00-469d-4447-aa6b-8dd33b2fad7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574478846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3574478846
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3107829706
Short name T399
Test name
Test status
Simulation time 1048086469 ps
CPU time 8.06 seconds
Started Aug 13 05:33:04 PM PDT 24
Finished Aug 13 05:33:12 PM PDT 24
Peak memory 201920 kb
Host smart-c01b337a-a334-46af-a671-53a98f6b366e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3107829706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3107829706
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.805358236
Short name T762
Test name
Test status
Simulation time 19139587 ps
CPU time 1.07 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:33:02 PM PDT 24
Peak memory 201968 kb
Host smart-f88c5f60-ac86-45df-9b74-9a438d1b3e3d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805358236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.805358236
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3849350517
Short name T243
Test name
Test status
Simulation time 5185045395 ps
CPU time 57.16 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:55 PM PDT 24
Peak memory 203020 kb
Host smart-2a702a0f-a8c3-460e-9ecf-813ee4d1b526
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3849350517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3849350517
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1479937394
Short name T617
Test name
Test status
Simulation time 1013094081 ps
CPU time 23.79 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:22 PM PDT 24
Peak memory 201924 kb
Host smart-9a88f00c-2f97-4f4f-b9be-37134c9282e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1479937394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1479937394
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3017141479
Short name T630
Test name
Test status
Simulation time 48214499 ps
CPU time 4.79 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201928 kb
Host smart-e3c925fd-089b-4f76-956b-3f6b1d95891b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3017141479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3017141479
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2192814226
Short name T73
Test name
Test status
Simulation time 775745318 ps
CPU time 96.42 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:34:33 PM PDT 24
Peak memory 204808 kb
Host smart-73f6358e-d382-4ef0-bbc8-1d295f8c746a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2192814226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.2192814226
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3983678161
Short name T622
Test name
Test status
Simulation time 1609043040 ps
CPU time 13.2 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:12 PM PDT 24
Peak memory 201892 kb
Host smart-3e883ae4-12b0-4f6e-9041-49bd5084de0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3983678161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3983678161
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.214027440
Short name T850
Test name
Test status
Simulation time 43902368 ps
CPU time 9.32 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:33:11 PM PDT 24
Peak memory 201824 kb
Host smart-cc546f6a-fb37-491b-9a6c-9c1f4ea07541
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=214027440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.214027440
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.12810048
Short name T219
Test name
Test status
Simulation time 3160204681 ps
CPU time 18.1 seconds
Started Aug 13 05:32:57 PM PDT 24
Finished Aug 13 05:33:15 PM PDT 24
Peak memory 201920 kb
Host smart-3b676cbe-b505-4737-ab27-d04bfd01f95a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=12810048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.12810048
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2202507359
Short name T678
Test name
Test status
Simulation time 252488060 ps
CPU time 5.85 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:33:07 PM PDT 24
Peak memory 201924 kb
Host smart-efcd46be-043d-44de-9eb1-524207e3d253
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2202507359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2202507359
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.943131137
Short name T401
Test name
Test status
Simulation time 703373197 ps
CPU time 10.41 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:33:10 PM PDT 24
Peak memory 201876 kb
Host smart-2bba8064-2e99-4e1f-9be7-a577997211c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=943131137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.943131137
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.2631736456
Short name T380
Test name
Test status
Simulation time 1135566740 ps
CPU time 14.37 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:14 PM PDT 24
Peak memory 201840 kb
Host smart-31d6d99a-f149-4c83-befe-1ba1ff06da94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2631736456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2631736456
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.473579926
Short name T190
Test name
Test status
Simulation time 31818309611 ps
CPU time 147.38 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:35:27 PM PDT 24
Peak memory 201988 kb
Host smart-8b1c059d-86be-462a-8ed8-cbb197f3b61f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473579926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.473579926
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1063987659
Short name T591
Test name
Test status
Simulation time 58658945279 ps
CPU time 112.99 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:34:51 PM PDT 24
Peak memory 201876 kb
Host smart-56550fb2-e72f-4a8f-95f8-b469d0f200b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1063987659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1063987659
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.752984058
Short name T736
Test name
Test status
Simulation time 36676301 ps
CPU time 5.22 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:33:01 PM PDT 24
Peak memory 201916 kb
Host smart-344ee102-8625-43c5-9892-7a4f2997c69c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752984058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.752984058
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.3310244356
Short name T790
Test name
Test status
Simulation time 53306668 ps
CPU time 5.34 seconds
Started Aug 13 05:33:02 PM PDT 24
Finished Aug 13 05:33:07 PM PDT 24
Peak memory 201952 kb
Host smart-68f924ea-200e-47f5-bc00-d04ca9073872
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3310244356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3310244356
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.1664949059
Short name T350
Test name
Test status
Simulation time 8785773 ps
CPU time 1.15 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:33:02 PM PDT 24
Peak memory 201912 kb
Host smart-1048062c-4ee2-43f3-8836-f4635f4d6d49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1664949059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1664949059
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.724927674
Short name T800
Test name
Test status
Simulation time 3932075828 ps
CPU time 7.25 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:05 PM PDT 24
Peak memory 201988 kb
Host smart-f9c133d5-cd20-4b77-bc73-c01b06a3acd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=724927674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.724927674
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1898851373
Short name T447
Test name
Test status
Simulation time 2288133762 ps
CPU time 12.3 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:33:13 PM PDT 24
Peak memory 202024 kb
Host smart-19f60d3b-d525-447f-b16c-1da9ae966f28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1898851373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1898851373
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1976220401
Short name T715
Test name
Test status
Simulation time 14290956 ps
CPU time 1.29 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:32:59 PM PDT 24
Peak memory 201968 kb
Host smart-3b5c23c6-017b-4575-9faf-b65c37489e1a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976220401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1976220401
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3083643062
Short name T391
Test name
Test status
Simulation time 44024242 ps
CPU time 4.4 seconds
Started Aug 13 05:32:59 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201868 kb
Host smart-0b7b4ed6-f02c-40bb-9b8e-c597e97a7067
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3083643062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3083643062
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.499659354
Short name T669
Test name
Test status
Simulation time 4357970870 ps
CPU time 43.6 seconds
Started Aug 13 05:33:01 PM PDT 24
Finished Aug 13 05:33:45 PM PDT 24
Peak memory 201956 kb
Host smart-d0fccbb2-3144-47a0-a9e1-bac8f14731bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=499659354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.499659354
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2347384637
Short name T636
Test name
Test status
Simulation time 1194204772 ps
CPU time 64.03 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:34:02 PM PDT 24
Peak memory 202896 kb
Host smart-5edcf4dd-980e-4434-b71c-b14efaede2d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2347384637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.2347384637
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1395457038
Short name T802
Test name
Test status
Simulation time 199615724 ps
CPU time 1.65 seconds
Started Aug 13 05:33:02 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201924 kb
Host smart-81dbd3c5-5b5b-4c00-aaa4-7a63ee604f28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1395457038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1395457038
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1119727910
Short name T663
Test name
Test status
Simulation time 971395136 ps
CPU time 23.17 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:23 PM PDT 24
Peak memory 201932 kb
Host smart-823ee463-6080-4d8d-a029-9107d46ea0c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1119727910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1119727910
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2532016754
Short name T195
Test name
Test status
Simulation time 38606587664 ps
CPU time 204.06 seconds
Started Aug 13 05:33:03 PM PDT 24
Finished Aug 13 05:36:27 PM PDT 24
Peak memory 203360 kb
Host smart-cca614f2-89e4-4aa2-9b87-4deafab0e644
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2532016754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.2532016754
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.340677019
Short name T461
Test name
Test status
Simulation time 573454514 ps
CPU time 5.69 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:13 PM PDT 24
Peak memory 201872 kb
Host smart-6e25fd56-904c-43c0-a8c2-229dd793dc9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=340677019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.340677019
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.2222517570
Short name T256
Test name
Test status
Simulation time 194000748 ps
CPU time 4.6 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:13 PM PDT 24
Peak memory 201968 kb
Host smart-7ee1fa86-8409-4a81-b564-1462f5b269cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2222517570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2222517570
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.1932696795
Short name T587
Test name
Test status
Simulation time 36746413 ps
CPU time 6.17 seconds
Started Aug 13 05:32:57 PM PDT 24
Finished Aug 13 05:33:04 PM PDT 24
Peak memory 201788 kb
Host smart-84d6e2b9-aa2e-4dd9-8cb9-fecd831d760d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1932696795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1932696795
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2645778287
Short name T396
Test name
Test status
Simulation time 49363504691 ps
CPU time 51.36 seconds
Started Aug 13 05:32:58 PM PDT 24
Finished Aug 13 05:33:49 PM PDT 24
Peak memory 201972 kb
Host smart-e73f0c1e-218a-418f-8cee-f74d51f548be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645778287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2645778287
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.851638899
Short name T258
Test name
Test status
Simulation time 19345490602 ps
CPU time 43.83 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:44 PM PDT 24
Peak memory 202028 kb
Host smart-d0ec3888-2e63-439f-a6c8-c0dc97c24b07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=851638899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.851638899
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2401446907
Short name T570
Test name
Test status
Simulation time 65008979 ps
CPU time 7.03 seconds
Started Aug 13 05:32:56 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201872 kb
Host smart-d89546bb-e237-4c3c-a2fd-a593118fdfca
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401446907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2401446907
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2399709598
Short name T559
Test name
Test status
Simulation time 449624031 ps
CPU time 5.44 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:33:18 PM PDT 24
Peak memory 201972 kb
Host smart-1655e05a-6ada-49eb-954e-8fb831782ea3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2399709598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2399709598
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.568237921
Short name T405
Test name
Test status
Simulation time 11632008 ps
CPU time 1.04 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:01 PM PDT 24
Peak memory 201752 kb
Host smart-fb9b65a7-0377-4b69-8ece-468129c8ffc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=568237921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.568237921
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.202470897
Short name T164
Test name
Test status
Simulation time 3651579579 ps
CPU time 7.95 seconds
Started Aug 13 05:32:57 PM PDT 24
Finished Aug 13 05:33:05 PM PDT 24
Peak memory 201980 kb
Host smart-55d14d36-4a72-40bc-8a23-c885450ebc6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=202470897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.202470897
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.848408848
Short name T860
Test name
Test status
Simulation time 1420692402 ps
CPU time 10.65 seconds
Started Aug 13 05:33:00 PM PDT 24
Finished Aug 13 05:33:11 PM PDT 24
Peak memory 201920 kb
Host smart-bbd4bb69-868b-4826-ba4e-15ae53b7f9e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=848408848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.848408848
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.497703581
Short name T797
Test name
Test status
Simulation time 13680294 ps
CPU time 1.11 seconds
Started Aug 13 05:33:02 PM PDT 24
Finished Aug 13 05:33:03 PM PDT 24
Peak memory 201928 kb
Host smart-73e17c96-56bf-44a7-9a7b-3ae1cf2cc9e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497703581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.497703581
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2293997919
Short name T278
Test name
Test status
Simulation time 1437840629 ps
CPU time 13.46 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:33:20 PM PDT 24
Peak memory 201872 kb
Host smart-83eb1a81-103c-41cf-87e5-3fb4cdb4e99b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2293997919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2293997919
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3644556806
Short name T851
Test name
Test status
Simulation time 597593862 ps
CPU time 59.24 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:34:08 PM PDT 24
Peak memory 202980 kb
Host smart-4a09c89b-73f6-4e9e-8047-c01875cd9e02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3644556806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3644556806
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.291227012
Short name T153
Test name
Test status
Simulation time 624780024 ps
CPU time 52.73 seconds
Started Aug 13 05:33:10 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 204224 kb
Host smart-ad57e940-6742-4abc-a3d6-19441c330d77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291227012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_
reset.291227012
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1787811485
Short name T723
Test name
Test status
Simulation time 212486513 ps
CPU time 26.11 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:34 PM PDT 24
Peak memory 203136 kb
Host smart-d4e1028d-ca3e-4db1-8f98-2cafbcfca41c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1787811485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.1787811485
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1987540013
Short name T13
Test name
Test status
Simulation time 454083175 ps
CPU time 8.51 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:33:16 PM PDT 24
Peak memory 201960 kb
Host smart-e1a3ad87-219c-4e3a-a2a5-e3837a1960fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1987540013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1987540013
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.547240309
Short name T56
Test name
Test status
Simulation time 1620643247 ps
CPU time 21.41 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:33:29 PM PDT 24
Peak memory 201888 kb
Host smart-477c0fbe-591c-430b-a71f-c7b6a46dbf54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547240309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.547240309
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1908449902
Short name T217
Test name
Test status
Simulation time 87905554796 ps
CPU time 220.26 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:36:48 PM PDT 24
Peak memory 203048 kb
Host smart-86eec6f0-8ac5-40ba-bbcb-f057f4e2f53f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1908449902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.1908449902
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1813389014
Short name T880
Test name
Test status
Simulation time 13104204 ps
CPU time 1.37 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:08 PM PDT 24
Peak memory 201880 kb
Host smart-7f3bf28c-90f6-4c48-b1c0-698fb0a2d8fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1813389014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1813389014
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2694785185
Short name T115
Test name
Test status
Simulation time 3121363030 ps
CPU time 10.19 seconds
Started Aug 13 05:33:04 PM PDT 24
Finished Aug 13 05:33:14 PM PDT 24
Peak memory 201984 kb
Host smart-cdf9e7fa-bf20-4d04-9a0b-42c3f20b0da3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2694785185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2694785185
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1546695939
Short name T35
Test name
Test status
Simulation time 1088066277 ps
CPU time 13.08 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:20 PM PDT 24
Peak memory 201908 kb
Host smart-b8aa58ca-5468-4d38-b0f6-74324f934847
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1546695939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1546695939
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1706351012
Short name T108
Test name
Test status
Simulation time 36894173262 ps
CPU time 159.2 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:35:47 PM PDT 24
Peak memory 201972 kb
Host smart-84279036-e544-4e58-a33e-e1e5f8f55946
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706351012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1706351012
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2592840199
Short name T23
Test name
Test status
Simulation time 20834135106 ps
CPU time 109.95 seconds
Started Aug 13 05:33:05 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 201960 kb
Host smart-4b4302ce-4071-417a-9a04-36851bdb4460
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2592840199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2592840199
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3998428662
Short name T716
Test name
Test status
Simulation time 82612375 ps
CPU time 4.19 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:33:12 PM PDT 24
Peak memory 201868 kb
Host smart-8b4d7549-b11c-4465-bf73-f4c9f349b4ec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998428662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3998428662
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.3435348387
Short name T900
Test name
Test status
Simulation time 437128105 ps
CPU time 4.72 seconds
Started Aug 13 05:33:05 PM PDT 24
Finished Aug 13 05:33:10 PM PDT 24
Peak memory 201944 kb
Host smart-dcabe816-792e-4845-a3d5-05778038a85e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3435348387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3435348387
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.3277593340
Short name T37
Test name
Test status
Simulation time 12179753 ps
CPU time 1.01 seconds
Started Aug 13 05:33:11 PM PDT 24
Finished Aug 13 05:33:12 PM PDT 24
Peak memory 201924 kb
Host smart-1bee9408-b419-45a0-b2e3-39dce07648ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3277593340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3277593340
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2569876682
Short name T141
Test name
Test status
Simulation time 4382491139 ps
CPU time 11.43 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:20 PM PDT 24
Peak memory 201900 kb
Host smart-66b9813d-3f38-4492-97ff-fcfa6e422c12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569876682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2569876682
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2101265054
Short name T70
Test name
Test status
Simulation time 2069525170 ps
CPU time 10.95 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:17 PM PDT 24
Peak memory 201980 kb
Host smart-cae24a67-dd7f-4934-899a-aea8322a69b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2101265054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2101265054
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3010446058
Short name T862
Test name
Test status
Simulation time 10260336 ps
CPU time 1.28 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:07 PM PDT 24
Peak memory 201888 kb
Host smart-9ffbdd0c-9b83-4f41-b2be-c437340f4857
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010446058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3010446058
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.46026335
Short name T756
Test name
Test status
Simulation time 988529720 ps
CPU time 19.74 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:33:27 PM PDT 24
Peak memory 201904 kb
Host smart-612908dd-a2f4-4704-b641-50e67bb91dd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46026335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.46026335
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2903512557
Short name T540
Test name
Test status
Simulation time 4278242615 ps
CPU time 48.88 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:57 PM PDT 24
Peak memory 201792 kb
Host smart-c5ed5a64-d83c-4617-8350-f1b6535be812
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2903512557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2903512557
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.720750718
Short name T816
Test name
Test status
Simulation time 1510202857 ps
CPU time 174.73 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:36:02 PM PDT 24
Peak memory 204316 kb
Host smart-4db4ba53-0845-4415-ad38-ec9e7ad158f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=720750718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_
reset.720750718
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.298135440
Short name T240
Test name
Test status
Simulation time 12531749 ps
CPU time 1.38 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:07 PM PDT 24
Peak memory 201800 kb
Host smart-7869be48-3831-43ec-9b94-703b1a374a8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=298135440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.298135440
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.875531099
Short name T643
Test name
Test status
Simulation time 1403819303 ps
CPU time 17.54 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:26 PM PDT 24
Peak memory 201824 kb
Host smart-1524e99a-39f5-4ea2-bfe3-8727411c3bfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=875531099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.875531099
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3929993310
Short name T99
Test name
Test status
Simulation time 83884560543 ps
CPU time 224.34 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:36:50 PM PDT 24
Peak memory 203068 kb
Host smart-e7428f84-0ea9-418e-af23-e296f7807c5a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3929993310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.3929993310
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.708976098
Short name T690
Test name
Test status
Simulation time 88252526 ps
CPU time 4.91 seconds
Started Aug 13 05:33:14 PM PDT 24
Finished Aug 13 05:33:19 PM PDT 24
Peak memory 201968 kb
Host smart-6036ce13-07cf-4a53-ba14-acabd8a2bb93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708976098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.708976098
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2596259002
Short name T655
Test name
Test status
Simulation time 1033267881 ps
CPU time 12.27 seconds
Started Aug 13 05:33:13 PM PDT 24
Finished Aug 13 05:33:26 PM PDT 24
Peak memory 201860 kb
Host smart-dbd42623-67da-4476-82cb-f2d5321814fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596259002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2596259002
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1399185650
Short name T346
Test name
Test status
Simulation time 1304015964 ps
CPU time 10.47 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:19 PM PDT 24
Peak memory 201708 kb
Host smart-d5dc1f30-abbc-4d9f-9893-caf61ced9c0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1399185650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1399185650
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1203887445
Short name T742
Test name
Test status
Simulation time 43318302973 ps
CPU time 169.58 seconds
Started Aug 13 05:33:09 PM PDT 24
Finished Aug 13 05:35:58 PM PDT 24
Peak memory 201996 kb
Host smart-aa351e08-6fe5-4582-9e7f-b0ed637890a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203887445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1203887445
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.748486197
Short name T231
Test name
Test status
Simulation time 1400574200 ps
CPU time 8.39 seconds
Started Aug 13 05:33:05 PM PDT 24
Finished Aug 13 05:33:13 PM PDT 24
Peak memory 201980 kb
Host smart-991a94c6-00f8-4e37-8c58-4e29bc28bffc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=748486197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.748486197
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2176545811
Short name T849
Test name
Test status
Simulation time 48909233 ps
CPU time 4.1 seconds
Started Aug 13 05:33:07 PM PDT 24
Finished Aug 13 05:33:11 PM PDT 24
Peak memory 201968 kb
Host smart-efcf5594-5265-4d5f-864b-aa30717d84b7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176545811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2176545811
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.131380689
Short name T297
Test name
Test status
Simulation time 1470997617 ps
CPU time 13.16 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:33:31 PM PDT 24
Peak memory 201908 kb
Host smart-67a65b2f-2385-4386-9621-c9802b644414
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=131380689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.131380689
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.1343933760
Short name T823
Test name
Test status
Simulation time 12663081 ps
CPU time 1.14 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:09 PM PDT 24
Peak memory 201916 kb
Host smart-5f44228a-b50b-4af1-b538-3dee68008518
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1343933760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1343933760
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.246487320
Short name T247
Test name
Test status
Simulation time 3158116900 ps
CPU time 9.04 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:15 PM PDT 24
Peak memory 201936 kb
Host smart-eca6217c-06e1-4fa5-9537-8ba705688177
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=246487320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.246487320
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2434961147
Short name T859
Test name
Test status
Simulation time 4199425535 ps
CPU time 11.29 seconds
Started Aug 13 05:33:08 PM PDT 24
Finished Aug 13 05:33:19 PM PDT 24
Peak memory 201988 kb
Host smart-a58a211d-d7b8-4c16-941a-f16aa4d4d40c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2434961147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2434961147
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2082103124
Short name T768
Test name
Test status
Simulation time 23219479 ps
CPU time 1.21 seconds
Started Aug 13 05:33:06 PM PDT 24
Finished Aug 13 05:33:08 PM PDT 24
Peak memory 201960 kb
Host smart-d46aeeb4-e3e3-42c2-a50e-5585c0ba38f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082103124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2082103124
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.636796301
Short name T364
Test name
Test status
Simulation time 5581501920 ps
CPU time 69.54 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:34:22 PM PDT 24
Peak memory 204232 kb
Host smart-cfbfccfa-62c2-4fef-baf5-c0576594f5ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=636796301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.636796301
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.77913298
Short name T731
Test name
Test status
Simulation time 4131938496 ps
CPU time 48.25 seconds
Started Aug 13 05:33:16 PM PDT 24
Finished Aug 13 05:34:04 PM PDT 24
Peak memory 201924 kb
Host smart-3a48e855-f142-470f-ba43-5bcea5c861a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77913298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.77913298
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.4284929743
Short name T507
Test name
Test status
Simulation time 3943584082 ps
CPU time 103.17 seconds
Started Aug 13 05:33:12 PM PDT 24
Finished Aug 13 05:34:55 PM PDT 24
Peak memory 204400 kb
Host smart-08c86a9c-4b2f-49b8-99c3-cdfec37de33f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4284929743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.4284929743
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2116882333
Short name T487
Test name
Test status
Simulation time 5989347451 ps
CPU time 52.77 seconds
Started Aug 13 05:33:10 PM PDT 24
Finished Aug 13 05:34:03 PM PDT 24
Peak memory 204320 kb
Host smart-56c1da39-69a5-4a1e-b77d-11cd68e49448
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2116882333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.2116882333
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.762398908
Short name T307
Test name
Test status
Simulation time 1413145077 ps
CPU time 6.09 seconds
Started Aug 13 05:33:17 PM PDT 24
Finished Aug 13 05:33:23 PM PDT 24
Peak memory 201956 kb
Host smart-ae47c5d9-73bb-46dd-a907-077400bf44b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=762398908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.762398908
Directory /workspace/9.xbar_unmapped_addr/latest
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