Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	503	1			T3	6		T5	1		T18	2
all_values[1]	469	1			T2	1		T3	5		T6	1
all_values[2]	495	1			T2	1		T3	4		T18	1
all_values[3]	482	1			T3	4		T21	5		T9	1
all_values[4]	496	1			T3	5		T18	4		T21	3
all_values[5]	472	1			T3	8		T6	1		T18	1
all_values[6]	472	1			T3	3		T18	3		T21	3
all_values[7]	488	1			T3	3		T18	2		T21	2
all_values[8]	520	1			T3	1		T21	4		T9	1
all_values[9]	504	1			T3	8		T18	1		T21	1
all_values[10]	501	1			T3	1		T21	1		T207	4
all_values[11]	504	1			T3	3		T18	2		T21	6
all_values[12]	517	1			T3	6		T6	1		T18	1
all_values[13]	482	1			T3	3		T5	1		T21	3
all_values[14]	515	1			T2	1		T3	3		T5	1
all_values[15]	531	1			T3	4		T9	1		T27	1
all_values[16]	501	1			T2	1		T3	2		T5	3
all_values[17]	480	1			T3	4		T18	2		T21	1
all_values[18]	505	1			T3	1		T5	1		T18	2
all_values[19]	531	1			T3	8		T18	1		T21	3
all_values[20]	509	1			T3	3		T18	2		T21	3
all_values[21]	476	1			T3	3		T6	1		T21	4
all_values[22]	481	1			T3	3		T21	4		T9	1
all_values[23]	477	1			T3	7		T6	1		T18	2
all_values[24]	494	1			T3	4		T5	1		T18	3
all_values[25]	464	1			T2	2		T3	3		T21	2
all_values[26]	536	1			T3	3		T5	1		T21	3