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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.30 100.00 95.80 100.00 100.00 100.00 100.00


Total test records in report: 900
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T759 /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2399080587 Aug 18 04:52:24 PM PDT 24 Aug 18 04:52:35 PM PDT 24 7841054297 ps
T760 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.379670604 Aug 18 04:58:42 PM PDT 24 Aug 18 04:58:51 PM PDT 24 1264782913 ps
T761 /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3928335813 Aug 18 04:58:09 PM PDT 24 Aug 18 04:58:12 PM PDT 24 39074199 ps
T762 /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3367866796 Aug 18 04:51:56 PM PDT 24 Aug 18 04:52:04 PM PDT 24 2097718966 ps
T763 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3222933386 Aug 18 04:57:46 PM PDT 24 Aug 18 05:01:30 PM PDT 24 9802768719 ps
T764 /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2787407477 Aug 18 04:52:26 PM PDT 24 Aug 18 04:53:43 PM PDT 24 31105282168 ps
T765 /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2782324328 Aug 18 04:52:14 PM PDT 24 Aug 18 04:52:15 PM PDT 24 10859639 ps
T766 /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.277038233 Aug 18 04:54:26 PM PDT 24 Aug 18 04:54:32 PM PDT 24 1612801522 ps
T767 /workspace/coverage/xbar_build_mode/43.xbar_random.368238865 Aug 18 04:58:26 PM PDT 24 Aug 18 04:58:38 PM PDT 24 736673726 ps
T768 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2368886069 Aug 18 04:58:52 PM PDT 24 Aug 18 05:00:09 PM PDT 24 14018730645 ps
T769 /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.906310356 Aug 18 04:58:07 PM PDT 24 Aug 18 04:58:10 PM PDT 24 145757743 ps
T770 /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3637692210 Aug 18 04:52:35 PM PDT 24 Aug 18 04:52:41 PM PDT 24 969729900 ps
T771 /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.4113138966 Aug 18 04:51:57 PM PDT 24 Aug 18 04:52:05 PM PDT 24 137910675 ps
T772 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1514036527 Aug 18 04:51:33 PM PDT 24 Aug 18 04:54:11 PM PDT 24 1034952524 ps
T773 /workspace/coverage/xbar_build_mode/29.xbar_random.3997987176 Aug 18 04:55:43 PM PDT 24 Aug 18 04:55:56 PM PDT 24 3718109781 ps
T774 /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.4232638494 Aug 18 04:57:31 PM PDT 24 Aug 18 04:57:37 PM PDT 24 52354483 ps
T775 /workspace/coverage/xbar_build_mode/8.xbar_smoke.2219214696 Aug 18 04:51:59 PM PDT 24 Aug 18 04:52:00 PM PDT 24 52019993 ps
T776 /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2740300184 Aug 18 04:58:20 PM PDT 24 Aug 18 04:58:27 PM PDT 24 850159156 ps
T777 /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1251071057 Aug 18 04:57:08 PM PDT 24 Aug 18 04:57:16 PM PDT 24 2918539789 ps
T778 /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3165745473 Aug 18 04:58:36 PM PDT 24 Aug 18 04:58:38 PM PDT 24 25868443 ps
T779 /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3259761881 Aug 18 04:58:35 PM PDT 24 Aug 18 04:58:58 PM PDT 24 3326674719 ps
T780 /workspace/coverage/xbar_build_mode/10.xbar_random.2352814907 Aug 18 04:52:06 PM PDT 24 Aug 18 04:52:08 PM PDT 24 54903364 ps
T781 /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.4279973283 Aug 18 04:54:57 PM PDT 24 Aug 18 04:55:05 PM PDT 24 64878369 ps
T782 /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1677785823 Aug 18 04:58:39 PM PDT 24 Aug 18 04:59:17 PM PDT 24 372811795 ps
T783 /workspace/coverage/xbar_build_mode/37.xbar_same_source.3322106869 Aug 18 04:58:08 PM PDT 24 Aug 18 04:58:10 PM PDT 24 24216967 ps
T784 /workspace/coverage/xbar_build_mode/38.xbar_error_random.2747065306 Aug 18 04:58:08 PM PDT 24 Aug 18 04:58:11 PM PDT 24 531376494 ps
T785 /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1133192690 Aug 18 04:51:27 PM PDT 24 Aug 18 04:51:36 PM PDT 24 5295434720 ps
T786 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2315071368 Aug 18 04:51:25 PM PDT 24 Aug 18 04:51:26 PM PDT 24 10033167 ps
T787 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1478602123 Aug 18 04:55:31 PM PDT 24 Aug 18 04:55:38 PM PDT 24 393018064 ps
T788 /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2289480620 Aug 18 04:58:28 PM PDT 24 Aug 18 05:00:37 PM PDT 24 46485199250 ps
T789 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1687497317 Aug 18 04:52:24 PM PDT 24 Aug 18 04:52:46 PM PDT 24 8028430095 ps
T790 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3701009611 Aug 18 04:51:38 PM PDT 24 Aug 18 04:56:21 PM PDT 24 1404666231 ps
T791 /workspace/coverage/xbar_build_mode/20.xbar_same_source.1434927261 Aug 18 04:53:05 PM PDT 24 Aug 18 04:53:11 PM PDT 24 72827508 ps
T792 /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1720442742 Aug 18 04:51:35 PM PDT 24 Aug 18 04:51:43 PM PDT 24 2485521719 ps
T793 /workspace/coverage/xbar_build_mode/7.xbar_smoke.2053997386 Aug 18 04:51:47 PM PDT 24 Aug 18 04:51:49 PM PDT 24 66343940 ps
T794 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3935721163 Aug 18 04:58:45 PM PDT 24 Aug 18 05:00:32 PM PDT 24 11558321421 ps
T795 /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1705495961 Aug 18 04:52:34 PM PDT 24 Aug 18 04:52:37 PM PDT 24 23429747 ps
T796 /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.4185359473 Aug 18 04:58:19 PM PDT 24 Aug 18 04:58:23 PM PDT 24 24783684 ps
T797 /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.452715241 Aug 18 04:58:44 PM PDT 24 Aug 18 04:58:46 PM PDT 24 169233714 ps
T798 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3089745650 Aug 18 04:52:44 PM PDT 24 Aug 18 04:53:04 PM PDT 24 4622996111 ps
T799 /workspace/coverage/xbar_build_mode/22.xbar_stress_all.903749773 Aug 18 04:53:13 PM PDT 24 Aug 18 04:54:02 PM PDT 24 5246885870 ps
T800 /workspace/coverage/xbar_build_mode/12.xbar_error_random.1156395632 Aug 18 04:52:14 PM PDT 24 Aug 18 04:52:15 PM PDT 24 28287322 ps
T801 /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3650779873 Aug 18 04:51:35 PM PDT 24 Aug 18 04:51:40 PM PDT 24 2003987708 ps
T802 /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3763808391 Aug 18 04:58:30 PM PDT 24 Aug 18 04:58:34 PM PDT 24 60038500 ps
T803 /workspace/coverage/xbar_build_mode/19.xbar_random.932409015 Aug 18 04:52:55 PM PDT 24 Aug 18 04:53:05 PM PDT 24 604590552 ps
T141 /workspace/coverage/xbar_build_mode/15.xbar_random.901962211 Aug 18 04:52:37 PM PDT 24 Aug 18 04:52:49 PM PDT 24 680375512 ps
T804 /workspace/coverage/xbar_build_mode/48.xbar_same_source.375013572 Aug 18 04:58:52 PM PDT 24 Aug 18 04:58:56 PM PDT 24 923079394 ps
T805 /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1284595724 Aug 18 04:58:09 PM PDT 24 Aug 18 04:58:27 PM PDT 24 3958684373 ps
T806 /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2292121715 Aug 18 04:51:47 PM PDT 24 Aug 18 04:51:57 PM PDT 24 9758438875 ps
T807 /workspace/coverage/xbar_build_mode/23.xbar_error_random.459730566 Aug 18 04:53:34 PM PDT 24 Aug 18 04:53:40 PM PDT 24 587458118 ps
T808 /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3708242988 Aug 18 04:56:12 PM PDT 24 Aug 18 04:56:19 PM PDT 24 801917057 ps
T809 /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1484901018 Aug 18 04:55:29 PM PDT 24 Aug 18 04:57:22 PM PDT 24 40873396492 ps
T810 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.101069447 Aug 18 04:57:29 PM PDT 24 Aug 18 04:58:24 PM PDT 24 1090537271 ps
T811 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1214514751 Aug 18 04:52:43 PM PDT 24 Aug 18 04:55:05 PM PDT 24 72304224834 ps
T812 /workspace/coverage/xbar_build_mode/10.xbar_smoke.1218619875 Aug 18 04:52:04 PM PDT 24 Aug 18 04:52:05 PM PDT 24 8141086 ps
T813 /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1043079272 Aug 18 04:51:44 PM PDT 24 Aug 18 04:52:56 PM PDT 24 15628184302 ps
T814 /workspace/coverage/xbar_build_mode/8.xbar_random.1470288392 Aug 18 04:51:56 PM PDT 24 Aug 18 04:52:08 PM PDT 24 4824256885 ps
T815 /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2726729033 Aug 18 04:54:19 PM PDT 24 Aug 18 04:57:38 PM PDT 24 75695769639 ps
T816 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1819786991 Aug 18 04:52:45 PM PDT 24 Aug 18 04:52:51 PM PDT 24 410052787 ps
T817 /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1171591738 Aug 18 04:58:19 PM PDT 24 Aug 18 04:58:22 PM PDT 24 469692569 ps
T818 /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.241306637 Aug 18 04:51:24 PM PDT 24 Aug 18 04:53:13 PM PDT 24 17603463932 ps
T109 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1617979072 Aug 18 04:54:38 PM PDT 24 Aug 18 04:55:58 PM PDT 24 29068997805 ps
T819 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2213867447 Aug 18 04:58:35 PM PDT 24 Aug 18 05:03:48 PM PDT 24 54268194280 ps
T820 /workspace/coverage/xbar_build_mode/24.xbar_smoke.2389841104 Aug 18 04:53:44 PM PDT 24 Aug 18 04:53:45 PM PDT 24 12150485 ps
T821 /workspace/coverage/xbar_build_mode/20.xbar_random.724972103 Aug 18 04:53:06 PM PDT 24 Aug 18 04:53:11 PM PDT 24 79581887 ps
T822 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1876449417 Aug 18 04:53:34 PM PDT 24 Aug 18 04:53:37 PM PDT 24 93524302 ps
T185 /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.696684048 Aug 18 04:57:58 PM PDT 24 Aug 18 04:59:11 PM PDT 24 21406781301 ps
T823 /workspace/coverage/xbar_build_mode/26.xbar_same_source.3906890525 Aug 18 04:54:44 PM PDT 24 Aug 18 04:54:49 PM PDT 24 36587382 ps
T824 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3701929692 Aug 18 04:58:52 PM PDT 24 Aug 18 04:59:42 PM PDT 24 3245068279 ps
T825 /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.320735061 Aug 18 04:51:29 PM PDT 24 Aug 18 04:51:33 PM PDT 24 29309201 ps
T826 /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1435058728 Aug 18 04:58:30 PM PDT 24 Aug 18 05:01:03 PM PDT 24 62265979219 ps
T110 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3553621422 Aug 18 04:55:36 PM PDT 24 Aug 18 04:57:20 PM PDT 24 6057264883 ps
T827 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2508906239 Aug 18 04:58:43 PM PDT 24 Aug 18 05:01:35 PM PDT 24 47623655714 ps
T828 /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3632692249 Aug 18 04:52:36 PM PDT 24 Aug 18 04:52:37 PM PDT 24 10516183 ps
T829 /workspace/coverage/xbar_build_mode/22.xbar_same_source.562339318 Aug 18 04:53:13 PM PDT 24 Aug 18 04:53:18 PM PDT 24 274429783 ps
T830 /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2261311014 Aug 18 04:51:42 PM PDT 24 Aug 18 04:51:47 PM PDT 24 217001234 ps
T137 /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1535882818 Aug 18 04:58:39 PM PDT 24 Aug 18 05:00:48 PM PDT 24 40878004441 ps
T831 /workspace/coverage/xbar_build_mode/25.xbar_same_source.3734722850 Aug 18 04:54:16 PM PDT 24 Aug 18 04:54:26 PM PDT 24 813091282 ps
T832 /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1454276534 Aug 18 04:51:38 PM PDT 24 Aug 18 04:51:47 PM PDT 24 82750981 ps
T833 /workspace/coverage/xbar_build_mode/31.xbar_smoke.1355827781 Aug 18 04:56:27 PM PDT 24 Aug 18 04:56:29 PM PDT 24 9237896 ps
T834 /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1726674628 Aug 18 04:58:30 PM PDT 24 Aug 18 04:58:34 PM PDT 24 94484299 ps
T835 /workspace/coverage/xbar_build_mode/26.xbar_smoke.2909126702 Aug 18 04:54:29 PM PDT 24 Aug 18 04:54:31 PM PDT 24 37604571 ps
T836 /workspace/coverage/xbar_build_mode/2.xbar_same_source.333708575 Aug 18 04:51:25 PM PDT 24 Aug 18 04:51:32 PM PDT 24 846510666 ps
T837 /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3317890651 Aug 18 04:52:06 PM PDT 24 Aug 18 04:52:12 PM PDT 24 746056778 ps
T838 /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2634942128 Aug 18 04:57:30 PM PDT 24 Aug 18 04:57:31 PM PDT 24 9162627 ps
T839 /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1612388192 Aug 18 04:53:44 PM PDT 24 Aug 18 04:53:45 PM PDT 24 9410076 ps
T840 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1748286772 Aug 18 04:58:30 PM PDT 24 Aug 18 05:00:21 PM PDT 24 16324011760 ps
T841 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.30362212 Aug 18 04:53:04 PM PDT 24 Aug 18 04:58:40 PM PDT 24 203508963988 ps
T842 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2934100653 Aug 18 04:57:40 PM PDT 24 Aug 18 04:59:04 PM PDT 24 22337034865 ps
T843 /workspace/coverage/xbar_build_mode/2.xbar_error_random.3798194724 Aug 18 04:51:28 PM PDT 24 Aug 18 04:51:41 PM PDT 24 2376770431 ps
T844 /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.891003566 Aug 18 04:53:25 PM PDT 24 Aug 18 04:53:33 PM PDT 24 1382650812 ps
T845 /workspace/coverage/xbar_build_mode/30.xbar_same_source.2910161817 Aug 18 04:56:11 PM PDT 24 Aug 18 04:56:16 PM PDT 24 36985539 ps
T846 /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2405624877 Aug 18 04:51:43 PM PDT 24 Aug 18 04:51:58 PM PDT 24 2259062146 ps
T847 /workspace/coverage/xbar_build_mode/34.xbar_same_source.434770912 Aug 18 04:57:39 PM PDT 24 Aug 18 04:57:40 PM PDT 24 141857385 ps
T848 /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.154699064 Aug 18 04:51:16 PM PDT 24 Aug 18 04:53:04 PM PDT 24 15277387999 ps
T849 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.831488069 Aug 18 04:55:53 PM PDT 24 Aug 18 04:56:09 PM PDT 24 3941896652 ps
T850 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1186121975 Aug 18 04:51:26 PM PDT 24 Aug 18 04:57:10 PM PDT 24 133613887518 ps
T851 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3920731691 Aug 18 04:56:42 PM PDT 24 Aug 18 04:57:28 PM PDT 24 226780229 ps
T852 /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2633753931 Aug 18 04:52:59 PM PDT 24 Aug 18 04:53:01 PM PDT 24 18124153 ps
T853 /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2970875010 Aug 18 04:58:17 PM PDT 24 Aug 18 04:58:41 PM PDT 24 271243768 ps
T854 /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2649673225 Aug 18 04:56:15 PM PDT 24 Aug 18 04:56:54 PM PDT 24 2711448104 ps
T855 /workspace/coverage/xbar_build_mode/18.xbar_stress_all.799987686 Aug 18 04:52:58 PM PDT 24 Aug 18 04:54:01 PM PDT 24 2959368255 ps
T856 /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.614343852 Aug 18 04:53:06 PM PDT 24 Aug 18 04:53:12 PM PDT 24 83351134 ps
T857 /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4221957187 Aug 18 04:57:57 PM PDT 24 Aug 18 04:58:04 PM PDT 24 339574120 ps
T858 /workspace/coverage/xbar_build_mode/27.xbar_error_random.3028710268 Aug 18 04:55:07 PM PDT 24 Aug 18 04:55:12 PM PDT 24 171912347 ps
T859 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.458023903 Aug 18 04:52:35 PM PDT 24 Aug 18 04:53:01 PM PDT 24 242187713 ps
T860 /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2131223488 Aug 18 04:52:35 PM PDT 24 Aug 18 04:52:42 PM PDT 24 1951131795 ps
T861 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2013822560 Aug 18 04:52:35 PM PDT 24 Aug 18 04:52:59 PM PDT 24 1482923578 ps
T862 /workspace/coverage/xbar_build_mode/36.xbar_same_source.3048299019 Aug 18 04:57:58 PM PDT 24 Aug 18 04:58:10 PM PDT 24 860549617 ps
T863 /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.539241692 Aug 18 04:55:53 PM PDT 24 Aug 18 04:56:20 PM PDT 24 17503701838 ps
T864 /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.856012517 Aug 18 04:58:07 PM PDT 24 Aug 18 04:58:10 PM PDT 24 48725588 ps
T122 /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1730761364 Aug 18 04:51:44 PM PDT 24 Aug 18 04:54:01 PM PDT 24 29092661926 ps
T865 /workspace/coverage/xbar_build_mode/48.xbar_random.3717648550 Aug 18 04:58:41 PM PDT 24 Aug 18 04:58:56 PM PDT 24 876920851 ps
T866 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2143370853 Aug 18 04:52:56 PM PDT 24 Aug 18 04:54:29 PM PDT 24 12850293509 ps
T867 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2706132062 Aug 18 04:58:50 PM PDT 24 Aug 18 04:59:21 PM PDT 24 2035820381 ps
T868 /workspace/coverage/xbar_build_mode/15.xbar_same_source.165089133 Aug 18 04:52:33 PM PDT 24 Aug 18 04:52:45 PM PDT 24 2819247035 ps
T869 /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3321570014 Aug 18 04:56:55 PM PDT 24 Aug 18 04:57:01 PM PDT 24 181194127 ps
T870 /workspace/coverage/xbar_build_mode/5.xbar_smoke.1031778972 Aug 18 04:51:34 PM PDT 24 Aug 18 04:51:36 PM PDT 24 345170303 ps
T871 /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4028821429 Aug 18 04:56:30 PM PDT 24 Aug 18 04:57:19 PM PDT 24 26371630735 ps
T872 /workspace/coverage/xbar_build_mode/39.xbar_smoke.3549073907 Aug 18 04:58:07 PM PDT 24 Aug 18 04:58:09 PM PDT 24 44200516 ps
T873 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4052948193 Aug 18 04:56:11 PM PDT 24 Aug 18 04:59:26 PM PDT 24 24079502867 ps
T874 /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.670784666 Aug 18 04:52:14 PM PDT 24 Aug 18 04:52:25 PM PDT 24 1201859245 ps
T117 /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2918747588 Aug 18 04:51:15 PM PDT 24 Aug 18 04:53:12 PM PDT 24 25899625931 ps
T875 /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1282680454 Aug 18 04:52:29 PM PDT 24 Aug 18 04:53:10 PM PDT 24 362327254 ps
T876 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3030732430 Aug 18 04:58:06 PM PDT 24 Aug 18 04:59:51 PM PDT 24 3276824032 ps
T877 /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2861224189 Aug 18 04:52:06 PM PDT 24 Aug 18 04:52:07 PM PDT 24 33963759 ps
T878 /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.4161610204 Aug 18 04:58:36 PM PDT 24 Aug 18 04:58:56 PM PDT 24 1901901821 ps
T879 /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2309198880 Aug 18 04:58:31 PM PDT 24 Aug 18 04:59:39 PM PDT 24 949338694 ps
T880 /workspace/coverage/xbar_build_mode/29.xbar_same_source.2659256651 Aug 18 04:55:54 PM PDT 24 Aug 18 04:56:05 PM PDT 24 2002796940 ps
T881 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.661380936 Aug 18 04:58:25 PM PDT 24 Aug 18 04:58:48 PM PDT 24 1239015917 ps
T882 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1295557345 Aug 18 04:58:30 PM PDT 24 Aug 18 04:59:03 PM PDT 24 3662329090 ps
T883 /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1305979901 Aug 18 04:58:42 PM PDT 24 Aug 18 04:58:53 PM PDT 24 2291822067 ps
T884 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.4237369954 Aug 18 04:53:45 PM PDT 24 Aug 18 04:54:36 PM PDT 24 415943555 ps
T885 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2449215332 Aug 18 04:52:24 PM PDT 24 Aug 18 04:52:52 PM PDT 24 419887185 ps
T886 /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2927914475 Aug 18 04:51:35 PM PDT 24 Aug 18 04:51:43 PM PDT 24 515368039 ps
T887 /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2028968537 Aug 18 04:54:28 PM PDT 24 Aug 18 04:54:30 PM PDT 24 13196074 ps
T888 /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.284793062 Aug 18 04:52:33 PM PDT 24 Aug 18 04:52:36 PM PDT 24 66314497 ps
T889 /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.928692232 Aug 18 04:54:37 PM PDT 24 Aug 18 04:54:41 PM PDT 24 40802665 ps
T890 /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4050158221 Aug 18 04:52:55 PM PDT 24 Aug 18 04:52:59 PM PDT 24 161696865 ps
T891 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.4058282652 Aug 18 04:52:44 PM PDT 24 Aug 18 04:53:20 PM PDT 24 13895147976 ps
T892 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2939180908 Aug 18 04:56:08 PM PDT 24 Aug 18 04:56:27 PM PDT 24 1404046409 ps
T893 /workspace/coverage/xbar_build_mode/32.xbar_smoke.1307146727 Aug 18 04:56:37 PM PDT 24 Aug 18 04:56:38 PM PDT 24 11147149 ps
T894 /workspace/coverage/xbar_build_mode/45.xbar_error_random.3493245583 Aug 18 04:58:31 PM PDT 24 Aug 18 04:58:33 PM PDT 24 50278219 ps
T136 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2394702890 Aug 18 04:56:56 PM PDT 24 Aug 18 04:57:51 PM PDT 24 2739370287 ps
T895 /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1484921943 Aug 18 04:52:06 PM PDT 24 Aug 18 04:52:10 PM PDT 24 248140504 ps
T896 /workspace/coverage/xbar_build_mode/17.xbar_same_source.2723816452 Aug 18 04:52:44 PM PDT 24 Aug 18 04:52:49 PM PDT 24 433806014 ps
T897 /workspace/coverage/xbar_build_mode/18.xbar_smoke.2387497526 Aug 18 04:52:59 PM PDT 24 Aug 18 04:53:01 PM PDT 24 117584501 ps
T898 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3210221507 Aug 18 04:52:14 PM PDT 24 Aug 18 04:52:31 PM PDT 24 51763456 ps
T899 /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2504978301 Aug 18 04:52:16 PM PDT 24 Aug 18 04:52:24 PM PDT 24 2736854782 ps
T900 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4232329471 Aug 18 04:51:59 PM PDT 24 Aug 18 04:52:43 PM PDT 24 2041092702 ps

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3287088201
Short name T13
Test name
Test status
Simulation time 19385140618 ps
CPU time 156.26 seconds
Started Aug 18 04:52:27 PM PDT 24
Finished Aug 18 04:55:04 PM PDT 24
Peak memory 205064 kb
Host smart-a9a74a38-8517-404d-a096-c90f049ba6f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3287088201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.3287088201
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.353511492
Short name T114
Test name
Test status
Simulation time 61629040688 ps
CPU time 311.9 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:56:47 PM PDT 24
Peak memory 205080 kb
Host smart-7cbbe487-18a9-4a3f-9d66-d8115dbd1de0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=353511492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow
_rsp.353511492
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1281341445
Short name T188
Test name
Test status
Simulation time 46615510812 ps
CPU time 331.34 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 05:01:24 PM PDT 24
Peak memory 204068 kb
Host smart-6ff66da8-2d19-4f7a-bc40-39b60aef2d92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1281341445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.1281341445
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3405977959
Short name T77
Test name
Test status
Simulation time 194958776447 ps
CPU time 364.69 seconds
Started Aug 18 04:51:29 PM PDT 24
Finished Aug 18 04:57:34 PM PDT 24
Peak memory 204800 kb
Host smart-9963040f-3a41-48a7-92e8-fa2b7ae9d3b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3405977959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.3405977959
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.979644635
Short name T9
Test name
Test status
Simulation time 4109307080 ps
CPU time 127.68 seconds
Started Aug 18 04:52:26 PM PDT 24
Finished Aug 18 04:54:34 PM PDT 24
Peak memory 205112 kb
Host smart-ea062748-357d-4b23-ad89-4340c314d2cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=979644635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res
et_error.979644635
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3173150992
Short name T66
Test name
Test status
Simulation time 227816997306 ps
CPU time 274.45 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 05:03:26 PM PDT 24
Peak memory 203044 kb
Host smart-4cd356ed-ed77-4c00-811f-3ea6444694f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3173150992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3173150992
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1158634763
Short name T27
Test name
Test status
Simulation time 2907668044 ps
CPU time 50.53 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:59:19 PM PDT 24
Peak memory 202920 kb
Host smart-83e5c433-39c3-4047-b284-f4fb00227a61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1158634763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1158634763
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3892277091
Short name T89
Test name
Test status
Simulation time 47755088027 ps
CPU time 274.68 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:58:52 PM PDT 24
Peak memory 203040 kb
Host smart-7db799f7-8a11-4019-a322-2f13cfd02857
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3892277091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.3892277091
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2334847395
Short name T25
Test name
Test status
Simulation time 14013541269 ps
CPU time 54.83 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 201844 kb
Host smart-8e6c6d82-e3bc-4e42-af41-8bf860f39593
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334847395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2334847395
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3842769346
Short name T12
Test name
Test status
Simulation time 1275647500 ps
CPU time 84.28 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:53:39 PM PDT 24
Peak memory 204452 kb
Host smart-ea1196de-b1e7-4b70-91a3-7018c2a3dbb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3842769346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.3842769346
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1748683766
Short name T6
Test name
Test status
Simulation time 138302042 ps
CPU time 45.85 seconds
Started Aug 18 04:52:45 PM PDT 24
Finished Aug 18 04:53:30 PM PDT 24
Peak memory 203360 kb
Host smart-cbc1b2e2-8f0f-433a-a3b8-96b1c38ec4e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1748683766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.1748683766
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.521176998
Short name T134
Test name
Test status
Simulation time 240756489836 ps
CPU time 348.6 seconds
Started Aug 18 04:52:58 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 202964 kb
Host smart-17ac1201-0ad0-4bb3-81e6-c6806becc777
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=521176998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo
w_rsp.521176998
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2989406486
Short name T8
Test name
Test status
Simulation time 576402308 ps
CPU time 11.21 seconds
Started Aug 18 04:52:05 PM PDT 24
Finished Aug 18 04:52:16 PM PDT 24
Peak memory 201824 kb
Host smart-1f9fee84-62b2-458c-bb5a-44307983359a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2989406486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2989406486
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1383243154
Short name T70
Test name
Test status
Simulation time 40585229155 ps
CPU time 153.35 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 05:00:43 PM PDT 24
Peak memory 202924 kb
Host smart-512a9a42-1af1-4468-b846-42265bcd754c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1383243154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1383243154
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3737708965
Short name T104
Test name
Test status
Simulation time 142184827629 ps
CPU time 355.4 seconds
Started Aug 18 04:58:00 PM PDT 24
Finished Aug 18 05:03:56 PM PDT 24
Peak memory 203792 kb
Host smart-65c7f668-0d67-4485-87d6-994b45c11ca1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3737708965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.3737708965
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.275711709
Short name T574
Test name
Test status
Simulation time 8183364572 ps
CPU time 166.82 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 05:00:57 PM PDT 24
Peak memory 207496 kb
Host smart-6168ddff-3224-46ac-8a3d-17d53b187243
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=275711709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand
_reset.275711709
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2889584891
Short name T24
Test name
Test status
Simulation time 45183503085 ps
CPU time 178.92 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:55:35 PM PDT 24
Peak memory 203204 kb
Host smart-1d7bf0cc-96f8-43af-b652-fdeb3672dd7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2889584891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.2889584891
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2697898850
Short name T532
Test name
Test status
Simulation time 31327807435 ps
CPU time 53.36 seconds
Started Aug 18 04:52:16 PM PDT 24
Finished Aug 18 04:53:09 PM PDT 24
Peak memory 201860 kb
Host smart-8c35a9e3-4d57-4aa6-b2a0-87c2c6cf6fbc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2697898850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.2697898850
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3039429877
Short name T497
Test name
Test status
Simulation time 8357516280 ps
CPU time 30.81 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:45 PM PDT 24
Peak memory 203204 kb
Host smart-170cf464-32da-42e9-9a70-28dc5cfdb9e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3039429877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.3039429877
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1495772520
Short name T461
Test name
Test status
Simulation time 4370087872 ps
CPU time 74.54 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:54:59 PM PDT 24
Peak memory 204616 kb
Host smart-a075807f-109d-4202-bf73-e2f0b3a6885f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1495772520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.1495772520
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1712992101
Short name T11
Test name
Test status
Simulation time 10097502026 ps
CPU time 114.23 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:54:31 PM PDT 24
Peak memory 206432 kb
Host smart-df16c025-e550-4019-a2d5-f51cfcd58f18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1712992101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.1712992101
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1753448727
Short name T430
Test name
Test status
Simulation time 661130995 ps
CPU time 9.17 seconds
Started Aug 18 04:51:15 PM PDT 24
Finished Aug 18 04:51:24 PM PDT 24
Peak memory 201824 kb
Host smart-bc6ebbf0-6bbe-4a05-8991-5805ba070148
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1753448727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1753448727
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2861862386
Short name T101
Test name
Test status
Simulation time 44942993241 ps
CPU time 240.98 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 203624 kb
Host smart-b62c6b7e-daa2-4e21-9965-667d64d1bde7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2861862386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2861862386
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1561167953
Short name T725
Test name
Test status
Simulation time 66041727 ps
CPU time 3.16 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:29 PM PDT 24
Peak memory 201824 kb
Host smart-19efd8c5-51d3-43da-b719-aa6943d15419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1561167953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1561167953
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.767703270
Short name T714
Test name
Test status
Simulation time 229532819 ps
CPU time 4.08 seconds
Started Aug 18 04:51:23 PM PDT 24
Finished Aug 18 04:51:27 PM PDT 24
Peak memory 201936 kb
Host smart-6e17a37c-c02e-4679-939a-4b35dd8f783c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=767703270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.767703270
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3272018302
Short name T464
Test name
Test status
Simulation time 22360638 ps
CPU time 1.77 seconds
Started Aug 18 04:51:15 PM PDT 24
Finished Aug 18 04:51:16 PM PDT 24
Peak memory 201764 kb
Host smart-366595ef-b790-42f2-af38-73083d2e7730
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3272018302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3272018302
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2918747588
Short name T117
Test name
Test status
Simulation time 25899625931 ps
CPU time 117.06 seconds
Started Aug 18 04:51:15 PM PDT 24
Finished Aug 18 04:53:12 PM PDT 24
Peak memory 201888 kb
Host smart-6c15fe8b-5de6-4baf-af67-a6331e685384
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918747588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2918747588
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.154699064
Short name T848
Test name
Test status
Simulation time 15277387999 ps
CPU time 107.51 seconds
Started Aug 18 04:51:16 PM PDT 24
Finished Aug 18 04:53:04 PM PDT 24
Peak memory 202012 kb
Host smart-e8875e6a-158b-4dd2-a7e4-2efdc544a03c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=154699064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.154699064
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.2044310399
Short name T322
Test name
Test status
Simulation time 211672133 ps
CPU time 5.59 seconds
Started Aug 18 04:51:15 PM PDT 24
Finished Aug 18 04:51:21 PM PDT 24
Peak memory 201828 kb
Host smart-ea621f89-36fd-4653-90fe-7dc9fadfc87b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044310399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2044310399
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1088850350
Short name T379
Test name
Test status
Simulation time 7636947499 ps
CPU time 11.95 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:38 PM PDT 24
Peak memory 201876 kb
Host smart-835e8734-f578-45fd-a21a-f5b0320e3fc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1088850350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1088850350
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.617630741
Short name T246
Test name
Test status
Simulation time 65252922 ps
CPU time 1.79 seconds
Started Aug 18 04:51:16 PM PDT 24
Finished Aug 18 04:51:18 PM PDT 24
Peak memory 201820 kb
Host smart-2dfbc4d9-c8d9-4f16-acd1-3a3fff4f7310
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=617630741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.617630741
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1944936350
Short name T249
Test name
Test status
Simulation time 16221999194 ps
CPU time 11.99 seconds
Started Aug 18 04:51:15 PM PDT 24
Finished Aug 18 04:51:27 PM PDT 24
Peak memory 201880 kb
Host smart-00212a1a-7b43-47f3-8e29-bb91c7a05317
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944936350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1944936350
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2927746746
Short name T755
Test name
Test status
Simulation time 2579445317 ps
CPU time 10.87 seconds
Started Aug 18 04:51:15 PM PDT 24
Finished Aug 18 04:51:26 PM PDT 24
Peak memory 201888 kb
Host smart-9a057521-e76a-45eb-9b52-07bfd8ba29c7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2927746746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2927746746
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.466515452
Short name T758
Test name
Test status
Simulation time 13450888 ps
CPU time 1.15 seconds
Started Aug 18 04:51:14 PM PDT 24
Finished Aug 18 04:51:16 PM PDT 24
Peak memory 201856 kb
Host smart-704ddd73-3877-412b-ba09-47536b0d0d23
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466515452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.466515452
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3079663685
Short name T223
Test name
Test status
Simulation time 1980006377 ps
CPU time 39.06 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:52:06 PM PDT 24
Peak memory 201928 kb
Host smart-40b5f1bf-95a2-4d0f-981b-7cf77d32a2ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3079663685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3079663685
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2920879613
Short name T515
Test name
Test status
Simulation time 199079196 ps
CPU time 4.88 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:31 PM PDT 24
Peak memory 201936 kb
Host smart-fd09dc6b-53cc-48c2-adfb-21d1c3dfaead
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2920879613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2920879613
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3797518394
Short name T690
Test name
Test status
Simulation time 9040667598 ps
CPU time 118.28 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 205888 kb
Host smart-9841769a-65c8-41de-b41f-f8ed1426ab44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3797518394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.3797518394
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2594272351
Short name T215
Test name
Test status
Simulation time 858814572 ps
CPU time 86.3 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:52:51 PM PDT 24
Peak memory 204280 kb
Host smart-df246c67-4c85-4f02-9138-7ec7733f4277
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2594272351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.2594272351
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2723050901
Short name T327
Test name
Test status
Simulation time 56749957 ps
CPU time 5.09 seconds
Started Aug 18 04:51:23 PM PDT 24
Finished Aug 18 04:51:29 PM PDT 24
Peak memory 201852 kb
Host smart-ed429928-66f9-4d86-9762-be6850c76a1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2723050901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2723050901
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3562255826
Short name T610
Test name
Test status
Simulation time 948317040 ps
CPU time 21.46 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:48 PM PDT 24
Peak memory 201948 kb
Host smart-2139eaba-449d-49be-a2a3-59e07c32578a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3562255826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3562255826
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1186121975
Short name T850
Test name
Test status
Simulation time 133613887518 ps
CPU time 343.59 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:57:10 PM PDT 24
Peak memory 202912 kb
Host smart-89d6abb4-7d0a-4709-b874-f39cda83eba3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1186121975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1186121975
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1650391066
Short name T254
Test name
Test status
Simulation time 549415511 ps
CPU time 7.54 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:33 PM PDT 24
Peak memory 201848 kb
Host smart-ba2cffa2-c00f-4f52-8496-8f227a0b54df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1650391066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1650391066
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.580943993
Short name T23
Test name
Test status
Simulation time 573649151 ps
CPU time 8.28 seconds
Started Aug 18 04:51:23 PM PDT 24
Finished Aug 18 04:51:31 PM PDT 24
Peak memory 201860 kb
Host smart-ea5de9b5-c77f-466a-8ade-400456b6fd1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=580943993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.580943993
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.4084801153
Short name T757
Test name
Test status
Simulation time 126518069 ps
CPU time 7.62 seconds
Started Aug 18 04:51:24 PM PDT 24
Finished Aug 18 04:51:32 PM PDT 24
Peak memory 201828 kb
Host smart-4020257c-4638-4f0e-b1b5-b6ea5ecb014c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4084801153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.4084801153
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2145100956
Short name T679
Test name
Test status
Simulation time 104954544049 ps
CPU time 184.95 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:54:31 PM PDT 24
Peak memory 201920 kb
Host smart-e3d4be6d-826e-4b26-8914-e7cef7f1cc63
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145100956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2145100956
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.241306637
Short name T818
Test name
Test status
Simulation time 17603463932 ps
CPU time 108.32 seconds
Started Aug 18 04:51:24 PM PDT 24
Finished Aug 18 04:53:13 PM PDT 24
Peak memory 201936 kb
Host smart-efc21849-50b5-4284-b85f-a98b2d7c0c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=241306637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.241306637
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.320735061
Short name T825
Test name
Test status
Simulation time 29309201 ps
CPU time 3.72 seconds
Started Aug 18 04:51:29 PM PDT 24
Finished Aug 18 04:51:33 PM PDT 24
Peak memory 201848 kb
Host smart-d98cbef1-30ca-424b-8ea1-14f7b409a21a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320735061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.320735061
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.1018642156
Short name T468
Test name
Test status
Simulation time 86313287 ps
CPU time 5.26 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:30 PM PDT 24
Peak memory 201940 kb
Host smart-a56a7152-6202-43ae-a2e2-7749a993c9f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1018642156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1018642156
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.1669810563
Short name T20
Test name
Test status
Simulation time 42443228 ps
CPU time 1.4 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:28 PM PDT 24
Peak memory 201912 kb
Host smart-5798bbd6-860a-4aa2-b455-d9a94f2eee7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1669810563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1669810563
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1133192690
Short name T785
Test name
Test status
Simulation time 5295434720 ps
CPU time 9.51 seconds
Started Aug 18 04:51:27 PM PDT 24
Finished Aug 18 04:51:36 PM PDT 24
Peak memory 201936 kb
Host smart-687de8b7-61fa-4448-a4de-1ba415c5e4a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133192690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1133192690
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1451341557
Short name T650
Test name
Test status
Simulation time 1188902074 ps
CPU time 8.7 seconds
Started Aug 18 04:51:24 PM PDT 24
Finished Aug 18 04:51:34 PM PDT 24
Peak memory 201956 kb
Host smart-8d86a00c-a2ac-41bd-8f12-dc04aa5f4f27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1451341557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1451341557
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.330888928
Short name T569
Test name
Test status
Simulation time 11097279 ps
CPU time 1.37 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:26 PM PDT 24
Peak memory 201956 kb
Host smart-419a5b4d-e50d-4e6e-bc7b-c54d5831659e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330888928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.330888928
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2377490038
Short name T389
Test name
Test status
Simulation time 9158303001 ps
CPU time 22.88 seconds
Started Aug 18 04:51:23 PM PDT 24
Finished Aug 18 04:51:46 PM PDT 24
Peak memory 202008 kb
Host smart-b58d62b5-3156-466f-86ee-b08b95524756
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2377490038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2377490038
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3356820326
Short name T126
Test name
Test status
Simulation time 4584319887 ps
CPU time 75.54 seconds
Started Aug 18 04:51:27 PM PDT 24
Finished Aug 18 04:52:43 PM PDT 24
Peak memory 203028 kb
Host smart-ad692e77-4c2c-4407-8a26-dc921a0f9147
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3356820326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3356820326
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.563891171
Short name T210
Test name
Test status
Simulation time 288765157 ps
CPU time 19.39 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:44 PM PDT 24
Peak memory 203912 kb
Host smart-0f865c7c-0c28-4640-826c-d87534a0f77c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=563891171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_
reset.563891171
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.4047981286
Short name T284
Test name
Test status
Simulation time 603835553 ps
CPU time 67.32 seconds
Started Aug 18 04:51:23 PM PDT 24
Finished Aug 18 04:52:31 PM PDT 24
Peak memory 204656 kb
Host smart-61ccdc26-dc2d-40e6-983b-74573c1f5820
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4047981286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.4047981286
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3951060770
Short name T51
Test name
Test status
Simulation time 29691938 ps
CPU time 1.82 seconds
Started Aug 18 04:51:27 PM PDT 24
Finished Aug 18 04:51:29 PM PDT 24
Peak memory 201788 kb
Host smart-789f4f56-4b86-48a1-8288-aa7e8203e96f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3951060770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3951060770
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.712192090
Short name T454
Test name
Test status
Simulation time 132784692 ps
CPU time 7.68 seconds
Started Aug 18 04:52:07 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201840 kb
Host smart-8234f0d4-b976-4ce0-9da7-40e0d3f999cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=712192090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.712192090
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.872383734
Short name T270
Test name
Test status
Simulation time 39422716487 ps
CPU time 171.44 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 203044 kb
Host smart-5f32f050-c886-4678-9521-ba7acc4c09c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=872383734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo
w_rsp.872383734
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.729945172
Short name T46
Test name
Test status
Simulation time 219847285 ps
CPU time 1.74 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:08 PM PDT 24
Peak memory 201940 kb
Host smart-f639f2a0-475e-44db-925b-776f2d507b4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=729945172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.729945172
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.4254284014
Short name T597
Test name
Test status
Simulation time 111182993 ps
CPU time 2.8 seconds
Started Aug 18 04:52:10 PM PDT 24
Finished Aug 18 04:52:13 PM PDT 24
Peak memory 201836 kb
Host smart-b50d898c-6f01-4211-875b-daf7cb52dfd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4254284014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4254284014
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.2352814907
Short name T780
Test name
Test status
Simulation time 54903364 ps
CPU time 1.9 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:08 PM PDT 24
Peak memory 201884 kb
Host smart-bdbd648f-4a46-4dd5-bb9c-25e5adc91056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2352814907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2352814907
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.2940288482
Short name T544
Test name
Test status
Simulation time 86445346599 ps
CPU time 83.22 seconds
Started Aug 18 04:52:07 PM PDT 24
Finished Aug 18 04:53:31 PM PDT 24
Peak memory 201964 kb
Host smart-6d34ab1d-436b-4980-ad37-9f74bdac6da1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940288482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2940288482
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3765464885
Short name T577
Test name
Test status
Simulation time 15270333361 ps
CPU time 63.21 seconds
Started Aug 18 04:52:04 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201888 kb
Host smart-0bda8748-c7d5-4b9b-acb8-8cc801f2939f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3765464885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3765464885
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3094446710
Short name T250
Test name
Test status
Simulation time 39341447 ps
CPU time 2.47 seconds
Started Aug 18 04:52:04 PM PDT 24
Finished Aug 18 04:52:07 PM PDT 24
Peak memory 201780 kb
Host smart-160c150b-2bbc-4ea2-aafb-01ec0d3c8abe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094446710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3094446710
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.2078186402
Short name T681
Test name
Test status
Simulation time 359118544 ps
CPU time 2.3 seconds
Started Aug 18 04:52:07 PM PDT 24
Finished Aug 18 04:52:10 PM PDT 24
Peak memory 201852 kb
Host smart-29a4aeb0-f6d6-468a-a1cb-65657b0567d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2078186402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2078186402
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.1218619875
Short name T812
Test name
Test status
Simulation time 8141086 ps
CPU time 1.09 seconds
Started Aug 18 04:52:04 PM PDT 24
Finished Aug 18 04:52:05 PM PDT 24
Peak memory 201808 kb
Host smart-864998ad-e84e-4fd6-9cc5-ed3aafd37d8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1218619875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1218619875
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.415236628
Short name T678
Test name
Test status
Simulation time 2809279024 ps
CPU time 10.4 seconds
Started Aug 18 04:52:04 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201968 kb
Host smart-62e104ea-dd5b-44a5-8af5-bf14aa272668
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=415236628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.415236628
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3317890651
Short name T837
Test name
Test status
Simulation time 746056778 ps
CPU time 6 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:12 PM PDT 24
Peak memory 201844 kb
Host smart-1128da49-7dc8-4d21-b248-1e2ae7047ccd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3317890651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3317890651
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1864376287
Short name T462
Test name
Test status
Simulation time 8702599 ps
CPU time 1.14 seconds
Started Aug 18 04:52:10 PM PDT 24
Finished Aug 18 04:52:11 PM PDT 24
Peak memory 201956 kb
Host smart-a4755eb6-b207-48fb-9439-8fc9bf9e2876
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864376287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1864376287
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2709798539
Short name T80
Test name
Test status
Simulation time 4116026467 ps
CPU time 41.28 seconds
Started Aug 18 04:52:08 PM PDT 24
Finished Aug 18 04:52:50 PM PDT 24
Peak memory 202056 kb
Host smart-3d308702-2f49-4c77-9b05-293ff73ffbb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2709798539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2709798539
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.882225899
Short name T539
Test name
Test status
Simulation time 1384523557 ps
CPU time 42.63 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:57 PM PDT 24
Peak memory 203044 kb
Host smart-04cf71a5-6a0a-44b6-b6bc-4b7a2d752d73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=882225899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.882225899
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3210221507
Short name T898
Test name
Test status
Simulation time 51763456 ps
CPU time 16.76 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:31 PM PDT 24
Peak memory 203472 kb
Host smart-be77eaa2-298b-47d2-856e-dbb91fed6269
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3210221507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.3210221507
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3460280570
Short name T589
Test name
Test status
Simulation time 144387554 ps
CPU time 18.79 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:32 PM PDT 24
Peak memory 201944 kb
Host smart-db7a0900-9e8c-4c6d-ab47-974b6a4e97f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3460280570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.3460280570
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.264142639
Short name T616
Test name
Test status
Simulation time 678596808 ps
CPU time 3.03 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:09 PM PDT 24
Peak memory 201840 kb
Host smart-b44d495d-5e2d-43f2-8908-7cb1717ccc79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=264142639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.264142639
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.284661037
Short name T754
Test name
Test status
Simulation time 1682541867 ps
CPU time 5.06 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:18 PM PDT 24
Peak memory 201928 kb
Host smart-000f3fc5-2bf3-43dd-91f9-d401c2315b0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284661037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.284661037
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2994006316
Short name T222
Test name
Test status
Simulation time 575284957 ps
CPU time 8.26 seconds
Started Aug 18 04:52:15 PM PDT 24
Finished Aug 18 04:52:23 PM PDT 24
Peak memory 201904 kb
Host smart-c3e6281a-bc62-42ba-9ffd-94c3fa5d1837
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2994006316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2994006316
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.49506450
Short name T558
Test name
Test status
Simulation time 47484631 ps
CPU time 1.31 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201840 kb
Host smart-f65947c1-2f3d-4f00-b48b-6a2064dba4eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49506450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.49506450
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.1009596789
Short name T601
Test name
Test status
Simulation time 77756250 ps
CPU time 6.14 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:20 PM PDT 24
Peak memory 201808 kb
Host smart-1fcbfa0a-e6f6-45a7-9535-4434e2489b57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1009596789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1009596789
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3518605165
Short name T556
Test name
Test status
Simulation time 2636981184 ps
CPU time 6.94 seconds
Started Aug 18 04:52:15 PM PDT 24
Finished Aug 18 04:52:22 PM PDT 24
Peak memory 201968 kb
Host smart-c7663753-3036-4150-9808-86b16d09f379
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518605165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3518605165
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3514614800
Short name T628
Test name
Test status
Simulation time 37359059599 ps
CPU time 98.04 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:53:53 PM PDT 24
Peak memory 201940 kb
Host smart-d3fdc295-9803-4cf3-8b93-0e8b24c994f1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3514614800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3514614800
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1856283738
Short name T251
Test name
Test status
Simulation time 82482212 ps
CPU time 7.12 seconds
Started Aug 18 04:52:15 PM PDT 24
Finished Aug 18 04:52:22 PM PDT 24
Peak memory 201828 kb
Host smart-bbe64349-6151-4588-877f-23ffb12b6082
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856283738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1856283738
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.948688922
Short name T382
Test name
Test status
Simulation time 43622810 ps
CPU time 3.66 seconds
Started Aug 18 04:52:12 PM PDT 24
Finished Aug 18 04:52:16 PM PDT 24
Peak memory 201892 kb
Host smart-c9993d47-a530-4cc4-a495-48f0a314351d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=948688922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.948688922
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.3768335408
Short name T263
Test name
Test status
Simulation time 176207027 ps
CPU time 1.42 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:16 PM PDT 24
Peak memory 201792 kb
Host smart-b041856b-1883-446b-96f1-d962d0b25282
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3768335408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3768335408
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4221693473
Short name T716
Test name
Test status
Simulation time 7277713520 ps
CPU time 8.2 seconds
Started Aug 18 04:52:15 PM PDT 24
Finished Aug 18 04:52:23 PM PDT 24
Peak memory 201788 kb
Host smart-42f49bbb-ff2f-42c9-8bfa-981a8a4ddff4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221693473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4221693473
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3652808667
Short name T594
Test name
Test status
Simulation time 1081433350 ps
CPU time 8.14 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:22 PM PDT 24
Peak memory 201952 kb
Host smart-fa3779f3-ce68-4edc-878e-8a3e64a7c053
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3652808667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3652808667
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1600662050
Short name T460
Test name
Test status
Simulation time 15270850 ps
CPU time 1.04 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:14 PM PDT 24
Peak memory 201844 kb
Host smart-de7beb64-81ab-400d-b7ac-656ce76fe7d2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600662050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1600662050
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2782324328
Short name T765
Test name
Test status
Simulation time 10859639 ps
CPU time 1.32 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201976 kb
Host smart-b1a40444-084d-4e6f-b5b6-d3b80d3b4bef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2782324328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2782324328
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2205449178
Short name T665
Test name
Test status
Simulation time 8716084724 ps
CPU time 64.47 seconds
Started Aug 18 04:52:12 PM PDT 24
Finished Aug 18 04:53:17 PM PDT 24
Peak memory 203044 kb
Host smart-e8c2f2e1-4648-4cd8-a9aa-707a7b877a32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2205449178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2205449178
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.670784666
Short name T874
Test name
Test status
Simulation time 1201859245 ps
CPU time 10.06 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:25 PM PDT 24
Peak memory 201912 kb
Host smart-95469465-099f-40f9-8b35-8d8971b2073b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=670784666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.670784666
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1224610612
Short name T381
Test name
Test status
Simulation time 304494428 ps
CPU time 5.84 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:19 PM PDT 24
Peak memory 201860 kb
Host smart-35f0be09-2e4a-4eb1-9b84-d3ac3c437275
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1224610612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1224610612
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2772883409
Short name T634
Test name
Test status
Simulation time 32111125485 ps
CPU time 121 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:54:14 PM PDT 24
Peak memory 201924 kb
Host smart-d637bb71-4f1a-4523-9ec7-3d52d93d9e95
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2772883409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.2772883409
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.928776261
Short name T324
Test name
Test status
Simulation time 14320488 ps
CPU time 1.45 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:26 PM PDT 24
Peak memory 201924 kb
Host smart-33bd014e-d9e3-445c-8044-5f672e9a65b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928776261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.928776261
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1156395632
Short name T800
Test name
Test status
Simulation time 28287322 ps
CPU time 1.24 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201836 kb
Host smart-f5b55637-d0ad-4ed8-ac1f-9d2eb3ff1e67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1156395632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1156395632
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.68917482
Short name T308
Test name
Test status
Simulation time 37098330 ps
CPU time 3.55 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:16 PM PDT 24
Peak memory 201832 kb
Host smart-69ffe2c7-c190-49f7-89ee-bf5512262248
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68917482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.68917482
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1930991452
Short name T741
Test name
Test status
Simulation time 19341954409 ps
CPU time 65.07 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 201960 kb
Host smart-ac32c22b-d177-4c2c-ab1d-0f19341eb28d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930991452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1930991452
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2972461217
Short name T44
Test name
Test status
Simulation time 6865019162 ps
CPU time 47.76 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 201908 kb
Host smart-6ec22d96-764a-453e-b7b0-d2db48123469
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2972461217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2972461217
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.403510674
Short name T351
Test name
Test status
Simulation time 53082508 ps
CPU time 5.73 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:19 PM PDT 24
Peak memory 201832 kb
Host smart-a7e65e92-8cac-4d34-812e-c1b68110618e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403510674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.403510674
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1783974247
Short name T708
Test name
Test status
Simulation time 34289052 ps
CPU time 1.89 seconds
Started Aug 18 04:52:15 PM PDT 24
Finished Aug 18 04:52:17 PM PDT 24
Peak memory 201860 kb
Host smart-800a15ff-138b-4a85-9b5b-db96f0917737
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783974247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1783974247
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.392595402
Short name T290
Test name
Test status
Simulation time 39318073 ps
CPU time 1.31 seconds
Started Aug 18 04:52:13 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201824 kb
Host smart-ee6cbbeb-92c3-4b2c-a5c4-b13d63c63828
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=392595402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.392595402
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2504978301
Short name T899
Test name
Test status
Simulation time 2736854782 ps
CPU time 8.44 seconds
Started Aug 18 04:52:16 PM PDT 24
Finished Aug 18 04:52:24 PM PDT 24
Peak memory 201832 kb
Host smart-690785ab-2f93-4dfb-a02f-f981a7af54d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504978301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2504978301
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3212654318
Short name T218
Test name
Test status
Simulation time 9439562644 ps
CPU time 9.05 seconds
Started Aug 18 04:52:16 PM PDT 24
Finished Aug 18 04:52:25 PM PDT 24
Peak memory 201928 kb
Host smart-2797e700-d1e5-4be0-9ca9-1d6d0c98b819
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3212654318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3212654318
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2838888392
Short name T431
Test name
Test status
Simulation time 17249607 ps
CPU time 1.13 seconds
Started Aug 18 04:52:14 PM PDT 24
Finished Aug 18 04:52:15 PM PDT 24
Peak memory 201944 kb
Host smart-4dc85b96-4808-474d-8771-2a25081d7e4f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838888392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2838888392
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1282680454
Short name T875
Test name
Test status
Simulation time 362327254 ps
CPU time 40.87 seconds
Started Aug 18 04:52:29 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 203012 kb
Host smart-869cb09d-6464-4ad0-8a3b-70c854cb97b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1282680454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1282680454
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.247362594
Short name T498
Test name
Test status
Simulation time 7263754884 ps
CPU time 30.92 seconds
Started Aug 18 04:52:28 PM PDT 24
Finished Aug 18 04:52:59 PM PDT 24
Peak memory 202020 kb
Host smart-4dfea68e-00fb-4343-9bdd-4a787077a84b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=247362594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.247362594
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2507237889
Short name T482
Test name
Test status
Simulation time 147988473 ps
CPU time 23.91 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:49 PM PDT 24
Peak memory 202952 kb
Host smart-c15bc030-6bcc-42f7-968e-104699030754
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2507237889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.2507237889
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2449215332
Short name T885
Test name
Test status
Simulation time 419887185 ps
CPU time 27.55 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:52 PM PDT 24
Peak memory 203856 kb
Host smart-c181590f-616b-4275-aee8-81ab1f077263
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2449215332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.2449215332
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1573185409
Short name T608
Test name
Test status
Simulation time 128436009 ps
CPU time 2.91 seconds
Started Aug 18 04:52:16 PM PDT 24
Finished Aug 18 04:52:19 PM PDT 24
Peak memory 201848 kb
Host smart-9bad15ee-4c74-4797-a613-b4a61672a03d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1573185409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1573185409
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1802391357
Short name T133
Test name
Test status
Simulation time 738165630 ps
CPU time 15.58 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:40 PM PDT 24
Peak memory 201828 kb
Host smart-05915b76-8905-444d-9188-8d9c0134f49b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1802391357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1802391357
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3285563409
Short name T196
Test name
Test status
Simulation time 69922096217 ps
CPU time 193.83 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:55:39 PM PDT 24
Peak memory 203056 kb
Host smart-ed2da3cf-4401-492c-9949-0847434e361e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3285563409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.3285563409
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2664840693
Short name T737
Test name
Test status
Simulation time 64500496 ps
CPU time 3.55 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:28 PM PDT 24
Peak memory 201840 kb
Host smart-a900b7c8-a29c-4cba-9fe6-91ef2f0f09bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2664840693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2664840693
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.2502141855
Short name T729
Test name
Test status
Simulation time 208517819 ps
CPU time 3.84 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:29 PM PDT 24
Peak memory 201944 kb
Host smart-c9864932-24bf-4596-ab60-3c336a1a7b50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2502141855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2502141855
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.1796589416
Short name T288
Test name
Test status
Simulation time 51147044 ps
CPU time 2.44 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:28 PM PDT 24
Peak memory 201816 kb
Host smart-2efd4729-80ed-4c91-acd7-b8df814b93da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1796589416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1796589416
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2399080587
Short name T759
Test name
Test status
Simulation time 7841054297 ps
CPU time 10.46 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:35 PM PDT 24
Peak memory 201876 kb
Host smart-5c0d3317-315f-4f70-b92e-175b1f96e9a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399080587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2399080587
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1079226011
Short name T33
Test name
Test status
Simulation time 64587412801 ps
CPU time 135.41 seconds
Started Aug 18 04:52:26 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 201992 kb
Host smart-9c283462-1721-4033-9f31-78fda1365cff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1079226011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1079226011
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.241920200
Short name T47
Test name
Test status
Simulation time 64144875 ps
CPU time 4.78 seconds
Started Aug 18 04:52:28 PM PDT 24
Finished Aug 18 04:52:33 PM PDT 24
Peak memory 201956 kb
Host smart-2376b0a6-b8a5-42f7-8008-d99cdc3618a4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241920200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.241920200
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.991042482
Short name T281
Test name
Test status
Simulation time 179780397 ps
CPU time 2.25 seconds
Started Aug 18 04:52:27 PM PDT 24
Finished Aug 18 04:52:29 PM PDT 24
Peak memory 201856 kb
Host smart-6641bd56-c877-4190-b259-a96937f4ccc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=991042482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.991042482
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.655998791
Short name T323
Test name
Test status
Simulation time 9199151 ps
CPU time 1.06 seconds
Started Aug 18 04:52:26 PM PDT 24
Finished Aug 18 04:52:28 PM PDT 24
Peak memory 201816 kb
Host smart-cb9e1f48-0495-491a-bb19-0cffb59ed171
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=655998791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.655998791
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.788268192
Short name T319
Test name
Test status
Simulation time 6560528667 ps
CPU time 11.78 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:36 PM PDT 24
Peak memory 201964 kb
Host smart-5f5cc8be-e9ec-4cbf-bcc7-5366773885a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=788268192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.788268192
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2422047932
Short name T220
Test name
Test status
Simulation time 2934630177 ps
CPU time 4.87 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:29 PM PDT 24
Peak memory 202016 kb
Host smart-58ffd3af-219e-4c85-bd35-1c56b7501ccc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2422047932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2422047932
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2347969533
Short name T366
Test name
Test status
Simulation time 9607230 ps
CPU time 1.05 seconds
Started Aug 18 04:52:27 PM PDT 24
Finished Aug 18 04:52:28 PM PDT 24
Peak memory 201852 kb
Host smart-9d05cf03-8399-4747-af0b-102267036190
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347969533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2347969533
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3793833240
Short name T340
Test name
Test status
Simulation time 260911940 ps
CPU time 30.81 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:55 PM PDT 24
Peak memory 202876 kb
Host smart-28868a9f-a8c1-4f22-be4e-d9e07e5cb40b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3793833240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3793833240
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1687497317
Short name T789
Test name
Test status
Simulation time 8028430095 ps
CPU time 22.13 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:46 PM PDT 24
Peak memory 201876 kb
Host smart-adbc05f5-df30-4752-ae1e-439ed0e3396e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1687497317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1687497317
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.4205190210
Short name T81
Test name
Test status
Simulation time 508288952 ps
CPU time 8.21 seconds
Started Aug 18 04:52:26 PM PDT 24
Finished Aug 18 04:52:35 PM PDT 24
Peak memory 201856 kb
Host smart-12756196-c9c4-4c8d-a330-c5cdf558b038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4205190210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4205190210
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2513738592
Short name T242
Test name
Test status
Simulation time 298972677 ps
CPU time 7.32 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:43 PM PDT 24
Peak memory 201772 kb
Host smart-ab93a989-3104-4b62-a667-c17ac05c345d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2513738592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2513738592
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.284793062
Short name T888
Test name
Test status
Simulation time 66314497 ps
CPU time 2.67 seconds
Started Aug 18 04:52:33 PM PDT 24
Finished Aug 18 04:52:36 PM PDT 24
Peak memory 201864 kb
Host smart-2d42d2cd-de58-4b51-9e91-297279db327b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=284793062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.284793062
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.3437088015
Short name T412
Test name
Test status
Simulation time 740251419 ps
CPU time 6.44 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:41 PM PDT 24
Peak memory 201848 kb
Host smart-403e0357-1e31-4fd4-8579-762f8c13b320
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437088015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3437088015
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.1199620326
Short name T237
Test name
Test status
Simulation time 151446214 ps
CPU time 3.5 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:28 PM PDT 24
Peak memory 201884 kb
Host smart-b973aa3f-7cf8-4acd-b13f-ce38ea2e7aa5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1199620326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1199620326
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2787407477
Short name T764
Test name
Test status
Simulation time 31105282168 ps
CPU time 76.49 seconds
Started Aug 18 04:52:26 PM PDT 24
Finished Aug 18 04:53:43 PM PDT 24
Peak memory 201964 kb
Host smart-16b64ad1-a47a-47c7-b721-46a83bb6b901
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787407477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2787407477
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.733112089
Short name T16
Test name
Test status
Simulation time 25197768668 ps
CPU time 133.33 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:54:38 PM PDT 24
Peak memory 201988 kb
Host smart-6a603e46-067d-4d19-bee0-186e6f8f7bb9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=733112089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.733112089
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2564972431
Short name T273
Test name
Test status
Simulation time 15668520 ps
CPU time 1.83 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:27 PM PDT 24
Peak memory 201836 kb
Host smart-21f507c9-2d7f-49d7-93b1-b8367b330a12
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564972431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2564972431
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.1049128984
Short name T30
Test name
Test status
Simulation time 609253906 ps
CPU time 5.1 seconds
Started Aug 18 04:52:37 PM PDT 24
Finished Aug 18 04:52:42 PM PDT 24
Peak memory 201788 kb
Host smart-daed35bf-5af2-4d85-93c6-6c111fa58c7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1049128984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1049128984
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.1496485858
Short name T630
Test name
Test status
Simulation time 111910533 ps
CPU time 1.36 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:27 PM PDT 24
Peak memory 201836 kb
Host smart-cc4bd145-e149-4953-ac99-609be77df2d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1496485858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1496485858
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2825057235
Short name T522
Test name
Test status
Simulation time 2930036485 ps
CPU time 8.41 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:33 PM PDT 24
Peak memory 201880 kb
Host smart-9390dd78-d2bc-43de-957c-dedeab5176d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825057235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2825057235
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.4217281990
Short name T248
Test name
Test status
Simulation time 3575312995 ps
CPU time 7.37 seconds
Started Aug 18 04:52:25 PM PDT 24
Finished Aug 18 04:52:33 PM PDT 24
Peak memory 201932 kb
Host smart-c26a6f56-76ab-4fe9-9309-6a66ffaec693
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4217281990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4217281990
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3704617090
Short name T493
Test name
Test status
Simulation time 24298605 ps
CPU time 1.14 seconds
Started Aug 18 04:52:24 PM PDT 24
Finished Aug 18 04:52:25 PM PDT 24
Peak memory 201844 kb
Host smart-138ff708-0eaf-4523-a819-4f2e1194afbd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704617090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3704617090
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3701884761
Short name T31
Test name
Test status
Simulation time 255166134 ps
CPU time 31.19 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:53:05 PM PDT 24
Peak memory 202888 kb
Host smart-de9d6845-f3bf-402c-b873-32197f499103
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3701884761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3701884761
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2013822560
Short name T861
Test name
Test status
Simulation time 1482923578 ps
CPU time 23.25 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:59 PM PDT 24
Peak memory 201940 kb
Host smart-0295a249-0eb6-4d22-bad6-e6dfd0627074
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2013822560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2013822560
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2259995310
Short name T206
Test name
Test status
Simulation time 326358168 ps
CPU time 27.81 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:53:02 PM PDT 24
Peak memory 204068 kb
Host smart-da94fa33-0a7f-43b6-b1ce-5985e8139043
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259995310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.2259995310
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1550757099
Short name T208
Test name
Test status
Simulation time 626705018 ps
CPU time 79.16 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:53:55 PM PDT 24
Peak memory 203828 kb
Host smart-cb24cbb8-1368-410d-a563-9a4eac3ff0d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1550757099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.1550757099
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1256569854
Short name T402
Test name
Test status
Simulation time 1973405992 ps
CPU time 5.35 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:42 PM PDT 24
Peak memory 201948 kb
Host smart-82d98bbb-490d-45c1-ae1a-69633080ce18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1256569854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1256569854
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3638945077
Short name T42
Test name
Test status
Simulation time 48496704 ps
CPU time 2.84 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:52:37 PM PDT 24
Peak memory 201840 kb
Host smart-53ab5c5d-b2da-4554-8f48-5838dfa43b41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3638945077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3638945077
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2957962944
Short name T197
Test name
Test status
Simulation time 178833085318 ps
CPU time 268.68 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:57:04 PM PDT 24
Peak memory 203000 kb
Host smart-58cad350-2f5e-4654-a7f8-419ce3e15669
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2957962944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.2957962944
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3997026345
Short name T15
Test name
Test status
Simulation time 84336117 ps
CPU time 4.44 seconds
Started Aug 18 04:52:33 PM PDT 24
Finished Aug 18 04:52:38 PM PDT 24
Peak memory 201924 kb
Host smart-ebe78be2-df70-41da-934f-d5b6accfd05e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3997026345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3997026345
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.1487110953
Short name T715
Test name
Test status
Simulation time 52150324 ps
CPU time 7.35 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:52:42 PM PDT 24
Peak memory 201948 kb
Host smart-a07b7d03-d830-486d-8aad-48e5064d0a82
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1487110953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1487110953
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.901962211
Short name T141
Test name
Test status
Simulation time 680375512 ps
CPU time 12.33 seconds
Started Aug 18 04:52:37 PM PDT 24
Finished Aug 18 04:52:49 PM PDT 24
Peak memory 201888 kb
Host smart-ad358239-fcb2-4eb0-978b-3c3f57ab57f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=901962211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.901962211
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3279665267
Short name T705
Test name
Test status
Simulation time 2193367705 ps
CPU time 6.71 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:43 PM PDT 24
Peak memory 201792 kb
Host smart-b966b4b6-36aa-473a-8d96-afa229a575ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279665267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3279665267
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2116724608
Short name T565
Test name
Test status
Simulation time 11027195768 ps
CPU time 62.92 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:53:37 PM PDT 24
Peak memory 201916 kb
Host smart-5a957383-d593-44f9-aa6b-1bd7b53f12de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2116724608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2116724608
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3511554300
Short name T508
Test name
Test status
Simulation time 38074236 ps
CPU time 3.98 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:40 PM PDT 24
Peak memory 201852 kb
Host smart-733abf95-0f0a-4f32-a475-54183d0b8697
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511554300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3511554300
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.165089133
Short name T868
Test name
Test status
Simulation time 2819247035 ps
CPU time 12.48 seconds
Started Aug 18 04:52:33 PM PDT 24
Finished Aug 18 04:52:45 PM PDT 24
Peak memory 201904 kb
Host smart-74df3511-4aed-4770-a547-2edcf6efa25a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=165089133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.165089133
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.4247100553
Short name T523
Test name
Test status
Simulation time 81396441 ps
CPU time 1.38 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:38 PM PDT 24
Peak memory 201864 kb
Host smart-8d95efac-6023-46cd-90e1-60b5c408e43d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4247100553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4247100553
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2131223488
Short name T860
Test name
Test status
Simulation time 1951131795 ps
CPU time 6.39 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:42 PM PDT 24
Peak memory 201916 kb
Host smart-786300e8-09ee-4a27-85a9-301a246be688
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131223488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2131223488
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3637692210
Short name T770
Test name
Test status
Simulation time 969729900 ps
CPU time 5.88 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:41 PM PDT 24
Peak memory 201928 kb
Host smart-d2fd7414-bd9b-4d73-8fec-67b6189aaa4f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3637692210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3637692210
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3632692249
Short name T828
Test name
Test status
Simulation time 10516183 ps
CPU time 1.23 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:37 PM PDT 24
Peak memory 201852 kb
Host smart-a7e334e5-f126-4e8e-b7e4-bc31534b317f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632692249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3632692249
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.3948545145
Short name T566
Test name
Test status
Simulation time 128664937 ps
CPU time 19.23 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:55 PM PDT 24
Peak memory 201960 kb
Host smart-fc7cc897-e0b6-4b6c-96b8-ea7849efc8b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3948545145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3948545145
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.458023903
Short name T859
Test name
Test status
Simulation time 242187713 ps
CPU time 25.19 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 202128 kb
Host smart-18674b07-1bc1-4bdc-932a-a285e06a006c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=458023903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.458023903
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3477454603
Short name T698
Test name
Test status
Simulation time 407462148 ps
CPU time 62.83 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:53:38 PM PDT 24
Peak memory 204440 kb
Host smart-5796f920-3fd9-4ac4-9c9b-8d1068ee33d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3477454603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.3477454603
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1705495961
Short name T795
Test name
Test status
Simulation time 23429747 ps
CPU time 2.82 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:52:37 PM PDT 24
Peak memory 201936 kb
Host smart-71749cc1-31b5-4e95-96cd-4fe18849fcfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1705495961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1705495961
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.695028683
Short name T645
Test name
Test status
Simulation time 3406886633 ps
CPU time 13.53 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:48 PM PDT 24
Peak memory 201916 kb
Host smart-e6641ff4-05fe-44f8-9f58-34af9116c9ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=695028683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.695028683
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3089745650
Short name T798
Test name
Test status
Simulation time 4622996111 ps
CPU time 19.07 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:53:04 PM PDT 24
Peak memory 201916 kb
Host smart-25818c31-98a0-49fa-b829-08bb6b6b35fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3089745650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.3089745650
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1819786991
Short name T816
Test name
Test status
Simulation time 410052787 ps
CPU time 5.65 seconds
Started Aug 18 04:52:45 PM PDT 24
Finished Aug 18 04:52:51 PM PDT 24
Peak memory 201936 kb
Host smart-628e7120-722e-492c-87cf-9bff703f4819
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1819786991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1819786991
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.3318544566
Short name T572
Test name
Test status
Simulation time 2492126841 ps
CPU time 12.4 seconds
Started Aug 18 04:52:45 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 202008 kb
Host smart-055f7db9-2633-4199-8d35-86c5fd8adab6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3318544566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3318544566
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.4224650636
Short name T183
Test name
Test status
Simulation time 18871259 ps
CPU time 2.15 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:38 PM PDT 24
Peak memory 201728 kb
Host smart-fd5474a2-3546-402e-b593-1df597a92d03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4224650636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4224650636
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3107377147
Short name T258
Test name
Test status
Simulation time 52247975398 ps
CPU time 93.22 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:54:09 PM PDT 24
Peak memory 201944 kb
Host smart-13ba63e7-f6c9-4d7e-84b2-e16b6c759574
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107377147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3107377147
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.281092817
Short name T624
Test name
Test status
Simulation time 31491964284 ps
CPU time 113.03 seconds
Started Aug 18 04:52:37 PM PDT 24
Finished Aug 18 04:54:30 PM PDT 24
Peak memory 201932 kb
Host smart-cc2722ec-8c42-4e2f-89e7-65e4b7ec292c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=281092817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.281092817
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2590693760
Short name T48
Test name
Test status
Simulation time 103281360 ps
CPU time 6.62 seconds
Started Aug 18 04:52:36 PM PDT 24
Finished Aug 18 04:52:43 PM PDT 24
Peak memory 201816 kb
Host smart-cf7be2d2-9592-440b-bd80-7d6df326dfb1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590693760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2590693760
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.925212524
Short name T640
Test name
Test status
Simulation time 1179867297 ps
CPU time 13.96 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 201856 kb
Host smart-e92b8397-d7f7-4299-8cc1-8c9d1f8a5b58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925212524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.925212524
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.897172623
Short name T421
Test name
Test status
Simulation time 50573874 ps
CPU time 1.59 seconds
Started Aug 18 04:52:34 PM PDT 24
Finished Aug 18 04:52:36 PM PDT 24
Peak memory 201900 kb
Host smart-801edb9e-0277-4e48-bfa0-72a146d75170
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=897172623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.897172623
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2195023431
Short name T472
Test name
Test status
Simulation time 5162095029 ps
CPU time 12.6 seconds
Started Aug 18 04:52:35 PM PDT 24
Finished Aug 18 04:52:48 PM PDT 24
Peak memory 201960 kb
Host smart-c780624f-a89e-41b8-80e7-3876a43f07c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195023431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2195023431
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2696692280
Short name T629
Test name
Test status
Simulation time 1994844114 ps
CPU time 8.55 seconds
Started Aug 18 04:52:33 PM PDT 24
Finished Aug 18 04:52:42 PM PDT 24
Peak memory 201808 kb
Host smart-64cc1657-7b11-49dd-aed0-d4c1e2644547
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2696692280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2696692280
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.179529343
Short name T241
Test name
Test status
Simulation time 10169757 ps
CPU time 1.34 seconds
Started Aug 18 04:52:37 PM PDT 24
Finished Aug 18 04:52:38 PM PDT 24
Peak memory 201928 kb
Host smart-652d256c-eb01-4948-a130-39638fb23d3c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179529343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.179529343
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.500000951
Short name T563
Test name
Test status
Simulation time 2620613411 ps
CPU time 39.3 seconds
Started Aug 18 04:52:45 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 203064 kb
Host smart-53e53f41-75d2-4b75-984a-003a283e7b47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=500000951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.500000951
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.4058282652
Short name T891
Test name
Test status
Simulation time 13895147976 ps
CPU time 36.35 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:53:20 PM PDT 24
Peak memory 202028 kb
Host smart-57b50913-d1b1-4b80-8c94-6272a3c72e53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4058282652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.4058282652
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.713272126
Short name T105
Test name
Test status
Simulation time 3399740154 ps
CPU time 73.93 seconds
Started Aug 18 04:52:46 PM PDT 24
Finished Aug 18 04:54:00 PM PDT 24
Peak memory 205104 kb
Host smart-68d87673-406c-436a-ad21-3fbf6d8f7ebb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=713272126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand
_reset.713272126
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.786701158
Short name T663
Test name
Test status
Simulation time 50012215 ps
CPU time 2.55 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:52:46 PM PDT 24
Peak memory 201860 kb
Host smart-acadb206-73cf-4916-bcfb-d629a96a3958
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=786701158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.786701158
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.35038794
Short name T321
Test name
Test status
Simulation time 33920332 ps
CPU time 6.58 seconds
Started Aug 18 04:52:43 PM PDT 24
Finished Aug 18 04:52:50 PM PDT 24
Peak memory 201832 kb
Host smart-5ccd2d72-b0db-476c-bf7e-57e3c2c65a6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35038794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.35038794
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1214514751
Short name T811
Test name
Test status
Simulation time 72304224834 ps
CPU time 142.64 seconds
Started Aug 18 04:52:43 PM PDT 24
Finished Aug 18 04:55:05 PM PDT 24
Peak memory 203008 kb
Host smart-1d68d12f-188c-487e-b5a6-9afd82129e22
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1214514751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.1214514751
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.681280446
Short name T233
Test name
Test status
Simulation time 209242546 ps
CPU time 5.63 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:52:50 PM PDT 24
Peak memory 201932 kb
Host smart-27b3b38a-5be0-4cfb-8b93-5021f8c476fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681280446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.681280446
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.473957477
Short name T651
Test name
Test status
Simulation time 38761418 ps
CPU time 1.17 seconds
Started Aug 18 04:52:43 PM PDT 24
Finished Aug 18 04:52:45 PM PDT 24
Peak memory 201936 kb
Host smart-eeeb09e3-0f67-4f43-9c6f-fb77485d75d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=473957477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.473957477
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.3490460561
Short name T69
Test name
Test status
Simulation time 131381877 ps
CPU time 1.51 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:52:45 PM PDT 24
Peak memory 201828 kb
Host smart-4b044f72-fbeb-48b6-8bfc-93804d8d14f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3490460561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3490460561
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2171956109
Short name T408
Test name
Test status
Simulation time 58911526532 ps
CPU time 156.24 seconds
Started Aug 18 04:52:46 PM PDT 24
Finished Aug 18 04:55:23 PM PDT 24
Peak memory 201944 kb
Host smart-f451affa-939f-4318-8699-437df1d9e113
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171956109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2171956109
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4274168138
Short name T553
Test name
Test status
Simulation time 4251206064 ps
CPU time 27.89 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:53:12 PM PDT 24
Peak memory 201880 kb
Host smart-b50dbe68-17b3-43ee-a0f2-908d5ae53519
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4274168138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4274168138
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2851034160
Short name T588
Test name
Test status
Simulation time 69497707 ps
CPU time 5.42 seconds
Started Aug 18 04:52:47 PM PDT 24
Finished Aug 18 04:52:52 PM PDT 24
Peak memory 201928 kb
Host smart-bd1b0835-d413-456b-aa43-4b6c0132c621
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851034160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2851034160
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2723816452
Short name T896
Test name
Test status
Simulation time 433806014 ps
CPU time 5.64 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:52:49 PM PDT 24
Peak memory 201824 kb
Host smart-ce573f8c-c1df-4dda-9264-1a861c937723
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2723816452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2723816452
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.1449786541
Short name T439
Test name
Test status
Simulation time 32887505 ps
CPU time 1.28 seconds
Started Aug 18 04:52:46 PM PDT 24
Finished Aug 18 04:52:47 PM PDT 24
Peak memory 201784 kb
Host smart-ddbd3e86-51c0-4b9b-9c6b-f177a88d2b97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449786541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1449786541
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3200504661
Short name T483
Test name
Test status
Simulation time 1679714952 ps
CPU time 8.27 seconds
Started Aug 18 04:52:46 PM PDT 24
Finished Aug 18 04:52:55 PM PDT 24
Peak memory 201792 kb
Host smart-e60a5c3a-b903-4d36-a425-0cb72481605c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200504661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3200504661
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3441124389
Short name T138
Test name
Test status
Simulation time 1599415828 ps
CPU time 5.87 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:52:50 PM PDT 24
Peak memory 201956 kb
Host smart-18b43087-eb2d-4058-ae40-8bcda60d9707
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3441124389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3441124389
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.54650410
Short name T671
Test name
Test status
Simulation time 9037264 ps
CPU time 1.12 seconds
Started Aug 18 04:52:45 PM PDT 24
Finished Aug 18 04:52:46 PM PDT 24
Peak memory 201924 kb
Host smart-672ebaa6-5b7e-4037-9536-7855f86e4437
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54650410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.54650410
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2464807776
Short name T316
Test name
Test status
Simulation time 14808818039 ps
CPU time 106.4 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:54:31 PM PDT 24
Peak memory 203508 kb
Host smart-75099d2e-8c68-460d-97f1-c9a9748265fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2464807776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2464807776
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3333527502
Short name T191
Test name
Test status
Simulation time 3162703861 ps
CPU time 59.57 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:53:44 PM PDT 24
Peak memory 202000 kb
Host smart-1ef58c7c-2e78-4bec-b801-122291d12357
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3333527502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3333527502
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.46256585
Short name T745
Test name
Test status
Simulation time 620600157 ps
CPU time 132.62 seconds
Started Aug 18 04:52:44 PM PDT 24
Finished Aug 18 04:54:57 PM PDT 24
Peak memory 207832 kb
Host smart-d980462b-506d-4b8d-ad48-747e789e6813
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46256585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_
reset.46256585
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2231337390
Short name T209
Test name
Test status
Simulation time 6482794000 ps
CPU time 102.72 seconds
Started Aug 18 04:52:45 PM PDT 24
Finished Aug 18 04:54:28 PM PDT 24
Peak memory 205984 kb
Host smart-008355c2-830a-41bd-9aff-911d2761d5f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2231337390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2231337390
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1541254720
Short name T416
Test name
Test status
Simulation time 98357596 ps
CPU time 6.3 seconds
Started Aug 18 04:52:43 PM PDT 24
Finished Aug 18 04:52:49 PM PDT 24
Peak memory 201860 kb
Host smart-0a461114-694a-465b-b350-20eceefb8275
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541254720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1541254720
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3233094730
Short name T409
Test name
Test status
Simulation time 362158978 ps
CPU time 7.65 seconds
Started Aug 18 04:52:59 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201836 kb
Host smart-23d9a2cf-dddb-4d97-932d-9f824c813e52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3233094730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3233094730
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1732503814
Short name T71
Test name
Test status
Simulation time 31263489567 ps
CPU time 216.2 seconds
Started Aug 18 04:53:01 PM PDT 24
Finished Aug 18 04:56:37 PM PDT 24
Peak memory 202964 kb
Host smart-c459b876-82fb-49b7-a19e-fd2e35516040
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1732503814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.1732503814
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3063386164
Short name T727
Test name
Test status
Simulation time 1264100066 ps
CPU time 10.03 seconds
Started Aug 18 04:52:54 PM PDT 24
Finished Aug 18 04:53:04 PM PDT 24
Peak memory 201844 kb
Host smart-44ba6964-2161-4989-81ad-ddd741482810
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3063386164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3063386164
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.556618976
Short name T21
Test name
Test status
Simulation time 194223548 ps
CPU time 3.96 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:52:59 PM PDT 24
Peak memory 201936 kb
Host smart-6cf83455-2928-4d4b-88c2-c0b76cf60a81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=556618976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.556618976
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.973888382
Short name T425
Test name
Test status
Simulation time 393509467 ps
CPU time 2.92 seconds
Started Aug 18 04:52:57 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 201828 kb
Host smart-4498d8fe-051e-4024-9fba-440258831c44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=973888382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.973888382
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.4136849387
Short name T704
Test name
Test status
Simulation time 10039530197 ps
CPU time 38.88 seconds
Started Aug 18 04:52:59 PM PDT 24
Finished Aug 18 04:53:38 PM PDT 24
Peak memory 201876 kb
Host smart-dcfe3fb2-fc33-48ee-86f0-350ca53219e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136849387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4136849387
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1298202748
Short name T660
Test name
Test status
Simulation time 22270238786 ps
CPU time 82.28 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 202016 kb
Host smart-aa57a4d8-099f-4312-a2e8-7a01b16b9b14
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1298202748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1298202748
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.158488971
Short name T261
Test name
Test status
Simulation time 23436900 ps
CPU time 1.99 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 202132 kb
Host smart-6cc57a83-5406-4cb9-807e-edbf89cca936
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158488971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.158488971
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.291855242
Short name T547
Test name
Test status
Simulation time 1882328503 ps
CPU time 13.92 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 201944 kb
Host smart-a771eae7-aa4e-46ba-a182-47e157d94de2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291855242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.291855242
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.2387497526
Short name T897
Test name
Test status
Simulation time 117584501 ps
CPU time 1.66 seconds
Started Aug 18 04:52:59 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 201808 kb
Host smart-3a6d8e04-ee2f-4baf-8f79-ffb5dc36d968
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2387497526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2387497526
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4123406974
Short name T130
Test name
Test status
Simulation time 2004628511 ps
CPU time 10.19 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:06 PM PDT 24
Peak memory 201776 kb
Host smart-44973a9f-4a51-46b6-b158-99100cd8a126
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123406974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4123406974
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2978956340
Short name T718
Test name
Test status
Simulation time 1383059759 ps
CPU time 6.6 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:03 PM PDT 24
Peak memory 201968 kb
Host smart-db91a0ca-854b-4cb4-b851-ddb2937d8695
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2978956340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2978956340
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.922346517
Short name T480
Test name
Test status
Simulation time 10499204 ps
CPU time 1.3 seconds
Started Aug 18 04:52:57 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 201856 kb
Host smart-d6f8cac7-b63e-4de3-b091-d9016f6b013c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922346517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.922346517
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.799987686
Short name T855
Test name
Test status
Simulation time 2959368255 ps
CPU time 62.04 seconds
Started Aug 18 04:52:58 PM PDT 24
Finished Aug 18 04:54:01 PM PDT 24
Peak memory 202992 kb
Host smart-ef4e49c1-fb06-4a1b-8224-e3a232ba6379
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=799987686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.799987686
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3699540459
Short name T334
Test name
Test status
Simulation time 821648434 ps
CPU time 33.78 seconds
Started Aug 18 04:52:54 PM PDT 24
Finished Aug 18 04:53:28 PM PDT 24
Peak memory 201956 kb
Host smart-a9926009-bca2-482c-8d1f-d9584d6eaf5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3699540459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3699540459
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.630050833
Short name T297
Test name
Test status
Simulation time 685959140 ps
CPU time 84.23 seconds
Started Aug 18 04:52:57 PM PDT 24
Finished Aug 18 04:54:22 PM PDT 24
Peak memory 203968 kb
Host smart-4a8857c6-ed6b-44fe-b989-934d776537f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=630050833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand
_reset.630050833
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.467688571
Short name T706
Test name
Test status
Simulation time 340854457 ps
CPU time 24.39 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:53:19 PM PDT 24
Peak memory 202968 kb
Host smart-d2768473-55a6-47a4-bb30-4b676e881668
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=467688571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res
et_error.467688571
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4050158221
Short name T890
Test name
Test status
Simulation time 161696865 ps
CPU time 4.13 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:52:59 PM PDT 24
Peak memory 201876 kb
Host smart-53a2680d-6bb1-42be-85bf-5bc9e7299f7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4050158221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4050158221
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1192434004
Short name T756
Test name
Test status
Simulation time 471237109 ps
CPU time 11.27 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:08 PM PDT 24
Peak memory 201948 kb
Host smart-d1eb170c-733e-4678-a858-66b23f729c13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1192434004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1192434004
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4146799376
Short name T564
Test name
Test status
Simulation time 2235000023 ps
CPU time 10.06 seconds
Started Aug 18 04:53:00 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 201912 kb
Host smart-80718323-682e-445d-9f62-b9ce83a3d24d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4146799376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4146799376
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.393614754
Short name T433
Test name
Test status
Simulation time 226024260 ps
CPU time 2.47 seconds
Started Aug 18 04:52:59 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 201864 kb
Host smart-ef6acef9-3b67-42f1-a3d8-09678b0671e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=393614754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.393614754
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.932409015
Short name T803
Test name
Test status
Simulation time 604590552 ps
CPU time 9.34 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:53:05 PM PDT 24
Peak memory 201908 kb
Host smart-698281e7-f431-4382-b3cc-a89b0a10c344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=932409015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.932409015
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2821663529
Short name T67
Test name
Test status
Simulation time 20494052077 ps
CPU time 46.51 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:53:41 PM PDT 24
Peak memory 201868 kb
Host smart-3221f506-899f-4d10-b05c-29c846654999
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821663529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2821663529
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.636235803
Short name T256
Test name
Test status
Simulation time 19355360644 ps
CPU time 113.91 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 201940 kb
Host smart-b7322198-8a66-4c67-893c-4696eb097100
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=636235803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.636235803
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.685935271
Short name T680
Test name
Test status
Simulation time 165944756 ps
CPU time 8.51 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:05 PM PDT 24
Peak memory 201856 kb
Host smart-85c60f15-dd79-475e-b8be-2e50d57a53d9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685935271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.685935271
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.4227425065
Short name T713
Test name
Test status
Simulation time 829601822 ps
CPU time 10.91 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:53:06 PM PDT 24
Peak memory 201864 kb
Host smart-9e4970e6-c74e-4557-91a9-edec7a6b1c1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4227425065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.4227425065
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2707190954
Short name T286
Test name
Test status
Simulation time 21188056 ps
CPU time 1.39 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 201732 kb
Host smart-e584f2f9-2a9f-49ec-8041-d4e92440b483
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2707190954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2707190954
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.51096898
Short name T19
Test name
Test status
Simulation time 2699863524 ps
CPU time 11.75 seconds
Started Aug 18 04:52:57 PM PDT 24
Finished Aug 18 04:53:09 PM PDT 24
Peak memory 201856 kb
Host smart-6cbb1c5e-8c15-4416-a464-892b2560233d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=51096898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.51096898
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2809403826
Short name T452
Test name
Test status
Simulation time 2821818423 ps
CPU time 8.29 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:05 PM PDT 24
Peak memory 201840 kb
Host smart-b7850b2b-7d1f-4824-9ea1-9d5b7ac2ccb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2809403826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2809403826
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3300920572
Short name T305
Test name
Test status
Simulation time 11010277 ps
CPU time 1.25 seconds
Started Aug 18 04:52:57 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 201860 kb
Host smart-aa3bacb5-0b73-4e49-9a22-34fe71fcc362
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300920572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3300920572
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3564718921
Short name T287
Test name
Test status
Simulation time 3497802879 ps
CPU time 64.23 seconds
Started Aug 18 04:52:58 PM PDT 24
Finished Aug 18 04:54:02 PM PDT 24
Peak memory 202012 kb
Host smart-93f0d97d-0308-4980-90f9-bb04a68c40a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3564718921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3564718921
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2143370853
Short name T866
Test name
Test status
Simulation time 12850293509 ps
CPU time 93.17 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 203020 kb
Host smart-d5c65e18-a6f9-469c-9e5f-9ce95b16a6a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2143370853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2143370853
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2764385356
Short name T548
Test name
Test status
Simulation time 6906043 ps
CPU time 0.91 seconds
Started Aug 18 04:52:58 PM PDT 24
Finished Aug 18 04:52:59 PM PDT 24
Peak memory 201780 kb
Host smart-26c54f4d-dff4-46b9-87ba-5ab4df3e5671
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2764385356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.2764385356
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2311296330
Short name T746
Test name
Test status
Simulation time 9798438423 ps
CPU time 58.42 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:54 PM PDT 24
Peak memory 203212 kb
Host smart-c340ce64-448b-4693-9091-ba9e8e83b416
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2311296330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re
set_error.2311296330
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2185482900
Short name T361
Test name
Test status
Simulation time 108282533 ps
CPU time 3.35 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:52:59 PM PDT 24
Peak memory 201864 kb
Host smart-b46f5597-12f3-4dc2-8df5-fce4aed91a49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2185482900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2185482900
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2002638750
Short name T559
Test name
Test status
Simulation time 877260454 ps
CPU time 21.21 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:48 PM PDT 24
Peak memory 201888 kb
Host smart-82fc8ff5-68e5-4a27-b88b-5d897aaf6cf9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2002638750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2002638750
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.408244127
Short name T738
Test name
Test status
Simulation time 146406177 ps
CPU time 4.59 seconds
Started Aug 18 04:51:24 PM PDT 24
Finished Aug 18 04:51:29 PM PDT 24
Peak memory 201860 kb
Host smart-8425c98a-eb1d-4b56-bfdb-79612726de84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=408244127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.408244127
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.3798194724
Short name T843
Test name
Test status
Simulation time 2376770431 ps
CPU time 12.51 seconds
Started Aug 18 04:51:28 PM PDT 24
Finished Aug 18 04:51:41 PM PDT 24
Peak memory 201908 kb
Host smart-6551e655-0c1f-46e1-be08-5caf575a209d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3798194724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3798194724
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.1108968752
Short name T303
Test name
Test status
Simulation time 513850478 ps
CPU time 8.81 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:35 PM PDT 24
Peak memory 201872 kb
Host smart-c3309970-49ad-4091-ad5f-b16fa86a2994
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1108968752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1108968752
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3071852130
Short name T614
Test name
Test status
Simulation time 39353777047 ps
CPU time 41.52 seconds
Started Aug 18 04:51:27 PM PDT 24
Finished Aug 18 04:52:09 PM PDT 24
Peak memory 201796 kb
Host smart-6a39accb-df05-4b79-80c9-dfaba4752610
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071852130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3071852130
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.413572606
Short name T576
Test name
Test status
Simulation time 9796514847 ps
CPU time 20.72 seconds
Started Aug 18 04:51:27 PM PDT 24
Finished Aug 18 04:51:48 PM PDT 24
Peak memory 201904 kb
Host smart-ad4195cb-8717-4f10-8171-0567ed89fdfc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=413572606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.413572606
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1705284116
Short name T314
Test name
Test status
Simulation time 54138842 ps
CPU time 4.3 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:31 PM PDT 24
Peak memory 201848 kb
Host smart-761e6aaa-c4a8-40cd-b54f-99e1e34975a9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705284116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1705284116
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.333708575
Short name T836
Test name
Test status
Simulation time 846510666 ps
CPU time 6.87 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:32 PM PDT 24
Peak memory 201952 kb
Host smart-50458339-cc43-4da3-96f2-422533d365e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=333708575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.333708575
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.1060877017
Short name T236
Test name
Test status
Simulation time 140518163 ps
CPU time 1.44 seconds
Started Aug 18 04:51:24 PM PDT 24
Finished Aug 18 04:51:26 PM PDT 24
Peak memory 201912 kb
Host smart-ea327a8c-9fa6-404d-9ad3-8a77723f326f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1060877017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1060877017
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2543685598
Short name T289
Test name
Test status
Simulation time 5529221569 ps
CPU time 9.18 seconds
Started Aug 18 04:51:27 PM PDT 24
Finished Aug 18 04:51:37 PM PDT 24
Peak memory 201812 kb
Host smart-7790924f-e914-42b9-b425-484bfbc423e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543685598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2543685598
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.708596042
Short name T229
Test name
Test status
Simulation time 2400895513 ps
CPU time 8.21 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:35 PM PDT 24
Peak memory 201940 kb
Host smart-ea693c51-24fc-4e71-afde-f32765cbd356
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=708596042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.708596042
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2315071368
Short name T786
Test name
Test status
Simulation time 10033167 ps
CPU time 1.16 seconds
Started Aug 18 04:51:25 PM PDT 24
Finished Aug 18 04:51:26 PM PDT 24
Peak memory 201956 kb
Host smart-c6f09185-e9da-4888-81c9-f684ab7f2ff1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315071368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2315071368
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3897592904
Short name T106
Test name
Test status
Simulation time 4917025005 ps
CPU time 45.87 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:52:20 PM PDT 24
Peak memory 202964 kb
Host smart-4110a1de-16ab-4857-87b7-5857144f934e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3897592904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3897592904
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3316440411
Short name T358
Test name
Test status
Simulation time 104344458 ps
CPU time 9.49 seconds
Started Aug 18 04:51:36 PM PDT 24
Finished Aug 18 04:51:46 PM PDT 24
Peak memory 201848 kb
Host smart-3a2dbeae-4f5b-4be0-aff2-cd9807ab1032
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3316440411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3316440411
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2816719333
Short name T376
Test name
Test status
Simulation time 325431524 ps
CPU time 30.54 seconds
Started Aug 18 04:51:36 PM PDT 24
Finished Aug 18 04:52:07 PM PDT 24
Peak memory 204216 kb
Host smart-fcca695c-9de1-42e9-b2bb-fc332bccbc08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2816719333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.2816719333
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.635443965
Short name T442
Test name
Test status
Simulation time 11098057 ps
CPU time 4.95 seconds
Started Aug 18 04:51:38 PM PDT 24
Finished Aug 18 04:51:43 PM PDT 24
Peak memory 201940 kb
Host smart-7093e8ca-70bc-497f-894c-06d5ea6f5d0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=635443965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese
t_error.635443965
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2409079994
Short name T492
Test name
Test status
Simulation time 528337881 ps
CPU time 1.79 seconds
Started Aug 18 04:51:26 PM PDT 24
Finished Aug 18 04:51:28 PM PDT 24
Peak memory 201860 kb
Host smart-a9e64c80-a9da-4265-bcb3-a31f29d4cf08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2409079994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2409079994
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.893362802
Short name T54
Test name
Test status
Simulation time 30287169 ps
CPU time 5.9 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:14 PM PDT 24
Peak memory 201776 kb
Host smart-350fb0f4-6f7a-4942-9896-61deb9669696
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=893362802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.893362802
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1658364338
Short name T187
Test name
Test status
Simulation time 23818927444 ps
CPU time 76.81 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:54:22 PM PDT 24
Peak memory 202960 kb
Host smart-6056f644-45d1-4e78-82d5-50f6ea62d434
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1658364338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.1658364338
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2845831971
Short name T639
Test name
Test status
Simulation time 158969514 ps
CPU time 3.01 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 201920 kb
Host smart-9a1d5d78-3380-498c-a2fd-99d244d2727d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2845831971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2845831971
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.5969478
Short name T1
Test name
Test status
Simulation time 66325700 ps
CPU time 2.37 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 201864 kb
Host smart-8ee9449e-4942-43d1-9fab-8284b85981b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5969478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.5969478
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.724972103
Short name T821
Test name
Test status
Simulation time 79581887 ps
CPU time 4.87 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:53:11 PM PDT 24
Peak memory 201808 kb
Host smart-0422a7e7-cc62-4570-ac19-ec91a7091eea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=724972103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.724972103
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3523754581
Short name T688
Test name
Test status
Simulation time 31436152946 ps
CPU time 111.78 seconds
Started Aug 18 04:53:10 PM PDT 24
Finished Aug 18 04:55:02 PM PDT 24
Peak memory 201880 kb
Host smart-4d32f61d-3854-4246-857e-767a3d71582d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523754581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3523754581
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.4131739476
Short name T201
Test name
Test status
Simulation time 35382756321 ps
CPU time 108.87 seconds
Started Aug 18 04:53:04 PM PDT 24
Finished Aug 18 04:54:53 PM PDT 24
Peak memory 202016 kb
Host smart-d595aa26-461b-43cf-bcc0-39afe9699558
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4131739476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.4131739476
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3616995010
Short name T507
Test name
Test status
Simulation time 26541051 ps
CPU time 3.38 seconds
Started Aug 18 04:53:04 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201844 kb
Host smart-76c1cf6c-a56d-4c0d-ba3e-22ba6da21aa2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616995010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3616995010
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.1434927261
Short name T791
Test name
Test status
Simulation time 72827508 ps
CPU time 4.88 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:11 PM PDT 24
Peak memory 201848 kb
Host smart-d0566996-3080-4460-81b4-c139d517f54c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1434927261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1434927261
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.2503615329
Short name T384
Test name
Test status
Simulation time 8974123 ps
CPU time 1.31 seconds
Started Aug 18 04:52:57 PM PDT 24
Finished Aug 18 04:52:58 PM PDT 24
Peak memory 201780 kb
Host smart-aba7e09d-d9fa-414c-b4f0-4c80aa47c804
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2503615329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2503615329
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3088947340
Short name T349
Test name
Test status
Simulation time 23326755986 ps
CPU time 12.6 seconds
Started Aug 18 04:52:55 PM PDT 24
Finished Aug 18 04:53:08 PM PDT 24
Peak memory 201952 kb
Host smart-1d3d8866-c1b1-459f-b1ef-320fe6c22f1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088947340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3088947340
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.4174060574
Short name T39
Test name
Test status
Simulation time 1087832884 ps
CPU time 7.61 seconds
Started Aug 18 04:52:56 PM PDT 24
Finished Aug 18 04:53:04 PM PDT 24
Peak memory 201844 kb
Host smart-5e432343-abf3-493d-8c71-5e0f9c2437b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4174060574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.4174060574
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2633753931
Short name T852
Test name
Test status
Simulation time 18124153 ps
CPU time 1.15 seconds
Started Aug 18 04:52:59 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 201840 kb
Host smart-89e6f0e2-875e-41d5-9ae1-65857259cea5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633753931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2633753931
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.3388804063
Short name T108
Test name
Test status
Simulation time 7217967101 ps
CPU time 76.57 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:54:22 PM PDT 24
Peak memory 204788 kb
Host smart-4cdf454c-c73e-4a51-be40-3c3f08de61dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3388804063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3388804063
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2259303484
Short name T226
Test name
Test status
Simulation time 172496699 ps
CPU time 14.36 seconds
Started Aug 18 04:53:10 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 201872 kb
Host smart-9b917881-cf8c-4b15-bce8-145ad73aace0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259303484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2259303484
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.569936210
Short name T731
Test name
Test status
Simulation time 1471560521 ps
CPU time 43.34 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:51 PM PDT 24
Peak memory 204228 kb
Host smart-c1dcdfbf-cb0b-442d-9025-b80df13d3106
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=569936210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand
_reset.569936210
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.4189351607
Short name T674
Test name
Test status
Simulation time 250548452 ps
CPU time 32.4 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:37 PM PDT 24
Peak memory 203336 kb
Host smart-f68ee790-fa87-4466-9ab2-f1422805733e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4189351607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.4189351607
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1752680227
Short name T396
Test name
Test status
Simulation time 289360456 ps
CPU time 6.06 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:11 PM PDT 24
Peak memory 201828 kb
Host smart-a4eacfff-850f-43d2-aa91-c078ad2f43f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1752680227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1752680227
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.902350887
Short name T140
Test name
Test status
Simulation time 357964847 ps
CPU time 5.96 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:53:13 PM PDT 24
Peak memory 201808 kb
Host smart-a12485c9-0f20-4d1f-a9a3-8315f6755035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=902350887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.902350887
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.30362212
Short name T841
Test name
Test status
Simulation time 203508963988 ps
CPU time 336.12 seconds
Started Aug 18 04:53:04 PM PDT 24
Finished Aug 18 04:58:40 PM PDT 24
Peak memory 203972 kb
Host smart-c0da13a9-534c-4a49-bb49-ccd141ad0f6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30362212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow
_rsp.30362212
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.498337162
Short name T162
Test name
Test status
Simulation time 154414619 ps
CPU time 2.41 seconds
Started Aug 18 04:53:10 PM PDT 24
Finished Aug 18 04:53:13 PM PDT 24
Peak memory 201860 kb
Host smart-852192c0-9e08-4aab-ab4b-4221ae45271f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=498337162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.498337162
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.3325249494
Short name T85
Test name
Test status
Simulation time 916884826 ps
CPU time 14.79 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:19 PM PDT 24
Peak memory 201868 kb
Host smart-d6655795-568e-4fa4-b556-420309a8c89e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3325249494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3325249494
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.4278648627
Short name T686
Test name
Test status
Simulation time 634976468 ps
CPU time 11.21 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 202072 kb
Host smart-aa0e5762-98f0-4e2f-b533-c1a3a9c65bbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4278648627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4278648627
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3454291825
Short name T75
Test name
Test status
Simulation time 76375527870 ps
CPU time 75.3 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:54:20 PM PDT 24
Peak memory 201844 kb
Host smart-c81b1d17-80e9-4b4d-b7df-b207b32012e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454291825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3454291825
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.769733123
Short name T582
Test name
Test status
Simulation time 4202221588 ps
CPU time 9.65 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:15 PM PDT 24
Peak memory 201912 kb
Host smart-10b2942b-5a0d-4d1c-96ec-838a05b8b9a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=769733123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.769733123
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1090799002
Short name T219
Test name
Test status
Simulation time 9124450 ps
CPU time 1.09 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201868 kb
Host smart-1dc6838a-d5a2-42e3-ac58-739d4847b383
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090799002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1090799002
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.2343511521
Short name T343
Test name
Test status
Simulation time 25888531 ps
CPU time 1.41 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:08 PM PDT 24
Peak memory 201852 kb
Host smart-9ca4d5d1-7938-455f-8276-7dbb25dc1840
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2343511521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2343511521
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1551257426
Short name T181
Test name
Test status
Simulation time 11521894 ps
CPU time 1.19 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201912 kb
Host smart-b8da988a-8313-4475-bf18-aa9f5b4f5695
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1551257426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1551257426
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3855311323
Short name T627
Test name
Test status
Simulation time 1452442937 ps
CPU time 5.6 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:13 PM PDT 24
Peak memory 201736 kb
Host smart-195f0130-7f56-46cb-8f95-17e07581b31c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855311323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3855311323
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1716495507
Short name T295
Test name
Test status
Simulation time 3927975847 ps
CPU time 7.84 seconds
Started Aug 18 04:53:08 PM PDT 24
Finished Aug 18 04:53:16 PM PDT 24
Peak memory 201840 kb
Host smart-4b09730d-b591-4035-9179-29357f3e3fb7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1716495507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1716495507
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1952598560
Short name T618
Test name
Test status
Simulation time 13727007 ps
CPU time 1.37 seconds
Started Aug 18 04:53:08 PM PDT 24
Finished Aug 18 04:53:10 PM PDT 24
Peak memory 201868 kb
Host smart-774400f7-5a89-4362-bc72-2ed9b69a4205
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952598560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1952598560
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3867822674
Short name T505
Test name
Test status
Simulation time 2689098180 ps
CPU time 48.92 seconds
Started Aug 18 04:53:09 PM PDT 24
Finished Aug 18 04:53:58 PM PDT 24
Peak memory 202964 kb
Host smart-5312b814-be09-4667-ab85-fe27f5041445
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3867822674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3867822674
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.197974756
Short name T385
Test name
Test status
Simulation time 1178225666 ps
CPU time 27.75 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:33 PM PDT 24
Peak memory 202880 kb
Host smart-c84e8a1a-960b-45e2-81ac-5b9d4e335f50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=197974756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.197974756
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2384551309
Short name T531
Test name
Test status
Simulation time 662994502 ps
CPU time 101.16 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:54:47 PM PDT 24
Peak memory 206592 kb
Host smart-74ebcb14-8061-474c-b712-a6ecb110b3f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2384551309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran
d_reset.2384551309
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3556009029
Short name T476
Test name
Test status
Simulation time 52475234 ps
CPU time 13.76 seconds
Started Aug 18 04:53:04 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 201844 kb
Host smart-c996e1f4-7261-42d8-beec-8f07d9ea15d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3556009029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.3556009029
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.93734871
Short name T58
Test name
Test status
Simulation time 57436378 ps
CPU time 1.58 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201908 kb
Host smart-c34dc971-a177-48c4-95f9-2d7331d8e2ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93734871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.93734871
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1239961202
Short name T475
Test name
Test status
Simulation time 1206992121 ps
CPU time 20.4 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:34 PM PDT 24
Peak memory 201836 kb
Host smart-0c420e91-e9a2-43ad-bac8-5c88a2e34909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1239961202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1239961202
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3467394538
Short name T710
Test name
Test status
Simulation time 20594822165 ps
CPU time 87.04 seconds
Started Aug 18 04:53:15 PM PDT 24
Finished Aug 18 04:54:42 PM PDT 24
Peak memory 202964 kb
Host smart-b7298f44-75cf-4a2b-968f-3d13ff1aaf36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3467394538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.3467394538
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3078478436
Short name T217
Test name
Test status
Simulation time 745143713 ps
CPU time 9.24 seconds
Started Aug 18 04:53:16 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 201936 kb
Host smart-a110da0a-64fe-4d1c-b227-ae1541c91176
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3078478436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3078478436
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.3388004825
Short name T535
Test name
Test status
Simulation time 46478705 ps
CPU time 1.4 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:53:14 PM PDT 24
Peak memory 201852 kb
Host smart-17cc4b0c-f4ad-406e-aa02-74cc8390deb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3388004825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3388004825
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.1404894026
Short name T712
Test name
Test status
Simulation time 852252354 ps
CPU time 5.75 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:11 PM PDT 24
Peak memory 201804 kb
Host smart-28234373-6877-42f0-941a-752eb2b7b77b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404894026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1404894026
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1560367247
Short name T163
Test name
Test status
Simulation time 23898499212 ps
CPU time 58.4 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:54:06 PM PDT 24
Peak memory 201796 kb
Host smart-63fcd9d7-7858-4a57-92c6-cf44821321f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560367247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1560367247
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1542946342
Short name T557
Test name
Test status
Simulation time 38635807601 ps
CPU time 76.97 seconds
Started Aug 18 04:53:15 PM PDT 24
Finished Aug 18 04:54:32 PM PDT 24
Peak memory 201912 kb
Host smart-f132d59a-5350-40e0-903e-7523d18e1744
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1542946342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1542946342
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.614343852
Short name T856
Test name
Test status
Simulation time 83351134 ps
CPU time 5.53 seconds
Started Aug 18 04:53:06 PM PDT 24
Finished Aug 18 04:53:12 PM PDT 24
Peak memory 201940 kb
Host smart-de9168f0-06f6-4b31-a40a-ef9071dd07ba
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614343852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.614343852
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.562339318
Short name T829
Test name
Test status
Simulation time 274429783 ps
CPU time 4.41 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 201964 kb
Host smart-20c8a77e-0ca2-4e18-95a9-a12dcf569c25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=562339318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.562339318
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.2448088133
Short name T596
Test name
Test status
Simulation time 74540303 ps
CPU time 1.76 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 201916 kb
Host smart-46a53de0-e03c-4fbc-a311-c21c6ba4617d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2448088133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2448088133
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1766207929
Short name T689
Test name
Test status
Simulation time 6351396772 ps
CPU time 7.71 seconds
Started Aug 18 04:53:07 PM PDT 24
Finished Aug 18 04:53:15 PM PDT 24
Peak memory 201952 kb
Host smart-68f735f8-95bf-49ba-bf4a-c51e70d30231
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766207929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1766207929
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2810357224
Short name T584
Test name
Test status
Simulation time 3344716051 ps
CPU time 7.51 seconds
Started Aug 18 04:53:05 PM PDT 24
Finished Aug 18 04:53:12 PM PDT 24
Peak memory 201924 kb
Host smart-339b1a95-fb29-467d-8af8-d791b3e5c674
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2810357224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2810357224
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1915062829
Short name T4
Test name
Test status
Simulation time 25253617 ps
CPU time 1.4 seconds
Started Aug 18 04:53:04 PM PDT 24
Finished Aug 18 04:53:06 PM PDT 24
Peak memory 201860 kb
Host smart-1a131d92-30e1-4ddd-b4d3-c3de12d7ae2e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915062829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1915062829
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.903749773
Short name T799
Test name
Test status
Simulation time 5246885870 ps
CPU time 48.84 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:54:02 PM PDT 24
Peak memory 203256 kb
Host smart-4e7f4d7c-0ecf-4a8c-a00b-58b1e1d985d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903749773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.903749773
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2342136482
Short name T365
Test name
Test status
Simulation time 334110371 ps
CPU time 36.56 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:51 PM PDT 24
Peak memory 202968 kb
Host smart-62bb4bef-cc84-456a-8e31-5cf53660fc6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2342136482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2342136482
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3296599308
Short name T742
Test name
Test status
Simulation time 288900791 ps
CPU time 71 seconds
Started Aug 18 04:53:18 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 204376 kb
Host smart-a22230d5-f050-49dc-ba7d-c7aed6b649af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296599308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.3296599308
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.463879653
Short name T93
Test name
Test status
Simulation time 623530304 ps
CPU time 88.13 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 206088 kb
Host smart-660bd625-077e-4307-a262-58088489bc01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=463879653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_res
et_error.463879653
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1128996149
Short name T429
Test name
Test status
Simulation time 3222305528 ps
CPU time 13.13 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:53:26 PM PDT 24
Peak memory 201896 kb
Host smart-64f385c8-6a59-4195-9db8-d7404626771b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1128996149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1128996149
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1876449417
Short name T822
Test name
Test status
Simulation time 93524302 ps
CPU time 2.03 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:37 PM PDT 24
Peak memory 201944 kb
Host smart-4337f16e-ef35-46d8-a941-dabc83f85027
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1876449417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1876449417
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1539980989
Short name T111
Test name
Test status
Simulation time 23252146864 ps
CPU time 110.33 seconds
Started Aug 18 04:53:37 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 203032 kb
Host smart-718b7f0f-8ed4-4089-ae3f-24e838ab1a6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1539980989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.1539980989
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3975626879
Short name T112
Test name
Test status
Simulation time 879008318 ps
CPU time 6.3 seconds
Started Aug 18 04:53:36 PM PDT 24
Finished Aug 18 04:53:43 PM PDT 24
Peak memory 201852 kb
Host smart-ddc86725-3197-4964-bddd-e9490aa2956c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3975626879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3975626879
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.459730566
Short name T807
Test name
Test status
Simulation time 587458118 ps
CPU time 5.76 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:40 PM PDT 24
Peak memory 201808 kb
Host smart-9b8b8c95-2ad2-4c38-8a8a-ac448f309356
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=459730566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.459730566
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.579381065
Short name T116
Test name
Test status
Simulation time 1290325977 ps
CPU time 16.78 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:39 PM PDT 24
Peak memory 201816 kb
Host smart-7df51552-4ce7-4b92-ad51-4df9bcebf86f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=579381065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.579381065
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.4208548727
Short name T417
Test name
Test status
Simulation time 6075203487 ps
CPU time 16.8 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:41 PM PDT 24
Peak memory 201792 kb
Host smart-85d18c98-567f-4b36-9e24-a070e134f606
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208548727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4208548727
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.790646766
Short name T28
Test name
Test status
Simulation time 84309416934 ps
CPU time 179.77 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 201992 kb
Host smart-77e53d36-1ad1-453e-adb7-d60b31395d49
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=790646766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.790646766
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.913381124
Short name T275
Test name
Test status
Simulation time 44880693 ps
CPU time 5.63 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:28 PM PDT 24
Peak memory 201796 kb
Host smart-6a3930a8-2e57-4a07-84dd-6e8584a4fa2d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913381124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.913381124
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.1344685303
Short name T293
Test name
Test status
Simulation time 131477932 ps
CPU time 4.13 seconds
Started Aug 18 04:53:38 PM PDT 24
Finished Aug 18 04:53:43 PM PDT 24
Peak memory 201920 kb
Host smart-37be533e-327d-492b-ab3f-f68e4804d93c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1344685303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1344685303
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.14873606
Short name T400
Test name
Test status
Simulation time 166528344 ps
CPU time 1.82 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:16 PM PDT 24
Peak memory 201800 kb
Host smart-2b6f2d2a-468c-49d9-a9a4-6acf9d01e888
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14873606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.14873606
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2575696826
Short name T156
Test name
Test status
Simulation time 5126236897 ps
CPU time 6.97 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:21 PM PDT 24
Peak memory 201876 kb
Host smart-b7bdf3f3-ac7d-4600-9bfe-5c98b0ac6dc6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575696826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2575696826
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.891003566
Short name T844
Test name
Test status
Simulation time 1382650812 ps
CPU time 7.87 seconds
Started Aug 18 04:53:25 PM PDT 24
Finished Aug 18 04:53:33 PM PDT 24
Peak memory 201876 kb
Host smart-8ea13f85-eb46-4e49-89fe-40d39db9fca2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=891003566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.891003566
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.638757190
Short name T312
Test name
Test status
Simulation time 9644950 ps
CPU time 1.35 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:15 PM PDT 24
Peak memory 201852 kb
Host smart-bd46f3b9-423b-4bd4-908d-9e47a97cc586
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638757190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.638757190
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.718109722
Short name T78
Test name
Test status
Simulation time 5622834709 ps
CPU time 24.54 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:59 PM PDT 24
Peak memory 203072 kb
Host smart-78c2ca62-595c-4d28-be34-002dbfa5ed95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=718109722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.718109722
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3494072617
Short name T363
Test name
Test status
Simulation time 12875399006 ps
CPU time 95.99 seconds
Started Aug 18 04:53:43 PM PDT 24
Finished Aug 18 04:55:20 PM PDT 24
Peak memory 203276 kb
Host smart-50aacfbf-cfb8-450d-8bd2-a92e99598413
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3494072617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3494072617
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.4237369954
Short name T884
Test name
Test status
Simulation time 415943555 ps
CPU time 50.5 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:54:36 PM PDT 24
Peak memory 202968 kb
Host smart-4f063ed0-cad7-4a90-b34f-f254d266085d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4237369954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.4237369954
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3692323548
Short name T267
Test name
Test status
Simulation time 8022879 ps
CPU time 1.15 seconds
Started Aug 18 04:53:40 PM PDT 24
Finished Aug 18 04:53:41 PM PDT 24
Peak memory 201916 kb
Host smart-c3a9d25e-1779-43d3-9485-6613398c05cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3692323548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3692323548
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3322644492
Short name T562
Test name
Test status
Simulation time 4676265416 ps
CPU time 20.71 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:54:12 PM PDT 24
Peak memory 201912 kb
Host smart-bcc9f061-4ee0-4adc-883d-d30782838c0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3322644492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3322644492
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2611306664
Short name T107
Test name
Test status
Simulation time 54319708552 ps
CPU time 218.97 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:57:34 PM PDT 24
Peak memory 202952 kb
Host smart-dcbe2ee2-2e3e-45a3-9bd9-7452e24ccdbc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2611306664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.2611306664
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1417144554
Short name T158
Test name
Test status
Simulation time 53834330 ps
CPU time 4.8 seconds
Started Aug 18 04:53:57 PM PDT 24
Finished Aug 18 04:54:02 PM PDT 24
Peak memory 201876 kb
Host smart-8c5ed2c4-07a9-4d69-b238-20f48bce1341
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1417144554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1417144554
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.367391014
Short name T157
Test name
Test status
Simulation time 13120672 ps
CPU time 1.43 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:53:54 PM PDT 24
Peak memory 201884 kb
Host smart-a7145a96-e35f-4b5b-9d48-db400d1186e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=367391014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.367391014
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.87056846
Short name T317
Test name
Test status
Simulation time 1555136915 ps
CPU time 6.55 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:53:52 PM PDT 24
Peak memory 201808 kb
Host smart-2ec351b7-6e7c-42a5-8847-6eefc3e12302
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87056846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.87056846
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1274011726
Short name T682
Test name
Test status
Simulation time 25542027087 ps
CPU time 118.9 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:55:43 PM PDT 24
Peak memory 201948 kb
Host smart-93d7479d-0aa3-49e8-8065-3d488f08a8ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274011726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1274011726
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.827009350
Short name T426
Test name
Test status
Simulation time 2470280065 ps
CPU time 16.96 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:54:12 PM PDT 24
Peak memory 202004 kb
Host smart-cea8ea0d-6953-4da5-bc09-8d973161b37d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=827009350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.827009350
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1362432200
Short name T602
Test name
Test status
Simulation time 16621073 ps
CPU time 1.5 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:53:47 PM PDT 24
Peak memory 201936 kb
Host smart-6aa956d3-170e-4a55-85ee-7d1990ef8e62
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362432200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1362432200
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.2082720003
Short name T35
Test name
Test status
Simulation time 371111428 ps
CPU time 4.08 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:53:56 PM PDT 24
Peak memory 201936 kb
Host smart-6217dd77-90df-4198-8ed5-b85231159ac7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2082720003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2082720003
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.2389841104
Short name T820
Test name
Test status
Simulation time 12150485 ps
CPU time 1.01 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:45 PM PDT 24
Peak memory 201808 kb
Host smart-2fa05183-7964-431e-adab-36082bd2df79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2389841104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2389841104
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1128104591
Short name T40
Test name
Test status
Simulation time 1501160252 ps
CPU time 7.19 seconds
Started Aug 18 04:53:43 PM PDT 24
Finished Aug 18 04:53:50 PM PDT 24
Peak memory 201908 kb
Host smart-9e6b86b8-b904-4841-a5b0-a5e8c6e9005f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128104591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1128104591
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2618255287
Short name T694
Test name
Test status
Simulation time 1176156373 ps
CPU time 7.93 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:52 PM PDT 24
Peak memory 201880 kb
Host smart-b090dfa8-2c39-4a78-ade4-90e2aec39803
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2618255287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2618255287
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1612388192
Short name T839
Test name
Test status
Simulation time 9410076 ps
CPU time 1.16 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:45 PM PDT 24
Peak memory 201856 kb
Host smart-75932b68-d83e-42dc-ba53-6c973786e2fc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612388192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1612388192
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.3291263338
Short name T356
Test name
Test status
Simulation time 131416782 ps
CPU time 10.74 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:54:07 PM PDT 24
Peak memory 201812 kb
Host smart-b6acf236-498c-45d7-a429-780fb79ac229
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3291263338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3291263338
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3661448936
Short name T216
Test name
Test status
Simulation time 586806001 ps
CPU time 47.06 seconds
Started Aug 18 04:54:03 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 202888 kb
Host smart-3dae9cea-e6c4-415c-9edb-db46aeaf7d02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3661448936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3661448936
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.664276547
Short name T5
Test name
Test status
Simulation time 23347501496 ps
CPU time 271.23 seconds
Started Aug 18 04:53:57 PM PDT 24
Finished Aug 18 04:58:29 PM PDT 24
Peak memory 209704 kb
Host smart-242ab89b-7db0-4e87-8231-f44c8e8b79e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=664276547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand
_reset.664276547
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3988632929
Short name T633
Test name
Test status
Simulation time 8225751 ps
CPU time 3.25 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:07 PM PDT 24
Peak memory 201868 kb
Host smart-f68c80bb-abe6-4b8c-b091-2106f44cfdef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3988632929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.3988632929
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1719239406
Short name T373
Test name
Test status
Simulation time 740131509 ps
CPU time 11.2 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:54:03 PM PDT 24
Peak memory 201848 kb
Host smart-e925f08f-0520-4d11-bb57-cb1831061f96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1719239406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1719239406
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2878890263
Short name T135
Test name
Test status
Simulation time 248486109 ps
CPU time 6.48 seconds
Started Aug 18 04:54:15 PM PDT 24
Finished Aug 18 04:54:21 PM PDT 24
Peak memory 201860 kb
Host smart-16c29299-6fda-4d2a-8e29-9ae4aa7a3368
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2878890263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2878890263
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1474802144
Short name T186
Test name
Test status
Simulation time 888169465 ps
CPU time 8.14 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:34 PM PDT 24
Peak memory 201920 kb
Host smart-d33f82fa-faae-4db5-87b6-1d9d3e28483b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1474802144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1474802144
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.2391113300
Short name T561
Test name
Test status
Simulation time 156201301 ps
CPU time 6.44 seconds
Started Aug 18 04:54:15 PM PDT 24
Finished Aug 18 04:54:22 PM PDT 24
Peak memory 201860 kb
Host smart-5a4af76b-b33f-444d-94bd-6f49a8f9e7bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2391113300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2391113300
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.3379637692
Short name T355
Test name
Test status
Simulation time 111825175 ps
CPU time 10.54 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:16 PM PDT 24
Peak memory 201844 kb
Host smart-5be28fa0-54d7-4000-af2b-4ef621cdafce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379637692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3379637692
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2726729033
Short name T815
Test name
Test status
Simulation time 75695769639 ps
CPU time 199.1 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:57:38 PM PDT 24
Peak memory 201888 kb
Host smart-e2074571-44f8-43a2-8fa0-73374db59941
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726729033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2726729033
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.298251435
Short name T92
Test name
Test status
Simulation time 14976307793 ps
CPU time 86.59 seconds
Started Aug 18 04:54:18 PM PDT 24
Finished Aug 18 04:55:45 PM PDT 24
Peak memory 201920 kb
Host smart-f8233ab5-25d1-4fd7-a74b-2019386dc497
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=298251435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.298251435
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2566430701
Short name T696
Test name
Test status
Simulation time 74303231 ps
CPU time 4.02 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:10 PM PDT 24
Peak memory 201740 kb
Host smart-6e6b86bf-1bf6-4407-a4ef-339e9261def2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566430701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2566430701
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.3734722850
Short name T831
Test name
Test status
Simulation time 813091282 ps
CPU time 10.35 seconds
Started Aug 18 04:54:16 PM PDT 24
Finished Aug 18 04:54:26 PM PDT 24
Peak memory 201840 kb
Host smart-f440d4d4-755c-4ac9-98c4-5d6a01783983
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3734722850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3734722850
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.1874637185
Short name T124
Test name
Test status
Simulation time 12403204 ps
CPU time 1.3 seconds
Started Aug 18 04:54:12 PM PDT 24
Finished Aug 18 04:54:13 PM PDT 24
Peak memory 201888 kb
Host smart-82d7e5c8-cdaa-4d2c-b87e-102ba2684564
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1874637185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1874637185
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.4174246409
Short name T177
Test name
Test status
Simulation time 6491630840 ps
CPU time 11.99 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:16 PM PDT 24
Peak memory 201812 kb
Host smart-4b5c4c68-fe27-4ce0-a835-7544bb57b480
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174246409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4174246409
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3637171692
Short name T666
Test name
Test status
Simulation time 1953103088 ps
CPU time 6.18 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:11 PM PDT 24
Peak memory 201916 kb
Host smart-780a783d-cd89-4393-b11b-2d70084d0a6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3637171692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3637171692
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.126342901
Short name T329
Test name
Test status
Simulation time 13063919 ps
CPU time 1 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:06 PM PDT 24
Peak memory 201844 kb
Host smart-7f80b972-b0e7-43f2-8203-abe87eae323c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126342901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.126342901
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1289084900
Short name T132
Test name
Test status
Simulation time 491252384 ps
CPU time 25.92 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 202920 kb
Host smart-b729c3f1-dba5-479f-a057-8a01d22f5321
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1289084900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1289084900
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3460675249
Short name T720
Test name
Test status
Simulation time 225290380 ps
CPU time 4.35 seconds
Started Aug 18 04:54:29 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 201852 kb
Host smart-f237f34f-6a5d-42ca-926a-c295f2e20d88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3460675249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3460675249
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3091174859
Short name T455
Test name
Test status
Simulation time 10090703706 ps
CPU time 71.46 seconds
Started Aug 18 04:54:27 PM PDT 24
Finished Aug 18 04:55:38 PM PDT 24
Peak memory 204708 kb
Host smart-fadf9d02-2454-45fe-b55b-d83fd5d2a782
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091174859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran
d_reset.3091174859
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.273815382
Short name T652
Test name
Test status
Simulation time 6191694773 ps
CPU time 58.64 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:55:25 PM PDT 24
Peak memory 203792 kb
Host smart-8c618f69-8b28-4a81-b615-95d2fdef0d32
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273815382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res
et_error.273815382
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2473017015
Short name T224
Test name
Test status
Simulation time 30539343 ps
CPU time 3.17 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:20 PM PDT 24
Peak memory 201928 kb
Host smart-6bf81242-7de8-44b9-87c0-b1f5359a404f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2473017015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2473017015
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2457736101
Short name T72
Test name
Test status
Simulation time 2058375687 ps
CPU time 15.2 seconds
Started Aug 18 04:54:40 PM PDT 24
Finished Aug 18 04:54:55 PM PDT 24
Peak memory 201856 kb
Host smart-ad9e85ba-8aac-40e8-bcaf-42707e8c331b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2457736101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2457736101
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1617979072
Short name T109
Test name
Test status
Simulation time 29068997805 ps
CPU time 79.67 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:55:58 PM PDT 24
Peak memory 202012 kb
Host smart-d1298fcb-c6d2-4060-98f7-4110482991c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1617979072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.1617979072
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2762629845
Short name T546
Test name
Test status
Simulation time 1023438746 ps
CPU time 7.98 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:54:56 PM PDT 24
Peak memory 201876 kb
Host smart-5f17bc85-5368-45ce-9bc7-8cff8dfade7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2762629845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2762629845
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.1888699622
Short name T161
Test name
Test status
Simulation time 81670019 ps
CPU time 4.79 seconds
Started Aug 18 04:54:37 PM PDT 24
Finished Aug 18 04:54:42 PM PDT 24
Peak memory 201956 kb
Host smart-d9195e08-724e-4192-aec2-56097dab89fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1888699622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1888699622
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.1981250278
Short name T447
Test name
Test status
Simulation time 74900455 ps
CPU time 5.19 seconds
Started Aug 18 04:54:37 PM PDT 24
Finished Aug 18 04:54:42 PM PDT 24
Peak memory 201772 kb
Host smart-d48790d6-50a0-4f4c-8255-9c6aa99b4315
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1981250278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1981250278
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.2153842720
Short name T326
Test name
Test status
Simulation time 204674413126 ps
CPU time 127.84 seconds
Started Aug 18 04:54:36 PM PDT 24
Finished Aug 18 04:56:44 PM PDT 24
Peak memory 201788 kb
Host smart-0151b878-282e-4020-887e-512d8dc680a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153842720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2153842720
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1328502671
Short name T612
Test name
Test status
Simulation time 2604973146 ps
CPU time 14.38 seconds
Started Aug 18 04:54:36 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 202020 kb
Host smart-a25cef11-dada-49b3-9a14-7b2ad0b5157a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1328502671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1328502671
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.928692232
Short name T889
Test name
Test status
Simulation time 40802665 ps
CPU time 4.4 seconds
Started Aug 18 04:54:37 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 201856 kb
Host smart-699f5758-1d8a-402a-b7ad-f9f4a562847d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928692232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.928692232
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.3906890525
Short name T823
Test name
Test status
Simulation time 36587382 ps
CPU time 4.4 seconds
Started Aug 18 04:54:44 PM PDT 24
Finished Aug 18 04:54:49 PM PDT 24
Peak memory 201864 kb
Host smart-48f42ee5-a41d-4cc0-9661-171f02c40583
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906890525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3906890525
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.2909126702
Short name T835
Test name
Test status
Simulation time 37604571 ps
CPU time 1.2 seconds
Started Aug 18 04:54:29 PM PDT 24
Finished Aug 18 04:54:31 PM PDT 24
Peak memory 201808 kb
Host smart-abb01435-5f6c-43a3-b538-8a8274f22093
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2909126702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2909126702
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.277038233
Short name T766
Test name
Test status
Simulation time 1612801522 ps
CPU time 5.75 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:32 PM PDT 24
Peak memory 201888 kb
Host smart-46c9cd36-645f-4b8a-a8de-396a7c92c2c4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=277038233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.277038233
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3431169462
Short name T504
Test name
Test status
Simulation time 9052450555 ps
CPU time 13.79 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:54:52 PM PDT 24
Peak memory 202208 kb
Host smart-7cf53614-060e-4913-acb1-dda0fee9354d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3431169462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3431169462
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2028968537
Short name T887
Test name
Test status
Simulation time 13196074 ps
CPU time 1.19 seconds
Started Aug 18 04:54:28 PM PDT 24
Finished Aug 18 04:54:30 PM PDT 24
Peak memory 201860 kb
Host smart-cc554037-462a-4520-aaf0-c00b1d2e8f63
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028968537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2028968537
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.1202779227
Short name T299
Test name
Test status
Simulation time 4946369444 ps
CPU time 59.52 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 202960 kb
Host smart-bc71c773-6bb4-43f6-aad7-24db624d296b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1202779227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1202779227
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1521490575
Short name T167
Test name
Test status
Simulation time 1026979964 ps
CPU time 15.86 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:55:04 PM PDT 24
Peak memory 201916 kb
Host smart-61dc3740-e491-4ea7-ab4f-619edbb04056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1521490575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1521490575
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.93961991
Short name T74
Test name
Test status
Simulation time 24135856843 ps
CPU time 224.63 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:58:29 PM PDT 24
Peak memory 204784 kb
Host smart-503f9275-5866-49c8-be20-e0131e0e387e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93961991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_
reset.93961991
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1486458311
Short name T395
Test name
Test status
Simulation time 514997353 ps
CPU time 46.49 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:55:34 PM PDT 24
Peak memory 204340 kb
Host smart-07e92b5f-3db2-425d-bcdd-b3fead57b62d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486458311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.1486458311
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3032746754
Short name T567
Test name
Test status
Simulation time 24373603 ps
CPU time 2.85 seconds
Started Aug 18 04:54:34 PM PDT 24
Finished Aug 18 04:54:37 PM PDT 24
Peak memory 201032 kb
Host smart-2823b9ff-0d25-4cea-ad9a-c948eabb7b68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3032746754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3032746754
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3592733861
Short name T153
Test name
Test status
Simulation time 602747480 ps
CPU time 5.27 seconds
Started Aug 18 04:54:54 PM PDT 24
Finished Aug 18 04:54:59 PM PDT 24
Peak memory 201936 kb
Host smart-6c7bfc83-6cdb-4f2e-83ae-26ee45909f4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3592733861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3592733861
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3136830930
Short name T707
Test name
Test status
Simulation time 15686741748 ps
CPU time 99.08 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:56:36 PM PDT 24
Peak memory 201888 kb
Host smart-29502a9f-eb61-4c5b-9f79-522768a26483
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3136830930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.3136830930
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3739688152
Short name T484
Test name
Test status
Simulation time 251297009 ps
CPU time 1.83 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 201960 kb
Host smart-3a45bc25-b1fc-48eb-bfae-f840edae6d65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3739688152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3739688152
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.3028710268
Short name T858
Test name
Test status
Simulation time 171912347 ps
CPU time 4.96 seconds
Started Aug 18 04:55:07 PM PDT 24
Finished Aug 18 04:55:12 PM PDT 24
Peak memory 201872 kb
Host smart-d48249d1-a711-4647-a110-0722bf33a771
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3028710268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3028710268
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.1123292904
Short name T94
Test name
Test status
Simulation time 714941317 ps
CPU time 15.26 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:55:12 PM PDT 24
Peak memory 201860 kb
Host smart-5712e3eb-7661-4501-877e-5ec13b02f682
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1123292904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1123292904
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3644942780
Short name T336
Test name
Test status
Simulation time 36159486898 ps
CPU time 82.51 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:56:18 PM PDT 24
Peak memory 201956 kb
Host smart-574ce7c3-3143-4045-af07-5cad3a870414
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644942780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3644942780
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.145971011
Short name T342
Test name
Test status
Simulation time 53181743842 ps
CPU time 136.82 seconds
Started Aug 18 04:54:58 PM PDT 24
Finished Aug 18 04:57:15 PM PDT 24
Peak memory 201936 kb
Host smart-4f964333-a330-4f1b-82cd-3cb2094e3a3c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=145971011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.145971011
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.4279973283
Short name T781
Test name
Test status
Simulation time 64878369 ps
CPU time 7.88 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:55:05 PM PDT 24
Peak memory 201812 kb
Host smart-71188bf0-27a4-4605-b6ec-cdac2c053636
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279973283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.4279973283
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.1227424797
Short name T380
Test name
Test status
Simulation time 9071385 ps
CPU time 1.18 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 201868 kb
Host smart-0754e742-21f4-4fa9-bd83-2c4e39b64d3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1227424797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1227424797
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.4240612853
Short name T357
Test name
Test status
Simulation time 81324224 ps
CPU time 1.81 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 201832 kb
Host smart-e92f5669-08eb-4ebc-9498-0f619a9fbb96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4240612853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.4240612853
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.544224776
Short name T279
Test name
Test status
Simulation time 4373748064 ps
CPU time 9.49 seconds
Started Aug 18 04:55:00 PM PDT 24
Finished Aug 18 04:55:09 PM PDT 24
Peak memory 201864 kb
Host smart-3110d0b4-a7a1-4b19-a45c-105f7148842f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=544224776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.544224776
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4050508352
Short name T61
Test name
Test status
Simulation time 1321675078 ps
CPU time 9.42 seconds
Started Aug 18 04:54:59 PM PDT 24
Finished Aug 18 04:55:08 PM PDT 24
Peak memory 201868 kb
Host smart-b788bea0-5b87-4016-b25e-e2671644c6fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4050508352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4050508352
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3136427866
Short name T432
Test name
Test status
Simulation time 10826038 ps
CPU time 1.08 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 201960 kb
Host smart-06b3e6e1-38f8-45fb-894b-43e8ff9393ed
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136427866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3136427866
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3293545970
Short name T485
Test name
Test status
Simulation time 643492997 ps
CPU time 33.46 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:51 PM PDT 24
Peak memory 202884 kb
Host smart-659b21f7-fe66-473f-9ca6-d006a8a8cb3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3293545970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3293545970
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2776829581
Short name T304
Test name
Test status
Simulation time 189641333 ps
CPU time 9.09 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 201948 kb
Host smart-40019bd4-f9c3-4c2a-86df-b18343b66922
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2776829581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2776829581
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.510744266
Short name T144
Test name
Test status
Simulation time 10271978078 ps
CPU time 93.07 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:56:51 PM PDT 24
Peak memory 205968 kb
Host smart-8f051a1b-7f70-49bd-801d-9ee0381e8208
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=510744266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.510744266
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1658341120
Short name T655
Test name
Test status
Simulation time 697571250 ps
CPU time 111.25 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:57:08 PM PDT 24
Peak memory 204468 kb
Host smart-a22c507b-7e5c-4c51-9215-7ffb332ea61a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1658341120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.1658341120
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3557654854
Short name T676
Test name
Test status
Simulation time 17095822 ps
CPU time 2.02 seconds
Started Aug 18 04:55:07 PM PDT 24
Finished Aug 18 04:55:09 PM PDT 24
Peak memory 201928 kb
Host smart-f7b7a310-7bbb-4e31-a71c-c7d9107140a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3557654854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3557654854
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1478602123
Short name T787
Test name
Test status
Simulation time 393018064 ps
CPU time 7.2 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:38 PM PDT 24
Peak memory 201932 kb
Host smart-6747915a-9c98-4f8c-bfa3-e9e5ccf83ba1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1478602123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1478602123
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2371761424
Short name T91
Test name
Test status
Simulation time 39165339304 ps
CPU time 112.49 seconds
Started Aug 18 04:55:25 PM PDT 24
Finished Aug 18 04:57:17 PM PDT 24
Peak memory 201984 kb
Host smart-897644b2-a960-439b-900f-b5477f4d741a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2371761424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.2371761424
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4220023711
Short name T14
Test name
Test status
Simulation time 9708739 ps
CPU time 1.17 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:35 PM PDT 24
Peak memory 201936 kb
Host smart-f7070c3b-1651-4617-96dd-b5dd4e6d4b80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4220023711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4220023711
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.2125404651
Short name T673
Test name
Test status
Simulation time 521752140 ps
CPU time 6.01 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:55:39 PM PDT 24
Peak memory 201872 kb
Host smart-7404359e-0246-43eb-a0bf-2bcbfcbe5604
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2125404651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2125404651
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.4045047883
Short name T65
Test name
Test status
Simulation time 1154693963 ps
CPU time 9.44 seconds
Started Aug 18 04:55:26 PM PDT 24
Finished Aug 18 04:55:36 PM PDT 24
Peak memory 201812 kb
Host smart-1728047f-0a8d-47ba-ad65-8151a6ee1697
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4045047883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4045047883
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1484901018
Short name T809
Test name
Test status
Simulation time 40873396492 ps
CPU time 113.07 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:57:22 PM PDT 24
Peak memory 201964 kb
Host smart-053e9d08-772c-485d-b848-f8f0d02aa429
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484901018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1484901018
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.525661341
Short name T345
Test name
Test status
Simulation time 26563938937 ps
CPU time 79.23 seconds
Started Aug 18 04:55:30 PM PDT 24
Finished Aug 18 04:56:50 PM PDT 24
Peak memory 201936 kb
Host smart-855104f5-f6b0-42fe-adee-bb226d713806
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=525661341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.525661341
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3320933696
Short name T232
Test name
Test status
Simulation time 194322910 ps
CPU time 7.72 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 201836 kb
Host smart-e4ad6459-ae9b-4345-ab75-19164c8bcf8c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320933696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3320933696
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.3531904015
Short name T684
Test name
Test status
Simulation time 252314124 ps
CPU time 2.83 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 201864 kb
Host smart-83aadae0-3478-4cb5-8f5c-c107655c2a3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3531904015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3531904015
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.3071121311
Short name T437
Test name
Test status
Simulation time 26577286 ps
CPU time 1.12 seconds
Started Aug 18 04:55:22 PM PDT 24
Finished Aug 18 04:55:23 PM PDT 24
Peak memory 201852 kb
Host smart-c2564820-912a-43a0-a995-9f20f73e7a3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3071121311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3071121311
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3975141341
Short name T38
Test name
Test status
Simulation time 1399631429 ps
CPU time 7.21 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:23 PM PDT 24
Peak memory 201812 kb
Host smart-2c75d075-534b-4ff0-aa66-0f82267a5e98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975141341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3975141341
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.416069101
Short name T752
Test name
Test status
Simulation time 630032700 ps
CPU time 5.43 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 04:55:33 PM PDT 24
Peak memory 201964 kb
Host smart-de5e5f13-01c7-4d33-b7a1-6d7a5db0e907
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=416069101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.416069101
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2723387174
Short name T87
Test name
Test status
Simulation time 12916369 ps
CPU time 1.28 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:20 PM PDT 24
Peak memory 201812 kb
Host smart-6082aa92-fa6e-49db-9371-b62d83c7d60a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723387174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2723387174
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3344457687
Short name T579
Test name
Test status
Simulation time 4009396646 ps
CPU time 59.75 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 203056 kb
Host smart-6d82693b-062e-478c-8bee-23d561e06811
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3344457687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3344457687
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2323943816
Short name T649
Test name
Test status
Simulation time 21610990399 ps
CPU time 71.32 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:56:48 PM PDT 24
Peak memory 201928 kb
Host smart-42c5da1c-9254-4334-88ca-17aebe9b6149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2323943816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2323943816
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3553621422
Short name T110
Test name
Test status
Simulation time 6057264883 ps
CPU time 103.38 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:57:20 PM PDT 24
Peak memory 205716 kb
Host smart-bce7d0fe-398f-494c-9c45-50fc16cd7295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3553621422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.3553621422
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1221341133
Short name T211
Test name
Test status
Simulation time 152459773 ps
CPU time 8.94 seconds
Started Aug 18 04:55:44 PM PDT 24
Finished Aug 18 04:55:54 PM PDT 24
Peak memory 201932 kb
Host smart-70cbee3f-51fc-4adf-8780-bc9aacd2d7ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1221341133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1221341133
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2247461939
Short name T615
Test name
Test status
Simulation time 58570248 ps
CPU time 2.97 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 201936 kb
Host smart-a6f629de-a6bf-4fd7-90ba-4ea458ca22e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2247461939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2247461939
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3173462615
Short name T165
Test name
Test status
Simulation time 189430015 ps
CPU time 12.79 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:56:05 PM PDT 24
Peak memory 201856 kb
Host smart-ba5f27fb-71cb-445a-9086-e79224f139f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3173462615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3173462615
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3107034428
Short name T675
Test name
Test status
Simulation time 518205786 ps
CPU time 9.11 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 04:56:11 PM PDT 24
Peak memory 201888 kb
Host smart-a8c9a83f-6eff-4d39-b130-f08aea92a81d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3107034428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3107034428
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.669492893
Short name T521
Test name
Test status
Simulation time 83219810 ps
CPU time 7.35 seconds
Started Aug 18 04:55:53 PM PDT 24
Finished Aug 18 04:56:00 PM PDT 24
Peak memory 201848 kb
Host smart-8e47eb22-d94b-4d06-9c13-2685161abeb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=669492893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.669492893
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.3997987176
Short name T773
Test name
Test status
Simulation time 3718109781 ps
CPU time 12.81 seconds
Started Aug 18 04:55:43 PM PDT 24
Finished Aug 18 04:55:56 PM PDT 24
Peak memory 201944 kb
Host smart-9466bea1-a350-4367-95b8-96f124fd4415
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3997987176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3997987176
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.831488069
Short name T849
Test name
Test status
Simulation time 3941896652 ps
CPU time 16.15 seconds
Started Aug 18 04:55:53 PM PDT 24
Finished Aug 18 04:56:09 PM PDT 24
Peak memory 201880 kb
Host smart-fb351156-c13d-4388-8db5-3a176be8a48d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=831488069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.831488069
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.539241692
Short name T863
Test name
Test status
Simulation time 17503701838 ps
CPU time 27.37 seconds
Started Aug 18 04:55:53 PM PDT 24
Finished Aug 18 04:56:20 PM PDT 24
Peak memory 201884 kb
Host smart-a979e0fb-7055-45da-a97d-a60e92724c81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=539241692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.539241692
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.124878708
Short name T550
Test name
Test status
Simulation time 29612415 ps
CPU time 4.01 seconds
Started Aug 18 04:55:44 PM PDT 24
Finished Aug 18 04:55:48 PM PDT 24
Peak memory 201856 kb
Host smart-4900c840-8221-4286-894a-6cdcfb26cf9f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124878708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.124878708
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.2659256651
Short name T880
Test name
Test status
Simulation time 2002796940 ps
CPU time 11.01 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:56:05 PM PDT 24
Peak memory 201872 kb
Host smart-c5cbd657-c8ba-4321-ae4f-82821efb0116
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2659256651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2659256651
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.2137397889
Short name T337
Test name
Test status
Simulation time 76952001 ps
CPU time 1.4 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 201912 kb
Host smart-d203a905-857d-4fae-8705-e6673745e4af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2137397889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2137397889
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3521671321
Short name T489
Test name
Test status
Simulation time 1914779059 ps
CPU time 8.34 seconds
Started Aug 18 04:55:42 PM PDT 24
Finished Aug 18 04:55:51 PM PDT 24
Peak memory 201792 kb
Host smart-e44a5173-4356-4627-a614-bdcef71a3da0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521671321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3521671321
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4082958441
Short name T375
Test name
Test status
Simulation time 1231991616 ps
CPU time 8.33 seconds
Started Aug 18 04:55:46 PM PDT 24
Finished Aug 18 04:55:55 PM PDT 24
Peak memory 201952 kb
Host smart-1dd06515-e2a3-4dce-b5f5-d7ed6398f901
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4082958441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4082958441
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3600650145
Short name T672
Test name
Test status
Simulation time 13086843 ps
CPU time 1.19 seconds
Started Aug 18 04:55:42 PM PDT 24
Finished Aug 18 04:55:43 PM PDT 24
Peak memory 201828 kb
Host smart-fb075094-0d30-4795-b859-64dfb6f68d93
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600650145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3600650145
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3812570997
Short name T617
Test name
Test status
Simulation time 11901195334 ps
CPU time 79.33 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:57:22 PM PDT 24
Peak memory 203076 kb
Host smart-4cacde6e-6909-4a04-9d2a-f655df1afa6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812570997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3812570997
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1911079461
Short name T695
Test name
Test status
Simulation time 10475296123 ps
CPU time 83.16 seconds
Started Aug 18 04:56:05 PM PDT 24
Finished Aug 18 04:57:28 PM PDT 24
Peak memory 202796 kb
Host smart-9e7f9692-7735-4f59-a1c1-12dd59c509c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1911079461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1911079461
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1778596494
Short name T603
Test name
Test status
Simulation time 273881162 ps
CPU time 20.05 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:24 PM PDT 24
Peak memory 202944 kb
Host smart-d9d0505a-896d-4678-8712-ea6d04385001
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1778596494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.1778596494
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.4269335169
Short name T611
Test name
Test status
Simulation time 1652219702 ps
CPU time 74.9 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:57:18 PM PDT 24
Peak memory 204720 kb
Host smart-2b30092b-7e09-4bef-b774-02a731d61380
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4269335169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.4269335169
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3315145666
Short name T259
Test name
Test status
Simulation time 614832775 ps
CPU time 10.92 seconds
Started Aug 18 04:55:55 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 201908 kb
Host smart-afc53319-e8c8-4182-987a-3ef34011a6c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3315145666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3315145666
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1742104487
Short name T301
Test name
Test status
Simulation time 42330778 ps
CPU time 3.4 seconds
Started Aug 18 04:51:36 PM PDT 24
Finished Aug 18 04:51:39 PM PDT 24
Peak memory 201940 kb
Host smart-ae1c4746-39e3-4a5a-b2b0-7f7851fa4965
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1742104487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1742104487
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1022571393
Short name T394
Test name
Test status
Simulation time 14197523 ps
CPU time 1.22 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:51:36 PM PDT 24
Peak memory 201872 kb
Host smart-6e797441-1ed7-40d1-812f-dc102a4244af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1022571393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1022571393
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.3115834460
Short name T129
Test name
Test status
Simulation time 43044231 ps
CPU time 4.8 seconds
Started Aug 18 04:51:37 PM PDT 24
Finished Aug 18 04:51:42 PM PDT 24
Peak memory 201952 kb
Host smart-cd91a3f9-eddd-46ca-adc3-11ef82dd32c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3115834460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3115834460
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.2810659223
Short name T471
Test name
Test status
Simulation time 95341787 ps
CPU time 3.83 seconds
Started Aug 18 04:51:38 PM PDT 24
Finished Aug 18 04:51:42 PM PDT 24
Peak memory 201892 kb
Host smart-37a265c1-e90f-4a9c-b056-3125bd268aa7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2810659223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2810659223
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.53860928
Short name T510
Test name
Test status
Simulation time 30441545421 ps
CPU time 121.42 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:53:36 PM PDT 24
Peak memory 201864 kb
Host smart-27a154b9-a85e-446d-8ac4-7c34c7391df8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=53860928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.53860928
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2623936297
Short name T478
Test name
Test status
Simulation time 19255067916 ps
CPU time 105.94 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:53:21 PM PDT 24
Peak memory 202004 kb
Host smart-5a6ead23-eace-43e1-9737-2154efe78926
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2623936297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2623936297
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.4075821816
Short name T549
Test name
Test status
Simulation time 149549003 ps
CPU time 7.25 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:41 PM PDT 24
Peak memory 201924 kb
Host smart-8d6e93b4-c390-4723-b90b-63361127cab2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075821816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.4075821816
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3046212230
Short name T43
Test name
Test status
Simulation time 65208786 ps
CPU time 4.97 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:40 PM PDT 24
Peak memory 201992 kb
Host smart-79ec661d-9dc1-4274-8d84-55d993636e47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3046212230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3046212230
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.2835613059
Short name T392
Test name
Test status
Simulation time 36347385 ps
CPU time 1.3 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:36 PM PDT 24
Peak memory 201912 kb
Host smart-1307816e-40cc-4126-8e2e-9aaa595e996a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2835613059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2835613059
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2519081478
Short name T18
Test name
Test status
Simulation time 2674719196 ps
CPU time 8.99 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:51:42 PM PDT 24
Peak memory 201964 kb
Host smart-fa6a7425-f4ff-409a-91a5-ee39539f5a38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519081478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2519081478
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3650779873
Short name T801
Test name
Test status
Simulation time 2003987708 ps
CPU time 4.37 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:51:40 PM PDT 24
Peak memory 201876 kb
Host smart-c63d5ec8-a957-4deb-bddf-000be36e4d2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3650779873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3650779873
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2901748120
Short name T26
Test name
Test status
Simulation time 13098666 ps
CPU time 1.32 seconds
Started Aug 18 04:51:32 PM PDT 24
Finished Aug 18 04:51:34 PM PDT 24
Peak memory 201844 kb
Host smart-97fd9257-e327-42bb-91c7-71c7e476fdf0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901748120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2901748120
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2493928200
Short name T369
Test name
Test status
Simulation time 498935338 ps
CPU time 52.67 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:52:28 PM PDT 24
Peak memory 202952 kb
Host smart-7161bd75-474f-4cac-81b8-b09143d2c828
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2493928200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2493928200
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1396409843
Short name T542
Test name
Test status
Simulation time 46329322 ps
CPU time 4.12 seconds
Started Aug 18 04:51:32 PM PDT 24
Finished Aug 18 04:51:37 PM PDT 24
Peak memory 201836 kb
Host smart-2c20fde6-67b7-4053-8339-7161e8ffb251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1396409843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1396409843
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1514036527
Short name T772
Test name
Test status
Simulation time 1034952524 ps
CPU time 157.31 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:54:11 PM PDT 24
Peak memory 207936 kb
Host smart-7ba485b5-57f1-4cbe-b70a-baf807669a15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1514036527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.1514036527
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1500204409
Short name T264
Test name
Test status
Simulation time 6833844 ps
CPU time 3.14 seconds
Started Aug 18 04:51:37 PM PDT 24
Finished Aug 18 04:51:40 PM PDT 24
Peak memory 201780 kb
Host smart-7a3f8fac-b025-4146-b08e-389e91ed130d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1500204409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1500204409
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2770749067
Short name T325
Test name
Test status
Simulation time 143123603 ps
CPU time 2.94 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:37 PM PDT 24
Peak memory 201852 kb
Host smart-e8328a98-bfa3-4665-8c06-4dff1dc1086a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2770749067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2770749067
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2939180908
Short name T892
Test name
Test status
Simulation time 1404046409 ps
CPU time 18.4 seconds
Started Aug 18 04:56:08 PM PDT 24
Finished Aug 18 04:56:27 PM PDT 24
Peak memory 201928 kb
Host smart-0eb8e32f-18a6-4491-b5dd-5f7c255d3c12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2939180908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2939180908
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.82691260
Short name T458
Test name
Test status
Simulation time 108993879176 ps
CPU time 229.45 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 05:00:02 PM PDT 24
Peak memory 203260 kb
Host smart-b63731e9-4ec7-4787-a569-d2aff4da8d18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=82691260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow
_rsp.82691260
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3708242988
Short name T808
Test name
Test status
Simulation time 801917057 ps
CPU time 6.69 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:19 PM PDT 24
Peak memory 201964 kb
Host smart-b3780e9d-fec1-4144-a86f-15f3deecee8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3708242988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3708242988
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.719570990
Short name T348
Test name
Test status
Simulation time 501960732 ps
CPU time 7.85 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:20 PM PDT 24
Peak memory 201936 kb
Host smart-53071781-6d51-478d-82fc-76745b79aaf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=719570990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.719570990
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.3833279740
Short name T360
Test name
Test status
Simulation time 656407898 ps
CPU time 1.93 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:04 PM PDT 24
Peak memory 201792 kb
Host smart-00f75979-c2cd-459f-9de9-5c8e6e98faa9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3833279740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3833279740
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2131704339
Short name T320
Test name
Test status
Simulation time 13072371419 ps
CPU time 55.73 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:57:00 PM PDT 24
Peak memory 201872 kb
Host smart-ae32775f-3372-4a9b-8256-23ab865f2775
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131704339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2131704339
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.4219408700
Short name T32
Test name
Test status
Simulation time 3092373036 ps
CPU time 17.13 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:19 PM PDT 24
Peak memory 201852 kb
Host smart-a3d3c0cf-ed4c-40cf-8921-737f54ec2fb2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4219408700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4219408700
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3536569651
Short name T57
Test name
Test status
Simulation time 252116027 ps
CPU time 4.18 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:08 PM PDT 24
Peak memory 201940 kb
Host smart-35ca42fd-1cc4-435d-908f-01b01566d3e9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536569651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3536569651
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.2910161817
Short name T845
Test name
Test status
Simulation time 36985539 ps
CPU time 4.51 seconds
Started Aug 18 04:56:11 PM PDT 24
Finished Aug 18 04:56:16 PM PDT 24
Peak memory 201792 kb
Host smart-430c6d69-420a-41bd-b8e4-d22aa539a2d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2910161817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2910161817
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.1788816508
Short name T235
Test name
Test status
Simulation time 13261997 ps
CPU time 1.16 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:04 PM PDT 24
Peak memory 201796 kb
Host smart-ded99800-e64c-4f87-97a2-07558d24b3ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1788816508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1788816508
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2582242705
Short name T346
Test name
Test status
Simulation time 8707274219 ps
CPU time 7.96 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:12 PM PDT 24
Peak memory 201876 kb
Host smart-39983365-ffa6-4218-aa2b-3e35d50b1abd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582242705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2582242705
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.4210744806
Short name T435
Test name
Test status
Simulation time 3089674037 ps
CPU time 9.66 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:12 PM PDT 24
Peak memory 202208 kb
Host smart-62e81be9-271c-40b9-b15b-9209b249db3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4210744806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4210744806
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2887182093
Short name T520
Test name
Test status
Simulation time 9737671 ps
CPU time 1.07 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:05 PM PDT 24
Peak memory 201856 kb
Host smart-6a710f0a-c135-4a28-950e-08ebbd2a44e6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887182093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2887182093
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2649673225
Short name T854
Test name
Test status
Simulation time 2711448104 ps
CPU time 39.62 seconds
Started Aug 18 04:56:15 PM PDT 24
Finished Aug 18 04:56:54 PM PDT 24
Peak memory 202012 kb
Host smart-72e396c1-d96a-4367-86a2-cb91bf8b5a17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2649673225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2649673225
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1546927350
Short name T294
Test name
Test status
Simulation time 403598563 ps
CPU time 19.81 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 201944 kb
Host smart-a8d521c9-9489-4767-94e0-9efcdff3cff7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1546927350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1546927350
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4052948193
Short name T873
Test name
Test status
Simulation time 24079502867 ps
CPU time 194.64 seconds
Started Aug 18 04:56:11 PM PDT 24
Finished Aug 18 04:59:26 PM PDT 24
Peak memory 206596 kb
Host smart-2618faba-8ec8-4b04-9ef2-cee869f0b4b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4052948193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.4052948193
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1169833950
Short name T184
Test name
Test status
Simulation time 578825520 ps
CPU time 117.05 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 206508 kb
Host smart-0d9046d7-ea39-4956-aed7-1b351ac2a419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1169833950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.1169833950
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1212022265
Short name T139
Test name
Test status
Simulation time 487757247 ps
CPU time 4.32 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:16 PM PDT 24
Peak memory 201824 kb
Host smart-5b592dbd-94f4-46ae-8f35-ef7d8e624d21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1212022265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1212022265
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.45602329
Short name T309
Test name
Test status
Simulation time 370038320 ps
CPU time 5.54 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 201860 kb
Host smart-44458abe-ba2a-49a1-b6b6-c4ccd93285e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45602329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.45602329
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3311619129
Short name T102
Test name
Test status
Simulation time 221630058791 ps
CPU time 200.73 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:59:51 PM PDT 24
Peak memory 202952 kb
Host smart-799c7a2e-8890-45c7-8713-406f29daa191
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3311619129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.3311619129
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1985428962
Short name T724
Test name
Test status
Simulation time 22890745 ps
CPU time 2.07 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:40 PM PDT 24
Peak memory 201860 kb
Host smart-864a50e4-f347-4658-aff1-e9f51d22dd6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1985428962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1985428962
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.1017382471
Short name T518
Test name
Test status
Simulation time 80385215 ps
CPU time 5.13 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:56:50 PM PDT 24
Peak memory 202120 kb
Host smart-9dd892b7-41f7-4547-b809-b95455add0d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1017382471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1017382471
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.3456725129
Short name T506
Test name
Test status
Simulation time 432688452 ps
CPU time 4.62 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:32 PM PDT 24
Peak memory 201784 kb
Host smart-583dc4fd-d3ba-48ec-b941-6e42baecb516
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3456725129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3456725129
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2043116978
Short name T463
Test name
Test status
Simulation time 6823767775 ps
CPU time 29.62 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:58 PM PDT 24
Peak memory 201944 kb
Host smart-d33f052c-29f9-4d08-8c80-fca4164732ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043116978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2043116978
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.4028821429
Short name T871
Test name
Test status
Simulation time 26371630735 ps
CPU time 49.09 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:57:19 PM PDT 24
Peak memory 201932 kb
Host smart-242bbd1e-1106-4dad-9ae7-c12a2184c7b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4028821429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.4028821429
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3737920617
Short name T726
Test name
Test status
Simulation time 91204131 ps
CPU time 6.29 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 201808 kb
Host smart-9023495a-bb90-4531-9b7f-7b694a251556
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737920617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3737920617
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.681559909
Short name T512
Test name
Test status
Simulation time 584258219 ps
CPU time 8.57 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:37 PM PDT 24
Peak memory 201868 kb
Host smart-bea744dd-576a-4b89-b4fd-d0bfa76a9c29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681559909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.681559909
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.1355827781
Short name T833
Test name
Test status
Simulation time 9237896 ps
CPU time 1.27 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:29 PM PDT 24
Peak memory 201912 kb
Host smart-623a0cc6-37e5-4cdd-b3ca-c45d08e456c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1355827781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1355827781
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3433090144
Short name T474
Test name
Test status
Simulation time 13664983168 ps
CPU time 11.04 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 201960 kb
Host smart-4d3968b3-695d-4349-a6cc-d480a9b889b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433090144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3433090144
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3548502183
Short name T578
Test name
Test status
Simulation time 2694887056 ps
CPU time 5.99 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 202016 kb
Host smart-00398e33-481f-4979-b878-557a26d1df5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3548502183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3548502183
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.323272708
Short name T307
Test name
Test status
Simulation time 20585854 ps
CPU time 1.08 seconds
Started Aug 18 04:56:33 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 201988 kb
Host smart-d761ab56-3a2e-4c1e-87e2-96686e75e530
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323272708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.323272708
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1286112042
Short name T735
Test name
Test status
Simulation time 20218731370 ps
CPU time 97.43 seconds
Started Aug 18 04:56:46 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 202944 kb
Host smart-689bfa45-6725-4212-a976-4306b344cd3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1286112042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1286112042
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3859869153
Short name T83
Test name
Test status
Simulation time 389921421 ps
CPU time 31.25 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:57:08 PM PDT 24
Peak memory 201844 kb
Host smart-706134a8-59d1-4cc7-9280-11c37fdce86e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3859869153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3859869153
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3920731691
Short name T851
Test name
Test status
Simulation time 226780229 ps
CPU time 46.21 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:57:28 PM PDT 24
Peak memory 204132 kb
Host smart-ca28dc19-400e-408a-8fc2-df28cad0b169
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3920731691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.3920731691
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.873427099
Short name T625
Test name
Test status
Simulation time 576790087 ps
CPU time 69.95 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:57:49 PM PDT 24
Peak memory 204992 kb
Host smart-c04592c3-8b68-4b9c-945d-51f80ee9149e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873427099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res
et_error.873427099
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.287309654
Short name T723
Test name
Test status
Simulation time 214266768 ps
CPU time 5.1 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 201912 kb
Host smart-8c27aaf0-0c63-4de8-9ccc-31146015a0d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=287309654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.287309654
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2264044530
Short name T404
Test name
Test status
Simulation time 38547674 ps
CPU time 5.3 seconds
Started Aug 18 04:56:46 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 201856 kb
Host smart-39620ccc-3c63-4df4-81ad-281b46becb5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2264044530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2264044530
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1061869040
Short name T434
Test name
Test status
Simulation time 135134591092 ps
CPU time 330.42 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 05:02:18 PM PDT 24
Peak memory 202964 kb
Host smart-0f882e79-611a-4f5c-8c05-e3c1aea4465e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1061869040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1061869040
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1846755056
Short name T127
Test name
Test status
Simulation time 162974169 ps
CPU time 5.7 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:57:01 PM PDT 24
Peak memory 201912 kb
Host smart-975334a9-d505-44c9-a65c-fed09df6afe3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846755056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1846755056
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.2698998074
Short name T590
Test name
Test status
Simulation time 34558887 ps
CPU time 3.53 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:56:51 PM PDT 24
Peak memory 201816 kb
Host smart-73dbf6d6-ab0d-4579-b226-97a8b514e691
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2698998074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2698998074
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.3908192991
Short name T501
Test name
Test status
Simulation time 1805091768 ps
CPU time 15.13 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:53 PM PDT 24
Peak memory 201812 kb
Host smart-43045644-2824-4197-abb6-8c593461b428
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3908192991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3908192991
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.576033190
Short name T573
Test name
Test status
Simulation time 18056165213 ps
CPU time 70.2 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:57:53 PM PDT 24
Peak memory 201880 kb
Host smart-0b95970a-87d9-4006-b23b-39e0f88b52c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=576033190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.576033190
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3601603920
Short name T459
Test name
Test status
Simulation time 10682427406 ps
CPU time 79.04 seconds
Started Aug 18 04:56:46 PM PDT 24
Finished Aug 18 04:58:06 PM PDT 24
Peak memory 202012 kb
Host smart-81d1c52f-29e1-4138-abdf-bcd76a6a285a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3601603920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3601603920
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.494758645
Short name T173
Test name
Test status
Simulation time 47009016 ps
CPU time 4.88 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:56:44 PM PDT 24
Peak memory 201936 kb
Host smart-3f5629f7-caa8-4585-9971-ead29d518ef9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494758645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.494758645
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.2319446470
Short name T631
Test name
Test status
Simulation time 27992233 ps
CPU time 1.7 seconds
Started Aug 18 04:56:50 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 201956 kb
Host smart-5665f356-00ab-462a-9a70-f6d5be762c1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2319446470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2319446470
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.1307146727
Short name T893
Test name
Test status
Simulation time 11147149 ps
CPU time 1.09 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 201900 kb
Host smart-c7444f57-1a42-4cef-aeca-056f1f1e3659
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1307146727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1307146727
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3582834643
Short name T73
Test name
Test status
Simulation time 4793922488 ps
CPU time 9.13 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:56:51 PM PDT 24
Peak memory 201800 kb
Host smart-87e791ce-e61a-4197-8b70-11c588f7c262
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582834643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3582834643
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1936583980
Short name T332
Test name
Test status
Simulation time 881113752 ps
CPU time 5.33 seconds
Started Aug 18 04:56:36 PM PDT 24
Finished Aug 18 04:56:42 PM PDT 24
Peak memory 201852 kb
Host smart-e83bf072-1672-4d3c-abf8-b6618550d0dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1936583980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1936583980
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2607603712
Short name T278
Test name
Test status
Simulation time 8675030 ps
CPU time 1.25 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:56:40 PM PDT 24
Peak memory 201936 kb
Host smart-4af946bd-724e-45aa-a0d3-f54d60b47194
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607603712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2607603712
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1069871721
Short name T131
Test name
Test status
Simulation time 401747622 ps
CPU time 29.43 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:57:26 PM PDT 24
Peak memory 202908 kb
Host smart-0cbf3a35-6e4d-4912-9c68-c3d98fd386df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1069871721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1069871721
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3793264993
Short name T125
Test name
Test status
Simulation time 18211889802 ps
CPU time 90.82 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:58:27 PM PDT 24
Peak memory 202020 kb
Host smart-64a0ab35-4513-4e99-81cb-f2bc410b3337
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3793264993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3793264993
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2394702890
Short name T136
Test name
Test status
Simulation time 2739370287 ps
CPU time 54.41 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:57:51 PM PDT 24
Peak memory 204628 kb
Host smart-3d8b609c-be12-45e4-824d-30562c47fbf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2394702890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran
d_reset.2394702890
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2527026364
Short name T148
Test name
Test status
Simulation time 6715708342 ps
CPU time 97.67 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 204524 kb
Host smart-6eafc262-64af-4105-a560-c8ec88ee12b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2527026364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.2527026364
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3321570014
Short name T869
Test name
Test status
Simulation time 181194127 ps
CPU time 5.93 seconds
Started Aug 18 04:56:55 PM PDT 24
Finished Aug 18 04:57:01 PM PDT 24
Peak memory 201940 kb
Host smart-6eda0871-b24b-433b-a71d-397f6cd198b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3321570014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3321570014
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.383978176
Short name T99
Test name
Test status
Simulation time 259232313 ps
CPU time 6.16 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:26 PM PDT 24
Peak memory 201840 kb
Host smart-597b94e8-e601-4d66-9fc7-b3c044583576
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=383978176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.383978176
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1670891919
Short name T415
Test name
Test status
Simulation time 7687081601 ps
CPU time 46.08 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:58:07 PM PDT 24
Peak memory 201896 kb
Host smart-77e13d43-09ad-47f8-aa6e-12086419b296
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1670891919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.1670891919
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2157332868
Short name T411
Test name
Test status
Simulation time 1102140395 ps
CPU time 7.49 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:37 PM PDT 24
Peak memory 201852 kb
Host smart-eb1835ac-43a4-427a-8416-5088611c0428
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2157332868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2157332868
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.1784936555
Short name T632
Test name
Test status
Simulation time 495788032 ps
CPU time 6.19 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 201860 kb
Host smart-ea3fa4ce-d16a-40c3-bf17-4a38cc7ed4e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1784936555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1784936555
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3155656500
Short name T494
Test name
Test status
Simulation time 923983734 ps
CPU time 7.37 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 201816 kb
Host smart-27477d4c-dd94-4bf6-8e96-a1853fecd066
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3155656500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3155656500
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3824333202
Short name T419
Test name
Test status
Simulation time 25458894748 ps
CPU time 72.08 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:58:31 PM PDT 24
Peak memory 201872 kb
Host smart-a12096ec-1cb3-4406-8323-d0f296ba446a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824333202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3824333202
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.617918042
Short name T239
Test name
Test status
Simulation time 3852315848 ps
CPU time 13.62 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:33 PM PDT 24
Peak memory 201884 kb
Host smart-f1dff825-1b7d-45bd-bce5-08ad800ac885
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=617918042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.617918042
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2738809545
Short name T635
Test name
Test status
Simulation time 11113626 ps
CPU time 1.32 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 201860 kb
Host smart-98beaa3b-fd6d-49fe-8043-aa885bb621d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738809545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2738809545
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.4052176865
Short name T79
Test name
Test status
Simulation time 793358785 ps
CPU time 9.86 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 201864 kb
Host smart-92f3e3c9-8209-4600-a346-0b2a7a7238c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4052176865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4052176865
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.766667567
Short name T653
Test name
Test status
Simulation time 85005132 ps
CPU time 1.77 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:10 PM PDT 24
Peak memory 201800 kb
Host smart-f2c8f79a-ac93-48ae-99ca-3466f8d32f05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=766667567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.766667567
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3549469553
Short name T717
Test name
Test status
Simulation time 16841258499 ps
CPU time 9.47 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:57:17 PM PDT 24
Peak memory 201864 kb
Host smart-c8a3a2a5-4475-4a89-9109-d9ecf5eeefd8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549469553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3549469553
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1251071057
Short name T777
Test name
Test status
Simulation time 2918539789 ps
CPU time 8 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:16 PM PDT 24
Peak memory 202008 kb
Host smart-c63132a1-3b53-45e9-8e42-032276f38abc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1251071057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1251071057
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2595608802
Short name T728
Test name
Test status
Simulation time 10812929 ps
CPU time 1.2 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:57:09 PM PDT 24
Peak memory 201868 kb
Host smart-d4511355-be60-40ec-b0aa-b394c11466de
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595608802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2595608802
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1764029691
Short name T86
Test name
Test status
Simulation time 774811723 ps
CPU time 20.18 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:52 PM PDT 24
Peak memory 203152 kb
Host smart-1ee684d2-6090-4ccc-a26c-b666bcb82b57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1764029691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1764029691
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3207624844
Short name T496
Test name
Test status
Simulation time 3815295184 ps
CPU time 53.29 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:58:22 PM PDT 24
Peak memory 201928 kb
Host smart-b36e98ca-3a57-4768-83ee-fac1a288b481
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3207624844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3207624844
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3890113002
Short name T118
Test name
Test status
Simulation time 3718277882 ps
CPU time 165.09 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 05:00:18 PM PDT 24
Peak memory 204276 kb
Host smart-bc5ac80d-8b34-4050-9e03-3a66f3187e24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3890113002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.3890113002
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.101069447
Short name T810
Test name
Test status
Simulation time 1090537271 ps
CPU time 54.59 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 204620 kb
Host smart-08b44c60-08f7-4ba3-8315-5c3658a71569
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=101069447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_res
et_error.101069447
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1959330953
Short name T331
Test name
Test status
Simulation time 528644817 ps
CPU time 8.64 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 201820 kb
Host smart-1bdc8f42-fde5-44eb-b270-f4d669f84237
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1959330953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1959330953
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3204214818
Short name T100
Test name
Test status
Simulation time 777300540 ps
CPU time 19.99 seconds
Started Aug 18 04:57:41 PM PDT 24
Finished Aug 18 04:58:01 PM PDT 24
Peak memory 201856 kb
Host smart-8d93e483-3959-4e11-953e-64731b090826
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3204214818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3204214818
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2934100653
Short name T842
Test name
Test status
Simulation time 22337034865 ps
CPU time 84.33 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 203020 kb
Host smart-e146c23c-c43a-494f-9fe9-29b199acbf4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2934100653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2934100653
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1566749348
Short name T581
Test name
Test status
Simulation time 29066994 ps
CPU time 2.69 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 201932 kb
Host smart-617a2909-4667-4de6-b97d-d4247bd7970c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1566749348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1566749348
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.1777124038
Short name T441
Test name
Test status
Simulation time 2231983488 ps
CPU time 8.35 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:49 PM PDT 24
Peak memory 201876 kb
Host smart-41385a6a-fec8-4edb-a1be-3b5d01026a60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1777124038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1777124038
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.1154578553
Short name T744
Test name
Test status
Simulation time 433319663 ps
CPU time 8.57 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 201892 kb
Host smart-a752e921-7162-4059-9059-920eaec807d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1154578553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1154578553
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1194723135
Short name T753
Test name
Test status
Simulation time 13997400426 ps
CPU time 59.43 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:58:31 PM PDT 24
Peak memory 201876 kb
Host smart-d351766e-9b4d-4222-9d0d-9bc1ed14f410
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194723135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1194723135
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1848728810
Short name T730
Test name
Test status
Simulation time 13345205707 ps
CPU time 67.68 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 201996 kb
Host smart-504eccdf-add2-4cc2-a3fc-01cc6e1655e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1848728810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1848728810
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.4232638494
Short name T774
Test name
Test status
Simulation time 52354483 ps
CPU time 5.67 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:37 PM PDT 24
Peak memory 201948 kb
Host smart-c933f531-60c6-4a52-9004-e31966c14ae3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232638494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4232638494
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.434770912
Short name T847
Test name
Test status
Simulation time 141857385 ps
CPU time 1.45 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:57:40 PM PDT 24
Peak memory 201944 kb
Host smart-0a01cfee-17e6-4e23-8e3f-41ad6ee1dfcf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=434770912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.434770912
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.1299942060
Short name T592
Test name
Test status
Simulation time 64215222 ps
CPU time 1.82 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:31 PM PDT 24
Peak memory 201804 kb
Host smart-51a9a7b7-e511-458e-a47d-7a78f0a9c427
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1299942060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1299942060
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.904787859
Short name T34
Test name
Test status
Simulation time 2288601498 ps
CPU time 8.27 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 201936 kb
Host smart-b8d3706d-36a0-40fd-814b-4fce11e59103
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=904787859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.904787859
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1340555733
Short name T661
Test name
Test status
Simulation time 967400678 ps
CPU time 5.06 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:35 PM PDT 24
Peak memory 201864 kb
Host smart-945cebcb-ef80-4189-a1a0-5acc262fecf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1340555733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1340555733
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2634942128
Short name T838
Test name
Test status
Simulation time 9162627 ps
CPU time 1.11 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:31 PM PDT 24
Peak memory 201828 kb
Host smart-eb28f7aa-e6ac-4dce-9472-dd0dd2ae6f5d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634942128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2634942128
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3515165834
Short name T274
Test name
Test status
Simulation time 257872415 ps
CPU time 11.72 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:52 PM PDT 24
Peak memory 201932 kb
Host smart-904f2334-7a3f-4144-ad59-ff9459e80786
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3515165834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3515165834
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1514700936
Short name T446
Test name
Test status
Simulation time 21671489194 ps
CPU time 76.02 seconds
Started Aug 18 04:57:46 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 203648 kb
Host smart-e0ecd24f-8bb4-4acb-80ef-0a12db4c600c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1514700936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1514700936
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3222933386
Short name T763
Test name
Test status
Simulation time 9802768719 ps
CPU time 223.7 seconds
Started Aug 18 04:57:46 PM PDT 24
Finished Aug 18 05:01:30 PM PDT 24
Peak memory 208116 kb
Host smart-f75cb26e-3219-42df-a80d-3d71596eb0b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3222933386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.3222933386
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3638381270
Short name T406
Test name
Test status
Simulation time 28730277 ps
CPU time 5.28 seconds
Started Aug 18 04:57:43 PM PDT 24
Finished Aug 18 04:57:49 PM PDT 24
Peak memory 201940 kb
Host smart-0d5c8afd-2fc5-4bb7-b081-d764eb54e158
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3638381270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.3638381270
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.4272700659
Short name T545
Test name
Test status
Simulation time 26031752 ps
CPU time 2.39 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:42 PM PDT 24
Peak memory 201952 kb
Host smart-320e802d-a007-47d3-ae89-dbd27af209bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4272700659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4272700659
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1246278397
Short name T60
Test name
Test status
Simulation time 275413109 ps
CPU time 6.54 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:05 PM PDT 24
Peak memory 201824 kb
Host smart-1edc8270-d8a3-46bb-ae6a-d07116cd75fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1246278397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1246278397
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1311781713
Short name T605
Test name
Test status
Simulation time 45768640912 ps
CPU time 277.8 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 05:02:36 PM PDT 24
Peak memory 203740 kb
Host smart-340be58a-8b79-4394-bb5f-7d63bd641649
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1311781713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1311781713
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2135863191
Short name T438
Test name
Test status
Simulation time 1622676994 ps
CPU time 9.27 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:07 PM PDT 24
Peak memory 201936 kb
Host smart-9c63fde1-46f0-4b0d-9f33-0dfc8a714e9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2135863191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2135863191
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.1371365974
Short name T403
Test name
Test status
Simulation time 123097346 ps
CPU time 5.49 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:04 PM PDT 24
Peak memory 201852 kb
Host smart-83a9aaf0-e024-4ae7-995a-810e03362530
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1371365974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1371365974
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.2609527941
Short name T228
Test name
Test status
Simulation time 1301310450 ps
CPU time 11.88 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:58:02 PM PDT 24
Peak memory 201840 kb
Host smart-b9679097-7646-4188-802b-03253838b390
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2609527941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2609527941
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1520064580
Short name T272
Test name
Test status
Simulation time 65951375192 ps
CPU time 152.82 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 05:00:22 PM PDT 24
Peak memory 201852 kb
Host smart-22a164e0-a7f1-45b8-934c-3ca6ed4d4e55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520064580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1520064580
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1815794164
Short name T477
Test name
Test status
Simulation time 16616264743 ps
CPU time 118.68 seconds
Started Aug 18 04:58:00 PM PDT 24
Finished Aug 18 04:59:58 PM PDT 24
Peak memory 201884 kb
Host smart-7882e785-62d9-4b26-91a6-984401dea58c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1815794164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1815794164
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.219704911
Short name T56
Test name
Test status
Simulation time 318972361 ps
CPU time 9.52 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:59 PM PDT 24
Peak memory 201864 kb
Host smart-bc5fdc7b-1218-4564-a740-26469fa3e291
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219704911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.219704911
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.3064794504
Short name T551
Test name
Test status
Simulation time 55068513 ps
CPU time 2.92 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:02 PM PDT 24
Peak memory 201960 kb
Host smart-60326ceb-2b48-4102-8337-8b9495328f6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3064794504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3064794504
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.1570471072
Short name T536
Test name
Test status
Simulation time 16973542 ps
CPU time 1.28 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 201772 kb
Host smart-6faa3dcc-9a86-4374-95dc-bc7a01c69826
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1570471072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1570471072
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.721514623
Short name T568
Test name
Test status
Simulation time 10735707712 ps
CPU time 7.4 seconds
Started Aug 18 04:57:51 PM PDT 24
Finished Aug 18 04:57:59 PM PDT 24
Peak memory 201880 kb
Host smart-c53347cb-437a-48d8-9f5d-c86b33007cf3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=721514623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.721514623
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.93826340
Short name T113
Test name
Test status
Simulation time 1267156666 ps
CPU time 7.23 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:58 PM PDT 24
Peak memory 201948 kb
Host smart-b7b1a678-e3d3-452f-af7e-d9553398b168
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=93826340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.93826340
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2105661439
Short name T2
Test name
Test status
Simulation time 8703803 ps
CPU time 1.21 seconds
Started Aug 18 04:57:51 PM PDT 24
Finished Aug 18 04:57:52 PM PDT 24
Peak memory 201924 kb
Host smart-da57eaf9-50f3-4786-baa0-7cf9a433021a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105661439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2105661439
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.835874757
Short name T428
Test name
Test status
Simulation time 4774067507 ps
CPU time 58.38 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 203192 kb
Host smart-1e7c8150-c0b9-439d-a41a-7dacb7c63a16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=835874757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.835874757
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3896999130
Short name T659
Test name
Test status
Simulation time 250132949 ps
CPU time 20.26 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:18 PM PDT 24
Peak memory 201748 kb
Host smart-264df153-8e15-460a-887c-d38acd59123d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3896999130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3896999130
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2729961168
Short name T469
Test name
Test status
Simulation time 1133261507 ps
CPU time 111.85 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:59:51 PM PDT 24
Peak memory 205544 kb
Host smart-16c08e35-7d0e-401c-a1d2-a09637be63cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2729961168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.2729961168
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.4138446363
Short name T491
Test name
Test status
Simulation time 402715963 ps
CPU time 37.76 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 203980 kb
Host smart-846cf817-317a-432c-8f4e-7bbcec01bf53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4138446363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.4138446363
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.4183587511
Short name T243
Test name
Test status
Simulation time 43720241 ps
CPU time 5.23 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:04 PM PDT 24
Peak memory 201956 kb
Host smart-e6ae9fb0-922f-4c86-bf2d-a70f847ea32d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4183587511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4183587511
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2354964451
Short name T64
Test name
Test status
Simulation time 1715533559 ps
CPU time 23.9 seconds
Started Aug 18 04:58:02 PM PDT 24
Finished Aug 18 04:58:26 PM PDT 24
Peak memory 201876 kb
Host smart-60b72200-5706-4bb4-9950-46e8a2422481
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2354964451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2354964451
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4221957187
Short name T857
Test name
Test status
Simulation time 339574120 ps
CPU time 6.75 seconds
Started Aug 18 04:57:57 PM PDT 24
Finished Aug 18 04:58:04 PM PDT 24
Peak memory 201936 kb
Host smart-3aeeb570-33a9-4adb-85fb-88ff291e6d10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4221957187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4221957187
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2240133855
Short name T526
Test name
Test status
Simulation time 958070156 ps
CPU time 6.6 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:05 PM PDT 24
Peak memory 201932 kb
Host smart-f3e1888c-9a53-48bc-b96b-161797189e6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2240133855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2240133855
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.431128614
Short name T410
Test name
Test status
Simulation time 63999873 ps
CPU time 7.42 seconds
Started Aug 18 04:58:00 PM PDT 24
Finished Aug 18 04:58:08 PM PDT 24
Peak memory 201852 kb
Host smart-605e13ee-a3c2-424d-a277-35cda3e090c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=431128614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.431128614
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.696684048
Short name T185
Test name
Test status
Simulation time 21406781301 ps
CPU time 72.94 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 201956 kb
Host smart-2c633aae-8b6d-43fe-891d-0ed07a5a378e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=696684048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.696684048
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.318855173
Short name T119
Test name
Test status
Simulation time 30665074114 ps
CPU time 94.84 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 202008 kb
Host smart-8d85ddd4-28d6-4666-b334-54bc7451213c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=318855173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.318855173
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1774541648
Short name T388
Test name
Test status
Simulation time 79715820 ps
CPU time 2.29 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:01 PM PDT 24
Peak memory 202124 kb
Host smart-cd38f5f1-ec60-40a9-8398-21f27652add6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774541648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1774541648
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.3048299019
Short name T862
Test name
Test status
Simulation time 860549617 ps
CPU time 11.05 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201848 kb
Host smart-a88ef7d2-f5c8-445a-bd8f-23c470a65f5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3048299019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3048299019
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.2245767169
Short name T488
Test name
Test status
Simulation time 83236253 ps
CPU time 1.27 seconds
Started Aug 18 04:57:57 PM PDT 24
Finished Aug 18 04:57:58 PM PDT 24
Peak memory 201768 kb
Host smart-cd40d88f-dc51-4884-89a4-80dae3392eab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2245767169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2245767169
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.66991546
Short name T63
Test name
Test status
Simulation time 3738096744 ps
CPU time 8.58 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:07 PM PDT 24
Peak memory 201972 kb
Host smart-bbfdc2f5-78c1-4e55-87ce-eacd5c80b531
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=66991546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.66991546
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1229865825
Short name T685
Test name
Test status
Simulation time 2356939368 ps
CPU time 13.45 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 202016 kb
Host smart-3c11e0f9-74ee-4cd1-966f-527a149b2635
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1229865825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1229865825
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1785088309
Short name T257
Test name
Test status
Simulation time 10853972 ps
CPU time 1.18 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:00 PM PDT 24
Peak memory 201872 kb
Host smart-33e0a156-333c-41e1-9b73-74754141e999
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785088309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1785088309
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.1004297986
Short name T180
Test name
Test status
Simulation time 254041530 ps
CPU time 18.12 seconds
Started Aug 18 04:58:02 PM PDT 24
Finished Aug 18 04:58:20 PM PDT 24
Peak memory 203912 kb
Host smart-788a2a37-0d75-4671-aca2-a682524d7096
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1004297986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1004297986
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1035725471
Short name T607
Test name
Test status
Simulation time 269759482 ps
CPU time 21.28 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:21 PM PDT 24
Peak memory 202964 kb
Host smart-bb2d196d-77da-4638-a28a-7a81bf2ebf86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1035725471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1035725471
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3909280966
Short name T667
Test name
Test status
Simulation time 4919560320 ps
CPU time 145.94 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 05:00:24 PM PDT 24
Peak memory 204648 kb
Host smart-cb24195a-f1cc-4059-9870-14d141fa8cc8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3909280966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.3909280966
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4230165904
Short name T513
Test name
Test status
Simulation time 8000402144 ps
CPU time 31.67 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:30 PM PDT 24
Peak memory 202992 kb
Host smart-c135cffc-787b-4efc-874b-ca8ab9c0d3c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4230165904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.4230165904
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3258147394
Short name T413
Test name
Test status
Simulation time 268823499 ps
CPU time 3.53 seconds
Started Aug 18 04:57:59 PM PDT 24
Finished Aug 18 04:58:03 PM PDT 24
Peak memory 201924 kb
Host smart-28eecac3-ac1e-49f2-8383-0e5b8f07b49a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3258147394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3258147394
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.127424494
Short name T300
Test name
Test status
Simulation time 4270517207 ps
CPU time 15.42 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:22 PM PDT 24
Peak memory 201920 kb
Host smart-c77639cd-053a-4a10-a8b7-7a2e64c47011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=127424494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.127424494
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.856012517
Short name T864
Test name
Test status
Simulation time 48725588 ps
CPU time 3.54 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201856 kb
Host smart-fbabd0ba-2387-45df-9ae1-182929feecfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856012517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.856012517
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.1564328805
Short name T372
Test name
Test status
Simulation time 35056187 ps
CPU time 2.19 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 201788 kb
Host smart-fc69d4ff-7f29-41e1-b640-71210f04e49b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1564328805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1564328805
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.308496785
Short name T424
Test name
Test status
Simulation time 416007627 ps
CPU time 4.97 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 201868 kb
Host smart-0f4d117d-1d67-4e32-ae6c-82c330b65235
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=308496785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.308496785
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1284595724
Short name T805
Test name
Test status
Simulation time 3958684373 ps
CPU time 17.78 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:27 PM PDT 24
Peak memory 201844 kb
Host smart-a72ce597-b514-4d84-af61-ddff77568815
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284595724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1284595724
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3886820077
Short name T245
Test name
Test status
Simulation time 7102025596 ps
CPU time 49.48 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 202004 kb
Host smart-ff03f5c2-2f8e-4eaf-ba7c-8ba512db8d2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3886820077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3886820077
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3334345486
Short name T683
Test name
Test status
Simulation time 52982760 ps
CPU time 3.99 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 201940 kb
Host smart-745c76b3-81ba-464b-9373-c302a528cd24
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334345486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3334345486
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3322106869
Short name T783
Test name
Test status
Simulation time 24216967 ps
CPU time 1.73 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201940 kb
Host smart-f5e0e718-50f1-4d76-a784-618d69e80f42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3322106869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3322106869
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.1396459556
Short name T748
Test name
Test status
Simulation time 50385153 ps
CPU time 1.36 seconds
Started Aug 18 04:58:02 PM PDT 24
Finished Aug 18 04:58:03 PM PDT 24
Peak memory 201808 kb
Host smart-396ae3ae-73a0-4077-973f-f482bb8e3a7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1396459556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1396459556
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1743572429
Short name T481
Test name
Test status
Simulation time 4148983674 ps
CPU time 7.36 seconds
Started Aug 18 04:57:57 PM PDT 24
Finished Aug 18 04:58:04 PM PDT 24
Peak memory 201984 kb
Host smart-eed02b13-befa-477c-a1e8-b0fbaea11403
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743572429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1743572429
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1034437112
Short name T620
Test name
Test status
Simulation time 4904971337 ps
CPU time 12.52 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:11 PM PDT 24
Peak memory 201932 kb
Host smart-20db2ba8-21de-443b-8fda-f5dfeb09d9fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1034437112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1034437112
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.401536623
Short name T22
Test name
Test status
Simulation time 9084375 ps
CPU time 1.42 seconds
Started Aug 18 04:58:01 PM PDT 24
Finished Aug 18 04:58:03 PM PDT 24
Peak memory 201948 kb
Host smart-ad0b4544-d3ec-4976-8a72-93cba54ab5e0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401536623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.401536623
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.2109362751
Short name T199
Test name
Test status
Simulation time 7832440554 ps
CPU time 51.18 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 204188 kb
Host smart-cc4cdc99-8f97-47de-a884-00028d8235ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2109362751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2109362751
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1846149527
Short name T179
Test name
Test status
Simulation time 4031110967 ps
CPU time 21.7 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:32 PM PDT 24
Peak memory 201956 kb
Host smart-99326795-b39d-4c83-8a63-ca9d0c28a0c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846149527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1846149527
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.233699002
Short name T202
Test name
Test status
Simulation time 2349105679 ps
CPU time 70.21 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:59:19 PM PDT 24
Peak memory 203684 kb
Host smart-c35d59fe-108f-4463-9222-f5875cadf35f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=233699002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_res
et_error.233699002
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2368156964
Short name T383
Test name
Test status
Simulation time 586678040 ps
CPU time 3.08 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:11 PM PDT 24
Peak memory 201852 kb
Host smart-7dac2d83-1e59-4263-894e-a0707f671343
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2368156964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2368156964
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2349927539
Short name T418
Test name
Test status
Simulation time 30094471 ps
CPU time 4.21 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 201840 kb
Host smart-6c36b170-c401-4242-99bc-c9fa43dfc149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2349927539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2349927539
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2776630897
Short name T166
Test name
Test status
Simulation time 59340206529 ps
CPU time 334.33 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 05:03:41 PM PDT 24
Peak memory 204104 kb
Host smart-cb8026da-f41d-4418-89b1-bcde01fda2ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2776630897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.2776630897
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.172901754
Short name T495
Test name
Test status
Simulation time 206151928 ps
CPU time 3.37 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201848 kb
Host smart-d761b389-0ad3-4092-8871-f73d03ac27d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=172901754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.172901754
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2747065306
Short name T784
Test name
Test status
Simulation time 531376494 ps
CPU time 3.23 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:11 PM PDT 24
Peak memory 201848 kb
Host smart-38cd12d4-5b97-4836-8e0b-5ffea7ad2f80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2747065306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2747065306
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3428024520
Short name T593
Test name
Test status
Simulation time 81926568 ps
CPU time 8.42 seconds
Started Aug 18 04:58:14 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 201796 kb
Host smart-77a734b3-7a28-446c-abf5-54892f849ca1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3428024520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3428024520
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.251344434
Short name T128
Test name
Test status
Simulation time 50825785043 ps
CPU time 113.02 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 05:00:02 PM PDT 24
Peak memory 201848 kb
Host smart-9ca063d0-817e-4b93-a673-d4353ac0c510
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=251344434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.251344434
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3781973013
Short name T529
Test name
Test status
Simulation time 5347936341 ps
CPU time 21.31 seconds
Started Aug 18 04:58:06 PM PDT 24
Finished Aug 18 04:58:27 PM PDT 24
Peak memory 201928 kb
Host smart-50e0a1e2-da74-4675-a5e7-b268c076d2c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3781973013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3781973013
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3928335813
Short name T761
Test name
Test status
Simulation time 39074199 ps
CPU time 3.03 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 201940 kb
Host smart-24753be1-7cbd-47ea-8fed-8025f2bb4619
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928335813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3928335813
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.1640488570
Short name T516
Test name
Test status
Simulation time 3324052372 ps
CPU time 5.38 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 201868 kb
Host smart-48c01480-0a0a-4127-b364-0c41dec636f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1640488570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1640488570
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.4038663985
Short name T467
Test name
Test status
Simulation time 39408575 ps
CPU time 1.24 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201808 kb
Host smart-9c7016d3-0c99-42f8-9cfd-dc4719c210a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4038663985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4038663985
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2072473436
Short name T371
Test name
Test status
Simulation time 1393434159 ps
CPU time 7.23 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:16 PM PDT 24
Peak memory 201904 kb
Host smart-562bd899-2d5a-4ac7-8a07-4d84b7992466
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072473436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2072473436
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3363178858
Short name T364
Test name
Test status
Simulation time 4947120622 ps
CPU time 5.34 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:16 PM PDT 24
Peak memory 202016 kb
Host smart-a493715f-cfe2-4335-acae-7dd361e2e95e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3363178858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3363178858
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.743961602
Short name T500
Test name
Test status
Simulation time 9522341 ps
CPU time 1.12 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:11 PM PDT 24
Peak memory 201988 kb
Host smart-c76fe7cc-10bd-4a85-b9df-f4b90ab75c53
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743961602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.743961602
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3779636891
Short name T451
Test name
Test status
Simulation time 17267082364 ps
CPU time 59.04 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:59:08 PM PDT 24
Peak memory 203000 kb
Host smart-5e3b85ba-ac29-41b1-86b4-4b15e44acbd5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3779636891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3779636891
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2628507937
Short name T313
Test name
Test status
Simulation time 438620981 ps
CPU time 44.08 seconds
Started Aug 18 04:58:11 PM PDT 24
Finished Aug 18 04:58:55 PM PDT 24
Peak memory 201844 kb
Host smart-73a5cee4-66ca-41ce-ab76-5403dedd9015
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2628507937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2628507937
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3030732430
Short name T876
Test name
Test status
Simulation time 3276824032 ps
CPU time 104.15 seconds
Started Aug 18 04:58:06 PM PDT 24
Finished Aug 18 04:59:51 PM PDT 24
Peak memory 205756 kb
Host smart-a1aa89b4-5ca5-4de4-9614-a32e45508f2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3030732430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.3030732430
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2431792278
Short name T123
Test name
Test status
Simulation time 6559709173 ps
CPU time 64.63 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 204216 kb
Host smart-632e0ecb-a787-432b-9829-2b4d5f1fab92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2431792278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.2431792278
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.363973345
Short name T347
Test name
Test status
Simulation time 43217473 ps
CPU time 2.65 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 201960 kb
Host smart-1f7fe1e5-c8ae-493c-a6c6-1a6bd7918d40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=363973345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.363973345
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2382037468
Short name T143
Test name
Test status
Simulation time 216511671 ps
CPU time 5.21 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:14 PM PDT 24
Peak memory 201772 kb
Host smart-6fc0df1c-1b4a-4b41-b844-c170db863f75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2382037468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2382037468
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1555134006
Short name T692
Test name
Test status
Simulation time 53940416832 ps
CPU time 278.69 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 05:02:47 PM PDT 24
Peak memory 203560 kb
Host smart-31843eac-1018-4adc-a0b3-6087231fbab6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1555134006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.1555134006
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.906310356
Short name T769
Test name
Test status
Simulation time 145757743 ps
CPU time 2.43 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201868 kb
Host smart-ced14e39-61f3-42e0-a85d-3ef0f12c135f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=906310356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.906310356
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.229446929
Short name T449
Test name
Test status
Simulation time 1036362821 ps
CPU time 12.48 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:21 PM PDT 24
Peak memory 201956 kb
Host smart-95d57414-f181-4664-b8ee-f0a73e748b97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=229446929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.229446929
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.489502126
Short name T693
Test name
Test status
Simulation time 966356669 ps
CPU time 11.8 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:21 PM PDT 24
Peak memory 201892 kb
Host smart-8ee06487-6f84-4d9c-bcce-93c3a23464e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=489502126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.489502126
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3838753168
Short name T172
Test name
Test status
Simulation time 50149969041 ps
CPU time 164.75 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 05:00:52 PM PDT 24
Peak memory 201944 kb
Host smart-1ad22e4b-936b-47a9-ae5b-d3e7f585eb9d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838753168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3838753168
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.649359591
Short name T554
Test name
Test status
Simulation time 20749594021 ps
CPU time 85.92 seconds
Started Aug 18 04:58:14 PM PDT 24
Finished Aug 18 04:59:40 PM PDT 24
Peak memory 201912 kb
Host smart-2a7b9144-f9c4-4cfb-8e11-79c93a98fb04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=649359591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.649359591
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1978297019
Short name T260
Test name
Test status
Simulation time 20960052 ps
CPU time 1.62 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:11 PM PDT 24
Peak memory 201944 kb
Host smart-c5c93aac-5af6-4314-8ef4-b8fdbc50e9e7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978297019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1978297019
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.3879621404
Short name T736
Test name
Test status
Simulation time 974844491 ps
CPU time 12.46 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:21 PM PDT 24
Peak memory 201840 kb
Host smart-441735d9-1782-4622-8c5b-e2609b324382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3879621404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3879621404
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3549073907
Short name T872
Test name
Test status
Simulation time 44200516 ps
CPU time 1.57 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:09 PM PDT 24
Peak memory 201808 kb
Host smart-ee7ea54a-7bc8-4395-846c-8749dbd6f929
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549073907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3549073907
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1418999602
Short name T338
Test name
Test status
Simulation time 6704862105 ps
CPU time 11.22 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:21 PM PDT 24
Peak memory 201956 kb
Host smart-3d68eeb7-b84d-4a18-a1ed-7af242ce0237
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418999602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1418999602
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1752669325
Short name T709
Test name
Test status
Simulation time 2257127632 ps
CPU time 7.37 seconds
Started Aug 18 04:58:07 PM PDT 24
Finished Aug 18 04:58:14 PM PDT 24
Peak memory 201940 kb
Host smart-4f35bf93-d008-46fb-8b8e-77afcb383c67
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1752669325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1752669325
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1905725595
Short name T440
Test name
Test status
Simulation time 12078779 ps
CPU time 1.21 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 201856 kb
Host smart-b4ee7e3e-a50a-4f2a-b25c-4490e3a18bda
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905725595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1905725595
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.4187889763
Short name T503
Test name
Test status
Simulation time 31990759 ps
CPU time 3.63 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 201800 kb
Host smart-51c43e6f-3c6e-4831-a50c-400698ab9e1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4187889763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4187889763
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1045574025
Short name T45
Test name
Test status
Simulation time 2414796221 ps
CPU time 23.48 seconds
Started Aug 18 04:58:10 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 202004 kb
Host smart-0dcf8df4-c53d-4b0e-87bd-2c3898790374
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1045574025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1045574025
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.854579404
Short name T456
Test name
Test status
Simulation time 2676169685 ps
CPU time 53.46 seconds
Started Aug 18 04:58:08 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 204020 kb
Host smart-9ad5ff6e-efb5-4d5a-ab74-2a23199aa7c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=854579404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand
_reset.854579404
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2545442583
Short name T534
Test name
Test status
Simulation time 1904267970 ps
CPU time 83.53 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 205452 kb
Host smart-8e6db932-6d50-48d7-8782-bf3d76af9346
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2545442583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.2545442583
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1659111502
Short name T378
Test name
Test status
Simulation time 476968818 ps
CPU time 4.22 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 201936 kb
Host smart-47c34751-c66e-4ec4-b62f-a16f700eb4e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1659111502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1659111502
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3317574601
Short name T53
Test name
Test status
Simulation time 1672434658 ps
CPU time 16.85 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:51:52 PM PDT 24
Peak memory 201932 kb
Host smart-f1a11196-7500-44fe-a33a-45cce7c4a1c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3317574601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3317574601
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1003708640
Short name T194
Test name
Test status
Simulation time 52590816895 ps
CPU time 263.95 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:55:57 PM PDT 24
Peak memory 202944 kb
Host smart-7bf9b051-e511-4566-8924-43b1906eef88
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1003708640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.1003708640
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2927914475
Short name T886
Test name
Test status
Simulation time 515368039 ps
CPU time 7.68 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:51:43 PM PDT 24
Peak memory 201940 kb
Host smart-cbf7e614-68f4-436e-9764-0a20bbb9cf27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2927914475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2927914475
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.279933719
Short name T619
Test name
Test status
Simulation time 58774738 ps
CPU time 6.98 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:41 PM PDT 24
Peak memory 201932 kb
Host smart-73ea6e5e-0e7c-4ec3-a984-00415084be73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=279933719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.279933719
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.2399051281
Short name T747
Test name
Test status
Simulation time 145855247 ps
CPU time 2.64 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:37 PM PDT 24
Peak memory 201896 kb
Host smart-e057ead7-eee4-42f3-902c-41483f9b68c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2399051281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2399051281
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3512886872
Short name T149
Test name
Test status
Simulation time 26710563456 ps
CPU time 71.64 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:52:46 PM PDT 24
Peak memory 201936 kb
Host smart-a94c752c-d191-428e-a7c7-0c0e7622b51b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512886872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3512886872
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3423106142
Short name T190
Test name
Test status
Simulation time 8803771176 ps
CPU time 61.35 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:52:35 PM PDT 24
Peak memory 201908 kb
Host smart-2f508b38-e0c4-4fd4-8ee5-9df03d71f0e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3423106142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3423106142
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2931809455
Short name T600
Test name
Test status
Simulation time 32977154 ps
CPU time 1.42 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:51:34 PM PDT 24
Peak memory 201944 kb
Host smart-71246118-dbbc-40b1-8e5d-2f7709c64d97
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931809455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2931809455
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.1717576649
Short name T370
Test name
Test status
Simulation time 552448376 ps
CPU time 5.82 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:51:40 PM PDT 24
Peak memory 201860 kb
Host smart-32511805-2108-4237-a364-e793584c2c1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1717576649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1717576649
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.337055836
Short name T570
Test name
Test status
Simulation time 9668080 ps
CPU time 1.07 seconds
Started Aug 18 04:51:32 PM PDT 24
Finished Aug 18 04:51:33 PM PDT 24
Peak memory 201812 kb
Host smart-6d8008cc-1a7a-4a43-b42f-8bd7d6419b48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=337055836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.337055836
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1720442742
Short name T792
Test name
Test status
Simulation time 2485521719 ps
CPU time 8.13 seconds
Started Aug 18 04:51:35 PM PDT 24
Finished Aug 18 04:51:43 PM PDT 24
Peak memory 201952 kb
Host smart-acd7ac4d-fdb2-4b0f-b9b2-55932811b801
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720442742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1720442742
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.571765173
Short name T41
Test name
Test status
Simulation time 4823549885 ps
CPU time 7.04 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:41 PM PDT 24
Peak memory 201848 kb
Host smart-f63fc9bf-3871-445c-aba8-13498df6ea0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=571765173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.571765173
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.80276516
Short name T465
Test name
Test status
Simulation time 9809379 ps
CPU time 1.27 seconds
Started Aug 18 04:51:32 PM PDT 24
Finished Aug 18 04:51:34 PM PDT 24
Peak memory 201884 kb
Host smart-11fd67de-0e03-47fd-b47e-acf399fdba64
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80276516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.80276516
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1454276534
Short name T832
Test name
Test status
Simulation time 82750981 ps
CPU time 8.72 seconds
Started Aug 18 04:51:38 PM PDT 24
Finished Aug 18 04:51:47 PM PDT 24
Peak memory 201944 kb
Host smart-02d03197-45e4-4829-921a-c52497166612
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1454276534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1454276534
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2126099503
Short name T262
Test name
Test status
Simulation time 978260941 ps
CPU time 60.03 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:52:35 PM PDT 24
Peak memory 201944 kb
Host smart-a15388cc-0639-43a3-b329-295881f7509e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2126099503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2126099503
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3701009611
Short name T790
Test name
Test status
Simulation time 1404666231 ps
CPU time 283.54 seconds
Started Aug 18 04:51:38 PM PDT 24
Finished Aug 18 04:56:21 PM PDT 24
Peak memory 210444 kb
Host smart-d8751a4a-b321-4a0c-b126-f4f524879307
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3701009611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.3701009611
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.480062910
Short name T473
Test name
Test status
Simulation time 1785869231 ps
CPU time 58.38 seconds
Started Aug 18 04:51:36 PM PDT 24
Finished Aug 18 04:52:35 PM PDT 24
Peak memory 203972 kb
Host smart-dafa7ef9-5437-4851-9a3f-b2b5866755ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=480062910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese
t_error.480062910
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.3070364413
Short name T10
Test name
Test status
Simulation time 2603768208 ps
CPU time 6.81 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:51:41 PM PDT 24
Peak memory 201932 kb
Host smart-3671f36a-7e71-45bc-8308-0c8d6e976048
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3070364413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3070364413
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.125038541
Short name T142
Test name
Test status
Simulation time 364689159 ps
CPU time 8.82 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:28 PM PDT 24
Peak memory 201768 kb
Host smart-b248835d-1aae-483d-9c46-df5b9cc73839
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125038541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.125038541
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.44333171
Short name T525
Test name
Test status
Simulation time 20958388191 ps
CPU time 61.46 seconds
Started Aug 18 04:58:21 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 202932 kb
Host smart-85ec7e68-440c-4e68-b60f-51c8d2a7db7d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=44333171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow
_rsp.44333171
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2505978905
Short name T527
Test name
Test status
Simulation time 47797009 ps
CPU time 2.8 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:58:22 PM PDT 24
Peak memory 201936 kb
Host smart-d579e4ce-077b-4949-baa9-836f9475383a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2505978905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2505978905
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2676662575
Short name T407
Test name
Test status
Simulation time 2538571963 ps
CPU time 10.64 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:58:29 PM PDT 24
Peak memory 201932 kb
Host smart-cd2178f6-cce1-4acc-945e-4d8db4956ded
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676662575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2676662575
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.1476980728
Short name T642
Test name
Test status
Simulation time 129956593 ps
CPU time 4.83 seconds
Started Aug 18 04:58:21 PM PDT 24
Finished Aug 18 04:58:26 PM PDT 24
Peak memory 201728 kb
Host smart-90529377-eada-45a3-8013-9cf4038b503f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1476980728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1476980728
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2121046950
Short name T171
Test name
Test status
Simulation time 67393169900 ps
CPU time 133.86 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 05:00:32 PM PDT 24
Peak memory 201964 kb
Host smart-5097f1bd-f519-4f85-bbd8-f1a0ab11d156
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121046950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2121046950
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1138052984
Short name T703
Test name
Test status
Simulation time 24507695436 ps
CPU time 166.6 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 05:01:06 PM PDT 24
Peak memory 202004 kb
Host smart-2ef7df60-5540-40ae-8786-a6d21450d8ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1138052984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1138052984
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3702189580
Short name T55
Test name
Test status
Simulation time 30982253 ps
CPU time 3.02 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:22 PM PDT 24
Peak memory 201944 kb
Host smart-64f75c74-c973-4e20-bf11-b14ee8748b27
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702189580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3702189580
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.504962128
Short name T637
Test name
Test status
Simulation time 379672524 ps
CPU time 5.46 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 201940 kb
Host smart-5f06e9d3-5300-4aff-bb3f-b768cfd3e3fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=504962128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.504962128
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.2428039499
Short name T528
Test name
Test status
Simulation time 10422316 ps
CPU time 1.13 seconds
Started Aug 18 04:58:09 PM PDT 24
Finished Aug 18 04:58:11 PM PDT 24
Peak memory 201752 kb
Host smart-9d37387a-81b3-436c-8c6a-189b85a4f67a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2428039499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2428039499
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2600175347
Short name T591
Test name
Test status
Simulation time 2289477120 ps
CPU time 9.47 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:58:30 PM PDT 24
Peak memory 202124 kb
Host smart-64ac629b-fe48-40d7-b0fc-6c0184ff4ef9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600175347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2600175347
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3281641433
Short name T268
Test name
Test status
Simulation time 626097149 ps
CPU time 4.79 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 201956 kb
Host smart-7c9e3d3b-81be-423b-a543-c049f63a7a2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3281641433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3281641433
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.498856795
Short name T387
Test name
Test status
Simulation time 10801828 ps
CPU time 1.27 seconds
Started Aug 18 04:58:14 PM PDT 24
Finished Aug 18 04:58:15 PM PDT 24
Peak memory 201876 kb
Host smart-e2f6a8a7-35ec-43fc-8e10-7f6a0b5e7330
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498856795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.498856795
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2386442141
Short name T277
Test name
Test status
Simulation time 7792955269 ps
CPU time 99.45 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:59:58 PM PDT 24
Peak memory 204468 kb
Host smart-03e688dd-1b13-4f33-9a61-6fcd0aab334c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2386442141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2386442141
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3809206524
Short name T664
Test name
Test status
Simulation time 8189663660 ps
CPU time 26.84 seconds
Started Aug 18 04:58:17 PM PDT 24
Finished Aug 18 04:58:44 PM PDT 24
Peak memory 203000 kb
Host smart-97386cba-3b67-4564-afff-234b2178b9ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3809206524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3809206524
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.243031022
Short name T315
Test name
Test status
Simulation time 804432878 ps
CPU time 121.15 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 05:00:21 PM PDT 24
Peak memory 206968 kb
Host smart-9e54405e-a266-4d38-b90a-e4b121c88878
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=243031022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand
_reset.243031022
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.873858319
Short name T687
Test name
Test status
Simulation time 299673374 ps
CPU time 55.14 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 204720 kb
Host smart-5cfde862-86a4-4e4a-82db-c5bcda6ba990
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873858319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res
et_error.873858319
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.717813820
Short name T238
Test name
Test status
Simulation time 1257148249 ps
CPU time 9.6 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:58:28 PM PDT 24
Peak memory 201908 kb
Host smart-953096f6-0f1f-4e54-9fda-0c28e41b244a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=717813820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.717813820
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.4185359473
Short name T796
Test name
Test status
Simulation time 24783684 ps
CPU time 3.56 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 201796 kb
Host smart-f8c034b7-5195-4641-a17c-d53f5b916c26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4185359473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4185359473
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2384390829
Short name T195
Test name
Test status
Simulation time 141754685382 ps
CPU time 174.2 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 05:01:13 PM PDT 24
Peak memory 203036 kb
Host smart-73199ebd-2da1-41e7-a237-7abd7f8ea53d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2384390829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.2384390829
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1171591738
Short name T817
Test name
Test status
Simulation time 469692569 ps
CPU time 3.76 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:22 PM PDT 24
Peak memory 201936 kb
Host smart-4e8884f7-d63e-4e62-9afe-e439cdb4b563
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1171591738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1171591738
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.3823626248
Short name T587
Test name
Test status
Simulation time 1054928699 ps
CPU time 3.64 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 201936 kb
Host smart-90044628-9a15-4e5e-9d78-b0fec5e498b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3823626248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3823626248
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.875509174
Short name T98
Test name
Test status
Simulation time 535157639 ps
CPU time 5.89 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 201840 kb
Host smart-8d1a1d08-7a5b-4004-9244-a866f47bd4d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=875509174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.875509174
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3921583315
Short name T120
Test name
Test status
Simulation time 96835031591 ps
CPU time 177.6 seconds
Started Aug 18 04:58:21 PM PDT 24
Finished Aug 18 05:01:19 PM PDT 24
Peak memory 201896 kb
Host smart-589270a7-3a52-4d2e-8ee0-4de2da68f747
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3921583315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3921583315
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2368729610
Short name T182
Test name
Test status
Simulation time 41312052 ps
CPU time 4.04 seconds
Started Aug 18 04:58:17 PM PDT 24
Finished Aug 18 04:58:21 PM PDT 24
Peak memory 201856 kb
Host smart-de94e439-caf3-4e45-9a94-cfa1a04df1e4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368729610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2368729610
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.2568854002
Short name T154
Test name
Test status
Simulation time 132400392 ps
CPU time 3.39 seconds
Started Aug 18 04:58:22 PM PDT 24
Finished Aug 18 04:58:25 PM PDT 24
Peak memory 201788 kb
Host smart-b91490ff-d57a-475a-bc9c-614bc28df648
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2568854002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2568854002
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1206551388
Short name T234
Test name
Test status
Simulation time 30982099 ps
CPU time 1.14 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:20 PM PDT 24
Peak memory 201800 kb
Host smart-733ef9cf-ce5d-4ba5-9e80-b93061b603ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1206551388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1206551388
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3912853710
Short name T68
Test name
Test status
Simulation time 2593102871 ps
CPU time 9.69 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:58:28 PM PDT 24
Peak memory 201928 kb
Host smart-3f89793a-43d8-4ae2-839d-653608075017
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912853710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3912853710
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3746053814
Short name T88
Test name
Test status
Simulation time 1338551929 ps
CPU time 10.12 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:58:30 PM PDT 24
Peak memory 201860 kb
Host smart-3e9a0109-b865-4c0a-8f34-46a7f2195a0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3746053814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3746053814
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.377148375
Short name T643
Test name
Test status
Simulation time 11239976 ps
CPU time 1.24 seconds
Started Aug 18 04:58:17 PM PDT 24
Finished Aug 18 04:58:19 PM PDT 24
Peak memory 201860 kb
Host smart-06e8b61c-a6d2-479e-98e8-1785b2f5cd79
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377148375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.377148375
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.3570786744
Short name T227
Test name
Test status
Simulation time 265106172 ps
CPU time 23.85 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:58:44 PM PDT 24
Peak memory 202908 kb
Host smart-f30e12fd-7bac-43a8-99cd-4a0b0e14259f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3570786744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3570786744
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3205558742
Short name T560
Test name
Test status
Simulation time 700197486 ps
CPU time 8.82 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:28 PM PDT 24
Peak memory 201844 kb
Host smart-4e4aedb0-d092-4ccf-bcd4-5f864daa71da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3205558742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3205558742
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.508512263
Short name T52
Test name
Test status
Simulation time 1287785632 ps
CPU time 158.57 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 05:00:57 PM PDT 24
Peak memory 204464 kb
Host smart-94352a56-e0b0-46ab-bdb1-4a1f473b291f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=508512263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand
_reset.508512263
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2970875010
Short name T853
Test name
Test status
Simulation time 271243768 ps
CPU time 23.97 seconds
Started Aug 18 04:58:17 PM PDT 24
Finished Aug 18 04:58:41 PM PDT 24
Peak memory 203480 kb
Host smart-e54057f9-2419-44a7-a406-468ae44d85e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2970875010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.2970875010
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2740300184
Short name T776
Test name
Test status
Simulation time 850159156 ps
CPU time 7.11 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:58:27 PM PDT 24
Peak memory 202120 kb
Host smart-ef9b147f-dd0a-413f-b894-39200fdcd686
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2740300184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2740300184
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3536305648
Short name T164
Test name
Test status
Simulation time 963329456 ps
CPU time 14.16 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 201940 kb
Host smart-c72306b8-5534-426d-8c27-7fd31d3e8ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3536305648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3536305648
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1231122234
Short name T147
Test name
Test status
Simulation time 8748081219 ps
CPU time 45.27 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 202020 kb
Host smart-191b5991-f31e-4da7-80e2-bdeb3b4029f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1231122234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.1231122234
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3631444538
Short name T151
Test name
Test status
Simulation time 40104111 ps
CPU time 3.02 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 201856 kb
Host smart-00ed7db4-4810-4dfa-944c-740de7a3d42c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3631444538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3631444538
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3912789073
Short name T457
Test name
Test status
Simulation time 644041130 ps
CPU time 3.92 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 201872 kb
Host smart-8ad13730-299b-413f-9346-ec26b5195986
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3912789073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3912789073
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.1383851443
Short name T240
Test name
Test status
Simulation time 234823187 ps
CPU time 4.54 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 201816 kb
Host smart-93db08ec-de1f-4847-bf1e-515cc98332b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1383851443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1383851443
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3828680339
Short name T609
Test name
Test status
Simulation time 19178896388 ps
CPU time 76.83 seconds
Started Aug 18 04:58:20 PM PDT 24
Finished Aug 18 04:59:37 PM PDT 24
Peak memory 201944 kb
Host smart-1da9e2c3-dd1e-4b42-9260-b93dcab9776f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828680339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3828680339
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1671543305
Short name T266
Test name
Test status
Simulation time 41338327657 ps
CPU time 87.71 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:59:47 PM PDT 24
Peak memory 201960 kb
Host smart-9ddc4d11-b2b0-43cd-a6f0-166273522d98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1671543305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1671543305
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2360127802
Short name T386
Test name
Test status
Simulation time 467224970 ps
CPU time 8.79 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:58:27 PM PDT 24
Peak memory 201824 kb
Host smart-98d97c8a-fa37-4bea-b802-1d8932140c82
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360127802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2360127802
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2234203214
Short name T76
Test name
Test status
Simulation time 1035810161 ps
CPU time 5.58 seconds
Started Aug 18 04:58:18 PM PDT 24
Finished Aug 18 04:58:24 PM PDT 24
Peak memory 201936 kb
Host smart-9685fc21-8cfe-49a1-8e32-873dda9a3f0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2234203214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2234203214
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.930641149
Short name T271
Test name
Test status
Simulation time 15005040 ps
CPU time 1.34 seconds
Started Aug 18 04:58:17 PM PDT 24
Finished Aug 18 04:58:19 PM PDT 24
Peak memory 201768 kb
Host smart-2e34ebad-901d-4a70-860e-6ff23c7a587d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=930641149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.930641149
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.4084950978
Short name T749
Test name
Test status
Simulation time 2368869000 ps
CPU time 6.66 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:26 PM PDT 24
Peak memory 201876 kb
Host smart-bf263a6e-85a0-4450-92e0-3f6440f8538e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084950978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4084950978
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3391867076
Short name T530
Test name
Test status
Simulation time 3199522810 ps
CPU time 7.78 seconds
Started Aug 18 04:58:19 PM PDT 24
Finished Aug 18 04:58:27 PM PDT 24
Peak memory 201988 kb
Host smart-d3c89b21-fc3e-4a81-9cb7-301d4d8065be
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3391867076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3391867076
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3695093353
Short name T575
Test name
Test status
Simulation time 9094823 ps
CPU time 1.16 seconds
Started Aug 18 04:58:21 PM PDT 24
Finished Aug 18 04:58:23 PM PDT 24
Peak memory 201800 kb
Host smart-fd2d866b-4564-4279-9c65-a150a940bdf8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695093353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3695093353
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2717638497
Short name T282
Test name
Test status
Simulation time 44118527 ps
CPU time 4.52 seconds
Started Aug 18 04:58:27 PM PDT 24
Finished Aug 18 04:58:32 PM PDT 24
Peak memory 201824 kb
Host smart-84c09248-8973-4fa8-a1f2-62cd268f39ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2717638497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2717638497
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.661380936
Short name T881
Test name
Test status
Simulation time 1239015917 ps
CPU time 22.48 seconds
Started Aug 18 04:58:25 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 201928 kb
Host smart-5ceb8ca2-8f43-4db5-a149-b33cb7d8858c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=661380936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.661380936
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2806852172
Short name T405
Test name
Test status
Simulation time 2114572660 ps
CPU time 42.3 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 204064 kb
Host smart-47994ab1-c19e-45a8-b669-063c471139aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2806852172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.2806852172
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3618372678
Short name T214
Test name
Test status
Simulation time 248826799 ps
CPU time 19.27 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 202964 kb
Host smart-d8648a32-f5c5-4f42-b7e3-394b615eb7a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3618372678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.3618372678
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3100704252
Short name T225
Test name
Test status
Simulation time 757070412 ps
CPU time 10.31 seconds
Started Aug 18 04:58:21 PM PDT 24
Finished Aug 18 04:58:31 PM PDT 24
Peak memory 201840 kb
Host smart-a20271d6-4994-4a27-a4a5-c2119d4ca601
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3100704252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3100704252
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1334166819
Short name T333
Test name
Test status
Simulation time 14564247 ps
CPU time 2.63 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:32 PM PDT 24
Peak memory 201852 kb
Host smart-ae30a6f0-1e86-4be7-8e7b-bc24c5a3295d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1334166819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1334166819
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1748286772
Short name T840
Test name
Test status
Simulation time 16324011760 ps
CPU time 110.91 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 05:00:21 PM PDT 24
Peak memory 201944 kb
Host smart-c789a029-a27f-4c55-9764-10eafaedaa20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1748286772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.1748286772
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1333180371
Short name T751
Test name
Test status
Simulation time 2082912738 ps
CPU time 7.56 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 201964 kb
Host smart-e0df9470-7c97-4254-9bb4-f9712ff2973c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1333180371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1333180371
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.3967819297
Short name T298
Test name
Test status
Simulation time 89650520 ps
CPU time 4.06 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:34 PM PDT 24
Peak memory 201908 kb
Host smart-e75023b7-f727-4ae4-a5b5-a3093feb5739
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3967819297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3967819297
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.368238865
Short name T767
Test name
Test status
Simulation time 736673726 ps
CPU time 11.35 seconds
Started Aug 18 04:58:26 PM PDT 24
Finished Aug 18 04:58:38 PM PDT 24
Peak memory 201912 kb
Host smart-15132dcc-a839-4d47-83ee-86f152cad68a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=368238865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.368238865
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2949588400
Short name T82
Test name
Test status
Simulation time 182553178543 ps
CPU time 145.2 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 05:00:54 PM PDT 24
Peak memory 201948 kb
Host smart-f47d5802-6cc0-435d-8618-298f69bcfbfe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949588400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2949588400
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3259761881
Short name T779
Test name
Test status
Simulation time 3326674719 ps
CPU time 23.33 seconds
Started Aug 18 04:58:35 PM PDT 24
Finished Aug 18 04:58:58 PM PDT 24
Peak memory 202004 kb
Host smart-0b398de2-596a-483c-82d2-2d3540ee3c11
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3259761881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3259761881
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2465807460
Short name T623
Test name
Test status
Simulation time 134012082 ps
CPU time 7.78 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 201940 kb
Host smart-b3346c44-2a02-4964-a9d4-a3072c2c5fbe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465807460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2465807460
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.3857616717
Short name T354
Test name
Test status
Simulation time 339213473 ps
CPU time 4.22 seconds
Started Aug 18 04:58:27 PM PDT 24
Finished Aug 18 04:58:31 PM PDT 24
Peak memory 201892 kb
Host smart-f5cb6d5d-58e8-4581-a29a-e9df15ed464d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3857616717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3857616717
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.1411868940
Short name T552
Test name
Test status
Simulation time 47845600 ps
CPU time 1.57 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:30 PM PDT 24
Peak memory 201828 kb
Host smart-425568e0-6a36-4599-8aa3-c392192743a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1411868940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1411868940
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3101865574
Short name T36
Test name
Test status
Simulation time 12388185400 ps
CPU time 8.15 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:37 PM PDT 24
Peak memory 201856 kb
Host smart-5b278ec5-0d62-484a-8492-3b13f4cdb30b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101865574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3101865574
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1897568422
Short name T479
Test name
Test status
Simulation time 3063016627 ps
CPU time 14.33 seconds
Started Aug 18 04:58:31 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 201928 kb
Host smart-eee1a133-0cc2-4a6b-8647-f2a078d062b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1897568422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1897568422
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.204892508
Short name T285
Test name
Test status
Simulation time 10582230 ps
CPU time 1.28 seconds
Started Aug 18 04:58:27 PM PDT 24
Finished Aug 18 04:58:29 PM PDT 24
Peak memory 201956 kb
Host smart-75e6fbdd-aa0a-4a79-8c7f-6371020f9166
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204892508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.204892508
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2952376518
Short name T49
Test name
Test status
Simulation time 2001721423 ps
CPU time 17.1 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:47 PM PDT 24
Peak memory 201976 kb
Host smart-f22d8da8-10e6-4e68-834e-df10b92252db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2952376518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2952376518
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1892359380
Short name T150
Test name
Test status
Simulation time 14391176583 ps
CPU time 44.27 seconds
Started Aug 18 04:58:26 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 201884 kb
Host smart-ea9c621f-5b80-42ac-98d4-296f234556fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1892359380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1892359380
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3971074385
Short name T296
Test name
Test status
Simulation time 280191725 ps
CPU time 44.97 seconds
Started Aug 18 04:58:35 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 204168 kb
Host smart-d62a149b-77ff-4e16-9513-edff34227538
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3971074385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.3971074385
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.343460197
Short name T722
Test name
Test status
Simulation time 574334183 ps
CPU time 42.03 seconds
Started Aug 18 04:58:31 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 203944 kb
Host smart-4704c94b-a352-4754-b2ac-13297f29ad79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=343460197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res
et_error.343460197
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.4118632526
Short name T362
Test name
Test status
Simulation time 72326817 ps
CPU time 5.41 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:35 PM PDT 24
Peak memory 201900 kb
Host smart-0f2d8c9a-3f11-42f2-b3e0-415fd7bbf0c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4118632526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4118632526
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2628645200
Short name T311
Test name
Test status
Simulation time 33747369 ps
CPU time 5.45 seconds
Started Aug 18 04:58:27 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 201936 kb
Host smart-2cfd9d69-536b-45c1-bced-6d0c3c386be6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2628645200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2628645200
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2213867447
Short name T819
Test name
Test status
Simulation time 54268194280 ps
CPU time 312.81 seconds
Started Aug 18 04:58:35 PM PDT 24
Finished Aug 18 05:03:48 PM PDT 24
Peak memory 203052 kb
Host smart-bc399c5f-e992-4b7e-82c2-c289bb22403c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2213867447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.2213867447
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2721264645
Short name T269
Test name
Test status
Simulation time 796299437 ps
CPU time 9.24 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:38 PM PDT 24
Peak memory 201952 kb
Host smart-0793ba7f-52ad-4245-92bf-22ad931bdbb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2721264645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2721264645
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.279729711
Short name T265
Test name
Test status
Simulation time 67669104 ps
CPU time 1.64 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:32 PM PDT 24
Peak memory 201852 kb
Host smart-e6d7f25a-de91-4ac9-92ec-cd1ea97f97bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=279729711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.279729711
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.448192147
Short name T606
Test name
Test status
Simulation time 257027978 ps
CPU time 3.7 seconds
Started Aug 18 04:58:32 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 201884 kb
Host smart-9934f69a-b4ce-4f2c-9873-b8096cb46cf3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=448192147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.448192147
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2289480620
Short name T788
Test name
Test status
Simulation time 46485199250 ps
CPU time 128.54 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 05:00:37 PM PDT 24
Peak memory 201876 kb
Host smart-c8b1920a-8587-4f82-8575-d8f79b99fae4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289480620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2289480620
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2088843478
Short name T636
Test name
Test status
Simulation time 17907708256 ps
CPU time 82.88 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:59:53 PM PDT 24
Peak memory 201932 kb
Host smart-239e0cb2-06ab-4d3b-9c15-b50e9a432fe4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2088843478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2088843478
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3763808391
Short name T802
Test name
Test status
Simulation time 60038500 ps
CPU time 3.79 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:34 PM PDT 24
Peak memory 201948 kb
Host smart-56118cb9-10e6-426b-93ee-6da3bd0f54a8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763808391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3763808391
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.1868097597
Short name T244
Test name
Test status
Simulation time 1142709451 ps
CPU time 4.75 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 201940 kb
Host smart-249d8cff-9df9-4117-9811-11b0279aed38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1868097597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1868097597
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.3502576996
Short name T423
Test name
Test status
Simulation time 12997918 ps
CPU time 1.36 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:29 PM PDT 24
Peak memory 201764 kb
Host smart-022f63cd-10f1-4ca4-afac-5fca48316422
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3502576996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3502576996
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.703649946
Short name T247
Test name
Test status
Simulation time 1828092329 ps
CPU time 5.98 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 201792 kb
Host smart-e2e14dbb-9b60-47c7-8c6d-0910f347a7b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=703649946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.703649946
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1174335510
Short name T352
Test name
Test status
Simulation time 2080600774 ps
CPU time 7.46 seconds
Started Aug 18 04:58:31 PM PDT 24
Finished Aug 18 04:58:38 PM PDT 24
Peak memory 201956 kb
Host smart-be21d53f-a1b9-44cb-9197-0d8acd13190c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1174335510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1174335510
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1980006712
Short name T368
Test name
Test status
Simulation time 10630626 ps
CPU time 1.02 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:31 PM PDT 24
Peak memory 201928 kb
Host smart-73fe0c86-9947-4c18-9335-44a8c02f7c5d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980006712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1980006712
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.4047282892
Short name T414
Test name
Test status
Simulation time 654244667 ps
CPU time 19.22 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 201944 kb
Host smart-4968a6d2-6625-4347-b29a-8345d4ccb7df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4047282892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4047282892
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1295557345
Short name T882
Test name
Test status
Simulation time 3662329090 ps
CPU time 33.74 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 201808 kb
Host smart-9fb468c9-bf4c-4334-b2dd-912e294c14e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1295557345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1295557345
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.824341039
Short name T533
Test name
Test status
Simulation time 5913148684 ps
CPU time 119.42 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 05:00:29 PM PDT 24
Peak memory 204584 kb
Host smart-e3ba0f09-9860-43ab-a1f2-aebd55037d2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=824341039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand
_reset.824341039
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3681543034
Short name T252
Test name
Test status
Simulation time 4202789556 ps
CPU time 129.43 seconds
Started Aug 18 04:58:35 PM PDT 24
Finished Aug 18 05:00:45 PM PDT 24
Peak memory 206592 kb
Host smart-e9b3ecc5-d84b-4493-a607-cd29430a37e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3681543034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.3681543034
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.954538470
Short name T90
Test name
Test status
Simulation time 44154097 ps
CPU time 2.66 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 201780 kb
Host smart-dd9831a3-09a1-4cc1-82c9-1e1303ced4b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=954538470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.954538470
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.4161610204
Short name T878
Test name
Test status
Simulation time 1901901821 ps
CPU time 19.87 seconds
Started Aug 18 04:58:36 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 201940 kb
Host smart-1f6b93a6-aa64-410b-ac60-43acad4c8bc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4161610204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.4161610204
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.389712393
Short name T739
Test name
Test status
Simulation time 49694388714 ps
CPU time 117.81 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 05:00:27 PM PDT 24
Peak memory 201936 kb
Host smart-33b3beb1-ce25-49bf-8f45-a388e0b78314
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=389712393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo
w_rsp.389712393
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1459495950
Short name T302
Test name
Test status
Simulation time 1125520334 ps
CPU time 8.79 seconds
Started Aug 18 04:58:27 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 201856 kb
Host smart-f9f6195b-3b0a-4d38-a959-a92e36d75ce3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1459495950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1459495950
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.3493245583
Short name T894
Test name
Test status
Simulation time 50278219 ps
CPU time 2.17 seconds
Started Aug 18 04:58:31 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 201960 kb
Host smart-d4bee3a3-2ad1-446d-8110-49b80bfec50d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3493245583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3493245583
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.3608364832
Short name T514
Test name
Test status
Simulation time 211262858 ps
CPU time 5.87 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:35 PM PDT 24
Peak memory 201808 kb
Host smart-7ae49248-9b74-44c3-9b83-af48481771cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3608364832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3608364832
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.3600106844
Short name T344
Test name
Test status
Simulation time 25810854626 ps
CPU time 78.3 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:59:48 PM PDT 24
Peak memory 201964 kb
Host smart-784bf9be-67dc-401f-affe-3f864d596407
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600106844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3600106844
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1435058728
Short name T826
Test name
Test status
Simulation time 62265979219 ps
CPU time 152.33 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 05:01:03 PM PDT 24
Peak memory 201904 kb
Host smart-3c613561-d166-4075-8537-ed0e921efe97
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1435058728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1435058728
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3165745473
Short name T778
Test name
Test status
Simulation time 25868443 ps
CPU time 2.63 seconds
Started Aug 18 04:58:36 PM PDT 24
Finished Aug 18 04:58:38 PM PDT 24
Peak memory 201944 kb
Host smart-0fdfe9b3-ca72-4009-a55b-f2651a848792
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165745473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3165745473
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.131147162
Short name T443
Test name
Test status
Simulation time 683738320 ps
CPU time 9.49 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:39 PM PDT 24
Peak memory 201836 kb
Host smart-47300c14-a1f8-4d5c-9a8c-7d889e159da7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=131147162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.131147162
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.13876215
Short name T145
Test name
Test status
Simulation time 51285226 ps
CPU time 1.42 seconds
Started Aug 18 04:58:31 PM PDT 24
Finished Aug 18 04:58:33 PM PDT 24
Peak memory 201880 kb
Host smart-b9d9b789-0fa0-47bb-8c06-2e1fb3804e95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13876215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.13876215
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2130325491
Short name T353
Test name
Test status
Simulation time 5679582876 ps
CPU time 8.9 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:38 PM PDT 24
Peak memory 201948 kb
Host smart-146c9904-cc74-4eaa-bcbf-8bcde7216338
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130325491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2130325491
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1992898425
Short name T613
Test name
Test status
Simulation time 1375107788 ps
CPU time 5.89 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:35 PM PDT 24
Peak memory 201756 kb
Host smart-81fca187-8136-4410-b7f5-fd09b9caddb0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1992898425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1992898425
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1636218806
Short name T420
Test name
Test status
Simulation time 11257359 ps
CPU time 1.13 seconds
Started Aug 18 04:58:27 PM PDT 24
Finished Aug 18 04:58:28 PM PDT 24
Peak memory 201940 kb
Host smart-7752d8e9-4e22-462c-8269-a510a119e105
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636218806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1636218806
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2913618494
Short name T159
Test name
Test status
Simulation time 203738089 ps
CPU time 10.72 seconds
Started Aug 18 04:58:29 PM PDT 24
Finished Aug 18 04:58:40 PM PDT 24
Peak memory 201748 kb
Host smart-851fa069-97e6-411b-bce1-e192d4c6bedc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2913618494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2913618494
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1058535148
Short name T662
Test name
Test status
Simulation time 154559972 ps
CPU time 18.76 seconds
Started Aug 18 04:58:35 PM PDT 24
Finished Aug 18 04:58:54 PM PDT 24
Peak memory 202984 kb
Host smart-9f97a8b2-3ffd-435d-bf01-07cd17dc14c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1058535148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1058535148
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2309198880
Short name T879
Test name
Test status
Simulation time 949338694 ps
CPU time 67.91 seconds
Started Aug 18 04:58:31 PM PDT 24
Finished Aug 18 04:59:39 PM PDT 24
Peak memory 205392 kb
Host smart-a4ce0a19-9c8f-4b89-a837-a79c41d1fd78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2309198880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.2309198880
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1726674628
Short name T834
Test name
Test status
Simulation time 94484299 ps
CPU time 3.8 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:34 PM PDT 24
Peak memory 201844 kb
Host smart-2a9bfece-93ef-4f74-bed9-c7ba02155d87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1726674628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1726674628
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2247329574
Short name T374
Test name
Test status
Simulation time 26341564 ps
CPU time 5.17 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 201940 kb
Host smart-d2e7a77d-0c2e-400d-819a-dc71e860ab13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2247329574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2247329574
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2508906239
Short name T827
Test name
Test status
Simulation time 47623655714 ps
CPU time 171.02 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 05:01:35 PM PDT 24
Peak memory 202932 kb
Host smart-0d6568f8-2007-4b18-8509-e845f0349999
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2508906239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.2508906239
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1115496870
Short name T670
Test name
Test status
Simulation time 27802645 ps
CPU time 2.37 seconds
Started Aug 18 04:58:40 PM PDT 24
Finished Aug 18 04:58:42 PM PDT 24
Peak memory 201952 kb
Host smart-294c903a-b89f-478d-ba0f-d7b261ccd9a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1115496870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1115496870
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.3455289895
Short name T470
Test name
Test status
Simulation time 61401864 ps
CPU time 6.69 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 04:58:50 PM PDT 24
Peak memory 201936 kb
Host smart-0aa50c6c-628d-413c-9795-76de3875c7a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3455289895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3455289895
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.4178989961
Short name T97
Test name
Test status
Simulation time 289604870 ps
CPU time 3.38 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:44 PM PDT 24
Peak memory 201776 kb
Host smart-29482585-5ba3-4fa1-9da7-5fab69c238aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178989961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.4178989961
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3318326351
Short name T339
Test name
Test status
Simulation time 49739526172 ps
CPU time 111.48 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 05:00:35 PM PDT 24
Peak memory 201968 kb
Host smart-fb981054-c2f9-4057-8610-f6116529f2d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318326351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3318326351
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1535882818
Short name T137
Test name
Test status
Simulation time 40878004441 ps
CPU time 128.79 seconds
Started Aug 18 04:58:39 PM PDT 24
Finished Aug 18 05:00:48 PM PDT 24
Peak memory 201928 kb
Host smart-5a0b6ec3-d452-43c4-8421-ee19ab6af69c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1535882818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1535882818
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2873062702
Short name T221
Test name
Test status
Simulation time 63278515 ps
CPU time 2.32 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:45 PM PDT 24
Peak memory 201944 kb
Host smart-77c00020-ac02-4435-beaa-34ad91ada7b7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873062702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2873062702
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.59762515
Short name T519
Test name
Test status
Simulation time 57680083 ps
CPU time 4.02 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 201852 kb
Host smart-0830cc43-39d7-4d21-80e3-039b584f3dae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59762515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.59762515
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.714042487
Short name T598
Test name
Test status
Simulation time 78999450 ps
CPU time 1.38 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:32 PM PDT 24
Peak memory 201884 kb
Host smart-dc5d4326-9eca-40e7-8057-6f68e0181916
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=714042487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.714042487
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.472209687
Short name T350
Test name
Test status
Simulation time 4355048531 ps
CPU time 6.94 seconds
Started Aug 18 04:58:30 PM PDT 24
Finished Aug 18 04:58:37 PM PDT 24
Peak memory 201824 kb
Host smart-3383c58e-6fe8-46d9-8f97-900e1efceaab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=472209687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.472209687
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2680027656
Short name T502
Test name
Test status
Simulation time 3728411278 ps
CPU time 10 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 201976 kb
Host smart-9613f579-6bcf-4a3e-a63e-9c1862e760d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2680027656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2680027656
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1461426981
Short name T647
Test name
Test status
Simulation time 10057720 ps
CPU time 1.11 seconds
Started Aug 18 04:58:28 PM PDT 24
Finished Aug 18 04:58:30 PM PDT 24
Peak memory 201856 kb
Host smart-9417a67f-7c8e-4552-8094-74bf10a7216c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461426981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1461426981
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.116976554
Short name T537
Test name
Test status
Simulation time 125106400 ps
CPU time 12.58 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 04:58:57 PM PDT 24
Peak memory 201944 kb
Host smart-71ed3893-6aed-4319-b25a-9133811b58d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=116976554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.116976554
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2726384328
Short name T740
Test name
Test status
Simulation time 73417589 ps
CPU time 7.66 seconds
Started Aug 18 04:58:45 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 201936 kb
Host smart-79006023-1009-4613-888b-d164ae8fc303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2726384328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2726384328
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2185769582
Short name T103
Test name
Test status
Simulation time 4037643289 ps
CPU time 127.62 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 05:00:49 PM PDT 24
Peak memory 204568 kb
Host smart-ac240099-2d0a-4bea-b2a2-046483dbf7a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2185769582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran
d_reset.2185769582
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3825583881
Short name T486
Test name
Test status
Simulation time 573758727 ps
CPU time 60.96 seconds
Started Aug 18 04:58:45 PM PDT 24
Finished Aug 18 04:59:46 PM PDT 24
Peak memory 204544 kb
Host smart-97be0b89-9515-4448-85ea-aa9889c91d0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3825583881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.3825583881
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.452715241
Short name T797
Test name
Test status
Simulation time 169233714 ps
CPU time 2.09 seconds
Started Aug 18 04:58:44 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 201956 kb
Host smart-d6602cb6-86c4-47f8-85b3-190dd2031fa7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=452715241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.452715241
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3116288656
Short name T657
Test name
Test status
Simulation time 40247270 ps
CPU time 5.78 seconds
Started Aug 18 04:58:40 PM PDT 24
Finished Aug 18 04:58:46 PM PDT 24
Peak memory 201812 kb
Host smart-0be40047-f0c5-4d5d-a349-75b4fd44062c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3116288656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3116288656
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.609719093
Short name T200
Test name
Test status
Simulation time 70457862475 ps
CPU time 306.34 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 05:03:48 PM PDT 24
Peak memory 203588 kb
Host smart-ac884c58-1ad0-468c-980e-bcb099d8c531
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=609719093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo
w_rsp.609719093
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.275932752
Short name T524
Test name
Test status
Simulation time 42746597 ps
CPU time 3.22 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:44 PM PDT 24
Peak memory 201808 kb
Host smart-3652c99b-35e4-44ac-9b43-20a6a8312126
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=275932752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.275932752
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2515742124
Short name T377
Test name
Test status
Simulation time 2176440290 ps
CPU time 14.95 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:57 PM PDT 24
Peak memory 201916 kb
Host smart-e1fb6bb7-e527-44cb-bbd8-be68a6092001
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2515742124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2515742124
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.1514563905
Short name T540
Test name
Test status
Simulation time 1203694729 ps
CPU time 15.43 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 201896 kb
Host smart-c167bd49-b98a-4a01-a89c-8729e7636d4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1514563905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1514563905
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1959363528
Short name T543
Test name
Test status
Simulation time 17605656205 ps
CPU time 73.2 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 04:59:56 PM PDT 24
Peak memory 201828 kb
Host smart-c90c7a10-e4a5-4ccd-b7f6-005d1cb8e07b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959363528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1959363528
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1446796876
Short name T701
Test name
Test status
Simulation time 60179313445 ps
CPU time 104.14 seconds
Started Aug 18 04:58:44 PM PDT 24
Finished Aug 18 05:00:28 PM PDT 24
Peak memory 202016 kb
Host smart-c8a8e8c3-a189-4a3a-8534-c942f409d600
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1446796876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1446796876
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.830062842
Short name T146
Test name
Test status
Simulation time 147022224 ps
CPU time 8.68 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:50 PM PDT 24
Peak memory 201856 kb
Host smart-3d1e3638-e1b9-4fd4-a24b-c8c73304ef7d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830062842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.830062842
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.1545562967
Short name T318
Test name
Test status
Simulation time 40524279 ps
CPU time 3.68 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:45 PM PDT 24
Peak memory 201952 kb
Host smart-5f448661-2417-43ee-9459-d5cc771f1236
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1545562967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1545562967
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.1437984244
Short name T622
Test name
Test status
Simulation time 28683640 ps
CPU time 1.04 seconds
Started Aug 18 04:58:40 PM PDT 24
Finished Aug 18 04:58:41 PM PDT 24
Peak memory 201808 kb
Host smart-273da447-24f0-426d-9ade-52415f34b134
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1437984244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1437984244
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.4050643321
Short name T517
Test name
Test status
Simulation time 4490520576 ps
CPU time 8.62 seconds
Started Aug 18 04:58:39 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 201948 kb
Host smart-4806396f-9e4d-44c8-ba82-c61d46fb41cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050643321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.4050643321
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.941375638
Short name T691
Test name
Test status
Simulation time 2129629600 ps
CPU time 11.02 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:52 PM PDT 24
Peak memory 201912 kb
Host smart-4e869622-252c-4ccd-a16e-a9e5c7accb82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=941375638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.941375638
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.9049507
Short name T487
Test name
Test status
Simulation time 14679521 ps
CPU time 1.06 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:42 PM PDT 24
Peak memory 201840 kb
Host smart-8a461ba0-78f9-4458-9afa-242c5b9e1575
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9049507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.9049507
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1677785823
Short name T782
Test name
Test status
Simulation time 372811795 ps
CPU time 37.6 seconds
Started Aug 18 04:58:39 PM PDT 24
Finished Aug 18 04:59:17 PM PDT 24
Peak memory 201956 kb
Host smart-66a44521-46cf-483c-8f83-e649e4349405
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1677785823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1677785823
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3935721163
Short name T794
Test name
Test status
Simulation time 11558321421 ps
CPU time 107.26 seconds
Started Aug 18 04:58:45 PM PDT 24
Finished Aug 18 05:00:32 PM PDT 24
Peak memory 202012 kb
Host smart-538e4bc4-98c5-4c93-ac92-659f0f29f673
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3935721163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3935721163
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2562057743
Short name T7
Test name
Test status
Simulation time 953905777 ps
CPU time 62.09 seconds
Started Aug 18 04:58:43 PM PDT 24
Finished Aug 18 04:59:45 PM PDT 24
Peak memory 203996 kb
Host smart-b10ca711-b90e-476a-b472-de529956d79e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2562057743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.2562057743
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3354688364
Short name T330
Test name
Test status
Simulation time 241239976 ps
CPU time 27.43 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:59:09 PM PDT 24
Peak memory 203104 kb
Host smart-ed960a25-8453-4ead-8c0b-024abdce4bb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3354688364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.3354688364
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.379670604
Short name T760
Test name
Test status
Simulation time 1264782913 ps
CPU time 9.33 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:51 PM PDT 24
Peak memory 201864 kb
Host smart-d873442d-6d71-4465-b138-c9b3bc4a2fbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=379670604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.379670604
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1350628924
Short name T734
Test name
Test status
Simulation time 69465452 ps
CPU time 11.23 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 201856 kb
Host smart-2b6d9c2b-099c-44f7-b23a-ae92971c89db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1350628924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1350628924
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3205747274
Short name T203
Test name
Test status
Simulation time 41368817318 ps
CPU time 217.12 seconds
Started Aug 18 04:58:54 PM PDT 24
Finished Aug 18 05:02:31 PM PDT 24
Peak memory 202956 kb
Host smart-5e152723-5c0a-4621-a7aa-267316bc6ba6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3205747274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.3205747274
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2728365439
Short name T391
Test name
Test status
Simulation time 815884946 ps
CPU time 7.68 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:59:00 PM PDT 24
Peak memory 201932 kb
Host smart-62a1167f-9875-4d28-bcfa-bd575c9fad45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2728365439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2728365439
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.313231210
Short name T599
Test name
Test status
Simulation time 1876406305 ps
CPU time 11.1 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 201908 kb
Host smart-97d17ec7-68b6-48fe-98f8-17bcee7377eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=313231210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.313231210
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.3717648550
Short name T865
Test name
Test status
Simulation time 876920851 ps
CPU time 14.87 seconds
Started Aug 18 04:58:41 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 201896 kb
Host smart-0cefac6c-7dec-490d-a70d-99d40b890fc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3717648550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3717648550
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2912780620
Short name T121
Test name
Test status
Simulation time 35100136350 ps
CPU time 158.02 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 05:01:31 PM PDT 24
Peak memory 201936 kb
Host smart-c4cac0e4-8ddc-48cb-8525-6e3f2e062dcc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912780620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2912780620
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.327669795
Short name T115
Test name
Test status
Simulation time 15665305847 ps
CPU time 77.37 seconds
Started Aug 18 04:58:50 PM PDT 24
Finished Aug 18 05:00:07 PM PDT 24
Peak memory 201984 kb
Host smart-d074a96d-e20e-413a-a8d8-1f0f45c0d3a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=327669795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.327669795
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.728696574
Short name T174
Test name
Test status
Simulation time 75753628 ps
CPU time 10.86 seconds
Started Aug 18 04:58:50 PM PDT 24
Finished Aug 18 04:59:01 PM PDT 24
Peak memory 201848 kb
Host smart-ffbbf8cb-1724-4cd7-9b7d-807b28267f27
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728696574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.728696574
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.375013572
Short name T804
Test name
Test status
Simulation time 923079394 ps
CPU time 3.9 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 201948 kb
Host smart-425bb674-46d5-4b51-8c95-3746f398ed29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=375013572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.375013572
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.3140325744
Short name T230
Test name
Test status
Simulation time 88096150 ps
CPU time 1.61 seconds
Started Aug 18 04:58:40 PM PDT 24
Finished Aug 18 04:58:41 PM PDT 24
Peak memory 201804 kb
Host smart-2a4511e8-88a4-440b-8bd7-49dd7c58dcdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3140325744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3140325744
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1305979901
Short name T883
Test name
Test status
Simulation time 2291822067 ps
CPU time 11.35 seconds
Started Aug 18 04:58:42 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 201956 kb
Host smart-d9d76d0b-4bc5-435a-9416-c859589ab58e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305979901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1305979901
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1027365555
Short name T399
Test name
Test status
Simulation time 1639701043 ps
CPU time 9.75 seconds
Started Aug 18 04:58:44 PM PDT 24
Finished Aug 18 04:58:54 PM PDT 24
Peak memory 201952 kb
Host smart-cac8ce8b-a940-46c8-bf1e-b24000c462d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1027365555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1027365555
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2986964067
Short name T276
Test name
Test status
Simulation time 36366482 ps
CPU time 1.29 seconds
Started Aug 18 04:58:40 PM PDT 24
Finished Aug 18 04:58:41 PM PDT 24
Peak memory 201844 kb
Host smart-d80e6649-2a74-471d-b91b-0e0463f948ee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986964067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2986964067
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1284691527
Short name T310
Test name
Test status
Simulation time 979003903 ps
CPU time 20.04 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 203028 kb
Host smart-0023a5a4-cc11-4477-80a9-d84177ef3255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1284691527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1284691527
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2706132062
Short name T867
Test name
Test status
Simulation time 2035820381 ps
CPU time 30.41 seconds
Started Aug 18 04:58:50 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 201956 kb
Host smart-e77719ba-5e83-41f3-95d2-4ee562177935
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2706132062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2706132062
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2605656207
Short name T626
Test name
Test status
Simulation time 455872450 ps
CPU time 35.7 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:59:30 PM PDT 24
Peak memory 204128 kb
Host smart-c2d20dc0-b75e-43e5-a3db-3a947e9a0c05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2605656207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.2605656207
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3701929692
Short name T824
Test name
Test status
Simulation time 3245068279 ps
CPU time 49.56 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:59:42 PM PDT 24
Peak memory 203960 kb
Host smart-04839e9f-2fec-4e78-b35f-0468fa1768ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3701929692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.3701929692
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.477390358
Short name T175
Test name
Test status
Simulation time 390999015 ps
CPU time 6.66 seconds
Started Aug 18 04:58:54 PM PDT 24
Finished Aug 18 04:59:00 PM PDT 24
Peak memory 201944 kb
Host smart-1485142f-19d9-4253-b1a1-3ecefa7e1358
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=477390358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.477390358
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.129433872
Short name T292
Test name
Test status
Simulation time 56314899 ps
CPU time 7.38 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 201944 kb
Host smart-c7c94a64-404d-4fd3-b8c3-f3da2b755e5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=129433872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.129433872
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2729312660
Short name T448
Test name
Test status
Simulation time 1353337685 ps
CPU time 7.47 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 04:59:01 PM PDT 24
Peak memory 201840 kb
Host smart-c488492d-9862-4ac6-9082-a0519bb004b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2729312660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2729312660
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2845621292
Short name T176
Test name
Test status
Simulation time 396372556 ps
CPU time 4.9 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 04:58:58 PM PDT 24
Peak memory 201848 kb
Host smart-93f7375d-7281-4a20-97c8-b8fe95c86b0c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2845621292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2845621292
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.964445696
Short name T398
Test name
Test status
Simulation time 1349722927 ps
CPU time 14.78 seconds
Started Aug 18 04:58:54 PM PDT 24
Finished Aug 18 04:59:09 PM PDT 24
Peak memory 201796 kb
Host smart-53a08ed7-e839-41bb-a9bb-0ce69bc28960
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964445696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.964445696
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1117859196
Short name T280
Test name
Test status
Simulation time 40456971968 ps
CPU time 157.95 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 05:01:31 PM PDT 24
Peak memory 201876 kb
Host smart-a92b81d3-d4c8-4440-9c66-9ec3d7ff65ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117859196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1117859196
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.411508530
Short name T656
Test name
Test status
Simulation time 14659371856 ps
CPU time 69.77 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 05:00:02 PM PDT 24
Peak memory 201884 kb
Host smart-fb2f73cf-fe54-4037-b6c6-5d3240565c8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=411508530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.411508530
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.914760857
Short name T160
Test name
Test status
Simulation time 26706922 ps
CPU time 2.61 seconds
Started Aug 18 04:58:54 PM PDT 24
Finished Aug 18 04:58:57 PM PDT 24
Peak memory 201840 kb
Host smart-7ab7ef46-6c3b-4d72-b492-8d1956b7812d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914760857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.914760857
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.1759563671
Short name T390
Test name
Test status
Simulation time 768804452 ps
CPU time 3.31 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:58:54 PM PDT 24
Peak memory 201888 kb
Host smart-5c00233b-97fb-4e0c-9d13-14776ea52f4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759563671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1759563671
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.4032248731
Short name T155
Test name
Test status
Simulation time 132110297 ps
CPU time 1.14 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:58:52 PM PDT 24
Peak memory 201824 kb
Host smart-9cbffb6a-5c89-41e7-a149-7a53fe68a125
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4032248731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4032248731
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2163602276
Short name T17
Test name
Test status
Simulation time 2333281612 ps
CPU time 7.76 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 201944 kb
Host smart-a66f1993-b3d0-49a9-96f3-e91213604220
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163602276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2163602276
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3099999850
Short name T732
Test name
Test status
Simulation time 8304497050 ps
CPU time 11.61 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:59:06 PM PDT 24
Peak memory 201900 kb
Host smart-af9e913e-0ccd-418c-b791-de0966e01b4e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3099999850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3099999850
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1150878404
Short name T255
Test name
Test status
Simulation time 9470448 ps
CPU time 1.12 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 201900 kb
Host smart-762919ad-ed0d-4c08-8db3-b0128564643b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150878404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1150878404
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.390866735
Short name T50
Test name
Test status
Simulation time 11228726964 ps
CPU time 55.05 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:59:47 PM PDT 24
Peak memory 203036 kb
Host smart-4af947c4-81c1-4072-9098-da05e6d99132
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=390866735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.390866735
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2368886069
Short name T768
Test name
Test status
Simulation time 14018730645 ps
CPU time 77.13 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 05:00:09 PM PDT 24
Peak memory 202948 kb
Host smart-673b709c-dd93-4b63-9cc8-a9252d8f86db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2368886069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2368886069
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2406643026
Short name T509
Test name
Test status
Simulation time 658625834 ps
CPU time 101.89 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 05:00:33 PM PDT 24
Peak memory 206044 kb
Host smart-c18f912d-4f5f-4b6e-beb9-8630773529fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2406643026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.2406643026
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.819933506
Short name T207
Test name
Test status
Simulation time 255422654 ps
CPU time 23.62 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:59:16 PM PDT 24
Peak memory 202952 kb
Host smart-637e127e-33fe-425e-854a-a16c40440725
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=819933506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_res
et_error.819933506
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1659255331
Short name T669
Test name
Test status
Simulation time 50598343 ps
CPU time 5.35 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:57 PM PDT 24
Peak memory 201900 kb
Host smart-c9a7f04e-94c7-4338-89af-2312f7d285af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1659255331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1659255331
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2055151577
Short name T621
Test name
Test status
Simulation time 66107040 ps
CPU time 11.9 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:57 PM PDT 24
Peak memory 201848 kb
Host smart-d0e3acfd-2e2f-4614-beb5-5aa50b16aa07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2055151577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2055151577
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1002012866
Short name T198
Test name
Test status
Simulation time 14528450469 ps
CPU time 76.55 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:53:00 PM PDT 24
Peak memory 201948 kb
Host smart-32e056b3-3883-4862-93fe-fa8402a1aae3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1002012866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.1002012866
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1686356921
Short name T668
Test name
Test status
Simulation time 791633612 ps
CPU time 2.77 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:46 PM PDT 24
Peak memory 201864 kb
Host smart-726759ee-09de-4a64-afd6-a65a31ef96d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1686356921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1686356921
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.2140115220
Short name T283
Test name
Test status
Simulation time 35032340 ps
CPU time 2.16 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:47 PM PDT 24
Peak memory 201892 kb
Host smart-527015a2-f80f-4958-b8f7-8f4d6552b319
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2140115220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2140115220
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.1476952256
Short name T168
Test name
Test status
Simulation time 390307045 ps
CPU time 4.96 seconds
Started Aug 18 04:51:46 PM PDT 24
Finished Aug 18 04:51:51 PM PDT 24
Peak memory 201848 kb
Host smart-fe9a3ab9-b8f6-4b88-807b-6bf38949043a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1476952256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1476952256
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1043079272
Short name T813
Test name
Test status
Simulation time 15628184302 ps
CPU time 71.41 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:52:56 PM PDT 24
Peak memory 201876 kb
Host smart-54f5097b-bd83-4288-b6fc-e2a43b09ef72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043079272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1043079272
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2405624877
Short name T846
Test name
Test status
Simulation time 2259062146 ps
CPU time 13.99 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:58 PM PDT 24
Peak memory 201952 kb
Host smart-75fff1b5-3cd8-4c8e-bb3b-64030726660a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2405624877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2405624877
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3608598070
Short name T499
Test name
Test status
Simulation time 29036036 ps
CPU time 2.34 seconds
Started Aug 18 04:51:47 PM PDT 24
Finished Aug 18 04:51:49 PM PDT 24
Peak memory 201944 kb
Host smart-8a411d47-b120-428a-910b-343834d26eb2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608598070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3608598070
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.4065414890
Short name T393
Test name
Test status
Simulation time 311896430 ps
CPU time 4.66 seconds
Started Aug 18 04:51:49 PM PDT 24
Finished Aug 18 04:51:54 PM PDT 24
Peak memory 201840 kb
Host smart-0b93573d-229a-4406-b48f-220d6dcb29d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4065414890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4065414890
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1031778972
Short name T870
Test name
Test status
Simulation time 345170303 ps
CPU time 1.51 seconds
Started Aug 18 04:51:34 PM PDT 24
Finished Aug 18 04:51:36 PM PDT 24
Peak memory 201852 kb
Host smart-d4a36cdb-8372-4e76-8b26-b03331c50895
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1031778972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1031778972
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2292121715
Short name T806
Test name
Test status
Simulation time 9758438875 ps
CPU time 10.43 seconds
Started Aug 18 04:51:47 PM PDT 24
Finished Aug 18 04:51:57 PM PDT 24
Peak memory 201952 kb
Host smart-3660558d-2712-4cd4-8894-10a4483c3d1c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292121715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2292121715
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1172371541
Short name T3
Test name
Test status
Simulation time 1408214262 ps
CPU time 7.56 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:51 PM PDT 24
Peak memory 201804 kb
Host smart-86203bfd-2586-49f0-8531-466c8b138b45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1172371541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1172371541
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1114843529
Short name T697
Test name
Test status
Simulation time 9075681 ps
CPU time 1.27 seconds
Started Aug 18 04:51:33 PM PDT 24
Finished Aug 18 04:51:35 PM PDT 24
Peak memory 201788 kb
Host smart-0075416a-0d99-4958-8d22-25a46a1cd17d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114843529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1114843529
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1624366373
Short name T571
Test name
Test status
Simulation time 1103812796 ps
CPU time 66.57 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:52:50 PM PDT 24
Peak memory 203912 kb
Host smart-ddd2ebba-6fa8-4162-a2a6-2ae9a1ec7dbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1624366373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1624366373
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3546335938
Short name T445
Test name
Test status
Simulation time 244130233 ps
CPU time 30.15 seconds
Started Aug 18 04:51:46 PM PDT 24
Finished Aug 18 04:52:17 PM PDT 24
Peak memory 202128 kb
Host smart-99e94b73-df18-43fd-9092-e356608d7c95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3546335938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3546335938
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3305213650
Short name T586
Test name
Test status
Simulation time 2623571198 ps
CPU time 42.65 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:52:26 PM PDT 24
Peak memory 204712 kb
Host smart-726876e8-ed8c-4f43-a510-87829793a610
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3305213650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3305213650
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.763313236
Short name T205
Test name
Test status
Simulation time 1406010732 ps
CPU time 57.99 seconds
Started Aug 18 04:51:48 PM PDT 24
Finished Aug 18 04:52:46 PM PDT 24
Peak memory 205008 kb
Host smart-88e5d71b-7de8-43eb-87b3-906b7981f901
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=763313236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese
t_error.763313236
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2261311014
Short name T830
Test name
Test status
Simulation time 217001234 ps
CPU time 4.33 seconds
Started Aug 18 04:51:42 PM PDT 24
Finished Aug 18 04:51:47 PM PDT 24
Peak memory 201832 kb
Host smart-7a878f22-734e-493e-b5b9-1ae64351cb36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2261311014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2261311014
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2471940480
Short name T328
Test name
Test status
Simulation time 23599246 ps
CPU time 2.62 seconds
Started Aug 18 04:51:48 PM PDT 24
Finished Aug 18 04:51:51 PM PDT 24
Peak memory 201836 kb
Host smart-d311f6ab-e099-4b24-b034-44768b9d8295
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2471940480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2471940480
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3840720720
Short name T638
Test name
Test status
Simulation time 65352411908 ps
CPU time 233.79 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 203340 kb
Host smart-2aeae843-d31f-4f5b-aabe-4316c48f9c00
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3840720720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.3840720720
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.903020151
Short name T291
Test name
Test status
Simulation time 998416774 ps
CPU time 7.51 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:52 PM PDT 24
Peak memory 201932 kb
Host smart-bc3cd09b-a4df-40e6-a4c5-423e02eae91f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903020151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.903020151
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.1009603620
Short name T466
Test name
Test status
Simulation time 1241050209 ps
CPU time 13.18 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:58 PM PDT 24
Peak memory 201784 kb
Host smart-a06691f8-e59c-4304-b9c0-3d08f65953ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1009603620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1009603620
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.1178905208
Short name T444
Test name
Test status
Simulation time 426676623 ps
CPU time 6.92 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:51 PM PDT 24
Peak memory 201808 kb
Host smart-fa32a082-aed2-493c-b69d-35c28b345830
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1178905208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1178905208
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1730761364
Short name T122
Test name
Test status
Simulation time 29092661926 ps
CPU time 136.8 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:54:01 PM PDT 24
Peak memory 201960 kb
Host smart-4bf1a793-5f30-456c-b904-595bd066aca4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730761364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1730761364
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3346877368
Short name T711
Test name
Test status
Simulation time 26455729221 ps
CPU time 121.37 seconds
Started Aug 18 04:51:46 PM PDT 24
Finished Aug 18 04:53:47 PM PDT 24
Peak memory 201924 kb
Host smart-2663687e-dd0e-48de-95bc-c1efe0533532
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3346877368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3346877368
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1704773158
Short name T367
Test name
Test status
Simulation time 39997321 ps
CPU time 5.5 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:50 PM PDT 24
Peak memory 201812 kb
Host smart-85506c01-a0ef-48fc-a530-29a50b863f26
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704773158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1704773158
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.3134575359
Short name T658
Test name
Test status
Simulation time 26538498 ps
CPU time 2.61 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:48 PM PDT 24
Peak memory 201952 kb
Host smart-1450056f-bdb3-4631-94f1-4db4df157f24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3134575359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3134575359
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.3910030900
Short name T580
Test name
Test status
Simulation time 47735538 ps
CPU time 1.36 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:47 PM PDT 24
Peak memory 201816 kb
Host smart-15660800-c184-40bd-9a6a-bf24adb12f07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3910030900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3910030900
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2328917442
Short name T541
Test name
Test status
Simulation time 2816869175 ps
CPU time 7.99 seconds
Started Aug 18 04:51:47 PM PDT 24
Finished Aug 18 04:51:55 PM PDT 24
Peak memory 201844 kb
Host smart-dcc486ef-dbcd-461b-a479-fa42663e4e91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328917442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2328917442
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1837769161
Short name T37
Test name
Test status
Simulation time 7064397500 ps
CPU time 6.81 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:52 PM PDT 24
Peak memory 202008 kb
Host smart-3a920565-cb56-4116-bc15-4454043440fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1837769161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1837769161
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4060950837
Short name T555
Test name
Test status
Simulation time 8986115 ps
CPU time 1.16 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:46 PM PDT 24
Peak memory 201964 kb
Host smart-39758fcd-b59b-41fa-9529-ec55d689518e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060950837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4060950837
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3006067014
Short name T96
Test name
Test status
Simulation time 377367541 ps
CPU time 23.42 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:52:08 PM PDT 24
Peak memory 201928 kb
Host smart-62a35de7-369a-4259-afbd-5152976cee7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3006067014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3006067014
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3608635245
Short name T178
Test name
Test status
Simulation time 5916174 ps
CPU time 0.77 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:46 PM PDT 24
Peak memory 193560 kb
Host smart-1a83d218-2c03-4b6f-97fb-34b709913243
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3608635245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3608635245
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3181472936
Short name T699
Test name
Test status
Simulation time 8434716903 ps
CPU time 173.56 seconds
Started Aug 18 04:51:46 PM PDT 24
Finished Aug 18 04:54:40 PM PDT 24
Peak memory 206392 kb
Host smart-7ca3ad79-ff6b-4cfa-ad43-bbfcad3bb683
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3181472936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand
_reset.3181472936
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1596260585
Short name T397
Test name
Test status
Simulation time 405446853 ps
CPU time 51.6 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:52:36 PM PDT 24
Peak memory 204580 kb
Host smart-824662bb-0163-4c7f-a500-33130e26dab7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1596260585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1596260585
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1435232140
Short name T401
Test name
Test status
Simulation time 409952742 ps
CPU time 8.36 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:53 PM PDT 24
Peak memory 201848 kb
Host smart-2cab0418-94e0-4b8e-80cc-fe61de072837
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1435232140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1435232140
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.4293995197
Short name T583
Test name
Test status
Simulation time 123042312 ps
CPU time 9.25 seconds
Started Aug 18 04:51:49 PM PDT 24
Finished Aug 18 04:51:58 PM PDT 24
Peak memory 201832 kb
Host smart-475c86fa-b94d-4d00-91e0-1f1cb6bb529e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4293995197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.4293995197
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3972287355
Short name T192
Test name
Test status
Simulation time 54197654760 ps
CPU time 312.96 seconds
Started Aug 18 04:51:51 PM PDT 24
Finished Aug 18 04:57:05 PM PDT 24
Peak memory 202932 kb
Host smart-464a7124-de8d-48e0-a371-012299272a27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3972287355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.3972287355
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1255334181
Short name T359
Test name
Test status
Simulation time 1190087486 ps
CPU time 10.67 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:54 PM PDT 24
Peak memory 201936 kb
Host smart-21da2acf-eb59-4172-8407-308b58f489dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1255334181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1255334181
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.3469936153
Short name T648
Test name
Test status
Simulation time 1021357434 ps
CPU time 14.49 seconds
Started Aug 18 04:51:49 PM PDT 24
Finished Aug 18 04:52:04 PM PDT 24
Peak memory 201836 kb
Host smart-571904a0-31c0-407a-afc9-af4375927674
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3469936153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3469936153
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.1854655453
Short name T677
Test name
Test status
Simulation time 1058340799 ps
CPU time 15.36 seconds
Started Aug 18 04:51:49 PM PDT 24
Finished Aug 18 04:52:04 PM PDT 24
Peak memory 201796 kb
Host smart-2c05ede1-1a30-446a-93ab-d05584ef738d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1854655453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1854655453
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3367678680
Short name T595
Test name
Test status
Simulation time 42830845295 ps
CPU time 163.4 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:54:27 PM PDT 24
Peak memory 201960 kb
Host smart-927fa28c-b231-437e-8d3f-4098c2fabae2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367678680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3367678680
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1227265363
Short name T170
Test name
Test status
Simulation time 5558357070 ps
CPU time 24.87 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:52:10 PM PDT 24
Peak memory 201912 kb
Host smart-4e6f96c6-dc3f-4ebf-ba6d-57794a6cd818
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1227265363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1227265363
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1579222925
Short name T654
Test name
Test status
Simulation time 23594323 ps
CPU time 1.84 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:46 PM PDT 24
Peak memory 201868 kb
Host smart-0333fcd7-ad55-4bd5-8d36-cb8032cef660
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579222925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1579222925
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.4102323702
Short name T585
Test name
Test status
Simulation time 1114824185 ps
CPU time 11.75 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:55 PM PDT 24
Peak memory 201920 kb
Host smart-b024dbfa-9187-4b08-80b9-de4613b6fe3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4102323702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4102323702
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.2053997386
Short name T793
Test name
Test status
Simulation time 66343940 ps
CPU time 1.39 seconds
Started Aug 18 04:51:47 PM PDT 24
Finished Aug 18 04:51:49 PM PDT 24
Peak memory 201900 kb
Host smart-afe4513d-0407-4ae1-af92-077e8ecc3236
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2053997386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2053997386
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1927524619
Short name T644
Test name
Test status
Simulation time 2993830288 ps
CPU time 7.75 seconds
Started Aug 18 04:51:45 PM PDT 24
Finished Aug 18 04:51:53 PM PDT 24
Peak memory 201956 kb
Host smart-4773bfb5-5d57-42b3-bc4b-a22683555f6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927524619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1927524619
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3765755792
Short name T59
Test name
Test status
Simulation time 1660127113 ps
CPU time 11.65 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:55 PM PDT 24
Peak memory 201944 kb
Host smart-085660ad-e5da-4724-a633-9cea60e3041c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3765755792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3765755792
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3627709542
Short name T152
Test name
Test status
Simulation time 8556198 ps
CPU time 1.1 seconds
Started Aug 18 04:51:43 PM PDT 24
Finished Aug 18 04:51:45 PM PDT 24
Peak memory 201888 kb
Host smart-085d5f6e-a578-4cf6-b5ce-4ac172c09202
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627709542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3627709542
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.760865814
Short name T436
Test name
Test status
Simulation time 104647400 ps
CPU time 14.18 seconds
Started Aug 18 04:51:58 PM PDT 24
Finished Aug 18 04:52:13 PM PDT 24
Peak memory 201812 kb
Host smart-d0e7d379-eb82-442d-8362-e1683f0c3330
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=760865814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.760865814
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3973370834
Short name T750
Test name
Test status
Simulation time 127934227 ps
CPU time 11.76 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:52:09 PM PDT 24
Peak memory 201812 kb
Host smart-2bc6da99-d0f9-4a9d-9284-5000f86b86f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3973370834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3973370834
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1768697533
Short name T29
Test name
Test status
Simulation time 9773729771 ps
CPU time 67.55 seconds
Started Aug 18 04:51:59 PM PDT 24
Finished Aug 18 04:53:07 PM PDT 24
Peak memory 205708 kb
Host smart-36ad0973-d7fb-49e4-8b49-e5926220f0a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1768697533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.1768697533
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4232329471
Short name T900
Test name
Test status
Simulation time 2041092702 ps
CPU time 44.47 seconds
Started Aug 18 04:51:59 PM PDT 24
Finished Aug 18 04:52:43 PM PDT 24
Peak memory 203724 kb
Host smart-a8bbdb72-bda4-4e91-a96f-9868f598d916
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4232329471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.4232329471
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.518417921
Short name T62
Test name
Test status
Simulation time 576636720 ps
CPU time 10.24 seconds
Started Aug 18 04:51:44 PM PDT 24
Finished Aug 18 04:51:54 PM PDT 24
Peak memory 201848 kb
Host smart-2b9abf01-93e2-483f-b551-c4579c3aa1d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518417921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.518417921
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.859921067
Short name T231
Test name
Test status
Simulation time 40032821 ps
CPU time 8.51 seconds
Started Aug 18 04:51:58 PM PDT 24
Finished Aug 18 04:52:07 PM PDT 24
Peak memory 201828 kb
Host smart-08261ebd-f960-46e6-ab78-92f8ec93b899
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=859921067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.859921067
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.4233690483
Short name T193
Test name
Test status
Simulation time 18920318157 ps
CPU time 132.31 seconds
Started Aug 18 04:51:58 PM PDT 24
Finished Aug 18 04:54:10 PM PDT 24
Peak memory 202964 kb
Host smart-08ef253a-66dd-417b-9bda-caf8e3dd5697
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4233690483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.4233690483
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.649018530
Short name T422
Test name
Test status
Simulation time 12701169 ps
CPU time 1.45 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:51:59 PM PDT 24
Peak memory 201776 kb
Host smart-d7a78ddd-5c0a-49bd-97a1-e6d45a87ca78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=649018530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.649018530
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.1470288392
Short name T814
Test name
Test status
Simulation time 4824256885 ps
CPU time 12.17 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:52:08 PM PDT 24
Peak memory 201936 kb
Host smart-728759f7-e964-4014-85fe-5c68b375ee99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1470288392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1470288392
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1640575368
Short name T427
Test name
Test status
Simulation time 49483535899 ps
CPU time 168.5 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:54:45 PM PDT 24
Peak memory 201872 kb
Host smart-6a72be86-9986-41e8-9332-5e6d94145b84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640575368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1640575368
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2148742037
Short name T604
Test name
Test status
Simulation time 13266189266 ps
CPU time 44.15 seconds
Started Aug 18 04:52:00 PM PDT 24
Finished Aug 18 04:52:44 PM PDT 24
Peak memory 202000 kb
Host smart-7eb148ed-f828-45ac-abc1-d033a0efea59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2148742037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2148742037
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.4113138966
Short name T771
Test name
Test status
Simulation time 137910675 ps
CPU time 7.82 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:52:05 PM PDT 24
Peak memory 201924 kb
Host smart-f0228aad-1536-4ea9-905a-5033dd7d096b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113138966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.4113138966
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2671910770
Short name T253
Test name
Test status
Simulation time 1094168601 ps
CPU time 12.32 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:52:10 PM PDT 24
Peak memory 201844 kb
Host smart-a7ad440a-4dd5-4222-9942-faaa39d6cfcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2671910770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2671910770
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.2219214696
Short name T775
Test name
Test status
Simulation time 52019993 ps
CPU time 1.6 seconds
Started Aug 18 04:51:59 PM PDT 24
Finished Aug 18 04:52:00 PM PDT 24
Peak memory 201804 kb
Host smart-4cc9e255-9f54-4b7e-b34c-3c63c6bb701a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219214696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2219214696
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3367866796
Short name T762
Test name
Test status
Simulation time 2097718966 ps
CPU time 7.8 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:52:04 PM PDT 24
Peak memory 201816 kb
Host smart-55b41d14-e819-4134-8053-f254ab8a648a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367866796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3367866796
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1098686921
Short name T450
Test name
Test status
Simulation time 4367383599 ps
CPU time 6.54 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:52:03 PM PDT 24
Peak memory 201936 kb
Host smart-019979e8-b6d9-49b9-ab19-dd2939308c3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1098686921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1098686921
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1083911519
Short name T538
Test name
Test status
Simulation time 10868893 ps
CPU time 1.18 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:51:58 PM PDT 24
Peak memory 201940 kb
Host smart-8f33a887-1156-4019-b122-9188c974bf4b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083911519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1083911519
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1901489989
Short name T733
Test name
Test status
Simulation time 1017395783 ps
CPU time 13.7 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:52:11 PM PDT 24
Peak memory 201872 kb
Host smart-173d76d4-936f-4356-8df2-33a63cd84314
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1901489989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1901489989
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1065180640
Short name T169
Test name
Test status
Simulation time 941927733 ps
CPU time 19.66 seconds
Started Aug 18 04:52:05 PM PDT 24
Finished Aug 18 04:52:24 PM PDT 24
Peak memory 201828 kb
Host smart-5739c5f4-6c58-44d2-aaf8-9a76b2c4c021
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1065180640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1065180640
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3680768064
Short name T212
Test name
Test status
Simulation time 107731282 ps
CPU time 19.25 seconds
Started Aug 18 04:51:58 PM PDT 24
Finished Aug 18 04:52:18 PM PDT 24
Peak memory 203056 kb
Host smart-a8812567-8c89-4676-a642-54e780416fa0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3680768064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.3680768064
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.5818342
Short name T204
Test name
Test status
Simulation time 6735211227 ps
CPU time 60.18 seconds
Started Aug 18 04:52:01 PM PDT 24
Finished Aug 18 04:53:01 PM PDT 24
Peak memory 204916 kb
Host smart-76ca3cf6-6041-4b8a-b8d9-454c99ee173f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5818342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_
error.5818342
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2861224189
Short name T877
Test name
Test status
Simulation time 33963759 ps
CPU time 1.43 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:07 PM PDT 24
Peak memory 201820 kb
Host smart-d657c392-6c1f-41b8-bc24-7238b142e77a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2861224189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2861224189
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2234310014
Short name T95
Test name
Test status
Simulation time 864439928 ps
CPU time 14.21 seconds
Started Aug 18 04:51:58 PM PDT 24
Finished Aug 18 04:52:12 PM PDT 24
Peak memory 201860 kb
Host smart-43699fa9-ec67-4f57-b22e-ddf34d5653cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2234310014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2234310014
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2896269371
Short name T189
Test name
Test status
Simulation time 82666935636 ps
CPU time 135.56 seconds
Started Aug 18 04:51:55 PM PDT 24
Finished Aug 18 04:54:11 PM PDT 24
Peak memory 203048 kb
Host smart-55fabffb-05fd-4203-a649-becdc195c76f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2896269371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.2896269371
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.374825332
Short name T511
Test name
Test status
Simulation time 102313241 ps
CPU time 2.23 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:08 PM PDT 24
Peak memory 201860 kb
Host smart-6dd0b4a1-2dc3-4a39-813f-a558856ed4b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=374825332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.374825332
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.1957903961
Short name T306
Test name
Test status
Simulation time 45826196 ps
CPU time 4.01 seconds
Started Aug 18 04:52:07 PM PDT 24
Finished Aug 18 04:52:11 PM PDT 24
Peak memory 201864 kb
Host smart-1cbd86e0-9c42-4102-97d9-2f6fa36927d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1957903961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1957903961
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.3843018594
Short name T719
Test name
Test status
Simulation time 162983539 ps
CPU time 4.44 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:52:01 PM PDT 24
Peak memory 201804 kb
Host smart-fa05b025-45c4-40eb-88cd-747b838df842
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3843018594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3843018594
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.371704639
Short name T700
Test name
Test status
Simulation time 14726024989 ps
CPU time 17.53 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:52:14 PM PDT 24
Peak memory 201888 kb
Host smart-bbda3da9-5f1d-47a5-b997-13a9487e1806
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=371704639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.371704639
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3051944966
Short name T335
Test name
Test status
Simulation time 3027910043 ps
CPU time 14 seconds
Started Aug 18 04:51:58 PM PDT 24
Finished Aug 18 04:52:12 PM PDT 24
Peak memory 201936 kb
Host smart-3d917e4e-1a84-4093-8937-99850f22f61e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3051944966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3051944966
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1272809285
Short name T743
Test name
Test status
Simulation time 19368713 ps
CPU time 2.05 seconds
Started Aug 18 04:52:05 PM PDT 24
Finished Aug 18 04:52:07 PM PDT 24
Peak memory 201812 kb
Host smart-8eff9d0e-a468-4a22-bf1e-99f14473b682
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272809285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1272809285
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.2395342203
Short name T721
Test name
Test status
Simulation time 1183038937 ps
CPU time 9.93 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:52:06 PM PDT 24
Peak memory 201872 kb
Host smart-67e1287f-335f-49fb-8435-6c02fe4d3d33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2395342203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2395342203
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.84926783
Short name T453
Test name
Test status
Simulation time 31635209 ps
CPU time 1.41 seconds
Started Aug 18 04:51:56 PM PDT 24
Finished Aug 18 04:51:58 PM PDT 24
Peak memory 201868 kb
Host smart-f2497dc9-ef6c-4a11-887d-daf07e5b7b87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84926783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.84926783
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3477356577
Short name T490
Test name
Test status
Simulation time 1204315594 ps
CPU time 5.93 seconds
Started Aug 18 04:51:59 PM PDT 24
Finished Aug 18 04:52:05 PM PDT 24
Peak memory 201912 kb
Host smart-d837ed8a-4366-4644-9ef0-0406d73b49d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477356577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3477356577
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.4096955516
Short name T646
Test name
Test status
Simulation time 1932097922 ps
CPU time 6.53 seconds
Started Aug 18 04:51:57 PM PDT 24
Finished Aug 18 04:52:04 PM PDT 24
Peak memory 201952 kb
Host smart-ef0e0fb0-116c-4e87-8e98-da80e895e430
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4096955516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4096955516
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1984725612
Short name T641
Test name
Test status
Simulation time 7760776 ps
CPU time 1.03 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:07 PM PDT 24
Peak memory 201832 kb
Host smart-660e945b-6dc9-4ace-a20f-175e570fc739
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984725612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1984725612
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2384583773
Short name T702
Test name
Test status
Simulation time 7737186071 ps
CPU time 57.4 seconds
Started Aug 18 04:52:08 PM PDT 24
Finished Aug 18 04:53:05 PM PDT 24
Peak memory 202944 kb
Host smart-1476da1b-e852-4c0f-a84f-d1d4cadcb4f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2384583773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2384583773
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4037852500
Short name T84
Test name
Test status
Simulation time 1649620634 ps
CPU time 15.01 seconds
Started Aug 18 04:52:05 PM PDT 24
Finished Aug 18 04:52:20 PM PDT 24
Peak memory 201856 kb
Host smart-0de097e6-2045-4a58-afe2-81c12a0f086e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4037852500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4037852500
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1299494521
Short name T213
Test name
Test status
Simulation time 697662445 ps
CPU time 78.03 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:53:24 PM PDT 24
Peak memory 206108 kb
Host smart-7e74a3da-69dd-4c5a-8e8a-039ec16fdbd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1299494521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.1299494521
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3405251980
Short name T341
Test name
Test status
Simulation time 1763156393 ps
CPU time 55.92 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:53:02 PM PDT 24
Peak memory 204080 kb
Host smart-11ec9f42-d9a2-4945-8411-aeae11dc93ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3405251980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res
et_error.3405251980
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1484921943
Short name T895
Test name
Test status
Simulation time 248140504 ps
CPU time 4.23 seconds
Started Aug 18 04:52:06 PM PDT 24
Finished Aug 18 04:52:10 PM PDT 24
Peak memory 201932 kb
Host smart-66c83f83-5614-4c89-bc15-a0f995140ceb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1484921943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1484921943
Directory /workspace/9.xbar_unmapped_addr/latest
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