Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 27 0 27 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 27 0 27 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 27 0 27 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 406 1 T16 5 T22 1 T36 1
all_values[1] 455 1 T5 1 T16 1 T24 1
all_values[2] 418 1 T5 1 T16 4 T25 2
all_values[3] 380 1 T5 1 T16 1 T22 1
all_values[4] 430 1 T5 1 T24 1 T36 1
all_values[5] 454 1 T5 1 T16 3 T24 1
all_values[6] 428 1 T5 1 T16 4 T24 1
all_values[7] 426 1 T16 1 T24 1 T25 1
all_values[8] 409 1 T5 1 T16 2 T24 1
all_values[9] 408 1 T5 1 T24 1 T25 1
all_values[10] 414 1 T16 1 T24 2 T148 2
all_values[11] 434 1 T16 2 T36 3 T42 1
all_values[12] 395 1 T5 2 T16 1 T24 1
all_values[13] 466 1 T16 3 T24 1 T36 1
all_values[14] 377 1 T36 1 T42 2 T148 3
all_values[15] 413 1 T5 1 T16 2 T25 2
all_values[16] 450 1 T16 1 T22 1 T25 2
all_values[17] 452 1 T5 3 T16 1 T24 1
all_values[18] 420 1 T16 2 T24 1 T42 1
all_values[19] 432 1 T16 4 T24 1 T25 1
all_values[20] 451 1 T5 2 T25 2 T44 3
all_values[21] 421 1 T16 4 T24 1 T44 5
all_values[22] 434 1 T16 1 T24 1 T25 1
all_values[23] 435 1 T16 2 T25 1 T148 1
all_values[24] 470 1 T16 1 T22 1 T24 1
all_values[25] 419 1 T5 1 T16 3 T24 1
all_values[26] 440 1 T5 1 T16 2 T24 1

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